diff options
-rw-r--r-- | arch/arm/mm/cache-uniphier.c | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/arch/arm/mm/cache-uniphier.c b/arch/arm/mm/cache-uniphier.c index a6fa7b73fbe0..c8e2f4947223 100644 --- a/arch/arm/mm/cache-uniphier.c +++ b/arch/arm/mm/cache-uniphier.c | |||
@@ -96,6 +96,7 @@ struct uniphier_cache_data { | |||
96 | void __iomem *ctrl_base; | 96 | void __iomem *ctrl_base; |
97 | void __iomem *rev_base; | 97 | void __iomem *rev_base; |
98 | void __iomem *op_base; | 98 | void __iomem *op_base; |
99 | void __iomem *way_ctrl_base; | ||
99 | u32 way_present_mask; | 100 | u32 way_present_mask; |
100 | u32 way_locked_mask; | 101 | u32 way_locked_mask; |
101 | u32 nsets; | 102 | u32 nsets; |
@@ -256,10 +257,13 @@ static void __init __uniphier_cache_set_locked_ways( | |||
256 | struct uniphier_cache_data *data, | 257 | struct uniphier_cache_data *data, |
257 | u32 way_mask) | 258 | u32 way_mask) |
258 | { | 259 | { |
260 | unsigned int cpu; | ||
261 | |||
259 | data->way_locked_mask = way_mask & data->way_present_mask; | 262 | data->way_locked_mask = way_mask & data->way_present_mask; |
260 | 263 | ||
261 | writel_relaxed(~data->way_locked_mask & data->way_present_mask, | 264 | for_each_possible_cpu(cpu) |
262 | data->ctrl_base + UNIPHIER_SSCLPDAWCR); | 265 | writel_relaxed(~data->way_locked_mask & data->way_present_mask, |
266 | data->way_ctrl_base + 4 * cpu); | ||
263 | } | 267 | } |
264 | 268 | ||
265 | static void uniphier_cache_maint_range(unsigned long start, unsigned long end, | 269 | static void uniphier_cache_maint_range(unsigned long start, unsigned long end, |
@@ -459,6 +463,8 @@ static int __init __uniphier_cache_init(struct device_node *np, | |||
459 | goto err; | 463 | goto err; |
460 | } | 464 | } |
461 | 465 | ||
466 | data->way_ctrl_base = data->ctrl_base + 0xc00; | ||
467 | |||
462 | if (*cache_level == 2) { | 468 | if (*cache_level == 2) { |
463 | u32 revision = readl(data->rev_base + UNIPHIER_SSCID); | 469 | u32 revision = readl(data->rev_base + UNIPHIER_SSCID); |
464 | /* | 470 | /* |
@@ -467,6 +473,22 @@ static int __init __uniphier_cache_init(struct device_node *np, | |||
467 | */ | 473 | */ |
468 | if (revision <= 0x16) | 474 | if (revision <= 0x16) |
469 | data->range_op_max_size = (u32)1 << 22; | 475 | data->range_op_max_size = (u32)1 << 22; |
476 | |||
477 | /* | ||
478 | * Unfortunatly, the offset address of active way control base | ||
479 | * varies from SoC to SoC. | ||
480 | */ | ||
481 | switch (revision) { | ||
482 | case 0x11: /* sLD3 */ | ||
483 | data->way_ctrl_base = data->ctrl_base + 0x870; | ||
484 | break; | ||
485 | case 0x12: /* LD4 */ | ||
486 | case 0x16: /* sld8 */ | ||
487 | data->way_ctrl_base = data->ctrl_base + 0x840; | ||
488 | break; | ||
489 | default: | ||
490 | break; | ||
491 | } | ||
470 | } | 492 | } |
471 | 493 | ||
472 | data->range_op_max_size -= data->line_size; | 494 | data->range_op_max_size -= data->line_size; |