2 files changed, 47 insertions, 7 deletions

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index f5dbdbf3e98d..d3727e877872 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -104,6 +104,7 @@ static DEFINE_PER_CPU(bool, has_rss);
 enum gic_intid_range {
         PPI_RANGE,
         SPI_RANGE,
+        EPPI_RANGE,
         ESPI_RANGE,
         LPI_RANGE,
         __INVALID_RANGE__
@@ -116,6 +117,8 @@ static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq)
                 return PPI_RANGE;
         case 32 ... 1019:
                 return SPI_RANGE;
+        case EPPI_BASE_INTID ... (EPPI_BASE_INTID + 63):
+                return EPPI_RANGE;
         case ESPI_BASE_INTID ... (ESPI_BASE_INTID + 1023):
                 return ESPI_RANGE;
         case 8192 ... GENMASK(23, 0):
@@ -137,13 +140,15 @@ static inline unsigned int gic_irq(struct irq_data *d)
 
 static inline int gic_irq_in_rdist(struct irq_data *d)
 {
-        return get_intid_range(d) == PPI_RANGE;
+        enum gic_intid_range range = get_intid_range(d);
+        return range == PPI_RANGE || range == EPPI_RANGE;
 }
 
 static inline void __iomem *gic_dist_base(struct irq_data *d)
 {
         switch (get_intid_range(d)) {
         case PPI_RANGE:
+        case EPPI_RANGE:
                 /* SGI+PPI -> SGI_base for this CPU */
                 return gic_data_rdist_sgi_base();
 
@@ -242,6 +247,14 @@ static u32 convert_offset_index(struct irq_data *d, u32 offset, u32 *index)
         case SPI_RANGE:
                 *index = d->hwirq;
                 return offset;
+        case EPPI_RANGE:
+                /*
+                 * Contrary to the ESPI range, the EPPI range is contiguous
+                 * to the PPI range in the registers, so let's adjust the
+                 * displacement accordingly. Consistency is overrated.
+                 */
+                *index = d->hwirq - EPPI_BASE_INTID + 32;
+                return offset;
         case ESPI_RANGE:
                 *index = d->hwirq - ESPI_BASE_INTID;
                 switch (offset) {
@@ -414,6 +427,8 @@ static u32 gic_get_ppi_index(struct irq_data *d)
         switch (get_intid_range(d)) {
         case PPI_RANGE:
                 return d->hwirq - 16;
+        case EPPI_RANGE:
+                return d->hwirq - EPPI_BASE_INTID + 16;
         default:
                 unreachable();
         }
@@ -507,6 +522,7 @@ static void gic_eoimode1_eoi_irq(struct irq_data *d)
 
 static int gic_set_type(struct irq_data *d, unsigned int type)
 {
+        enum gic_intid_range range;
         unsigned int irq = gic_irq(d);
         void (*rwp_wait)(void);
         void __iomem *base;
@@ -517,9 +533,11 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
         if (irq < 16)
                 return -EINVAL;
 
+        range = get_intid_range(d);
+
         /* SPIs have restrictions on the supported types */
-        if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
-                         type != IRQ_TYPE_EDGE_RISING)
+        if ((range == SPI_RANGE || range == ESPI_RANGE) &&
+            type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
                 return -EINVAL;
 
         if (gic_irq_in_rdist(d)) {
@@ -533,9 +551,9 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
         offset = convert_offset_index(d, GICD_ICFGR, &index);
 
         ret = gic_configure_irq(index, type, base + offset, rwp_wait);
-        if (ret && irq < 32) {
+        if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) {
                 /* Misconfigured PPIs are usually not fatal */
-                pr_warn("GIC: PPI%d is secure or misconfigured\n", irq - 16);
+                pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
                 ret = 0;
         }
 
@@ -833,7 +851,7 @@ static int __gic_update_rdist_properties(struct redist_region *region,
         u64 typer = gic_read_typer(ptr + GICR_TYPER);
         gic_data.rdists.has_vlpis &= !!(typer & GICR_TYPER_VLPIS);
         gic_data.rdists.has_direct_lpi &= !!(typer & GICR_TYPER_DirectLPIS);
-        gic_data.ppi_nr = 16;
+        gic_data.ppi_nr = min(GICR_TYPER_NR_PPIS(typer), gic_data.ppi_nr);
 
         return 1;
 }
@@ -1222,6 +1240,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
 
         switch (__get_intid_range(hw)) {
         case PPI_RANGE:
+        case EPPI_RANGE:
                 irq_set_percpu_devid(irq);
                 irq_domain_set_info(d, irq, hw, chip, d->host_data,
                                     handle_percpu_devid_irq, NULL, NULL);
@@ -1266,15 +1285,24 @@ static int gic_irq_domain_translate(struct irq_domain *d,
                         *hwirq = fwspec->param[1] + 32;
                         break;
                 case 1:                 /* PPI */
-                case GIC_IRQ_TYPE_PARTITION:
                         *hwirq = fwspec->param[1] + 16;
                         break;
                 case 2:                 /* ESPI */
                         *hwirq = fwspec->param[1] + ESPI_BASE_INTID;
                         break;
+                case 3:                 /* EPPI */
+                        *hwirq = fwspec->param[1] + EPPI_BASE_INTID;
+                        break;
                 case GIC_IRQ_TYPE_LPI:  /* LPI */
                         *hwirq = fwspec->param[1];
                         break;
+                case GIC_IRQ_TYPE_PARTITION:
+                        *hwirq = fwspec->param[1];
+                        if (fwspec->param[1] >= 16)
+                                *hwirq += EPPI_BASE_INTID - 16;
+                        else
+                                *hwirq += 16;
+                        break;
                 default:
                         return -EINVAL;
                 }
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index c523bf1faa55..9ec3349dee04 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -124,6 +124,18 @@
 
 #define GICR_TYPER_CPU_NUMBER(r)        (((r) >> 8) & 0xffff)
 
+#define EPPI_BASE_INTID                 1056
+
+#define GICR_TYPER_NR_PPIS(r)                                           \
+        ({                                                              \
+                unsigned int __ppinum = ((r) >> 27) & 0x1f;             \
+                unsigned int __nr_ppis = 16;                            \
+                if (__ppinum == 1 || __ppinum == 2)                     \
+                        __nr_ppis +=  __ppinum * 32;                    \
+                                                                        \
+                __nr_ppis;                                              \
+         })
+
 #define GICR_WAKER_ProcessorSleep       (1U << 1)
 #define GICR_WAKER_ChildrenAsleep       (1U << 2)