diff options
-rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 25 | ||||
-rw-r--r-- | include/linux/clk/tegra.h | 1 |
2 files changed, 26 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 6f29125ec439..f3e51e640d4d 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c | |||
@@ -181,6 +181,11 @@ | |||
181 | #define SATA_PLL_CFG0 0x490 | 181 | #define SATA_PLL_CFG0 0x490 |
182 | #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) | 182 | #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) |
183 | #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) | 183 | #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) |
184 | #define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4) | ||
185 | #define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5) | ||
186 | #define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6) | ||
187 | #define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7) | ||
188 | |||
184 | #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) | 189 | #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) |
185 | #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) | 190 | #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) |
186 | 191 | ||
@@ -483,6 +488,26 @@ void tegra210_sata_pll_hw_sequence_start(void) | |||
483 | } | 488 | } |
484 | EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start); | 489 | EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start); |
485 | 490 | ||
491 | void tegra210_set_sata_pll_seq_sw(bool state) | ||
492 | { | ||
493 | u32 val; | ||
494 | |||
495 | val = readl_relaxed(clk_base + SATA_PLL_CFG0); | ||
496 | if (state) { | ||
497 | val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; | ||
498 | val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; | ||
499 | val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; | ||
500 | val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; | ||
501 | } else { | ||
502 | val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL; | ||
503 | val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; | ||
504 | val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; | ||
505 | val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; | ||
506 | } | ||
507 | writel_relaxed(val, clk_base + SATA_PLL_CFG0); | ||
508 | } | ||
509 | EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw); | ||
510 | |||
486 | static inline void _pll_misc_chk_default(void __iomem *base, | 511 | static inline void _pll_misc_chk_default(void __iomem *base, |
487 | struct tegra_clk_pll_params *params, | 512 | struct tegra_clk_pll_params *params, |
488 | u8 misc_num, u32 default_val, u32 mask) | 513 | u8 misc_num, u32 default_val, u32 mask) |
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h index e17d32831e28..d23c9cf26993 100644 --- a/include/linux/clk/tegra.h +++ b/include/linux/clk/tegra.h | |||
@@ -125,6 +125,7 @@ extern void tegra210_xusb_pll_hw_control_enable(void); | |||
125 | extern void tegra210_xusb_pll_hw_sequence_start(void); | 125 | extern void tegra210_xusb_pll_hw_sequence_start(void); |
126 | extern void tegra210_sata_pll_hw_control_enable(void); | 126 | extern void tegra210_sata_pll_hw_control_enable(void); |
127 | extern void tegra210_sata_pll_hw_sequence_start(void); | 127 | extern void tegra210_sata_pll_hw_sequence_start(void); |
128 | extern void tegra210_set_sata_pll_seq_sw(bool state); | ||
128 | extern void tegra210_put_utmipll_in_iddq(void); | 129 | extern void tegra210_put_utmipll_in_iddq(void); |
129 | extern void tegra210_put_utmipll_out_iddq(void); | 130 | extern void tegra210_put_utmipll_out_iddq(void); |
130 | 131 | ||