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-rw-r--r--arch/m68k/coldfire/device.c159
-rw-r--r--arch/m68k/coldfire/m5206.c12
-rw-r--r--arch/m68k/coldfire/m520x.c24
-rw-r--r--arch/m68k/coldfire/m523x.c18
-rw-r--r--arch/m68k/coldfire/m5249.c25
-rw-r--r--arch/m68k/coldfire/m525x.c10
-rw-r--r--arch/m68k/coldfire/m527x.c28
-rw-r--r--arch/m68k/coldfire/m528x.c18
-rw-r--r--arch/m68k/coldfire/m5307.c14
-rw-r--r--arch/m68k/coldfire/m53xx.c20
-rw-r--r--arch/m68k/coldfire/m5407.c14
-rw-r--r--arch/m68k/coldfire/m5441x.c12
-rw-r--r--arch/m68k/coldfire/m54xx.c17
-rw-r--r--arch/m68k/include/asm/m5206sim.h8
-rw-r--r--arch/m68k/include/asm/m520xsim.h8
-rw-r--r--arch/m68k/include/asm/m523xsim.h10
-rw-r--r--arch/m68k/include/asm/m527xsim.h8
-rw-r--r--arch/m68k/include/asm/m528xsim.h9
-rw-r--r--arch/m68k/include/asm/m5307sim.h9
-rw-r--r--arch/m68k/include/asm/m53xxsim.h8
-rw-r--r--arch/m68k/include/asm/m5407sim.h8
-rw-r--r--arch/m68k/include/asm/m54xxsim.h11
22 files changed, 432 insertions, 18 deletions
diff --git a/arch/m68k/coldfire/device.c b/arch/m68k/coldfire/device.c
index a0fc0c192427..84938fdbbada 100644
--- a/arch/m68k/coldfire/device.c
+++ b/arch/m68k/coldfire/device.c
@@ -327,6 +327,147 @@ static struct platform_device mcf_qspi = {
327}; 327};
328#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ 328#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
329 329
330#if IS_ENABLED(CONFIG_I2C_IMX)
331static struct resource mcf_i2c0_resources[] = {
332 {
333 .start = MCFI2C_BASE0,
334 .end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
335 .flags = IORESOURCE_MEM,
336 },
337 {
338 .start = MCF_IRQ_I2C0,
339 .end = MCF_IRQ_I2C0,
340 .flags = IORESOURCE_IRQ,
341 },
342};
343
344static struct platform_device mcf_i2c0 = {
345 .name = "imx1-i2c",
346 .id = 0,
347 .num_resources = ARRAY_SIZE(mcf_i2c0_resources),
348 .resource = mcf_i2c0_resources,
349};
350#ifdef MCFI2C_BASE1
351
352static struct resource mcf_i2c1_resources[] = {
353 {
354 .start = MCFI2C_BASE1,
355 .end = MCFI2C_BASE1 + MCFI2C_SIZE1 - 1,
356 .flags = IORESOURCE_MEM,
357 },
358 {
359 .start = MCF_IRQ_I2C1,
360 .end = MCF_IRQ_I2C1,
361 .flags = IORESOURCE_IRQ,
362 },
363};
364
365static struct platform_device mcf_i2c1 = {
366 .name = "imx1-i2c",
367 .id = 1,
368 .num_resources = ARRAY_SIZE(mcf_i2c1_resources),
369 .resource = mcf_i2c1_resources,
370};
371
372#endif /* MCFI2C_BASE1 */
373
374#ifdef MCFI2C_BASE2
375
376static struct resource mcf_i2c2_resources[] = {
377 {
378 .start = MCFI2C_BASE2,
379 .end = MCFI2C_BASE2 + MCFI2C_SIZE2 - 1,
380 .flags = IORESOURCE_MEM,
381 },
382 {
383 .start = MCF_IRQ_I2C2,
384 .end = MCF_IRQ_I2C2,
385 .flags = IORESOURCE_IRQ,
386 },
387};
388
389static struct platform_device mcf_i2c2 = {
390 .name = "imx1-i2c",
391 .id = 2,
392 .num_resources = ARRAY_SIZE(mcf_i2c2_resources),
393 .resource = mcf_i2c2_resources,
394};
395
396#endif /* MCFI2C_BASE2 */
397
398#ifdef MCFI2C_BASE3
399
400static struct resource mcf_i2c3_resources[] = {
401 {
402 .start = MCFI2C_BASE3,
403 .end = MCFI2C_BASE3 + MCFI2C_SIZE3 - 1,
404 .flags = IORESOURCE_MEM,
405 },
406 {
407 .start = MCF_IRQ_I2C3,
408 .end = MCF_IRQ_I2C3,
409 .flags = IORESOURCE_IRQ,
410 },
411};
412
413static struct platform_device mcf_i2c3 = {
414 .name = "imx1-i2c",
415 .id = 3,
416 .num_resources = ARRAY_SIZE(mcf_i2c3_resources),
417 .resource = mcf_i2c3_resources,
418};
419
420#endif /* MCFI2C_BASE3 */
421
422#ifdef MCFI2C_BASE4
423
424static struct resource mcf_i2c4_resources[] = {
425 {
426 .start = MCFI2C_BASE4,
427 .end = MCFI2C_BASE4 + MCFI2C_SIZE4 - 1,
428 .flags = IORESOURCE_MEM,
429 },
430 {
431 .start = MCF_IRQ_I2C4,
432 .end = MCF_IRQ_I2C4,
433 .flags = IORESOURCE_IRQ,
434 },
435};
436
437static struct platform_device mcf_i2c4 = {
438 .name = "imx1-i2c",
439 .id = 4,
440 .num_resources = ARRAY_SIZE(mcf_i2c4_resources),
441 .resource = mcf_i2c4_resources,
442};
443
444#endif /* MCFI2C_BASE4 */
445
446#ifdef MCFI2C_BASE5
447
448static struct resource mcf_i2c5_resources[] = {
449 {
450 .start = MCFI2C_BASE5,
451 .end = MCFI2C_BASE5 + MCFI2C_SIZE5 - 1,
452 .flags = IORESOURCE_MEM,
453 },
454 {
455 .start = MCF_IRQ_I2C5,
456 .end = MCF_IRQ_I2C5,
457 .flags = IORESOURCE_IRQ,
458 },
459};
460
461static struct platform_device mcf_i2c5 = {
462 .name = "imx1-i2c",
463 .id = 5,
464 .num_resources = ARRAY_SIZE(mcf_i2c5_resources),
465 .resource = mcf_i2c5_resources,
466};
467
468#endif /* MCFI2C_BASE5 */
469#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
470
330static struct platform_device *mcf_devices[] __initdata = { 471static struct platform_device *mcf_devices[] __initdata = {
331 &mcf_uart, 472 &mcf_uart,
332#if IS_ENABLED(CONFIG_FEC) 473#if IS_ENABLED(CONFIG_FEC)
@@ -338,6 +479,24 @@ static struct platform_device *mcf_devices[] __initdata = {
338#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 479#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
339 &mcf_qspi, 480 &mcf_qspi,
340#endif 481#endif
482#if IS_ENABLED(CONFIG_I2C_IMX)
483 &mcf_i2c0,
484#ifdef MCFI2C_BASE1
485 &mcf_i2c1,
486#endif
487#ifdef MCFI2C_BASE2
488 &mcf_i2c2,
489#endif
490#ifdef MCFI2C_BASE3
491 &mcf_i2c3,
492#endif
493#ifdef MCFI2C_BASE4
494 &mcf_i2c4,
495#endif
496#ifdef MCFI2C_BASE5
497 &mcf_i2c5,
498#endif
499#endif
341}; 500};
342 501
343/* 502/*
diff --git a/arch/m68k/coldfire/m5206.c b/arch/m68k/coldfire/m5206.c
index 8945f5e7b39c..a3bcf0883f98 100644
--- a/arch/m68k/coldfire/m5206.c
+++ b/arch/m68k/coldfire/m5206.c
@@ -26,6 +26,7 @@ DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); 26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
29 30
30struct clk *mcf_clks[] = { 31struct clk *mcf_clks[] = {
31 &clk_pll, 32 &clk_pll,
@@ -34,11 +35,21 @@ struct clk *mcf_clks[] = {
34 &clk_mcftmr1, 35 &clk_mcftmr1,
35 &clk_mcfuart0, 36 &clk_mcfuart0,
36 &clk_mcfuart1, 37 &clk_mcfuart1,
38 &clk_mcfi2c0,
37 NULL 39 NULL
38}; 40};
39 41
40/***************************************************************************/ 42/***************************************************************************/
41 43
44static void __init m5206_i2c_init(void)
45{
46#if IS_ENABLED(CONFIG_I2C_IMX)
47 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
48 MCFSIM_I2CICR);
49 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
50#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
51}
52
42void __init config_BSP(char *commandp, int size) 53void __init config_BSP(char *commandp, int size)
43{ 54{
44#if defined(CONFIG_NETtel) 55#if defined(CONFIG_NETtel)
@@ -53,6 +64,7 @@ void __init config_BSP(char *commandp, int size)
53 mcf_mapirq2imr(25, MCFINTC_EINT1); 64 mcf_mapirq2imr(25, MCFINTC_EINT1);
54 mcf_mapirq2imr(28, MCFINTC_EINT4); 65 mcf_mapirq2imr(28, MCFINTC_EINT4);
55 mcf_mapirq2imr(31, MCFINTC_EINT7); 66 mcf_mapirq2imr(31, MCFINTC_EINT7);
67 m5206_i2c_init();
56} 68}
57 69
58/***************************************************************************/ 70/***************************************************************************/
diff --git a/arch/m68k/coldfire/m520x.c b/arch/m68k/coldfire/m520x.c
index 173834f251eb..5ba69217ce6c 100644
--- a/arch/m68k/coldfire/m520x.c
+++ b/arch/m68k/coldfire/m520x.c
@@ -28,7 +28,7 @@ DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
28DEFINE_CLK(0, "edma", 17, MCF_CLK); 28DEFINE_CLK(0, "edma", 17, MCF_CLK);
29DEFINE_CLK(0, "intc.0", 18, MCF_CLK); 29DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
30DEFINE_CLK(0, "iack.0", 21, MCF_CLK); 30DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
31DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK); 31DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
32DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK); 32DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
33DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK); 33DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
34DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK); 34DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
@@ -53,7 +53,7 @@ struct clk *mcf_clks[] = {
53 &__clk_0_17, /* edma */ 53 &__clk_0_17, /* edma */
54 &__clk_0_18, /* intc.0 */ 54 &__clk_0_18, /* intc.0 */
55 &__clk_0_21, /* iack.0 */ 55 &__clk_0_21, /* iack.0 */
56 &__clk_0_22, /* mcfi2c.0 */ 56 &__clk_0_22, /* imx1-i2c.0 */
57 &__clk_0_23, /* mcfqspi.0 */ 57 &__clk_0_23, /* mcfqspi.0 */
58 &__clk_0_24, /* mcfuart.0 */ 58 &__clk_0_24, /* mcfuart.0 */
59 &__clk_0_25, /* mcfuart.1 */ 59 &__clk_0_25, /* mcfuart.1 */
@@ -71,7 +71,7 @@ struct clk *mcf_clks[] = {
71 &__clk_0_40, /* sys.0 */ 71 &__clk_0_40, /* sys.0 */
72 &__clk_0_41, /* gpio.0 */ 72 &__clk_0_41, /* gpio.0 */
73 &__clk_0_42, /* sdram.0 */ 73 &__clk_0_42, /* sdram.0 */
74NULL, 74 NULL,
75}; 75};
76 76
77static struct clk * const enable_clks[] __initconst = { 77static struct clk * const enable_clks[] __initconst = {
@@ -94,7 +94,7 @@ static struct clk * const enable_clks[] __initconst = {
94static struct clk * const disable_clks[] __initconst = { 94static struct clk * const disable_clks[] __initconst = {
95 &__clk_0_12, /* fec.0 */ 95 &__clk_0_12, /* fec.0 */
96 &__clk_0_17, /* edma */ 96 &__clk_0_17, /* edma */
97 &__clk_0_22, /* mcfi2c.0 */ 97 &__clk_0_22, /* imx1-i2c.0 */
98 &__clk_0_23, /* mcfqspi.0 */ 98 &__clk_0_23, /* mcfqspi.0 */
99 &__clk_0_28, /* mcftmr.0 */ 99 &__clk_0_28, /* mcftmr.0 */
100 &__clk_0_29, /* mcftmr.1 */ 100 &__clk_0_29, /* mcftmr.1 */
@@ -133,6 +133,21 @@ static void __init m520x_qspi_init(void)
133 133
134/***************************************************************************/ 134/***************************************************************************/
135 135
136static void __init m520x_i2c_init(void)
137{
138#if IS_ENABLED(CONFIG_I2C_IMX)
139 u8 par;
140
141 /* setup Port FECI2C Pin Assignment Register for I2C */
142 /* set PAR_SCL to SCL and PAR_SDA to SDA */
143 par = readb(MCF_GPIO_PAR_FECI2C);
144 par |= 0x0f;
145 writeb(par, MCF_GPIO_PAR_FECI2C);
146#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
147}
148
149/***************************************************************************/
150
136static void __init m520x_uarts_init(void) 151static void __init m520x_uarts_init(void)
137{ 152{
138 u16 par; 153 u16 par;
@@ -175,6 +190,7 @@ void __init config_BSP(char *commandp, int size)
175 m520x_uarts_init(); 190 m520x_uarts_init();
176 m520x_fec_init(); 191 m520x_fec_init();
177 m520x_qspi_init(); 192 m520x_qspi_init();
193 m520x_i2c_init();
178} 194}
179 195
180/***************************************************************************/ 196/***************************************************************************/
diff --git a/arch/m68k/coldfire/m523x.c b/arch/m68k/coldfire/m523x.c
index a191a467eff2..f7a0fcc5618c 100644
--- a/arch/m68k/coldfire/m523x.c
+++ b/arch/m68k/coldfire/m523x.c
@@ -34,6 +34,7 @@ DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
34DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); 34DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
35DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); 35DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
36DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); 36DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
37DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
37 38
38struct clk *mcf_clks[] = { 39struct clk *mcf_clks[] = {
39 &clk_pll, 40 &clk_pll,
@@ -47,6 +48,7 @@ struct clk *mcf_clks[] = {
47 &clk_mcfuart2, 48 &clk_mcfuart2,
48 &clk_mcfqspi0, 49 &clk_mcfqspi0,
49 &clk_fec0, 50 &clk_fec0,
51 &clk_mcfi2c0,
50 NULL 52 NULL
51}; 53};
52 54
@@ -68,6 +70,21 @@ static void __init m523x_qspi_init(void)
68 70
69/***************************************************************************/ 71/***************************************************************************/
70 72
73static void __init m523x_i2c_init(void)
74{
75#if IS_ENABLED(CONFIG_I2C_IMX)
76 u8 par;
77
78 /* setup Port AS Pin Assignment Register for I2C */
79 /* set PASPA0 to SCL and PASPA1 to SDA */
80 par = readb(MCFGPIO_PAR_FECI2C);
81 par |= 0x0f;
82 writeb(par, MCFGPIO_PAR_FECI2C);
83#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
84}
85
86/***************************************************************************/
87
71static void __init m523x_fec_init(void) 88static void __init m523x_fec_init(void)
72{ 89{
73 /* Set multi-function pins to ethernet use */ 90 /* Set multi-function pins to ethernet use */
@@ -81,6 +98,7 @@ void __init config_BSP(char *commandp, int size)
81 mach_sched_init = hw_timer_init; 98 mach_sched_init = hw_timer_init;
82 m523x_fec_init(); 99 m523x_fec_init();
83 m523x_qspi_init(); 100 m523x_qspi_init();
101 m523x_i2c_init();
84} 102}
85 103
86/***************************************************************************/ 104/***************************************************************************/
diff --git a/arch/m68k/coldfire/m5249.c b/arch/m68k/coldfire/m5249.c
index e48f55adc447..b16cf9b4580c 100644
--- a/arch/m68k/coldfire/m5249.c
+++ b/arch/m68k/coldfire/m5249.c
@@ -27,6 +27,8 @@ DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); 29DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
30DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
31DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
30 32
31struct clk *mcf_clks[] = { 33struct clk *mcf_clks[] = {
32 &clk_pll, 34 &clk_pll,
@@ -36,6 +38,8 @@ struct clk *mcf_clks[] = {
36 &clk_mcfuart0, 38 &clk_mcfuart0,
37 &clk_mcfuart1, 39 &clk_mcfuart1,
38 &clk_mcfqspi0, 40 &clk_mcfqspi0,
41 &clk_mcfi2c0,
42 &clk_mcfi2c1,
39 NULL 43 NULL
40}; 44};
41 45
@@ -85,6 +89,26 @@ static void __init m5249_qspi_init(void)
85 89
86/***************************************************************************/ 90/***************************************************************************/
87 91
92static void __init m5249_i2c_init(void)
93{
94#if IS_ENABLED(CONFIG_I2C_IMX)
95 u32 r;
96
97 /* first I2C controller uses regular irq setup */
98 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
99 MCFSIM_I2CICR);
100 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
101
102 /* second I2C controller is completely different */
103 r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
104 r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
105 r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
106 writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
107#endif /* CONFIG_I2C_IMX */
108}
109
110/***************************************************************************/
111
88#ifdef CONFIG_M5249C3 112#ifdef CONFIG_M5249C3
89 113
90static void __init m5249_smc91x_init(void) 114static void __init m5249_smc91x_init(void)
@@ -111,6 +135,7 @@ void __init config_BSP(char *commandp, int size)
111 m5249_smc91x_init(); 135 m5249_smc91x_init();
112#endif 136#endif
113 m5249_qspi_init(); 137 m5249_qspi_init();
138 m5249_i2c_init();
114} 139}
115 140
116/***************************************************************************/ 141/***************************************************************************/
diff --git a/arch/m68k/coldfire/m525x.c b/arch/m68k/coldfire/m525x.c
index 3d8583e2187c..110e2cd34e62 100644
--- a/arch/m68k/coldfire/m525x.c
+++ b/arch/m68k/coldfire/m525x.c
@@ -27,6 +27,8 @@ DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); 29DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
30DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
31DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
30 32
31struct clk *mcf_clks[] = { 33struct clk *mcf_clks[] = {
32 &clk_pll, 34 &clk_pll,
@@ -36,6 +38,8 @@ struct clk *mcf_clks[] = {
36 &clk_mcfuart0, 38 &clk_mcfuart0,
37 &clk_mcfuart1, 39 &clk_mcfuart1,
38 &clk_mcfqspi0, 40 &clk_mcfqspi0,
41 &clk_mcfi2c0,
42 &clk_mcfi2c1,
39 NULL 43 NULL
40}; 44};
41 45
@@ -59,12 +63,12 @@ static void __init m525x_qspi_init(void)
59 63
60static void __init m525x_i2c_init(void) 64static void __init m525x_i2c_init(void)
61{ 65{
62#if IS_ENABLED(CONFIG_I2C_COLDFIRE) 66#if IS_ENABLED(CONFIG_I2C_IMX)
63 u32 r; 67 u32 r;
64 68
65 /* first I2C controller uses regular irq setup */ 69 /* first I2C controller uses regular irq setup */
66 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, 70 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
67 MCFSIM_I2CICR); 71 MCFSIM_I2CICR);
68 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C); 72 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
69 73
70 /* second I2C controller is completely different */ 74 /* second I2C controller is completely different */
@@ -72,7 +76,7 @@ static void __init m525x_i2c_init(void)
72 r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1); 76 r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
73 r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1); 77 r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
74 writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1)); 78 writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
75#endif /* IS_ENABLED(CONFIG_I2C_COLDFIRE) */ 79#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
76} 80}
77 81
78/***************************************************************************/ 82/***************************************************************************/
diff --git a/arch/m68k/coldfire/m527x.c b/arch/m68k/coldfire/m527x.c
index c0b3e28f91df..b10b436b5a31 100644
--- a/arch/m68k/coldfire/m527x.c
+++ b/arch/m68k/coldfire/m527x.c
@@ -36,6 +36,7 @@ DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
36DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); 36DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
37DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); 37DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
38DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK); 38DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
39DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
39 40
40struct clk *mcf_clks[] = { 41struct clk *mcf_clks[] = {
41 &clk_pll, 42 &clk_pll,
@@ -50,6 +51,7 @@ struct clk *mcf_clks[] = {
50 &clk_mcfqspi0, 51 &clk_mcfqspi0,
51 &clk_fec0, 52 &clk_fec0,
52 &clk_fec1, 53 &clk_fec1,
54 &clk_mcfi2c0,
53 NULL 55 NULL
54}; 56};
55 57
@@ -76,6 +78,31 @@ static void __init m527x_qspi_init(void)
76 78
77/***************************************************************************/ 79/***************************************************************************/
78 80
81static void __init m527x_i2c_init(void)
82{
83#if IS_ENABLED(CONFIG_I2C_IMX)
84#if defined(CONFIG_M5271)
85 u8 par;
86
87 /* setup Port FECI2C Pin Assignment Register for I2C */
88 /* set PAR_SCL to SCL and PAR_SDA to SDA */
89 par = readb(MCFGPIO_PAR_FECI2C);
90 par |= 0x0f;
91 writeb(par, MCFGPIO_PAR_FECI2C);
92#elif defined(CONFIG_M5275)
93 u16 par;
94
95 /* setup Port FECI2C Pin Assignment Register for I2C */
96 /* set PAR_SCL to SCL and PAR_SDA to SDA */
97 par = readw(MCFGPIO_PAR_FECI2C);
98 par |= 0x0f;
99 writew(par, MCFGPIO_PAR_FECI2C);
100#endif
101#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
102}
103
104/***************************************************************************/
105
79static void __init m527x_uarts_init(void) 106static void __init m527x_uarts_init(void)
80{ 107{
81 u16 sepmask; 108 u16 sepmask;
@@ -122,6 +149,7 @@ void __init config_BSP(char *commandp, int size)
122 m527x_uarts_init(); 149 m527x_uarts_init();
123 m527x_fec_init(); 150 m527x_fec_init();
124 m527x_qspi_init(); 151 m527x_qspi_init();
152 m527x_i2c_init();
125} 153}
126 154
127/***************************************************************************/ 155/***************************************************************************/
diff --git a/arch/m68k/coldfire/m528x.c b/arch/m68k/coldfire/m528x.c
index 12f9e370d8dd..ea76998d5ab9 100644
--- a/arch/m68k/coldfire/m528x.c
+++ b/arch/m68k/coldfire/m528x.c
@@ -36,6 +36,7 @@ DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
36DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); 36DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
37DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK); 37DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
38DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK); 38DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
39DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
39 40
40struct clk *mcf_clks[] = { 41struct clk *mcf_clks[] = {
41 &clk_pll, 42 &clk_pll,
@@ -49,6 +50,7 @@ struct clk *mcf_clks[] = {
49 &clk_mcfuart2, 50 &clk_mcfuart2,
50 &clk_mcfqspi0, 51 &clk_mcfqspi0,
51 &clk_fec0, 52 &clk_fec0,
53 &clk_mcfi2c0,
52 NULL 54 NULL
53}; 55};
54 56
@@ -64,6 +66,21 @@ static void __init m528x_qspi_init(void)
64 66
65/***************************************************************************/ 67/***************************************************************************/
66 68
69static void __init m528x_i2c_init(void)
70{
71#if IS_ENABLED(CONFIG_I2C_IMX)
72 u16 paspar;
73
74 /* setup Port AS Pin Assignment Register for I2C */
75 /* set PASPA0 to SCL and PASPA1 to SDA */
76 paspar = readw(MCFGPIO_PASPAR);
77 paspar |= 0xF;
78 writew(paspar, MCFGPIO_PASPAR);
79#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
80}
81
82/***************************************************************************/
83
67static void __init m528x_uarts_init(void) 84static void __init m528x_uarts_init(void)
68{ 85{
69 u8 port; 86 u8 port;
@@ -127,6 +144,7 @@ void __init config_BSP(char *commandp, int size)
127 m528x_uarts_init(); 144 m528x_uarts_init();
128 m528x_fec_init(); 145 m528x_fec_init();
129 m528x_qspi_init(); 146 m528x_qspi_init();
147 m528x_i2c_init();
130} 148}
131 149
132/***************************************************************************/ 150/***************************************************************************/
diff --git a/arch/m68k/coldfire/m5307.c b/arch/m68k/coldfire/m5307.c
index 2da1d146e344..cc5e8a50a423 100644
--- a/arch/m68k/coldfire/m5307.c
+++ b/arch/m68k/coldfire/m5307.c
@@ -35,6 +35,7 @@ DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
35DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); 35DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
36DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 36DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
37DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 37DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
38DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
38 39
39struct clk *mcf_clks[] = { 40struct clk *mcf_clks[] = {
40 &clk_pll, 41 &clk_pll,
@@ -43,11 +44,23 @@ struct clk *mcf_clks[] = {
43 &clk_mcftmr1, 44 &clk_mcftmr1,
44 &clk_mcfuart0, 45 &clk_mcfuart0,
45 &clk_mcfuart1, 46 &clk_mcfuart1,
47 &clk_mcfi2c0,
46 NULL 48 NULL
47}; 49};
48 50
49/***************************************************************************/ 51/***************************************************************************/
50 52
53static void __init m5307_i2c_init(void)
54{
55#if IS_ENABLED(CONFIG_I2C_IMX)
56 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
57 MCFSIM_I2CICR);
58 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
59#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
60}
61
62/***************************************************************************/
63
51void __init config_BSP(char *commandp, int size) 64void __init config_BSP(char *commandp, int size)
52{ 65{
53#if defined(CONFIG_NETtel) || \ 66#if defined(CONFIG_NETtel) || \
@@ -73,6 +86,7 @@ void __init config_BSP(char *commandp, int size)
73 */ 86 */
74 wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK); 87 wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
75#endif 88#endif
89 m5307_i2c_init();
76} 90}
77 91
78/***************************************************************************/ 92/***************************************************************************/
diff --git a/arch/m68k/coldfire/m53xx.c b/arch/m68k/coldfire/m53xx.c
index 2502f63960bc..cf1917934b8a 100644
--- a/arch/m68k/coldfire/m53xx.c
+++ b/arch/m68k/coldfire/m53xx.c
@@ -38,7 +38,7 @@ DEFINE_CLK(0, "edma", 17, MCF_CLK);
38DEFINE_CLK(0, "intc.0", 18, MCF_CLK); 38DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
39DEFINE_CLK(0, "intc.1", 19, MCF_CLK); 39DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
40DEFINE_CLK(0, "iack.0", 21, MCF_CLK); 40DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
41DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK); 41DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
42DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK); 42DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
43DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK); 43DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
44DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK); 44DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
@@ -77,7 +77,7 @@ struct clk *mcf_clks[] = {
77 &__clk_0_18, /* intc.0 */ 77 &__clk_0_18, /* intc.0 */
78 &__clk_0_19, /* intc.1 */ 78 &__clk_0_19, /* intc.1 */
79 &__clk_0_21, /* iack.0 */ 79 &__clk_0_21, /* iack.0 */
80 &__clk_0_22, /* mcfi2c.0 */ 80 &__clk_0_22, /* imx1-i2c.0 */
81 &__clk_0_23, /* mcfqspi.0 */ 81 &__clk_0_23, /* mcfqspi.0 */
82 &__clk_0_24, /* mcfuart.0 */ 82 &__clk_0_24, /* mcfuart.0 */
83 &__clk_0_25, /* mcfuart.1 */ 83 &__clk_0_25, /* mcfuart.1 */
@@ -133,7 +133,7 @@ static struct clk * const disable_clks[] __initconst = {
133 &__clk_0_8, /* mcfcan.0 */ 133 &__clk_0_8, /* mcfcan.0 */
134 &__clk_0_12, /* fec.0 */ 134 &__clk_0_12, /* fec.0 */
135 &__clk_0_17, /* edma */ 135 &__clk_0_17, /* edma */
136 &__clk_0_22, /* mcfi2c.0 */ 136 &__clk_0_22, /* imx1-i2c.0 */
137 &__clk_0_23, /* mcfqspi.0 */ 137 &__clk_0_23, /* mcfqspi.0 */
138 &__clk_0_30, /* mcftmr.2 */ 138 &__clk_0_30, /* mcftmr.2 */
139 &__clk_0_31, /* mcftmr.3 */ 139 &__clk_0_31, /* mcftmr.3 */
@@ -176,6 +176,19 @@ static void __init m53xx_qspi_init(void)
176 176
177/***************************************************************************/ 177/***************************************************************************/
178 178
179static void __init m53xx_i2c_init(void)
180{
181#if IS_ENABLED(CONFIG_I2C_IMX)
182 /* setup Port AS Pin Assignment Register for I2C */
183 /* set PASPA0 to SCL and PASPA1 to SDA */
184 u8 r = readb(MCFGPIO_PAR_FECI2C);
185 r |= 0x0f;
186 writeb(r, MCFGPIO_PAR_FECI2C);
187#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
188}
189
190/***************************************************************************/
191
179static void __init m53xx_uarts_init(void) 192static void __init m53xx_uarts_init(void)
180{ 193{
181 /* UART GPIO initialization */ 194 /* UART GPIO initialization */
@@ -218,6 +231,7 @@ void __init config_BSP(char *commandp, int size)
218 m53xx_uarts_init(); 231 m53xx_uarts_init();
219 m53xx_fec_init(); 232 m53xx_fec_init();
220 m53xx_qspi_init(); 233 m53xx_qspi_init();
234 m53xx_i2c_init();
221 235
222#ifdef CONFIG_BDM_DISABLE 236#ifdef CONFIG_BDM_DISABLE
223 /* 237 /*
diff --git a/arch/m68k/coldfire/m5407.c b/arch/m68k/coldfire/m5407.c
index 738eba6be40e..38863ddbeab0 100644
--- a/arch/m68k/coldfire/m5407.c
+++ b/arch/m68k/coldfire/m5407.c
@@ -26,6 +26,7 @@ DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK); 26DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK); 27DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 28DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
29DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
29 30
30struct clk *mcf_clks[] = { 31struct clk *mcf_clks[] = {
31 &clk_pll, 32 &clk_pll,
@@ -34,11 +35,23 @@ struct clk *mcf_clks[] = {
34 &clk_mcftmr1, 35 &clk_mcftmr1,
35 &clk_mcfuart0, 36 &clk_mcfuart0,
36 &clk_mcfuart1, 37 &clk_mcfuart1,
38 &clk_mcfi2c0,
37 NULL 39 NULL
38}; 40};
39 41
40/***************************************************************************/ 42/***************************************************************************/
41 43
44static void __init m5407_i2c_init(void)
45{
46#if IS_ENABLED(CONFIG_I2C_IMX)
47 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
48 MCFSIM_I2CICR);
49 mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
50#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
51}
52
53/***************************************************************************/
54
42void __init config_BSP(char *commandp, int size) 55void __init config_BSP(char *commandp, int size)
43{ 56{
44 mach_sched_init = hw_timer_init; 57 mach_sched_init = hw_timer_init;
@@ -48,6 +61,7 @@ void __init config_BSP(char *commandp, int size)
48 mcf_mapirq2imr(27, MCFINTC_EINT3); 61 mcf_mapirq2imr(27, MCFINTC_EINT3);
49 mcf_mapirq2imr(29, MCFINTC_EINT5); 62 mcf_mapirq2imr(29, MCFINTC_EINT5);
50 mcf_mapirq2imr(31, MCFINTC_EINT7); 63 mcf_mapirq2imr(31, MCFINTC_EINT7);
64 m5407_i2c_init();
51} 65}
52 66
53/***************************************************************************/ 67/***************************************************************************/
diff --git a/arch/m68k/coldfire/m5441x.c b/arch/m68k/coldfire/m5441x.c
index 98a13cce93d8..dc589b039b62 100644
--- a/arch/m68k/coldfire/m5441x.c
+++ b/arch/m68k/coldfire/m5441x.c
@@ -19,13 +19,13 @@
19DEFINE_CLK(0, "flexbus", 2, MCF_CLK); 19DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
20DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK); 20DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
21DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK); 21DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK);
22DEFINE_CLK(0, "mcfi2c.1", 14, MCF_CLK); 22DEFINE_CLK(0, "imx1-i2c.1", 14, MCF_CLK);
23DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK); 23DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
24DEFINE_CLK(0, "edma", 17, MCF_CLK); 24DEFINE_CLK(0, "edma", 17, MCF_CLK);
25DEFINE_CLK(0, "intc.0", 18, MCF_CLK); 25DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
26DEFINE_CLK(0, "intc.1", 19, MCF_CLK); 26DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
27DEFINE_CLK(0, "intc.2", 20, MCF_CLK); 27DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
28DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK); 28DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
29DEFINE_CLK(0, "mcfdspi.0", 23, MCF_CLK); 29DEFINE_CLK(0, "mcfdspi.0", 23, MCF_CLK);
30DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK); 30DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
31DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK); 31DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
@@ -59,10 +59,10 @@ DEFINE_CLK(0, "switch.1", 56, MCF_CLK);
59DEFINE_CLK(0, "nand.0", 63, MCF_CLK); 59DEFINE_CLK(0, "nand.0", 63, MCF_CLK);
60 60
61DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK); 61DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK);
62DEFINE_CLK(1, "mcfi2c.2", 4, MCF_CLK); 62DEFINE_CLK(1, "imx1-i2c.2", 4, MCF_CLK);
63DEFINE_CLK(1, "mcfi2c.3", 5, MCF_CLK); 63DEFINE_CLK(1, "imx1-i2c.3", 5, MCF_CLK);
64DEFINE_CLK(1, "mcfi2c.4", 6, MCF_CLK); 64DEFINE_CLK(1, "imx1-i2c.4", 6, MCF_CLK);
65DEFINE_CLK(1, "mcfi2c.5", 7, MCF_CLK); 65DEFINE_CLK(1, "imx1-i2c.5", 7, MCF_CLK);
66DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK); 66DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK);
67DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK); 67DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK);
68DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK); 68DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK);
diff --git a/arch/m68k/coldfire/m54xx.c b/arch/m68k/coldfire/m54xx.c
index 386df3b68cdf..c552851ec617 100644
--- a/arch/m68k/coldfire/m54xx.c
+++ b/arch/m68k/coldfire/m54xx.c
@@ -37,6 +37,7 @@ DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
37DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK); 37DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
38DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK); 38DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
39DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK); 39DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
40DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
40 41
41struct clk *mcf_clks[] = { 42struct clk *mcf_clks[] = {
42 &clk_pll, 43 &clk_pll,
@@ -47,6 +48,7 @@ struct clk *mcf_clks[] = {
47 &clk_mcfuart1, 48 &clk_mcfuart1,
48 &clk_mcfuart2, 49 &clk_mcfuart2,
49 &clk_mcfuart3, 50 &clk_mcfuart3,
51 &clk_mcfi2c0,
50 NULL 52 NULL
51}; 53};
52 54
@@ -65,6 +67,20 @@ static void __init m54xx_uarts_init(void)
65 67
66/***************************************************************************/ 68/***************************************************************************/
67 69
70static void __init m54xx_i2c_init(void)
71{
72#if IS_ENABLED(CONFIG_I2C_IMX)
73 u32 r;
74
75 /* set the fec/i2c/irq pin assignment register for i2c */
76 r = readl(MCF_PAR_FECI2CIRQ);
77 r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
78 writel(r, MCF_PAR_FECI2CIRQ);
79#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
80}
81
82/***************************************************************************/
83
68static void mcf54xx_reset(void) 84static void mcf54xx_reset(void)
69{ 85{
70 /* disable interrupts and enable the watchdog */ 86 /* disable interrupts and enable the watchdog */
@@ -86,6 +102,7 @@ void __init config_BSP(char *commandp, int size)
86 mach_reset = mcf54xx_reset; 102 mach_reset = mcf54xx_reset;
87 mach_sched_init = hw_timer_init; 103 mach_sched_init = hw_timer_init;
88 m54xx_uarts_init(); 104 m54xx_uarts_init();
105 m54xx_i2c_init();
89} 106}
90 107
91/***************************************************************************/ 108/***************************************************************************/
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 4cf864f5ea7a..0ddf3efbcae9 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -110,6 +110,7 @@
110/* 110/*
111 * Define system peripheral IRQ usage. 111 * Define system peripheral IRQ usage.
112 */ 112 */
113#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
113#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 114#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
114#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 115#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
115#define MCF_IRQ_UART0 73 /* UART0 */ 116#define MCF_IRQ_UART0 73 /* UART0 */
@@ -138,6 +139,7 @@
138#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */ 139#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
139#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */ 140#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
140#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */ 141#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
142#define MCFSIM_I2CICR MCFSIM_ICR11 /* I2C ICR */
141#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */ 143#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
142#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */ 144#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
143#ifdef CONFIG_M5206e 145#ifdef CONFIG_M5206e
@@ -145,5 +147,11 @@
145#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */ 147#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
146#endif 148#endif
147 149
150/*
151 * I2C Controller
152*/
153#define MCFI2C_BASE0 (MCF_MBAR + 0x1e0)
154#define MCFI2C_SIZE0 0x40
155
148/****************************************************************************/ 156/****************************************************************************/
149#endif /* m5206sim_h */ 157#endif /* m5206sim_h */
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index db3f8ee4a6c6..6d50cefa76c3 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -50,6 +50,7 @@
50#define MCFINT_UART0 26 /* Interrupt number for UART0 */ 50#define MCFINT_UART0 26 /* Interrupt number for UART0 */
51#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 51#define MCFINT_UART1 27 /* Interrupt number for UART1 */
52#define MCFINT_UART2 28 /* Interrupt number for UART2 */ 52#define MCFINT_UART2 28 /* Interrupt number for UART2 */
53#define MCFINT_I2C0 30 /* Interrupt number for I2C */
53#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 54#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
54#define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */ 55#define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */
55#define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */ 56#define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */
@@ -67,6 +68,7 @@
67#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 68#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
68#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 69#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
69 70
71#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
70/* 72/*
71 * SDRAM configuration registers. 73 * SDRAM configuration registers.
72 */ 74 */
@@ -200,5 +202,11 @@
200#define MCFPM_PPMLR0 0xfc040034 202#define MCFPM_PPMLR0 0xfc040034
201#define MCFPM_LPCR 0xfc0a0007 203#define MCFPM_LPCR 0xfc0a0007
202 204
205/*
206 * I2C module.
207 */
208#define MCFI2C_BASE0 0xFC058000
209#define MCFI2C_SIZE0 0x40
210
203/****************************************************************************/ 211/****************************************************************************/
204#endif /* m520xsim_h */ 212#endif /* m520xsim_h */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 5e06b4eb57f3..d43f6ab1edc9 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -37,7 +37,8 @@
37#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 37#define MCFINT_UART0 13 /* Interrupt number for UART0 */
38#define MCFINT_UART1 14 /* Interrupt number for UART1 */ 38#define MCFINT_UART1 14 /* Interrupt number for UART1 */
39#define MCFINT_UART2 15 /* Interrupt number for UART2 */ 39#define MCFINT_UART2 15 /* Interrupt number for UART2 */
40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 40#define MCFINT_I2C0 17 /* Interrupt number for I2C */
41#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
41#define MCFINT_FECRX0 23 /* Interrupt number for FEC */ 42#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
42#define MCFINT_FECTX0 27 /* Interrupt number for FEC */ 43#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
43#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */ 44#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
@@ -53,6 +54,7 @@
53 54
54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 55#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
55#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 56#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
57#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
56 58
57/* 59/*
58 * SDRAM configuration registers. 60 * SDRAM configuration registers.
@@ -208,5 +210,11 @@
208#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) 210#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
209#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) 211#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
210 212
213/*
214 * I2C module.
215 */
216#define MCFI2C_BASE0 (MCF_IPSBAR + 0x300)
217#define MCFI2C_SIZE0 0x40
218
211/****************************************************************************/ 219/****************************************************************************/
212#endif /* m523xsim_h */ 220#endif /* m523xsim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 2c648a043f24..35f6fbc89b92 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -37,6 +37,7 @@
37#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 37#define MCFINT_UART0 13 /* Interrupt number for UART0 */
38#define MCFINT_UART1 14 /* Interrupt number for UART1 */ 38#define MCFINT_UART1 14 /* Interrupt number for UART1 */
39#define MCFINT_UART2 15 /* Interrupt number for UART2 */ 39#define MCFINT_UART2 15 /* Interrupt number for UART2 */
40#define MCFINT_I2C0 17 /* Interrupt number for I2C */
40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 41#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
41#define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */ 42#define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */
42#define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */ 43#define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */
@@ -61,6 +62,7 @@
61 62
62#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 63#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
63#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 64#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
65#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
64 66
65/* 67/*
66 * SDRAM configuration registers. 68 * SDRAM configuration registers.
@@ -353,5 +355,11 @@
353#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 355#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
354#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 356#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
355 357
358/*
359 * I2C module.
360 */
361#define MCFI2C_BASE0 (MCF_IPSBAR + 0x300)
362#define MCFI2C_SIZE0 0x40
363
356/****************************************************************************/ 364/****************************************************************************/
357#endif /* m527xsim_h */ 365#endif /* m527xsim_h */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index cf68ca0ac3a5..67f6182d10a4 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -37,6 +37,7 @@
37#define MCFINT_UART0 13 /* Interrupt number for UART0 */ 37#define MCFINT_UART0 13 /* Interrupt number for UART0 */
38#define MCFINT_UART1 14 /* Interrupt number for UART1 */ 38#define MCFINT_UART1 14 /* Interrupt number for UART1 */
39#define MCFINT_UART2 15 /* Interrupt number for UART2 */ 39#define MCFINT_UART2 15 /* Interrupt number for UART2 */
40#define MCFINT_I2C0 17 /* Interrupt number for I2C */
40#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 41#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
41#define MCFINT_FECRX0 23 /* Interrupt number for FEC */ 42#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
42#define MCFINT_FECTX0 27 /* Interrupt number for FEC */ 43#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
@@ -53,6 +54,8 @@
53 54
54#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 55#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
55#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 56#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
57#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
58
56/* 59/*
57 * SDRAM configuration registers. 60 * SDRAM configuration registers.
58 */ 61 */
@@ -242,5 +245,11 @@
242#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 245#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
243#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 246#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
244 247
248/*
249 * I2C module
250 */
251#define MCFI2C_BASE0 (MCF_IPSBAR + 0x300)
252#define MCFI2C_SIZE0 0x40
253
245/****************************************************************************/ 254/****************************************************************************/
246#endif /* m528xsim_h */ 255#endif /* m528xsim_h */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 5d0bb7ec31f8..d2595e04eb1d 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -148,6 +148,7 @@
148#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 148#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
149#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 149#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
150#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 150#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
151#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
151#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 152#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
152#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 153#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
153#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 154#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
@@ -155,7 +156,6 @@
155#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 156#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
156#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 157#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
157 158
158
159/* 159/*
160 * Some symbol defines for the Parallel Port Pin Assignment Register 160 * Some symbol defines for the Parallel Port Pin Assignment Register
161 */ 161 */
@@ -174,10 +174,17 @@
174/* 174/*
175 * Define system peripheral IRQ usage. 175 * Define system peripheral IRQ usage.
176 */ 176 */
177#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
177#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 178#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
178#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 179#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
179#define MCF_IRQ_UART0 73 /* UART0 */ 180#define MCF_IRQ_UART0 73 /* UART0 */
180#define MCF_IRQ_UART1 74 /* UART1 */ 181#define MCF_IRQ_UART1 74 /* UART1 */
181 182
183/*
184 * I2C module
185 */
186#define MCFI2C_BASE0 (MCF_MBAR + 0x280)
187#define MCFI2C_SIZE0 0x40
188
182/****************************************************************************/ 189/****************************************************************************/
183#endif /* m5307sim_h */ 190#endif /* m5307sim_h */
diff --git a/arch/m68k/include/asm/m53xxsim.h b/arch/m68k/include/asm/m53xxsim.h
index faa1a2133bfd..53329ae4d3e3 100644
--- a/arch/m68k/include/asm/m53xxsim.h
+++ b/arch/m68k/include/asm/m53xxsim.h
@@ -19,6 +19,7 @@
19#define MCFINT_UART0 26 /* Interrupt number for UART0 */ 19#define MCFINT_UART0 26 /* Interrupt number for UART0 */
20#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 20#define MCFINT_UART1 27 /* Interrupt number for UART1 */
21#define MCFINT_UART2 28 /* Interrupt number for UART2 */ 21#define MCFINT_UART2 28 /* Interrupt number for UART2 */
22#define MCFINT_I2C0 30 /* Interrupt number for I2C */
22#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 23#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
23#define MCFINT_FECRX0 36 /* Interrupt number for FEC */ 24#define MCFINT_FECRX0 36 /* Interrupt number for FEC */
24#define MCFINT_FECTX0 40 /* Interrupt number for FEC */ 25#define MCFINT_FECTX0 40 /* Interrupt number for FEC */
@@ -32,6 +33,7 @@
32#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 33#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
33#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 34#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
34 35
36#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
35#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 37#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
36 38
37#define MCF_WTM_WCR 0xFC098000 39#define MCF_WTM_WCR 0xFC098000
@@ -1237,5 +1239,11 @@
1237#define MCFEPORT_EPPDR (0xFC094005) 1239#define MCFEPORT_EPPDR (0xFC094005)
1238#define MCFEPORT_EPFR (0xFC094006) 1240#define MCFEPORT_EPFR (0xFC094006)
1239 1241
1242/*
1243 * I2C Module
1244 */
1245#define MCFI2C_BASE0 (0xFc058000)
1246#define MCFI2C_SIZE0 0x40
1247
1240/********************************************************************/ 1248/********************************************************************/
1241#endif /* m53xxsim_h */ 1249#endif /* m53xxsim_h */
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index a7550bc5cd1e..ab40c16ba989 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -112,6 +112,7 @@
112#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 112#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
113#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 113#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
114#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 114#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
115#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
115#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 116#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
116#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 117#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
117#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 118#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
@@ -137,10 +138,17 @@
137/* 138/*
138 * Define system peripheral IRQ usage. 139 * Define system peripheral IRQ usage.
139 */ 140 */
141#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
140#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 142#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
141#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 143#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
142#define MCF_IRQ_UART0 73 /* UART0 */ 144#define MCF_IRQ_UART0 73 /* UART0 */
143#define MCF_IRQ_UART1 74 /* UART1 */ 145#define MCF_IRQ_UART1 74 /* UART1 */
144 146
147/*
148 * I2C module
149 */
150#define MCFI2C_BASE0 (MCF_MBAR + 0x280)
151#define MCFI2C_SIZE0 0x40
152
145/****************************************************************************/ 153/****************************************************************************/
146#endif /* m5407sim_h */ 154#endif /* m5407sim_h */
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index 73d937ff36eb..7758d0a1a84d 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -45,6 +45,7 @@
45 */ 45 */
46#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */ 46#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */
47#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */ 47#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */
48#define MCF_IRQ_I2C0 (MCFINT_VECBASE + 40)
48#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35) 49#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
49#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34) 50#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
50#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33) 51#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
@@ -107,4 +108,14 @@
107#define MCF_PAR_PSC_RTS_RTS (0x30) 108#define MCF_PAR_PSC_RTS_RTS (0x30)
108#define MCF_PAR_PSC_CANRX (0x40) 109#define MCF_PAR_PSC_CANRX (0x40)
109 110
111#define MCF_PAR_FECI2CIRQ (MCF_MBAR + 0x00000a44) /* FEC/I2C/IRQ */
112#define MCF_PAR_FECI2CIRQ_SDA (1 << 3)
113#define MCF_PAR_FECI2CIRQ_SCL (1 << 2)
114
115/*
116 * I2C module.
117 */
118#define MCFI2C_BASE0 (MCF_MBAR + 0x8f00)
119#define MCFI2C_SIZE0 0x40
120
110#endif /* m54xxsim_h */ 121#endif /* m54xxsim_h */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-30 23:26:17 -0400