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-rw-r--r--drivers/irqchip/irq-armada-370-xp.c18
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index b455c876974e..ea57fba263cf 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -77,6 +77,16 @@ static DEFINE_MUTEX(msi_used_lock);
77static phys_addr_t msi_doorbell_addr; 77static phys_addr_t msi_doorbell_addr;
78#endif 78#endif
79 79
80static inline bool is_percpu_irq(irq_hw_number_t irq)
81{
82 switch (irq) {
83 case ARMADA_370_XP_TIMER0_PER_CPU_IRQ:
84 return true;
85 default:
86 return false;
87 }
88}
89
80/* 90/*
81 * In SMP mode: 91 * In SMP mode:
82 * For shared global interrupts, mask/unmask global enable bit 92 * For shared global interrupts, mask/unmask global enable bit
@@ -86,7 +96,7 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
86{ 96{
87 irq_hw_number_t hwirq = irqd_to_hwirq(d); 97 irq_hw_number_t hwirq = irqd_to_hwirq(d);
88 98
89 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) 99 if (!is_percpu_irq(hwirq))
90 writel(hwirq, main_int_base + 100 writel(hwirq, main_int_base +
91 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); 101 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
92 else 102 else
@@ -98,7 +108,7 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
98{ 108{
99 irq_hw_number_t hwirq = irqd_to_hwirq(d); 109 irq_hw_number_t hwirq = irqd_to_hwirq(d);
100 110
101 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) 111 if (!is_percpu_irq(hwirq))
102 writel(hwirq, main_int_base + 112 writel(hwirq, main_int_base +
103 ARMADA_370_XP_INT_SET_ENABLE_OFFS); 113 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
104 else 114 else
@@ -287,14 +297,14 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
287 unsigned int virq, irq_hw_number_t hw) 297 unsigned int virq, irq_hw_number_t hw)
288{ 298{
289 armada_370_xp_irq_mask(irq_get_irq_data(virq)); 299 armada_370_xp_irq_mask(irq_get_irq_data(virq));
290 if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) 300 if (!is_percpu_irq(hw))
291 writel(hw, per_cpu_int_base + 301 writel(hw, per_cpu_int_base +
292 ARMADA_370_XP_INT_CLEAR_MASK_OFFS); 302 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
293 else 303 else
294 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); 304 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
295 irq_set_status_flags(virq, IRQ_LEVEL); 305 irq_set_status_flags(virq, IRQ_LEVEL);
296 306
297 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) { 307 if (is_percpu_irq(hw)) {
298 irq_set_percpu_devid(virq); 308 irq_set_percpu_devid(virq);
299 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, 309 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
300 handle_percpu_devid_irq); 310 handle_percpu_devid_irq);