188 files changed, 3789 insertions, 4242 deletions

diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
new file mode 100644
index 000000000000..f4f7451e5e8a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/intel-ixp4xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel IXP4xx Device Tree Bindings
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - linksys,nslu2
+          - const: intel,ixp42x
+      - items:
+          - enum:
+              - gateworks,gw2358
+          - const: intel,ixp43x
diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt
index 85a23f551f02..233eb8294204 100644
--- a/Documentation/devicetree/bindings/bus/ti-sysc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt
@@ -94,6 +94,8 @@ Optional properties:
 
 - ti,no-idle-on-init    interconnect target module should not be idled at init
 
+- ti,no-idle            interconnect target module should not be idled
+
 Example: Single instance of MUSB controller on omap4 using interconnect ranges
 using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
 
@@ -131,6 +133,6 @@ using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
                 };
         };
 
-Note that other SoCs, such as am335x can have multipe child devices. On am335x
+Note that other SoCs, such as am335x can have multiple child devices. On am335x
 there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA
-instance as children of a single interconnet target module.
+instance as children of a single interconnect target module.
diff --git a/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
new file mode 100644
index 000000000000..8cb136c376fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Linaro Ltd.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/firmware/intel-ixp4xx-network-processing-engine.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel IXP4xx Network Processing Engine
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+  On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
+  processor that can load a firmware to perform offloading of networking
+  and crypto tasks. It also manages the MDIO bus to the ethernet PHYs
+  on the IXP4xx platform. All IXP4xx platforms have three NPEs at
+  consecutive memory locations. They are all included in the same
+  device node since they are not independent of each other.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: intel,ixp4xx-network-processing-engine
+
+  reg:
+    minItems: 3
+    maxItems: 3
+    items:
+      - description: NPE0 register range
+      - description: NPE1 register range
+      - description: NPE2 register range
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    npe@c8006000 {
+         compatible = "intel,ixp4xx-network-processing-engine";
+         reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
new file mode 100644
index 000000000000..bae10e261fa9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2018 Linaro Ltd.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt/intel-ixp4xx-interrupt.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel IXP4xx XScale Networking Processors Interrupt Controller
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+  This interrupt controller is found in the Intel IXP4xx processors.
+  Some processors have 32 interrupts, some have up to 64 interrupts.
+  The exact number of interrupts is determined from the compatible
+  string.
+
+  The distinct IXP4xx families with different interrupt controller
+  variations are IXP42x, IXP43x, IXP45x and IXP46x. Those four
+  families were the only ones to reach the developer and consumer
+  market.
+
+properties:
+  compatible:
+    items:
+      - enum:
+        - intel,ixp42x-interrupt
+        - intel,ixp43x-interrupt
+        - intel,ixp45x-interrupt
+        - intel,ixp46x-interrupt
+
+  reg:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - '#interrupt-cells'
+
+examples:
+  - |
+    intcon: interrupt-controller@c8003000 {
+        compatible = "intel,ixp43x-interrupt";
+        reg = <0xc8003000 0x100>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+    };
diff --git a/Documentation/devicetree/bindings/misc/intel,ixp4xx-queue-manager.yaml b/Documentation/devicetree/bindings/misc/intel,ixp4xx-queue-manager.yaml
new file mode 100644
index 000000000000..d2313b1d9405
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,ixp4xx-queue-manager.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Linaro Ltd.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/intel-ixp4xx-ahb-queue-manager.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel IXP4xx AHB Queue Manager
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+  The IXP4xx AHB Queue Manager maintains queues as circular buffers in
+  an 8KB embedded SRAM along with hardware pointers. It is used by both
+  the XScale processor and the NPEs (Network Processing Units) in the
+  IXP4xx for accelerating queues, especially for networking. Clients pick
+  queues from the queue manager with foo-queue = <&qmgr N> where the
+  &qmgr is a phandle to the queue manager and N is the queue resource
+  number. The queue resources available and their specific purpose
+  on a certain IXP4xx system will vary.
+
+properties:
+  compatible:
+    items:
+      - const: intel,ixp4xx-ahb-queue-manager
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Interrupt for queues 0-31
+      - description: Interrupt for queues 32-63
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    qmgr: queue-manager@60000000 {
+         compatible = "intel,ixp4xx-ahb-queue-manager";
+         reg = <0x60000000 0x4000>;
+         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
+    };
diff --git a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
new file mode 100644
index 000000000000..a36a0746c056
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2018 Linaro Ltd.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/timer/intel-ixp4xx-timer.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel IXP4xx XScale Networking Processors Timers
+
+maintainers:
+  - Linus Walleij <linus.walleij@linaro.org>
+
+description: This timer is found in the Intel IXP4xx processors.
+
+properties:
+  compatible:
+    items:
+      - const: intel,ixp4xx-timer
+
+  reg:
+    description: Should contain registers location and length
+
+  interrupts:
+    minItems: 1
+    maxItems: 2
+    items:
+      - description: Timer 1 interrupt
+      - description: Timer 2 interrupt
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    timer@c8005000 {
+        compatible = "intel,ixp4xx-timer";
+        reg = <0xc8005000 0x100>;
+        interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 59efb8bd33e0..5254b352623b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1733,11 +1733,21 @@ L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
 
 ARM/INTEL IXP4XX ARM ARCHITECTURE
+M:      Linus Walleij <linusw@kernel.org>
 M:      Imre Kaloz <kaloz@openwrt.org>
 M:      Krzysztof Halasa <khalasa@piap.pl>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
+F:      Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml
+F:      Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt
+F:      Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
+F:      Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
 F:      arch/arm/mach-ixp4xx/
+F:      drivers/clocksource/timer-ixp4xx.c
+F:      drivers/gpio/gpio-ixp4xx.c
+F:      drivers/irqchip/irq-ixp4xx.c
+F:      include/linux/irqchip/irq-ixp4xx.h
+F:      include/linux/platform_data/timer-ixp4xx.h
 
 ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
 M:      Jonathan Cameron <jic23@cam.ac.uk>
@@ -2238,6 +2248,7 @@ F:	arch/arm/mach-socfpga/
 F:      arch/arm/boot/dts/socfpga*
 F:      arch/arm/configs/socfpga_defconfig
 F:      arch/arm64/boot/dts/altera/
+F:      arch/arm64/boot/dts/intel/
 W:      http://www.rocketboards.org
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git
 
@@ -7990,10 +8001,10 @@ F:	Documentation/media/v4l-drivers/ipu3.rst
 INTEL IXP4XX QMGR, NPE, ETHERNET and HSS SUPPORT
 M:      Krzysztof Halasa <khalasa@piap.pl>
 S:      Maintained
-F:      arch/arm/mach-ixp4xx/include/mach/qmgr.h
-F:      arch/arm/mach-ixp4xx/include/mach/npe.h
-F:      arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
-F:      arch/arm/mach-ixp4xx/ixp4xx_npe.c
+F:      include/linux/soc/ixp4xx/qmgr.h
+F:      include/linux/soc/ixp4xx/npe.h
+F:      drivers/soc/ixp4xx/ixp4xx-qmgr.c
+F:      drivers/soc/ixp4xx/ixp4xx-npe.c
 F:      drivers/net/ethernet/xscale/ixp4xx_eth.c
 F:      drivers/net/wan/ixp4xx_hss.c
 
@@ -15654,7 +15665,7 @@ F:	include/linux/clk/ti.h
 
 TI DAVINCI MACHINE SUPPORT
 M:      Sekhar Nori <nsekhar@ti.com>
-M:      Kevin Hilman <khilman@kernel.org>
+R:      Bartosz Golaszewski <bgolaszewski@baylibre.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci.git
 S:      Supported
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5fd344bd06b9..8869742a85df 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -426,12 +426,15 @@ config ARCH_IXP4XX
         depends on MMU
         select ARCH_HAS_DMA_SET_COHERENT_MASK
         select ARCH_SUPPORTS_BIG_ENDIAN
-        select CLKSRC_MMIO
         select CPU_XSCALE
         select DMABOUNCE if PCI
         select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_MULTI_HANDLER
+        select GPIO_IXP4XX
         select GPIOLIB
         select HAVE_PCI
+        select IXP4XX_IRQ
+        select IXP4XX_TIMER
         select NEED_MACH_IO_H
         select USB_EHCI_BIG_ENDIAN_DESC
         select USB_EHCI_BIG_ENDIAN_MMIO
@@ -897,8 +900,6 @@ config PLAT_PXA
 config PLAT_VERSATILE
         bool
 
-source "arch/arm/firmware/Kconfig"
-
 source "arch/arm/mm/Kconfig"
 
 config IWMMXT
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index e388af4594a6..9a8862fee738 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1676,6 +1676,7 @@ config DEBUG_UART_PHYS
         default 0xe6e68000 if DEBUG_RCAR_GEN2_SCIF1
         default 0xe6ee0000 if DEBUG_RCAR_GEN2_SCIF4
         default 0xe8008000 if DEBUG_R7S72100_SCIF2
+        default 0xf0000000 if DEBUG_DIGICOLOR_UA0
         default 0xf0000be0 if ARCH_EBSA110
         default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE
         default 0xf1012100 if DEBUG_MVEBU_UART1_ALTERNATE
@@ -1727,6 +1728,7 @@ config DEBUG_UART_VIRT
         default 0xe0010fe0 if ARCH_RPC
         default 0xf0000be0 if ARCH_EBSA110
         default 0xf0010000 if DEBUG_ASM9260_UART
+        default 0xf0100000 if DEBUG_DIGICOLOR_UA0
         default 0xf01fb000 if DEBUG_NOMADIK_UART
         default 0xf0201000 if DEBUG_BCM2835 || DEBUG_BCM2836
         default 0xf1000300 if DEBUG_BCM_5301X
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 807a7d06c2a0..05ecc004de86 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -290,7 +290,6 @@ core-y				+= arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
 core-y                          += arch/arm/probes/
 core-y                          += arch/arm/net/
 core-y                          += arch/arm/crypto/
-core-y                          += arch/arm/firmware/
 core-y                          += $(machdirs) $(platdirs)
 
 drivers-$(CONFIG_OPROFILE)      += arch/arm/oprofile/
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f4f5aeaf3298..7af4e3289a89 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -229,6 +229,9 @@ dtb-$(CONFIG_ARCH_HIX5HD2) += \
 dtb-$(CONFIG_ARCH_INTEGRATOR) += \
         integratorap.dtb \
         integratorcp.dtb
+dtb-$(CONFIG_ARCH_IXP4XX) += \
+        intel-ixp42x-linksys-nslu2.dtb \
+        intel-ixp43x-gateworks-gw2358.dtb
 dtb-$(CONFIG_ARCH_KEYSTONE) += \
         keystone-k2hk-evm.dtb \
         keystone-k2l-evm.dtb \
diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
index fb01fa6e4224..c40a7af6ebee 100644
--- a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
+++ b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
@@ -88,6 +88,7 @@
                 regulator-min-microvolt = <5000000>;
                 regulator-max-microvolt = <5000000>;
                 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+                startup-delay-us = <70000>;
                 enable-active-high;
         };
 
@@ -99,6 +100,7 @@
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
                 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+                startup-delay-us = <70000>;
                 enable-active-high;
                 regulator-always-on;
         };
@@ -216,7 +218,7 @@
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         phy-reset-duration = <10>;
         phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
         phy-supply = <&reg_enet>;
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 65c184bb8fb0..d9de49efa802 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -92,7 +92,7 @@
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
index adc9455e42c7..37c63402157b 100644
--- a/arch/arm/boot/dts/imx6q-ba16.dtsi
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -171,7 +171,7 @@
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts
index d8ccb533b6b7..84b30bd6908f 100644
--- a/arch/arm/boot/dts/imx6q-marsboard.dts
+++ b/arch/arm/boot/dts/imx6q-marsboard.dts
@@ -110,7 +110,7 @@
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
index 2ce8399a10ba..bfff87ce2e1f 100644
--- a/arch/arm/boot/dts/imx6q-tbs2910.dts
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -98,7 +98,7 @@
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-apf6.dtsi b/arch/arm/boot/dts/imx6qdl-apf6.dtsi
index 1ebf29f43a24..4738c3c1ab50 100644
--- a/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apf6.dtsi
@@ -51,7 +51,7 @@
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         phy-reset-duration = <10>;
         phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
         status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 1280de50a984..f3404dd10537 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -292,7 +292,7 @@
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
         fsl,err006687-workaround-present;
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index a0705066ccba..185fb17a3500 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -202,7 +202,7 @@
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
index 4ccb7afc4b35..6d7f6b9035bc 100644
--- a/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sr-som.dtsi
@@ -53,7 +53,7 @@
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         phy-reset-duration = <2>;
         phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
         status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index b7d5fb421404..50d9a989e06a 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -224,7 +224,7 @@
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index b0ee324afe58..315044ccd65f 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -75,7 +75,7 @@
 &fec1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet1>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         phy-handle = <&ethphy1>;
         fsl,magic-packet;
         status = "okay";
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index 08ede56c3f10..f6972deb5e39 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -191,7 +191,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet1>;
         phy-supply = <&reg_enet_3v3>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         phy-handle = <&ethphy1>;
         phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
         status = "okay";
diff --git a/arch/arm/boot/dts/imx7d-pico.dtsi b/arch/arm/boot/dts/imx7d-pico.dtsi
index 3fd595a71202..6f50ebf31a0a 100644
--- a/arch/arm/boot/dts/imx7d-pico.dtsi
+++ b/arch/arm/boot/dts/imx7d-pico.dtsi
@@ -92,7 +92,7 @@
                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
         assigned-clock-rates = <0>, <100000000>;
-        phy-mode = "rgmii";
+        phy-mode = "rgmii-id";
         phy-handle = <&ethphy0>;
         fsl,magic-packet;
         phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
new file mode 100644
index 000000000000..8fcd95805ff4
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for Linksys NSLU2
+ */
+
+/dts-v1/;
+
+#include "intel-ixp42x.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "Linksys NSLU2 (Network Storage Link for USB 2.0 Disk Drives)";
+        compatible = "linksys,nslu2", "intel,ixp42x";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory@0 {
+                /* 32 MB SDRAM */
+                device_type = "memory";
+                reg = <0x00000000 0x2000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
+                stdout-path = "uart0:115200n8";
+        };
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led-status {
+                        label = "nslu2:red:status";
+                        gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led-ready {
+                        label = "nslu2:green:ready";
+                        gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+                led-disk-1 {
+                        label = "nslu2:green:disk-1";
+                        gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+                led-disk-2 {
+                        label = "nslu2:green:disk-2";
+                        gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                button-power {
+                        wakeup-source;
+                        linux,code = <KEY_POWER>;
+                        label = "power";
+                        gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+                };
+                button-reset {
+                        wakeup-source;
+                        linux,code = <KEY_ESC>;
+                        label = "reset";
+                        gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        i2c {
+                compatible = "i2c-gpio";
+                sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+                scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                rtc@6f {
+                        compatible = "xicor,x1205";
+                        reg = <0x6f>;
+                };
+        };
+
+        gpio-poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+                timeout-ms = <5000>;
+        };
+
+        /* The first 16MB region on the expansion bus */
+        flash@50000000 {
+                compatible = "intel,ixp4xx-flash", "cfi-flash";
+                bank-width = <2>;
+                /*
+                 * 8 MB of Flash in 0x20000 byte blocks
+                 * mapped in at 0x50000000
+                 */
+                reg = <0x50000000 0x800000>;
+
+                partitions {
+                        compatible = "redboot-fis";
+                        /* Eraseblock at 0x7e0000 */
+                        fis-index-block = <0x3f>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel-ixp42x.dtsi
new file mode 100644
index 000000000000..a9622ca850cc
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp42x.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for Intel XScale Network Processors
+ * in the IXP 42x series. This series has 32 interrupts.
+ */
+#include "intel-ixp4xx.dtsi"
+
+/ {
+        soc {
+                interrupt-controller@c8003000 {
+                        compatible = "intel,ixp42x-interrupt";
+                };
+
+                /*
+                 * This is the USB Device Mode (UDC) controller, which is used
+                 * to present the IXP4xx as a device on a USB bus.
+                 */
+                usb@c800b000 {
+                        compatible = "intel,ixp4xx-udc";
+                        reg = <0xc800b000 0x1000>;
+                        interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
new file mode 100644
index 000000000000..ba1163a1e1e7
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for Gateworks IXP43x-based Cambria GW2358
+ */
+
+/dts-v1/;
+
+#include "intel-ixp43x.dtsi"
+
+/ {
+        model = "Gateworks Cambria GW2358";
+        compatible = "gateworks,gw2358", "intel,ixp43x";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory@0 {
+                /* 128 MB SDRAM */
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
+                stdout-path = "uart0:115200n8";
+        };
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led-user {
+                        label = "gw2358:green:LED";
+                        gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+
+        i2c {
+                compatible = "i2c-gpio";
+                sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+                scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                hwmon@28 {
+                        compatible = "adi,ad7418";
+                        reg = <0x28>;
+                };
+                rtc: ds1672@68 {
+                        compatible = "dallas,ds1672";
+                        reg = <0x68>;
+                };
+                eeprom@51 {
+                        compatible = "atmel,24c08";
+                        reg = <0x51>;
+                        pagesize = <16>;
+                        size = <1024>;
+                        read-only;
+                };
+                pld0: pld@56 {
+                        compatible = "gateworks,pld-gpio";
+                        reg = <0x56>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                /* This PLD just handles the LED and user button */
+                pld1: pld@57 {
+                        compatible = "gateworks,pld-gpio";
+                        reg = <0x57>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+        };
+
+        flash@50000000 {
+                compatible = "intel,ixp4xx-flash", "cfi-flash";
+                bank-width = <2>;
+                /*
+                 * 32 MB of Flash in 0x20000 byte blocks
+                 * mapped in at 0x50000000
+                 */
+                reg = <0x50000000 0x2000000>;
+
+                partitions {
+                        compatible = "redboot-fis";
+                        /* Eraseblock at 0x1fe0000 */
+                        fis-index-block = <0xff>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/intel-ixp43x.dtsi b/arch/arm/boot/dts/intel-ixp43x.dtsi
new file mode 100644
index 000000000000..494fb2ff57a0
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp43x.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for Intel XScale Network Processors
+ * in the IXP 43x series. This series has 64 interrupts and adds a few more
+ * peripherals over the 42x series.
+ */
+#include "intel-ixp4xx.dtsi"
+
+/ {
+        soc {
+                interrupt-controller@c8003000 {
+                        compatible = "intel,ixp43x-interrupt";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
new file mode 100644
index 000000000000..f8cd506659dc
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for Intel XScale Network Processors
+ * in the IXP45x and IXP46x series. This series has 64 interrupts and adds a
+ * few more peripherals over the 42x and 43x series so this extends the
+ * basic IXP4xx DTSI.
+ */
+#include "intel-ixp4xx.dtsi"
+
+/ {
+        soc {
+                interrupt-controller@c8003000 {
+                        compatible = "intel,ixp43x-interrupt";
+                };
+
+                /*
+                 * This is the USB Device Mode (UDC) controller, which is used
+                 * to present the IXP4xx as a device on a USB bus.
+                 */
+                usb@c800b000 {
+                        compatible = "intel,ixp4xx-udc";
+                        reg = <0xc800b000 0x1000>;
+                        interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+
+                i2c@c8011000 {
+                        compatible = "intel,ixp4xx-i2c";
+                        reg = <0xc8011000 0x18>;
+                        interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
new file mode 100644
index 000000000000..d4a09584f417
--- /dev/null
+++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for Intel XScale Network Processors
+ * in the IXP 4xx series.
+ */
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                compatible = "simple-bus";
+                interrupt-parent = <&intcon>;
+
+                qmgr: queue-manager@60000000 {
+                        compatible = "intel,ixp4xx-ahb-queue-manager";
+                        reg = <0x60000000 0x4000>;
+                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                uart0: serial@c8000000 {
+                        compatible = "intel,xscale-uart";
+                        reg = <0xc8000000 0x1000>;
+                        /*
+                         * The reg-offset and reg-shift is a side effect
+                         * of running the platform in big endian mode.
+                         */
+                        reg-offset = <3>;
+                        reg-shift = <2>;
+                        interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
+                        clock-frequency = <14745600>;
+                        no-loopback-test;
+                };
+
+                gpio0: gpio@c8004000 {
+                        compatible = "intel,ixp4xx-gpio";
+                        reg = <0xc8004000 0x1000>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                intcon: interrupt-controller@c8003000 {
+                        /*
+                         * Note: no compatible string. The subvariant of the
+                         * chip needs to define what version it is. The
+                         * location of the interrupt controller is fixed in
+                         * memory across all variants.
+                         */
+                        reg = <0xc8003000 0x100>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                timer@c8005000 {
+                        compatible = "intel,ixp4xx-timer";
+                        reg = <0xc8005000 0x100>;
+                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                npe@c8006000 {
+                        compatible = "intel,ixp4xx-network-processing-engine";
+                        reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index 97e1fb7ea932..9b1fe99d55b1 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -145,7 +145,7 @@
 };
 
 &enet0 {
-        tbi-handle = <&tbi1>;
+        tbi-handle = <&tbi0>;
         phy-handle = <&sgmii_phy2>;
         phy-connection-type = "sgmii";
         status = "okay";
@@ -225,6 +225,13 @@
         sgmii_phy2: ethernet-phy@2 {
                 reg = <0x2>;
         };
+        tbi0: tbi-phy@1f {
+                reg = <0x1f>;
+                device_type = "tbi-phy";
+        };
+};
+
+&mdio1 {
         tbi1: tbi-phy@1f {
                 reg = <0x1f>;
                 device_type = "tbi-phy";
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index b10ff5877b4c..fe6eecf01da1 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -729,7 +729,7 @@
                 };
 
                 mdio0: mdio@2d24000 {
-                        compatible = "gianfar";
+                        compatible = "fsl,etsec2-mdio";
                         device_type = "mdio";
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -737,6 +737,15 @@
                               <0x0 0x2d10030 0x0 0x4>;
                 };
 
+                mdio1: mdio@2d64000 {
+                        compatible = "fsl,etsec2-mdio";
+                        device_type = "mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x0 0x2d64000 0x0 0x4000>,
+                              <0x0 0x2d50030 0x0 0x4>;
+                };
+
                 ptp_clock@2d10e00 {
                         compatible = "fsl,etsec-ptp";
                         reg = <0x0 0x2d10e00 0x0 0xb0>;
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 43fe215e83ea..14a7d0288b45 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -169,6 +169,8 @@
                         clock-names = "ahb", "mod";
                         resets = <&ccu RST_BUS_NAND>;
                         reset-names = "ahb";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;
                         status = "disabled";
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index d635edfb6ff2..c95c54284da2 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -9,7 +9,6 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_EXYNOS3=y
-CONFIG_EXYNOS5420_MCPM=y
 CONFIG_SMP=y
 CONFIG_BIG_LITTLE=y
 CONFIG_NR_CPUS=8
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index b7b1cd00a294..9a78c8940105 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -33,7 +33,6 @@ CONFIG_MACH_BERLIN_BG2CD=y
 CONFIG_MACH_BERLIN_BG2Q=y
 CONFIG_ARCH_DIGICOLOR=y
 CONFIG_ARCH_EXYNOS=y
-CONFIG_EXYNOS5420_MCPM=y
 CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_HISI=y
 CONFIG_ARCH_HI3xxx=y
diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig
deleted file mode 100644
index ad396af68e47..000000000000
--- a/arch/arm/firmware/Kconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-config ARCH_SUPPORTS_FIRMWARE
-        bool
-
-config ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
-        bool
-        select ARCH_SUPPORTS_FIRMWARE
-
-menu "Firmware options"
-        depends on ARCH_SUPPORTS_FIRMWARE
-
-config TRUSTED_FOUNDATIONS
-        bool "Trusted Foundations secure monitor support"
-        depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
-        default y
-        help
-          Some devices (including most Tegra-based consumer devices on the
-          market) are booted with the Trusted Foundations secure monitor
-          active, requiring some core operations to be performed by the secure
-          monitor instead of the kernel.
-
-          This option allows the kernel to invoke the secure monitor whenever
-          required on devices using Trusted Foundations. See
-          arch/arm/include/asm/trusted_foundations.h or the
-          tlm,trusted-foundations device tree binding documentation for details
-          on how to use it.
-
-          Say n if you don't know what this is about.
-
-endmenu
diff --git a/arch/arm/firmware/Makefile b/arch/arm/firmware/Makefile
deleted file mode 100644
index 6e41336b0bc4..000000000000
--- a/arch/arm/firmware/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-obj-$(CONFIG_TRUSTED_FOUNDATIONS)       += trusted_foundations.o
-
-# tf_generic_smc() fails to build with -fsanitize-coverage=trace-pc
-KCOV_INSTRUMENT                := n
diff --git a/arch/arm/include/asm/firmware.h b/arch/arm/include/asm/firmware.h
index 34c1d96ef46d..6698272bbcbf 100644
--- a/arch/arm/include/asm/firmware.h
+++ b/arch/arm/include/asm/firmware.h
@@ -24,7 +24,7 @@ struct firmware_ops {
         /*
          * Inform the firmware we intend to enter CPU idle mode
          */
-        int (*prepare_idle)(void);
+        int (*prepare_idle)(unsigned long mode);
         /*
          * Enters CPU idle mode
          */
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index ff097ecfa451..51a892702e27 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -29,6 +29,7 @@
 #include <linux/platform_data/spi-davinci.h>
 #include <linux/platform_data/usb-davinci.h>
 #include <linux/platform_data/ti-aemif.h>
+#include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/nvmem-provider.h>
 
@@ -53,14 +54,50 @@ static const short da830_evm_usb11_pins[] = {
         -1
 };
 
-static struct gpiod_lookup_table da830_evm_usb_gpio_lookup = {
+static struct regulator_consumer_supply da830_evm_usb_supplies[] = {
+        REGULATOR_SUPPLY("vbus", NULL),
+};
+
+static struct regulator_init_data da830_evm_usb_vbus_data = {
+        .consumer_supplies      = da830_evm_usb_supplies,
+        .num_consumer_supplies  = ARRAY_SIZE(da830_evm_usb_supplies),
+};
+
+static struct fixed_voltage_config da830_evm_usb_vbus = {
+        .supply_name            = "vbus",
+        .microvolts             = 33000000,
+        .init_data              = &da830_evm_usb_vbus_data,
+};
+
+static struct platform_device da830_evm_usb_vbus_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 0,
+        .dev            = {
+                .platform_data = &da830_evm_usb_vbus,
+        },
+};
+
+static struct gpiod_lookup_table da830_evm_usb_oc_gpio_lookup = {
         .dev_id         = "ohci-da8xx",
         .table = {
-                GPIO_LOOKUP("davinci_gpio", ON_BD_USB_DRV, "vbus", 0),
                 GPIO_LOOKUP("davinci_gpio", ON_BD_USB_OVC, "oc", 0),
+                { }
         },
 };
 
+static struct gpiod_lookup_table da830_evm_usb_vbus_gpio_lookup = {
+        .dev_id         = "reg-fixed-voltage.0",
+        .table = {
+                GPIO_LOOKUP("davinci_gpio", ON_BD_USB_DRV, "vbus", 0),
+                { }
+        },
+};
+
+static struct gpiod_lookup_table *da830_evm_usb_gpio_lookups[] = {
+        &da830_evm_usb_oc_gpio_lookup,
+        &da830_evm_usb_vbus_gpio_lookup,
+};
+
 static struct da8xx_ohci_root_hub da830_evm_usb11_pdata = {
         /* TPS2065 switch @ 5V */
         .potpgt         = (3 + 1) / 2,  /* 3 ms max */
@@ -75,6 +112,9 @@ static __init void da830_evm_usb_init(void)
                 pr_warn("%s: USB PHY CLK registration failed: %d\n",
                         __func__, ret);
 
+        gpiod_add_lookup_tables(da830_evm_usb_gpio_lookups,
+                                ARRAY_SIZE(da830_evm_usb_gpio_lookups));
+
         ret = da8xx_register_usb_phy();
         if (ret)
                 pr_warn("%s: USB PHY registration failed: %d\n",
@@ -100,7 +140,11 @@ static __init void da830_evm_usb_init(void)
                 return;
         }
 
-        gpiod_add_lookup_table(&da830_evm_usb_gpio_lookup);
+        ret = platform_device_register(&da830_evm_usb_vbus_device);
+        if (ret) {
+                pr_warn("%s: Unable to register the vbus supply\n", __func__);
+                return;
+        }
 
         ret = da8xx_register_usb11(&da830_evm_usb11_pdata);
         if (ret)
@@ -156,6 +200,7 @@ static struct gpiod_lookup_table mmc_gpios_table = {
                             GPIO_ACTIVE_LOW),
                 GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_WP_PIN, "wp",
                             GPIO_ACTIVE_LOW),
+                { }
         },
 };
 
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 1fdc9283a8c5..4ee65a8a3b80 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -784,6 +784,7 @@ static struct gpiod_lookup_table mmc_gpios_table = {
                             GPIO_ACTIVE_LOW),
                 GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_WP_PIN, "wp",
                             GPIO_ACTIVE_HIGH),
+                { }
         },
 };
 
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 64d81fc86f14..5113273fda69 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -121,6 +121,7 @@ static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
                             GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
                 GPIO_LOOKUP("davinci_gpio", DM355_I2C_SCL_PIN, "scl",
                             GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+                { }
         },
 };
 
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index de15f782816e..9d87d4e440ea 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -663,6 +663,7 @@ static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
                             GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
                 GPIO_LOOKUP("davinci_gpio", DM644X_I2C_SCL_PIN, "scl",
                             GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
+                { }
         },
 };
 
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 0896af2bed24..db177a6a7e48 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -21,6 +21,7 @@
 #include <linux/platform_data/mtd-davinci.h>
 #include <linux/platform_data/mtd-davinci-aemif.h>
 #include <linux/platform_data/ti-aemif.h>
+#include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
@@ -298,14 +299,50 @@ static const short da850_hawk_usb11_pins[] = {
         -1
 };
 
-static struct gpiod_lookup_table hawk_usb_gpio_lookup = {
+static struct regulator_consumer_supply hawk_usb_supplies[] = {
+        REGULATOR_SUPPLY("vbus", NULL),
+};
+
+static struct regulator_init_data hawk_usb_vbus_data = {
+        .consumer_supplies      = hawk_usb_supplies,
+        .num_consumer_supplies  = ARRAY_SIZE(hawk_usb_supplies),
+};
+
+static struct fixed_voltage_config hawk_usb_vbus = {
+        .supply_name            = "vbus",
+        .microvolts             = 3300000,
+        .init_data              = &hawk_usb_vbus_data,
+};
+
+static struct platform_device hawk_usb_vbus_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 0,
+        .dev            = {
+                .platform_data = &hawk_usb_vbus,
+        },
+};
+
+static struct gpiod_lookup_table hawk_usb_oc_gpio_lookup = {
         .dev_id         = "ohci-da8xx",
         .table = {
-                GPIO_LOOKUP("davinci_gpio", DA850_USB1_VBUS_PIN, "vbus", 0),
                 GPIO_LOOKUP("davinci_gpio", DA850_USB1_OC_PIN, "oc", 0),
+                { }
         },
 };
 
+static struct gpiod_lookup_table hawk_usb_vbus_gpio_lookup = {
+        .dev_id         = "reg-fixed-voltage.0",
+        .table = {
+                GPIO_LOOKUP("davinci_gpio", DA850_USB1_VBUS_PIN, NULL, 0),
+                { }
+        },
+};
+
+static struct gpiod_lookup_table *hawk_usb_gpio_lookups[] = {
+        &hawk_usb_oc_gpio_lookup,
+        &hawk_usb_vbus_gpio_lookup,
+};
+
 static struct da8xx_ohci_root_hub omapl138_hawk_usb11_pdata = {
         /* TPS2087 switch @ 5V */
         .potpgt         = (3 + 1) / 2,  /* 3 ms max */
@@ -326,12 +363,19 @@ static __init void omapl138_hawk_usb_init(void)
                 pr_warn("%s: USB PHY CLK registration failed: %d\n",
                         __func__, ret);
 
+        gpiod_add_lookup_tables(hawk_usb_gpio_lookups,
+                                ARRAY_SIZE(hawk_usb_gpio_lookups));
+
         ret = da8xx_register_usb_phy();
         if (ret)
                 pr_warn("%s: USB PHY registration failed: %d\n",
                         __func__, ret);
 
-        gpiod_add_lookup_table(&hawk_usb_gpio_lookup);
+        ret = platform_device_register(&hawk_usb_vbus_device);
+        if (ret) {
+                pr_warn("%s: Unable to register the vbus supply\n", __func__);
+                return;
+        }
 
         ret = da8xx_register_usb11(&omapl138_hawk_usb11_pdata);
         if (ret)
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index bda6c3a5c923..5d3a3e302012 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -15,7 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/sizes.h>
 
-#include <mach/hardware.h>
+#include "hardware.h"
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index d2eee707d27f..b9f523d9dc8c 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -20,8 +20,9 @@
 #include <linux/io.h>
 #include <linux/spinlock.h>
 #include <linux/clkdev.h>
+#include <linux/soc/cirrus/ep93xx.h>
 
-#include <mach/hardware.h>
+#include "hardware.h"
 
 #include <asm/div64.h>
 
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 706515faee06..cc1382f879af 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -39,11 +39,13 @@
 #include <linux/usb/ohci_pdriver.h>
 #include <linux/random.h>
 
-#include <mach/hardware.h>
+#include "hardware.h"
 #include <linux/platform_data/video-ep93xx.h>
 #include <linux/platform_data/keypad-ep93xx.h>
 #include <linux/platform_data/spi-ep93xx.h>
-#include <mach/gpio-ep93xx.h>
+#include <linux/soc/cirrus/ep93xx.h>
+
+#include "gpio-ep93xx.h"
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -123,7 +125,7 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
 /**
  * ep93xx_chip_revision() - returns the EP93xx chip revision
  *
- * See <mach/platform.h> for more information.
+ * See "platform.h" for more information.
  */
 unsigned int ep93xx_chip_revision(void)
 {
diff --git a/arch/arm/mach-ep93xx/dma.c b/arch/arm/mach-ep93xx/dma.c
index 88a4c9b089a5..821427107b11 100644
--- a/arch/arm/mach-ep93xx/dma.c
+++ b/arch/arm/mach-ep93xx/dma.c
@@ -26,7 +26,7 @@
 #include <linux/platform_device.h>
 
 #include <linux/platform_data/dma-ep93xx.h>
-#include <mach/hardware.h>
+#include "hardware.h"
 
 #include "soc.h"
 
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 34e18e9556d9..c8c47122cf1d 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -33,10 +33,10 @@
 
 #include <sound/cs4271.h>
 
-#include <mach/hardware.h>
+#include "hardware.h"
 #include <linux/platform_data/video-ep93xx.h>
 #include <linux/platform_data/spi-ep93xx.h>
-#include <mach/gpio-ep93xx.h>
+#include "gpio-ep93xx.h"
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index 0cca5b183309..ac48e3476587 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -15,7 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/sizes.h>
 
-#include <mach/hardware.h>
+#include "hardware.h"
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h b/arch/arm/mach-ep93xx/gpio-ep93xx.h
index 242af4a401ea..242af4a401ea 100644
--- a/arch/arm/mach-ep93xx/include/mach/gpio-ep93xx.h
+++ b/arch/arm/mach-ep93xx/gpio-ep93xx.h
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/hardware.h
index 8938906e780a..e7d850e04782 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/hardware.h
@@ -6,7 +6,7 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
-#include <mach/platform.h>
+#include "platform.h"
 
 /*
  * The EP93xx has two external crystal oscillators.  To generate the
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 373583c29825..c7f64e4ff6c7 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -16,7 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include "hardware.h"
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/platform.h
index 6c41c794bed5..b4045a186239 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/platform.h
@@ -5,6 +5,7 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/platform_data/eth-ep93xx.h>
 #include <linux/reboot.h>
 
 struct device;
@@ -15,23 +16,9 @@ struct ep93xxfb_mach_info;
 struct ep93xx_keypad_platform_data;
 struct ep93xx_spi_info;
 
-struct ep93xx_eth_data
-{
-        unsigned char   dev_addr[6];
-        unsigned char   phy_id;
-};
-
 void ep93xx_map_io(void);
 void ep93xx_init_irq(void);
 
-#define EP93XX_CHIP_REV_D0      3
-#define EP93XX_CHIP_REV_D1      4
-#define EP93XX_CHIP_REV_E0      5
-#define EP93XX_CHIP_REV_E1      6
-#define EP93XX_CHIP_REV_E2      7
-
-unsigned int ep93xx_chip_revision(void);
-
 void ep93xx_register_flash(unsigned int width,
                            resource_size_t start, resource_size_t size);
 
@@ -41,19 +28,11 @@ void ep93xx_register_spi(struct ep93xx_spi_info *info,
                          struct spi_board_info *devices, int num);
 void ep93xx_register_fb(struct ep93xxfb_mach_info *data);
 void ep93xx_register_pwm(int pwm0, int pwm1);
-int ep93xx_pwm_acquire_gpio(struct platform_device *pdev);
-void ep93xx_pwm_release_gpio(struct platform_device *pdev);
 void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data);
-int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
-void ep93xx_keypad_release_gpio(struct platform_device *pdev);
 void ep93xx_register_i2s(void);
-int ep93xx_i2s_acquire(void);
-void ep93xx_i2s_release(void);
 void ep93xx_register_ac97(void);
 void ep93xx_register_ide(void);
 void ep93xx_register_adc(void);
-int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
-void ep93xx_ide_release_gpio(struct platform_device *pdev);
 
 struct device *ep93xx_init_devices(void);
 extern void ep93xx_timer_init(void);
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index f0f38c0dba52..5a3c32fa7ace 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -27,8 +27,8 @@
 #include <linux/gpio.h>
 #include <linux/gpio/machine.h>
 
-#include <mach/hardware.h>
-#include <mach/gpio-ep93xx.h>
+#include "hardware.h"
+#include "gpio-ep93xx.h"
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index cf0cb58b3454..f8f89551dbed 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -25,9 +25,9 @@
 
 #include <linux/mtd/platnand.h>
 
-#include <mach/hardware.h>
+#include "hardware.h"
 #include <linux/platform_data/video-ep93xx.h>
-#include <mach/gpio-ep93xx.h>
+#include "gpio-ep93xx.h"
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index a3a20c83c6b8..e9f369067293 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -24,8 +24,8 @@
 #include <linux/platform_data/spi-ep93xx.h>
 #include <linux/gpio/machine.h>
 
-#include <mach/gpio-ep93xx.h>
-#include <mach/hardware.h>
+#include "gpio-ep93xx.h"
+#include "hardware.h"
 #include <mach/irqs.h>
 
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index f95a644769e4..d44db6d67f35 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -31,10 +31,10 @@
 
 #include <sound/cs4271.h>
 
-#include <mach/hardware.h>
+#include "hardware.h"
 #include <linux/platform_data/video-ep93xx.h>
 #include <linux/platform_data/spi-ep93xx.h>
-#include <mach/gpio-ep93xx.h>
+#include "gpio-ep93xx.h"
 
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index b40963cf91c7..1c518b8ee520 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -106,21 +106,15 @@ config SOC_EXYNOS5420
         bool "SAMSUNG EXYNOS5420"
         default y
         depends on ARCH_EXYNOS5
+        select MCPM if SMP
+        select ARM_CCI400_PORT_CTRL
+        select ARM_CPU_SUSPEND
 
 config SOC_EXYNOS5800
         bool "SAMSUNG EXYNOS5800"
         default y
         depends on SOC_EXYNOS5420
 
-config EXYNOS5420_MCPM
-        bool "Exynos5420 Multi-Cluster PM support"
-        depends on MCPM && SOC_EXYNOS5420
-        select ARM_CCI400_PORT_CTRL
-        select ARM_CPU_SUSPEND
-        help
-          This is needed to provide CPU and cluster power management
-          on Exynos5420 implementing big.LITTLE.
-
 config EXYNOS_CPU_SUSPEND
         bool
         select ARM_CPU_SUSPEND
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index cd00c82a1add..264dbaa89c3d 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -18,5 +18,5 @@ plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o             :=-Wa,-march=armv7-a$(plus_sec)
 AFLAGS_sleep.o                  :=-Wa,-march=armv7-a$(plus_sec)
 
-obj-$(CONFIG_EXYNOS5420_MCPM)   += mcpm-exynos.o
+obj-$(CONFIG_MCPM)              += mcpm-exynos.o
 CFLAGS_mcpm-exynos.o            += -march=armv7-a
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 1b8699e94098..c93356a8d662 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -91,6 +91,7 @@ extern u32 cp15_save_power;
 
 extern void __iomem *sysram_ns_base_addr;
 extern void __iomem *sysram_base_addr;
+extern phys_addr_t sysram_base_phys;
 extern void __iomem *pmu_base_addr;
 void exynos_sysram_init(void);
 
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 865dcc4c3181..9aa483366ebc 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -33,6 +33,7 @@ static struct platform_device exynos_cpuidle = {
 };
 
 void __iomem *sysram_base_addr __ro_after_init;
+phys_addr_t sysram_base_phys __ro_after_init;
 void __iomem *sysram_ns_base_addr __ro_after_init;
 
 void __init exynos_sysram_init(void)
@@ -43,6 +44,8 @@ void __init exynos_sysram_init(void)
                 if (!of_device_is_available(node))
                         continue;
                 sysram_base_addr = of_iomap(node, 0);
+                sysram_base_phys = of_translate_address(node,
+                                           of_get_address(node, 0, NULL, NULL));
                 break;
         }
 
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index d602e3bf3f96..2eaf2dbb8e81 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -196,6 +196,7 @@ bool __init exynos_secure_firmware_available(void)
                 return false;
 
         addr = of_get_address(nd, 0, NULL, NULL);
+        of_node_put(nd);
         if (!addr) {
                 pr_err("%s: No address specified.\n", __func__);
                 return false;
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
index 72bc035bedbe..9a681b421ae1 100644
--- a/arch/arm/mach-exynos/mcpm-exynos.c
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -75,14 +75,25 @@ static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
                  */
                 if (cluster &&
                     cluster == MPIDR_AFFINITY_LEVEL(cpu_logical_map(0), 1)) {
+                        unsigned int timeout = 16;
+
                         /*
                          * Before we reset the Little cores, we should wait
                          * the SPARE2 register is set to 1 because the init
                          * codes of the iROM will set the register after
                          * initialization.
                          */
-                        while (!pmu_raw_readl(S5P_PMU_SPARE2))
+                        while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) {
+                                timeout--;
                                 udelay(10);
+                        }
+
+                        if (timeout == 0) {
+                                pr_err("cpu %u cluster %u powerup failed\n",
+                                       cpu, cluster);
+                                exynos_cpu_power_down(cpunr);
+                                return -ETIMEDOUT;
+                        }
 
                         pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu),
                                         EXYNOS_SWRESET);
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index abcac6164233..0cbbae8bf1f8 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -214,13 +214,20 @@ static inline void __iomem *cpu_boot_reg(int cpu)
  */
 void exynos_core_restart(u32 core_id)
 {
+        unsigned int timeout = 16;
         u32 val;
 
         if (!of_machine_is_compatible("samsung,exynos3250"))
                 return;
 
-        while (!pmu_raw_readl(S5P_PMU_SPARE2))
+        while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) {
+                timeout--;
                 udelay(10);
+        }
+        if (timeout == 0) {
+                pr_err("cpu core %u restart failed\n", core_id);
+                return;
+        }
         udelay(10);
 
         val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
diff --git a/arch/arm/mach-exynos/smc.h b/arch/arm/mach-exynos/smc.h
index f355185d4239..98832e50852d 100644
--- a/arch/arm/mach-exynos/smc.h
+++ b/arch/arm/mach-exynos/smc.h
@@ -25,6 +25,13 @@
 #define SMC_CMD_L2X0INVALL      (-24)
 #define SMC_CMD_L2X0DEBUG       (-25)
 
+/* For Accessing CP15/SFR (General) */
+#define SMC_CMD_REG             (-101)
+
+/* defines for SMC_CMD_REG */
+#define SMC_REG_CLASS_SFR_W     (0x1 << 30)
+#define SMC_REG_ID_SFR_W(addr)  (SMC_REG_CLASS_SFR_W | ((addr) >> 2))
+
 #ifndef __ASSEMBLY__
 
 extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3);
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 0850505ac78b..be122af0de8f 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -31,6 +31,7 @@
 #include <asm/suspend.h>
 
 #include "common.h"
+#include "smc.h"
 
 #define REG_TABLE_END (-1U)
 
@@ -62,6 +63,8 @@ struct exynos_pm_state {
         int cpu_state;
         unsigned int pmu_spare3;
         void __iomem *sysram_base;
+        phys_addr_t sysram_phys;
+        bool secure_firmware;
 };
 
 static const struct exynos_pm_data *pm_data __ro_after_init;
@@ -265,9 +268,7 @@ static int exynos5420_cpu_suspend(unsigned long arg)
         unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
         unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 
-        writel_relaxed(0x0, pm_state.sysram_base + EXYNOS5420_CPU_STATE);
-
-        if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
+        if (IS_ENABLED(CONFIG_MCPM)) {
                 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
                 mcpm_cpu_suspend();
         }
@@ -341,11 +342,16 @@ static void exynos5420_pm_prepare(void)
          */
         pm_state.cpu_state = readl_relaxed(pm_state.sysram_base +
                                            EXYNOS5420_CPU_STATE);
+        writel_relaxed(0x0, pm_state.sysram_base + EXYNOS5420_CPU_STATE);
+        if (pm_state.secure_firmware)
+                exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(pm_state.sysram_phys +
+                                                         EXYNOS5420_CPU_STATE),
+                           0, 0);
 
         exynos_pm_enter_sleep_mode();
 
         /* ensure at least INFORM0 has the resume address */
-        if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
+        if (IS_ENABLED(CONFIG_MCPM))
                 pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
 
         tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
@@ -444,8 +450,27 @@ early_wakeup:
 
 static void exynos5420_prepare_pm_resume(void)
 {
-        if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
+        unsigned int mpidr, cluster;
+
+        mpidr = read_cpuid_mpidr();
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        if (IS_ENABLED(CONFIG_MCPM))
                 WARN_ON(mcpm_cpu_powered_up());
+
+        if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
+                /*
+                 * When system is resumed on the LITTLE/KFC core (cluster 1),
+                 * the DSCR is not properly updated until the power is turned
+                 * on also for the cluster 0. Enable it for a while to
+                 * propagate the SPNIDEN and SPIDEN signals from Secure JTAG
+                 * block and avoid undefined instruction issue on CP14 reset.
+                 */
+                pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                                EXYNOS_COMMON_CONFIGURATION(0));
+                pmu_raw_writel(0,
+                                EXYNOS_COMMON_CONFIGURATION(0));
+        }
 }
 
 static void exynos5420_pm_resume(void)
@@ -460,6 +485,11 @@ static void exynos5420_pm_resume(void)
         /* Restore the sysram cpu state register */
         writel_relaxed(pm_state.cpu_state,
                        pm_state.sysram_base + EXYNOS5420_CPU_STATE);
+        if (pm_state.secure_firmware)
+                exynos_smc(SMC_CMD_REG,
+                           SMC_REG_ID_SFR_W(pm_state.sysram_phys +
+                                            EXYNOS5420_CPU_STATE),
+                           EXYNOS_AFTR_MAGIC, 0);
 
         pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
                         S5P_CENTRAL_SEQ_OPTION);
@@ -639,8 +669,10 @@ void __init exynos_pm_init(void)
 
         if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
                 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
+                of_node_put(np);
                 return;
         }
+        of_node_put(np);
 
         pm_data = (const struct exynos_pm_data *) match->data;
 
@@ -659,8 +691,11 @@ void __init exynos_pm_init(void)
          * Applicable as of now only to Exynos542x. If booted under secure
          * firmware, the non-secure region of sysram should be used.
          */
-        if (exynos_secure_firmware_available())
+        if (exynos_secure_firmware_available()) {
+                pm_state.sysram_phys = sysram_base_phys;
                 pm_state.sysram_base = sysram_ns_base_addr;
-        else
+                pm_state.secure_firmware = true;
+        } else {
                 pm_state.sysram_base = sysram_base_addr;
+        }
 }
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index e67e0b2d4ce0..e527532f6931 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -354,9 +354,11 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
          *
          * Note that IRQ #32 is GIC SPI #0.
          */
-        imx_gpc_hwirq_unmask(0);
+        if (mode != WAIT_CLOCKED)
+                imx_gpc_hwirq_unmask(0);
         writel_relaxed(val, ccm_base + CLPCR);
-        imx_gpc_hwirq_mask(0);
+        if (mode != WAIT_CLOCKED)
+                imx_gpc_hwirq_mask(0);
 
         return 0;
 }
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index fea008123eb1..83afb80d38a8 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -4,6 +4,20 @@ menu "Intel IXP4xx Implementation Options"
 
 comment "IXP4xx Platforms"
 
+config MACH_IXP4XX_OF
+        bool
+        prompt "Devce Tree IXP4xx boards"
+        default y
+        select ARM_APPENDED_DTB # Old Redboot bootloaders deployed
+        select I2C
+        select I2C_IOP3XX
+        select PCI
+        select SERIAL_OF_PLATFORM
+        select TIMER_OF
+        select USE_OF
+        help
+          Say 'Y' here to support Device Tree-based IXP4xx platforms.
+
 config MACH_NSLU2
         bool
         prompt "Linksys NSLU2"
@@ -222,19 +236,6 @@ config IXP4XX_INDIRECT_PCI
           need to use the indirect method instead. If you don't know
           what you need, leave this option unselected.
 
-config IXP4XX_QMGR
-        tristate "IXP4xx Queue Manager support"
-        help
-          This driver supports IXP4xx built-in hardware queue manager
-          and is automatically selected by Ethernet and HSS drivers.
-
-config IXP4XX_NPE
-        tristate "IXP4xx Network Processor Engine support"
-        select FW_LOADER
-        help
-          This driver supports IXP4xx built-in network coprocessors
-          and is automatically selected by Ethernet and HSS drivers.
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index f09994500a34..1fa4e6605782 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -6,6 +6,9 @@
 obj-pci-y       :=
 obj-pci-n       :=
 
+# Device tree platform
+obj-pci-$(CONFIG_MACH_IXP4XX_OF)        += ixp4xx-of.o
+
 obj-pci-$(CONFIG_ARCH_IXDP4XX)          += ixdp425-pci.o
 obj-pci-$(CONFIG_MACH_AVILA)            += avila-pci.o
 obj-pci-$(CONFIG_MACH_IXDPG425)         += ixdpg425-pci.o
@@ -40,5 +43,3 @@ obj-$(CONFIG_MACH_GORAMO_MLR)	+= goramo_mlr.o
 obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-setup.o
 
 obj-$(CONFIG_PCI)               += $(obj-pci-$(CONFIG_PCI)) common-pci.o
-obj-$(CONFIG_IXP4XX_QMGR)       += ixp4xx_qmgr.o
-obj-$(CONFIG_IXP4XX_NPE)        += ixp4xx_npe.o
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c
index 548c7d43ade6..9c834f0f4231 100644
--- a/arch/arm/mach-ixp4xx/avila-pci.c
+++ b/arch/arm/mach-ixp4xx/avila-pci.c
@@ -27,6 +27,8 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
+#include "irqs.h"
+
 #define AVILA_MAX_DEV   4
 #define LOFT_MAX_DEV    6
 #define IRQ_LINES       4
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index 44cbbce6bda6..1981b33109cb 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -28,6 +28,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
+#include "irqs.h"
+
 #define AVILA_SDA_PIN   7
 #define AVILA_SCL_PIN   6
 
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 846e033c56fa..cc5f15679d29 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -22,41 +22,30 @@
 #include <linux/serial_core.h>
 #include <linux/interrupt.h>
 #include <linux/bitops.h>
-#include <linux/time.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
 #include <linux/io.h>
 #include <linux/export.h>
-#include <linux/gpio/driver.h>
 #include <linux/cpu.h>
 #include <linux/pci.h>
 #include <linux/sched_clock.h>
+#include <linux/bitops.h>
+#include <linux/irqchip/irq-ixp4xx.h>
+#include <linux/platform_data/timer-ixp4xx.h>
 #include <mach/udc.h>
 #include <mach/hardware.h>
 #include <mach/io.h>
 #include <linux/uaccess.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
+#include <asm/exception.h>
 #include <asm/irq.h>
 #include <asm/system_misc.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 
-#define IXP4XX_TIMER_FREQ 66666000
-
-/*
- * The timer register doesn't allow to specify the two least significant bits of
- * the timeout value and assumes them being zero. So make sure IXP4XX_LATCH is
- * the best value with the two least significant bits unset.
- */
-#define IXP4XX_LATCH DIV_ROUND_CLOSEST(IXP4XX_TIMER_FREQ, \
-                                       (IXP4XX_OST_RELOAD_MASK + 1) * HZ) * \
-                        (IXP4XX_OST_RELOAD_MASK + 1)
+#include "irqs.h"
 
-static void __init ixp4xx_clocksource_init(void);
-static void __init ixp4xx_clockevent_init(void);
-static struct clock_event_device clockevent_ixp4xx;
+#define IXP4XX_TIMER_FREQ 66666000
 
 /*************************************************************************
  * IXP4xx chipset I/O mapping
@@ -77,11 +66,6 @@ static struct map_desc ixp4xx_io_desc[] __initdata = {
                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
                 .type           = MT_DEVICE
-        }, {    /* Queue Manager */
-                .virtual        = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
-                .pfn            = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
-                .length         = IXP4XX_QMGR_REGION_SIZE,
-                .type           = MT_DEVICE
         },
 };
 
@@ -90,258 +74,23 @@ void __init ixp4xx_map_io(void)
         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
 }
 
-/*
- * GPIO-functions
- */
-/*
- * The following converted to the real HW bits the gpio_line_config
- */
-/* GPIO pin types */
-#define IXP4XX_GPIO_OUT                 0x1
-#define IXP4XX_GPIO_IN                  0x2
-
-/* GPIO signal types */
-#define IXP4XX_GPIO_LOW                 0
-#define IXP4XX_GPIO_HIGH                1
-
-/* GPIO Clocks */
-#define IXP4XX_GPIO_CLK_0               14
-#define IXP4XX_GPIO_CLK_1               15
-
-static void gpio_line_config(u8 line, u32 direction)
-{
-        if (direction == IXP4XX_GPIO_IN)
-                *IXP4XX_GPIO_GPOER |= (1 << line);
-        else
-                *IXP4XX_GPIO_GPOER &= ~(1 << line);
-}
-
-static void gpio_line_get(u8 line, int *value)
-{
-        *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
-}
-
-static void gpio_line_set(u8 line, int value)
-{
-        if (value == IXP4XX_GPIO_HIGH)
-            *IXP4XX_GPIO_GPOUTR |= (1 << line);
-        else if (value == IXP4XX_GPIO_LOW)
-            *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
-}
-
-/*************************************************************************
- * IXP4xx chipset IRQ handling
- *
- * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
- *       (be it PCI or something else) configures that GPIO line
- *       as an IRQ.
- **************************************************************************/
-enum ixp4xx_irq_type {
-        IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
-};
-
-/* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
-static unsigned long long ixp4xx_irq_edge = 0;
-
-/*
- * IRQ -> GPIO mapping table
- */
-static signed char irq2gpio[32] = {
-        -1, -1, -1, -1, -1, -1,  0,  1,
-        -1, -1, -1, -1, -1, -1, -1, -1,
-        -1, -1, -1,  2,  3,  4,  5,  6,
-         7,  8,  9, 10, 11, 12, -1, -1,
-};
-
-static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
-{
-        int irq;
-
-        for (irq = 0; irq < 32; irq++) {
-                if (irq2gpio[irq] == gpio)
-                        return irq;
-        }
-        return -EINVAL;
-}
-
-static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
-{
-        int line = irq2gpio[d->irq];
-        u32 int_style;
-        enum ixp4xx_irq_type irq_type;
-        volatile u32 *int_reg;
-
-        /*
-         * Only for GPIO IRQs
-         */
-        if (line < 0)
-                return -EINVAL;
-
-        switch (type){
-        case IRQ_TYPE_EDGE_BOTH:
-                int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
-                irq_type = IXP4XX_IRQ_EDGE;
-                break;
-        case IRQ_TYPE_EDGE_RISING:
-                int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
-                irq_type = IXP4XX_IRQ_EDGE;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
-                irq_type = IXP4XX_IRQ_EDGE;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
-                irq_type = IXP4XX_IRQ_LEVEL;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
-                irq_type = IXP4XX_IRQ_LEVEL;
-                break;
-        default:
-                return -EINVAL;
-        }
-
-        if (irq_type == IXP4XX_IRQ_EDGE)
-                ixp4xx_irq_edge |= (1 << d->irq);
-        else
-                ixp4xx_irq_edge &= ~(1 << d->irq);
-
-        if (line >= 8) {        /* pins 8-15 */
-                line -= 8;
-                int_reg = IXP4XX_GPIO_GPIT2R;
-        } else {                /* pins 0-7 */
-                int_reg = IXP4XX_GPIO_GPIT1R;
-        }
-
-        /* Clear the style for the appropriate pin */
-        *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
-                        (line * IXP4XX_GPIO_STYLE_SIZE));
-
-        *IXP4XX_GPIO_GPISR = (1 << line);
-
-        /* Set the new style */
-        *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
-
-        /* Configure the line as an input */
-        gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
-
-        return 0;
-}
-
-static void ixp4xx_irq_mask(struct irq_data *d)
-{
-        if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
-                *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
-        else
-                *IXP4XX_ICMR &= ~(1 << d->irq);
-}
-
-static void ixp4xx_irq_ack(struct irq_data *d)
-{
-        int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
-
-        if (line >= 0)
-                *IXP4XX_GPIO_GPISR = (1 << line);
-}
-
-/*
- * Level triggered interrupts on GPIO lines can only be cleared when the
- * interrupt condition disappears.
- */
-static void ixp4xx_irq_unmask(struct irq_data *d)
-{
-        if (!(ixp4xx_irq_edge & (1 << d->irq)))
-                ixp4xx_irq_ack(d);
-
-        if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
-                *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
-        else
-                *IXP4XX_ICMR |= (1 << d->irq);
-}
-
-static struct irq_chip ixp4xx_irq_chip = {
-        .name           = "IXP4xx",
-        .irq_ack        = ixp4xx_irq_ack,
-        .irq_mask       = ixp4xx_irq_mask,
-        .irq_unmask     = ixp4xx_irq_unmask,
-        .irq_set_type   = ixp4xx_set_irq_type,
-};
-
 void __init ixp4xx_init_irq(void)
 {
-        int i = 0;
-
         /*
          * ixp4xx does not implement the XScale PWRMODE register
          * so it must not call cpu_do_idle().
          */
         cpu_idle_poll_ctrl(true);
 
-        /* Route all sources to IRQ instead of FIQ */
-        *IXP4XX_ICLR = 0x0;
-
-        /* Disable all interrupt */
-        *IXP4XX_ICMR = 0x0; 
-
-        if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
-                /* Route upper 32 sources to IRQ instead of FIQ */
-                *IXP4XX_ICLR2 = 0x00;
-
-                /* Disable upper 32 interrupts */
-                *IXP4XX_ICMR2 = 0x00;
-        }
-
-        /* Default to all level triggered */
-        for(i = 0; i < NR_IRQS; i++) {
-                irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
-                                         handle_level_irq);
-                irq_clear_status_flags(i, IRQ_NOREQUEST);
-        }
+        ixp4xx_irq_init(IXP4XX_INTC_BASE_PHYS,
+                        (cpu_is_ixp46x() || cpu_is_ixp43x()));
 }
 
-
-/*************************************************************************
- * IXP4xx timer tick
- * We use OS timer1 on the CPU for the timer tick and the timestamp 
- * counter as a source of real clock ticks to account for missed jiffies.
- *************************************************************************/
-
-static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
-{
-        struct clock_event_device *evt = dev_id;
-
-        /* Clear Pending Interrupt by writing '1' to it */
-        *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
-
-        evt->event_handler(evt);
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction ixp4xx_timer_irq = {
-        .name           = "timer1",
-        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = ixp4xx_timer_interrupt,
-        .dev_id         = &clockevent_ixp4xx,
-};
-
 void __init ixp4xx_timer_init(void)
 {
-        /* Reset/disable counter */
-        *IXP4XX_OSRT1 = 0;
-
-        /* Clear Pending Interrupt by writing '1' to it */
-        *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
-
-        /* Reset time-stamp counter */
-        *IXP4XX_OSTS = 0;
-
-        /* Connect the interrupt handler and enable the interrupt */
-        setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
-
-        ixp4xx_clocksource_init();
-        ixp4xx_clockevent_init();
+        return ixp4xx_timer_setup(IXP4XX_TIMER_BASE_PHYS,
+                                  IRQ_IXP4XX_TIMER1,
+                                  IXP4XX_TIMER_FREQ);
 }
 
 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
@@ -364,6 +113,24 @@ static struct resource ixp4xx_udc_resources[] = {
         },
 };
 
+static struct resource ixp4xx_gpio_resource[] = {
+        {
+                .start = IXP4XX_GPIO_BASE_PHYS,
+                .end = IXP4XX_GPIO_BASE_PHYS + 0xfff,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device ixp4xx_gpio_device = {
+        .name           = "ixp4xx-gpio",
+        .id             = -1,
+        .dev = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource = ixp4xx_gpio_resource,
+        .num_resources  = ARRAY_SIZE(ixp4xx_gpio_resource),
+};
+
 /*
  * USB device controller. The IXP4xx uses the same controller as PXA25X,
  * so we just use the same device.
@@ -378,7 +145,61 @@ static struct platform_device ixp4xx_udc_device = {
         },
 };
 
+static struct resource ixp4xx_npe_resources[] = {
+        {
+                .start = IXP4XX_NPEA_BASE_PHYS,
+                .end = IXP4XX_NPEA_BASE_PHYS + 0xfff,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IXP4XX_NPEB_BASE_PHYS,
+                .end = IXP4XX_NPEB_BASE_PHYS + 0xfff,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IXP4XX_NPEC_BASE_PHYS,
+                .end = IXP4XX_NPEC_BASE_PHYS + 0xfff,
+                .flags = IORESOURCE_MEM,
+        },
+
+};
+
+static struct platform_device ixp4xx_npe_device = {
+        .name           = "ixp4xx-npe",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(ixp4xx_npe_resources),
+        .resource       = ixp4xx_npe_resources,
+};
+
+static struct resource ixp4xx_qmgr_resources[] = {
+        {
+                .start = IXP4XX_QMGR_BASE_PHYS,
+                .end = IXP4XX_QMGR_BASE_PHYS + 0x3fff,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_IXP4XX_QM1,
+                .end = IRQ_IXP4XX_QM1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_IXP4XX_QM2,
+                .end = IRQ_IXP4XX_QM2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ixp4xx_qmgr_device = {
+        .name           = "ixp4xx-qmgr",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(ixp4xx_qmgr_resources),
+        .resource       = ixp4xx_qmgr_resources,
+};
+
 static struct platform_device *ixp4xx_devices[] __initdata = {
+        &ixp4xx_npe_device,
+        &ixp4xx_qmgr_device,
+        &ixp4xx_gpio_device,
         &ixp4xx_udc_device,
 };
 
@@ -413,56 +234,12 @@ static struct platform_device *ixp46x_devices[] __initdata = {
 unsigned long ixp4xx_exp_bus_size;
 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
 
-static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-{
-        gpio_line_config(gpio, IXP4XX_GPIO_IN);
-
-        return 0;
-}
-
-static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
-                                        int level)
-{
-        gpio_line_set(gpio, level);
-        gpio_line_config(gpio, IXP4XX_GPIO_OUT);
-
-        return 0;
-}
-
-static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
-{
-        int value;
-
-        gpio_line_get(gpio, &value);
-
-        return value;
-}
-
-static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
-                                  int value)
-{
-        gpio_line_set(gpio, value);
-}
-
-static struct gpio_chip ixp4xx_gpio_chip = {
-        .label                  = "IXP4XX_GPIO_CHIP",
-        .direction_input        = ixp4xx_gpio_direction_input,
-        .direction_output       = ixp4xx_gpio_direction_output,
-        .get                    = ixp4xx_gpio_get_value,
-        .set                    = ixp4xx_gpio_set_value,
-        .to_irq                 = ixp4xx_gpio_to_irq,
-        .base                   = 0,
-        .ngpio                  = 16,
-};
-
 void __init ixp4xx_sys_init(void)
 {
         ixp4xx_exp_bus_size = SZ_16M;
 
         platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
 
-        gpiochip_add_data(&ixp4xx_gpio_chip, NULL);
-
         if (cpu_is_ixp46x()) {
                 int region;
 
@@ -481,103 +258,8 @@ void __init ixp4xx_sys_init(void)
                         ixp4xx_exp_bus_size >> 20);
 }
 
-/*
- * sched_clock()
- */
-static u64 notrace ixp4xx_read_sched_clock(void)
-{
-        return *IXP4XX_OSTS;
-}
-
-/*
- * clocksource
- */
-
-static u64 ixp4xx_clocksource_read(struct clocksource *c)
-{
-        return *IXP4XX_OSTS;
-}
-
 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
 EXPORT_SYMBOL(ixp4xx_timer_freq);
-static void __init ixp4xx_clocksource_init(void)
-{
-        sched_clock_register(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
-
-        clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
-                        ixp4xx_clocksource_read);
-}
-
-/*
- * clockevents
- */
-static int ixp4xx_set_next_event(unsigned long evt,
-                                 struct clock_event_device *unused)
-{
-        unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
-
-        *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
-
-        return 0;
-}
-
-static int ixp4xx_shutdown(struct clock_event_device *evt)
-{
-        unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
-        unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
-
-        opts &= ~IXP4XX_OST_ENABLE;
-        *IXP4XX_OSRT1 = osrt | opts;
-        return 0;
-}
-
-static int ixp4xx_set_oneshot(struct clock_event_device *evt)
-{
-        unsigned long opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
-        unsigned long osrt = 0;
-
-        /* period set by 'set next_event' */
-        *IXP4XX_OSRT1 = osrt | opts;
-        return 0;
-}
-
-static int ixp4xx_set_periodic(struct clock_event_device *evt)
-{
-        unsigned long opts = IXP4XX_OST_ENABLE;
-        unsigned long osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK;
-
-        *IXP4XX_OSRT1 = osrt | opts;
-        return 0;
-}
-
-static int ixp4xx_resume(struct clock_event_device *evt)
-{
-        unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
-        unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
-
-        opts |= IXP4XX_OST_ENABLE;
-        *IXP4XX_OSRT1 = osrt | opts;
-        return 0;
-}
-
-static struct clock_event_device clockevent_ixp4xx = {
-        .name                   = "ixp4xx timer1",
-        .features               = CLOCK_EVT_FEAT_PERIODIC |
-                                  CLOCK_EVT_FEAT_ONESHOT,
-        .rating                 = 200,
-        .set_state_shutdown     = ixp4xx_shutdown,
-        .set_state_periodic     = ixp4xx_set_periodic,
-        .set_state_oneshot      = ixp4xx_set_oneshot,
-        .tick_resume            = ixp4xx_resume,
-        .set_next_event         = ixp4xx_set_next_event,
-};
-
-static void __init ixp4xx_clockevent_init(void)
-{
-        clockevent_ixp4xx.cpumask = cpumask_of(0);
-        clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
-                                        0xf, 0xfffffffe);
-}
 
 void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
 {
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c
index 5d14ce2aee6d..a16c35d2bb96 100644
--- a/arch/arm/mach-ixp4xx/coyote-pci.c
+++ b/arch/arm/mach-ixp4xx/coyote-pci.c
@@ -23,6 +23,8 @@
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 
+#include "irqs.h"
+
 #define SLOT0_DEVID     14
 #define SLOT1_DEVID     15
 
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 7e40fe70933b..7ca43ca2816d 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -25,6 +25,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
+#include "irqs.h"
+
 #define COYOTE_IDE_BASE_PHYS    IXP4XX_EXP_BUS_BASE(3)
 #define COYOTE_IDE_BASE_VIRT    0xFFFE1000
 #define COYOTE_IDE_REGION_SIZE  0x1000
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c
index 8dca76937723..6899023bd1b7 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-pci.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c
@@ -22,6 +22,8 @@
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 
+#include "irqs.h"
+
 #define MAX_DEV         4
 #define IRQ_LINES       3
 
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 397190f3a8da..4d4c62fced71 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -35,6 +35,8 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/time.h>
 
+#include "irqs.h"
+
 #define DSMG600_SDA_PIN         5
 #define DSMG600_SCL_PIN         4
 
@@ -268,9 +270,6 @@ static void __init dsmg600_init(void)
 {
         ixp4xx_sys_init();
 
-        /* Make sure that GPIO14 and GPIO15 are not used as clocks */
-        *IXP4XX_GPIO_GPCLKR = 0;
-
         dsmg600_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
         dsmg600_flash_resource.end =
                 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c
index fd4a8625b4ae..6c08bb9d9807 100644
--- a/arch/arm/mach-ixp4xx/fsg-pci.c
+++ b/arch/arm/mach-ixp4xx/fsg-pci.c
@@ -22,6 +22,8 @@
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 
+#include "irqs.h"
+
 #define MAX_DEV         3
 #define IRQ_LINES       3
 
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index f0a152e365b1..648932d8d7a8 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -29,6 +29,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
+#include "irqs.h"
+
 #define FSG_SDA_PIN             12
 #define FSG_SCL_PIN             13
 
diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c
index d9d6cc089707..903c75330b76 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-pci.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c
@@ -27,6 +27,8 @@
 
 #include <asm/mach/pci.h>
 
+#include "irqs.h"
+
 void __init gateway7001_pci_preinit(void)
 {
         irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index 1be6faf6da9a..678e7dfff0e5 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -28,6 +28,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
+#include "irqs.h"
+
 static struct flash_platform_data gateway7001_flash_data = {
         .map_name       = "cfi_probe",
         .width          = 2,
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
index 551d114c9e14..1223d160448f 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
@@ -30,6 +30,8 @@
 #include <mach/hardware.h>
 #include <asm/mach/pci.h>
 
+#include "irqs.h"
+
 #define SLOT0_DEVID     0
 #define SLOT1_DEVID     1
 #define INTA            10 /* slot 1 has INTA and INTB crossed */
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 16a12994fb53..5dbdde8e2338 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -36,6 +36,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
+#include "irqs.h"
+
 /* GPIO 5,6,7 and 12 are hard wired to the Kendin KS8995M Switch
    and operate as an SPI type interface.  The details of the interface
    are available on Kendin/Micrel's web site. */
diff --git a/arch/arm/mach-ixp4xx/include/mach/entry-macro.S b/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
deleted file mode 100644
index 79adf83e2c3d..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for IXP4xx-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
-                ldr     \irqstat, [\irqstat]            @ get interrupts
-                cmp     \irqstat, #0
-                beq     1001f                           @ upper IRQ?
-                clz     \irqnr, \irqstat
-                mov     \base, #31
-                sub     \irqnr, \base, \irqnr
-                b       1002f                           @ lower IRQ being
-                                                        @ handled
-
-1001:
-                /*
-                 * IXP465/IXP435 has an upper IRQ status register
-                 */
-#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
-                ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
-                ldr     \irqstat, [\irqstat]            @ get upper interrupts
-                mov     \irqnr, #63
-                clz     \irqstat, \irqstat
-                cmp     \irqstat, #32
-                subne   \irqnr, \irqnr, \irqstat
-#endif
-1002:
-                .endm
-
-
diff --git a/arch/arm/mach-ixp4xx/include/mach/irqs.h b/arch/arm/mach-ixp4xx/include/mach/irqs.h
deleted file mode 100644
index 7e6d4cce7c27..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/irqs.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/irqs.h 
- *
- * IRQ definitions for IXP4XX based systems
- *
- * Copyright (C) 2002 Intel Corporation.
- * Copyright (C) 2003 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef _ARCH_IXP4XX_IRQS_H_
-#define _ARCH_IXP4XX_IRQS_H_
-
-#define IRQ_IXP4XX_NPEA         0
-#define IRQ_IXP4XX_NPEB         1
-#define IRQ_IXP4XX_NPEC         2
-#define IRQ_IXP4XX_QM1          3
-#define IRQ_IXP4XX_QM2          4
-#define IRQ_IXP4XX_TIMER1       5
-#define IRQ_IXP4XX_GPIO0        6
-#define IRQ_IXP4XX_GPIO1        7
-#define IRQ_IXP4XX_PCI_INT      8
-#define IRQ_IXP4XX_PCI_DMA1     9
-#define IRQ_IXP4XX_PCI_DMA2     10
-#define IRQ_IXP4XX_TIMER2       11
-#define IRQ_IXP4XX_USB          12
-#define IRQ_IXP4XX_UART2        13
-#define IRQ_IXP4XX_TIMESTAMP    14
-#define IRQ_IXP4XX_UART1        15
-#define IRQ_IXP4XX_WDOG         16
-#define IRQ_IXP4XX_AHB_PMU      17
-#define IRQ_IXP4XX_XSCALE_PMU   18
-#define IRQ_IXP4XX_GPIO2        19
-#define IRQ_IXP4XX_GPIO3        20
-#define IRQ_IXP4XX_GPIO4        21
-#define IRQ_IXP4XX_GPIO5        22
-#define IRQ_IXP4XX_GPIO6        23
-#define IRQ_IXP4XX_GPIO7        24
-#define IRQ_IXP4XX_GPIO8        25
-#define IRQ_IXP4XX_GPIO9        26
-#define IRQ_IXP4XX_GPIO10       27
-#define IRQ_IXP4XX_GPIO11       28
-#define IRQ_IXP4XX_GPIO12       29
-#define IRQ_IXP4XX_SW_INT1      30
-#define IRQ_IXP4XX_SW_INT2      31
-#define IRQ_IXP4XX_USB_HOST     32
-#define IRQ_IXP4XX_I2C          33
-#define IRQ_IXP4XX_SSP          34
-#define IRQ_IXP4XX_TSYNC        35
-#define IRQ_IXP4XX_EAU_DONE     36
-#define IRQ_IXP4XX_SHA_DONE     37
-#define IRQ_IXP4XX_SWCP_PE      58
-#define IRQ_IXP4XX_QM_PE        60
-#define IRQ_IXP4XX_MCU_ECC      61
-#define IRQ_IXP4XX_EXP_PE       62
-
-#define _IXP4XX_GPIO_IRQ(n)     (IRQ_IXP4XX_GPIO ## n)
-#define IXP4XX_GPIO_IRQ(n)      _IXP4XX_GPIO_IRQ(n)
-
-/*
- * Only first 32 sources are valid if running on IXP42x systems
- */
-#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
-#define NR_IRQS                 64
-#else
-#define NR_IRQS                 32
-#endif
-
-#define XSCALE_PMU_IRQ          (IRQ_IXP4XX_XSCALE_PMU)
-
-#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
index b7ddd27419c2..588b76651085 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -43,8 +43,6 @@
  * Queue Manager
  */
 #define IXP4XX_QMGR_BASE_PHYS           0x60000000
-#define IXP4XX_QMGR_BASE_VIRT           IOMEM(0xFEF15000)
-#define IXP4XX_QMGR_REGION_SIZE         0x00004000
 
 /*
  * Peripheral space, including debug UART. Must be section-aligned so that
@@ -132,9 +130,6 @@
 #define IXP4XX_INTC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
 #define IXP4XX_GPIO_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
 #define IXP4XX_TIMER_BASE_VIRT          (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
-#define IXP4XX_NPEA_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x6000)
-#define IXP4XX_NPEB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x7000)
-#define IXP4XX_NPEC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x8000)
 #define IXP4XX_EthB_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
 #define IXP4XX_EthC_BASE_VIRT           (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
 #define IXP4XX_USB_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
@@ -148,95 +143,6 @@
 #define IXP4XX_SSP_BASE_VIRT            (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
 
 /*
- * Constants to make it easy to access  Interrupt Controller registers
- */
-#define IXP4XX_ICPR_OFFSET      0x00 /* Interrupt Status */
-#define IXP4XX_ICMR_OFFSET      0x04 /* Interrupt Enable */
-#define IXP4XX_ICLR_OFFSET      0x08 /* Interrupt IRQ/FIQ Select */
-#define IXP4XX_ICIP_OFFSET      0x0C /* IRQ Status */
-#define IXP4XX_ICFP_OFFSET      0x10 /* FIQ Status */
-#define IXP4XX_ICHR_OFFSET      0x14 /* Interrupt Priority */
-#define IXP4XX_ICIH_OFFSET      0x18 /* IRQ Highest Pri Int */
-#define IXP4XX_ICFH_OFFSET      0x1C /* FIQ Highest Pri Int */
-
-/*
- * IXP465-only
- */
-#define IXP4XX_ICPR2_OFFSET     0x20 /* Interrupt Status 2 */
-#define IXP4XX_ICMR2_OFFSET     0x24 /* Interrupt Enable 2 */
-#define IXP4XX_ICLR2_OFFSET     0x28 /* Interrupt IRQ/FIQ Select 2 */
-#define IXP4XX_ICIP2_OFFSET     0x2C /* IRQ Status */
-#define IXP4XX_ICFP2_OFFSET     0x30 /* FIQ Status */
-#define IXP4XX_ICEEN_OFFSET     0x34 /* Error High Pri Enable */
-
-
-/*
- * Interrupt Controller Register Definitions.
- */
-
-#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
-
-#define IXP4XX_ICPR     IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
-#define IXP4XX_ICMR     IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
-#define IXP4XX_ICLR     IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
-#define IXP4XX_ICIP     IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
-#define IXP4XX_ICFP     IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
-#define IXP4XX_ICHR     IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
-#define IXP4XX_ICIH     IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET) 
-#define IXP4XX_ICFH     IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
-#define IXP4XX_ICPR2    IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
-#define IXP4XX_ICMR2    IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
-#define IXP4XX_ICLR2    IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
-#define IXP4XX_ICIP2    IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
-#define IXP4XX_ICFP2    IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
-#define IXP4XX_ICEEN    IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
-                                                                                
-/*
- * Constants to make it easy to access GPIO registers
- */
-#define IXP4XX_GPIO_GPOUTR_OFFSET       0x00
-#define IXP4XX_GPIO_GPOER_OFFSET        0x04
-#define IXP4XX_GPIO_GPINR_OFFSET        0x08
-#define IXP4XX_GPIO_GPISR_OFFSET        0x0C
-#define IXP4XX_GPIO_GPIT1R_OFFSET       0x10
-#define IXP4XX_GPIO_GPIT2R_OFFSET       0x14
-#define IXP4XX_GPIO_GPCLKR_OFFSET       0x18
-#define IXP4XX_GPIO_GPDBSELR_OFFSET     0x1C
-
-/* 
- * GPIO Register Definitions.
- * [Only perform 32bit reads/writes]
- */
-#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
-
-#define IXP4XX_GPIO_GPOUTR      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
-#define IXP4XX_GPIO_GPOER       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
-#define IXP4XX_GPIO_GPINR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
-#define IXP4XX_GPIO_GPISR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
-#define IXP4XX_GPIO_GPIT1R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
-#define IXP4XX_GPIO_GPIT2R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
-#define IXP4XX_GPIO_GPCLKR      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
-#define IXP4XX_GPIO_GPDBSELR    IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
-
-/*
- * GPIO register bit definitions
- */
-
-/* Interrupt styles
- */
-#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH   0x0
-#define IXP4XX_GPIO_STYLE_ACTIVE_LOW    0x1
-#define IXP4XX_GPIO_STYLE_RISING_EDGE   0x2
-#define IXP4XX_GPIO_STYLE_FALLING_EDGE  0x3
-#define IXP4XX_GPIO_STYLE_TRANSITIONAL  0x4
-
-/* 
- * Mask used to clear interrupt styles 
- */
-#define IXP4XX_GPIO_STYLE_CLEAR         0x7
-#define IXP4XX_GPIO_STYLE_SIZE          3
-
-/*
  * Constants to make it easy to access Timer Control/Status registers
  */
 #define IXP4XX_OSTS_OFFSET      0x00  /* Continious TimeStamp */
diff --git a/arch/arm/mach-ixp4xx/include/mach/qmgr.h b/arch/arm/mach-ixp4xx/include/mach/qmgr.h
deleted file mode 100644
index 4de8da536dbb..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/qmgr.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of version 2 of the GNU General Public License
- * as published by the Free Software Foundation.
- */
-
-#ifndef IXP4XX_QMGR_H
-#define IXP4XX_QMGR_H
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-
-#define DEBUG_QMGR      0
-
-#define HALF_QUEUES     32
-#define QUEUES          64
-#define MAX_QUEUE_LENGTH 4      /* in dwords */
-
-#define QUEUE_STAT1_EMPTY               1 /* queue status bits */
-#define QUEUE_STAT1_NEARLY_EMPTY        2
-#define QUEUE_STAT1_NEARLY_FULL         4
-#define QUEUE_STAT1_FULL                8
-#define QUEUE_STAT2_UNDERFLOW           1
-#define QUEUE_STAT2_OVERFLOW            2
-
-#define QUEUE_WATERMARK_0_ENTRIES       0
-#define QUEUE_WATERMARK_1_ENTRY         1
-#define QUEUE_WATERMARK_2_ENTRIES       2
-#define QUEUE_WATERMARK_4_ENTRIES       3
-#define QUEUE_WATERMARK_8_ENTRIES       4
-#define QUEUE_WATERMARK_16_ENTRIES      5
-#define QUEUE_WATERMARK_32_ENTRIES      6
-#define QUEUE_WATERMARK_64_ENTRIES      7
-
-/* queue interrupt request conditions */
-#define QUEUE_IRQ_SRC_EMPTY             0
-#define QUEUE_IRQ_SRC_NEARLY_EMPTY      1
-#define QUEUE_IRQ_SRC_NEARLY_FULL       2
-#define QUEUE_IRQ_SRC_FULL              3
-#define QUEUE_IRQ_SRC_NOT_EMPTY         4
-#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY  5
-#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL   6
-#define QUEUE_IRQ_SRC_NOT_FULL          7
-
-struct qmgr_regs {
-        u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
-        u32 stat1[4];           /* 0x400 - 0x40F */
-        u32 stat2[2];           /* 0x410 - 0x417 */
-        u32 statne_h;           /* 0x418 - queue nearly empty */
-        u32 statf_h;            /* 0x41C - queue full */
-        u32 irqsrc[4];          /* 0x420 - 0x42F IRC source */
-        u32 irqen[2];           /* 0x430 - 0x437 IRQ enabled */
-        u32 irqstat[2];         /* 0x438 - 0x43F - IRQ access only */
-        u32 reserved[1776];
-        u32 sram[2048];         /* 0x2000 - 0x3FFF - config and buffer */
-};
-
-void qmgr_set_irq(unsigned int queue, int src,
-                  void (*handler)(void *pdev), void *pdev);
-void qmgr_enable_irq(unsigned int queue);
-void qmgr_disable_irq(unsigned int queue);
-
-/* request_ and release_queue() must be called from non-IRQ context */
-
-#if DEBUG_QMGR
-extern char qmgr_queue_descs[QUEUES][32];
-
-int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
-                       unsigned int nearly_empty_watermark,
-                       unsigned int nearly_full_watermark,
-                       const char *desc_format, const char* name);
-#else
-int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
-                         unsigned int nearly_empty_watermark,
-                         unsigned int nearly_full_watermark);
-#define qmgr_request_queue(queue, len, nearly_empty_watermark,          \
-                           nearly_full_watermark, desc_format, name)    \
-        __qmgr_request_queue(queue, len, nearly_empty_watermark,        \
-                             nearly_full_watermark)
-#endif
-
-void qmgr_release_queue(unsigned int queue);
-
-
-static inline void qmgr_put_entry(unsigned int queue, u32 val)
-{
-        struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
-#if DEBUG_QMGR
-        BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
-
-        printk(KERN_DEBUG "Queue %s(%i) put %X\n",
-               qmgr_queue_descs[queue], queue, val);
-#endif
-        __raw_writel(val, &qmgr_regs->acc[queue][0]);
-}
-
-static inline u32 qmgr_get_entry(unsigned int queue)
-{
-        u32 val;
-        const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
-        val = __raw_readl(&qmgr_regs->acc[queue][0]);
-#if DEBUG_QMGR
-        BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
-
-        printk(KERN_DEBUG "Queue %s(%i) get %X\n",
-               qmgr_queue_descs[queue], queue, val);
-#endif
-        return val;
-}
-
-static inline int __qmgr_get_stat1(unsigned int queue)
-{
-        const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
-        return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
-                >> ((queue & 7) << 2)) & 0xF;
-}
-
-static inline int __qmgr_get_stat2(unsigned int queue)
-{
-        const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
-        BUG_ON(queue >= HALF_QUEUES);
-        return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
-                >> ((queue & 0xF) << 1)) & 0x3;
-}
-
-/**
- * qmgr_stat_empty() - checks if a hardware queue is empty
- * @queue:      queue number
- *
- * Returns non-zero value if the queue is empty.
- */
-static inline int qmgr_stat_empty(unsigned int queue)
-{
-        BUG_ON(queue >= HALF_QUEUES);
-        return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY;
-}
-
-/**
- * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
- * @queue:      queue number
- *
- * Returns non-zero value if the queue is below low watermark.
- */
-static inline int qmgr_stat_below_low_watermark(unsigned int queue)
-{
-        const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
-        if (queue >= HALF_QUEUES)
-                return (__raw_readl(&qmgr_regs->statne_h) >>
-                        (queue - HALF_QUEUES)) & 0x01;
-        return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY;
-}
-
-/**
- * qmgr_stat_above_high_watermark() - checks if a queue is above high watermark
- * @queue:      queue number
- *
- * Returns non-zero value if the queue is above high watermark
- */
-static inline int qmgr_stat_above_high_watermark(unsigned int queue)
-{
-        BUG_ON(queue >= HALF_QUEUES);
-        return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL;
-}
-
-/**
- * qmgr_stat_full() - checks if a hardware queue is full
- * @queue:      queue number
- *
- * Returns non-zero value if the queue is full.
- */
-static inline int qmgr_stat_full(unsigned int queue)
-{
-        const struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
-        if (queue >= HALF_QUEUES)
-                return (__raw_readl(&qmgr_regs->statf_h) >>
-                        (queue - HALF_QUEUES)) & 0x01;
-        return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL;
-}
-
-/**
- * qmgr_stat_underflow() - checks if a hardware queue experienced underflow
- * @queue:      queue number
- *
- * Returns non-zero value if the queue experienced underflow.
- */
-static inline int qmgr_stat_underflow(unsigned int queue)
-{
-        return __qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW;
-}
-
-/**
- * qmgr_stat_overflow() - checks if a hardware queue experienced overflow
- * @queue:      queue number
- *
- * Returns non-zero value if the queue experienced overflow.
- */
-static inline int qmgr_stat_overflow(unsigned int queue)
-{
-        return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW;
-}
-
-#endif
diff --git a/arch/arm/mach-ixp4xx/irqs.h b/arch/arm/mach-ixp4xx/irqs.h
new file mode 100644
index 000000000000..6b7f220cf9e0
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/irqs.h
@@ -0,0 +1,68 @@
+/*
+ * arch/arm/mach-ixp4xx/include/mach/irqs.h 
+ *
+ * IRQ definitions for IXP4XX based systems
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ARCH_IXP4XX_IRQS_H_
+#define _ARCH_IXP4XX_IRQS_H_
+
+#define IRQ_IXP4XX_BASE         16
+
+#define IRQ_IXP4XX_NPEA         (IRQ_IXP4XX_BASE + 0)
+#define IRQ_IXP4XX_NPEB         (IRQ_IXP4XX_BASE + 1)
+#define IRQ_IXP4XX_NPEC         (IRQ_IXP4XX_BASE + 2)
+#define IRQ_IXP4XX_QM1          (IRQ_IXP4XX_BASE + 3)
+#define IRQ_IXP4XX_QM2          (IRQ_IXP4XX_BASE + 4)
+#define IRQ_IXP4XX_TIMER1       (IRQ_IXP4XX_BASE + 5)
+#define IRQ_IXP4XX_GPIO0        (IRQ_IXP4XX_BASE + 6)
+#define IRQ_IXP4XX_GPIO1        (IRQ_IXP4XX_BASE + 7)
+#define IRQ_IXP4XX_PCI_INT      (IRQ_IXP4XX_BASE + 8)
+#define IRQ_IXP4XX_PCI_DMA1     (IRQ_IXP4XX_BASE + 9)
+#define IRQ_IXP4XX_PCI_DMA2     (IRQ_IXP4XX_BASE + 10)
+#define IRQ_IXP4XX_TIMER2       (IRQ_IXP4XX_BASE + 11)
+#define IRQ_IXP4XX_USB          (IRQ_IXP4XX_BASE + 12)
+#define IRQ_IXP4XX_UART2        (IRQ_IXP4XX_BASE + 13)
+#define IRQ_IXP4XX_TIMESTAMP    (IRQ_IXP4XX_BASE + 14)
+#define IRQ_IXP4XX_UART1        (IRQ_IXP4XX_BASE + 15)
+#define IRQ_IXP4XX_WDOG         (IRQ_IXP4XX_BASE + 16)
+#define IRQ_IXP4XX_AHB_PMU      (IRQ_IXP4XX_BASE + 17)
+#define IRQ_IXP4XX_XSCALE_PMU   (IRQ_IXP4XX_BASE + 18)
+#define IRQ_IXP4XX_GPIO2        (IRQ_IXP4XX_BASE + 19)
+#define IRQ_IXP4XX_GPIO3        (IRQ_IXP4XX_BASE + 20)
+#define IRQ_IXP4XX_GPIO4        (IRQ_IXP4XX_BASE + 21)
+#define IRQ_IXP4XX_GPIO5        (IRQ_IXP4XX_BASE + 22)
+#define IRQ_IXP4XX_GPIO6        (IRQ_IXP4XX_BASE + 23)
+#define IRQ_IXP4XX_GPIO7        (IRQ_IXP4XX_BASE + 24)
+#define IRQ_IXP4XX_GPIO8        (IRQ_IXP4XX_BASE + 25)
+#define IRQ_IXP4XX_GPIO9        (IRQ_IXP4XX_BASE + 26)
+#define IRQ_IXP4XX_GPIO10       (IRQ_IXP4XX_BASE + 27)
+#define IRQ_IXP4XX_GPIO11       (IRQ_IXP4XX_BASE + 28)
+#define IRQ_IXP4XX_GPIO12       (IRQ_IXP4XX_BASE + 29)
+#define IRQ_IXP4XX_SW_INT1      (IRQ_IXP4XX_BASE + 30)
+#define IRQ_IXP4XX_SW_INT2      (IRQ_IXP4XX_BASE + 31)
+#define IRQ_IXP4XX_USB_HOST     (IRQ_IXP4XX_BASE + 32)
+#define IRQ_IXP4XX_I2C          (IRQ_IXP4XX_BASE + 33)
+#define IRQ_IXP4XX_SSP          (IRQ_IXP4XX_BASE + 34)
+#define IRQ_IXP4XX_TSYNC        (IRQ_IXP4XX_BASE + 35)
+#define IRQ_IXP4XX_EAU_DONE     (IRQ_IXP4XX_BASE + 36)
+#define IRQ_IXP4XX_SHA_DONE     (IRQ_IXP4XX_BASE + 37)
+#define IRQ_IXP4XX_SWCP_PE      (IRQ_IXP4XX_BASE + 58)
+#define IRQ_IXP4XX_QM_PE        (IRQ_IXP4XX_BASE + 60)
+#define IRQ_IXP4XX_MCU_ECC      (IRQ_IXP4XX_BASE + 61)
+#define IRQ_IXP4XX_EXP_PE       (IRQ_IXP4XX_BASE + 62)
+
+#define _IXP4XX_GPIO_IRQ(n)     (IRQ_IXP4XX_GPIO ## n)
+#define IXP4XX_GPIO_IRQ(n)      _IXP4XX_GPIO_IRQ(n)
+
+#define XSCALE_PMU_IRQ          (IRQ_IXP4XX_XSCALE_PMU)
+
+#endif
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c
index 318424dd3c50..c1340465b2ea 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -24,6 +24,8 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 
+#include "irqs.h"
+
 #define MAX_DEV         4
 #define IRQ_LINES       4
 
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 57d7df79d838..6f0f7ed18ea8 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -32,6 +32,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
+#include "irqs.h"
+
 #define IXDP425_SDA_PIN         7
 #define IXDP425_SCL_PIN         6
 
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
index 1f8717ba13dc..ac0e9bc6eb4d 100644
--- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
@@ -23,6 +23,8 @@
 
 #include <asm/mach/pci.h>
 
+#include "irqs.h"
+
 void __init ixdpg425_pci_preinit(void)
 {
         irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
diff --git a/arch/arm/mach-ixp4xx/ixp4xx-of.c b/arch/arm/mach-ixp4xx/ixp4xx-of.c
new file mode 100644
index 000000000000..7449b8319c8a
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/ixp4xx-of.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IXP4xx Device Tree boot support
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/ixp4xx-regs.h>
+
+static struct map_desc ixp4xx_of_io_desc[] __initdata = {
+        /*
+         * This is needed for runtime system configuration checks,
+         * such as reading if hardware so-and-so is present. This
+         * could eventually be converted into a syscon once all boards
+         * are converted to device tree.
+         */
+        {
+                .virtual = IXP4XX_EXP_CFG_BASE_VIRT,
+                .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
+                .length = SZ_4K,
+                .type = MT_DEVICE,
+        },
+#ifdef CONFIG_DEBUG_UART_8250
+        /* This is needed for LL-debug/earlyprintk/debug-macro.S */
+        {
+                .virtual = CONFIG_DEBUG_UART_VIRT,
+                .pfn = __phys_to_pfn(CONFIG_DEBUG_UART_PHYS),
+                .length = SZ_4K,
+                .type = MT_DEVICE,
+        },
+#endif
+};
+
+static void __init ixp4xx_of_map_io(void)
+{
+        iotable_init(ixp4xx_of_io_desc, ARRAY_SIZE(ixp4xx_of_io_desc));
+}
+
+/*
+ * We handle 4 differen SoC families. These compatible strings are enough
+ * to provide the core so that different boards can add their more detailed
+ * specifics.
+ */
+static const char *ixp4xx_of_board_compat[] = {
+        "intel,ixp42x",
+        "intel,ixp43x",
+        "intel,ixp45x",
+        "intel,ixp46x",
+        NULL,
+};
+
+DT_MACHINE_START(IXP4XX_DT, "IXP4xx (Device Tree)")
+        .map_io         = ixp4xx_of_map_io,
+        .dt_compat      = ixp4xx_of_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c
index 8f0eba0a6800..925ef805f966 100644
--- a/arch/arm/mach-ixp4xx/nas100d-pci.c
+++ b/arch/arm/mach-ixp4xx/nas100d-pci.c
@@ -21,6 +21,8 @@
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 
+#include "irqs.h"
+
 #define MAX_DEV         3
 #define IRQ_LINES       3
 
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index 4138d6aa4c52..c142cfa8c5d6 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -34,6 +34,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
+#include "irqs.h"
+
 #define NAS100D_SDA_PIN         5
 #define NAS100D_SCL_PIN         6
 
@@ -279,9 +281,6 @@ static void __init nas100d_init(void)
 
         ixp4xx_sys_init();
 
-        /* gpio 14 and 15 are _not_ clocks */
-        *IXP4XX_GPIO_GPCLKR = 0;
-
         nas100d_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
         nas100d_flash_resource.end =
                 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c
index 032defe111aa..d69ee4066d20 100644
--- a/arch/arm/mach-ixp4xx/nslu2-pci.c
+++ b/arch/arm/mach-ixp4xx/nslu2-pci.c
@@ -21,6 +21,8 @@
 #include <asm/mach/pci.h>
 #include <asm/mach-types.h>
 
+#include "irqs.h"
+
 #define MAX_DEV         3
 #define IRQ_LINES       3
 
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index 341b263482ef..ee1877fcfafe 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -32,6 +32,8 @@
 #include <asm/mach/flash.h>
 #include <asm/mach/time.h>
 
+#include "irqs.h"
+
 #define NSLU2_SDA_PIN           7
 #define NSLU2_SCL_PIN           6
 
@@ -125,10 +127,18 @@ static struct platform_device nslu2_i2c_gpio = {
         },
 };
 
+static struct resource nslu2_beeper_resources[] = {
+        {
+                .start  = IRQ_IXP4XX_TIMER2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
 static struct platform_device nslu2_beeper = {
         .name                   = "ixp4xx-beeper",
         .id                     = NSLU2_GPIO_BUZZ,
-        .num_resources          = 0,
+        .resource               = nslu2_beeper_resources,
+        .num_resources          = ARRAY_SIZE(nslu2_beeper_resources),
 };
 
 static struct resource nslu2_uart_resources[] = {
diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c
index c92e5b82af36..cf83f7e24179 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-pci.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c
@@ -27,6 +27,8 @@
 
 #include <asm/mach/pci.h>
 
+#include "irqs.h"
+
 void __init wg302v2_pci_preinit(void)
 {
         irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index 90b3c604e8b6..8711e299229b 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -29,6 +29,8 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
 
+#include "irqs.h"
+
 static struct flash_platform_data wg302v2_flash_data = {
         .map_name       = "cfi_probe",
         .width          = 2,
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index b3be60a8e467..66701bf43248 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Platform support for LPC32xx SoC
  *
@@ -5,44 +6,14 @@
  *
  * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
  * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/clcd.h>
 #include <linux/amba/pl08x.h>
-#include <linux/amba/mmci.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/clk.h>
-#include <linux/mtd/lpc32xx_slc.h>
 #include <linux/mtd/lpc32xx_mlc.h>
+#include <linux/mtd/lpc32xx_slc.h>
+#include <linux/of_platform.h>
 
-#include <asm/setup.h>
-#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <mach/board.h>
 #include "common.h"
 
 static struct pl08x_channel_data pl08x_slave_channels[] = {
@@ -90,8 +61,6 @@ static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
 };
 
 static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL),
-        OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL),
         OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
         OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
                        &lpc32xx_slc_data),
@@ -104,11 +73,6 @@ static void __init lpc3250_machine_init(void)
 {
         lpc32xx_serial_init();
 
-        /* Test clock needed for UDA1380 initial init */
-        __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
-                LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
-                LPC32XX_CLKPWR_TEST_CLK_SEL);
-
         of_platform_default_populate(NULL, lpc32xx_auxdata_lookup, NULL);
 }
 
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 129455e822e4..6316da3623b3 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -336,6 +336,15 @@ static inline void omap5_secondary_hyp_startup(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_DRA7XX
+extern int dra7xx_pciess_reset(struct omap_hwmod *oh);
+#else
+static inline int dra7xx_pciess_reset(struct omap_hwmod *oh)
+{
+        return 0;
+}
+#endif
+
 void pdata_quirks_init(const struct of_device_id *);
 void omap_auxdata_legacy_init(struct device *dev);
 void omap_pcs_legacy_init(int irq, void (*rearm)(void));
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index 37ff25ee3d89..1d8efc303daf 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -53,15 +53,10 @@ int omap_i2c_reset(struct omap_hwmod *oh)
         u16 i2c_con;
         int c = 0;
 
-        if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
-                i2c_con = OMAP4_I2C_CON_OFFSET;
-        } else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
+        if (soc_is_omap24xx() || soc_is_omap34xx() || soc_is_am35xx())
                 i2c_con = OMAP2_I2C_CON_OFFSET;
-        } else {
-                WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
-                     oh->name);
-                return -EINVAL;
-        }
+        else
+                i2c_con = OMAP4_I2C_CON_OFFSET;
 
         /* Disable I2C */
         v = omap_hwmod_read(oh, i2c_con);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index bb8e0bb7ef5d..5e69c8caa1db 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -411,14 +411,9 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
 
 static void __init __maybe_unused omap_hwmod_init_postsetup(void)
 {
-        u8 postsetup_state;
+        u8 postsetup_state = _HWMOD_STATE_DEFAULT;
 
         /* Set the default postsetup state for all hwmods */
-#ifdef CONFIG_PM
-        postsetup_state = _HWMOD_STATE_IDLE;
-#else
-        postsetup_state = _HWMOD_STATE_ENABLED;
-#endif
         omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
 }
 
diff --git a/arch/arm/mach-omap2/mmc.h b/arch/arm/mach-omap2/mmc.h
index 9145a6f720fc..7f4e053c3434 100644
--- a/arch/arm/mach-omap2/mmc.h
+++ b/arch/arm/mach-omap2/mmc.h
@@ -7,7 +7,15 @@
 #define OMAP4_MMC_REG_OFFSET    0x100
 
 struct omap_hwmod;
+
+#ifdef CONFIG_SOC_OMAP2420
 int omap_msdi_reset(struct omap_hwmod *oh);
+#else
+static inline int omap_msdi_reset(struct omap_hwmod *oh)
+{
+        return 0;
+}
+#endif
 
 /* called from board-specific card detection service routine */
 extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 17558be4bf0a..7dcbe1736f7e 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -436,13 +436,13 @@ static int irq_notifier(struct notifier_block *self, unsigned long cmd,	void *v)
 {
         switch (cmd) {
         case CPU_CLUSTER_PM_ENTER:
-                if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+                if (omap_type() == OMAP2_DEVICE_TYPE_GP || soc_is_am43xx())
                         irq_save_context();
                 else
                         irq_save_secure_context();
                 break;
         case CPU_CLUSTER_PM_EXIT:
-                if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+                if (omap_type() == OMAP2_DEVICE_TYPE_GP || soc_is_am43xx())
                         irq_restore_context();
                 break;
         }
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index baadddf9aad4..405ac24def05 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -155,6 +155,8 @@
 #include "soc.h"
 #include "common.h"
 #include "clockdomain.h"
+#include "hdq1w.h"
+#include "mmc.h"
 #include "powerdomain.h"
 #include "cm2xxx.h"
 #include "cm3xxx.h"
@@ -165,6 +167,7 @@
 #include "prm33xx.h"
 #include "prminst44xx.h"
 #include "pm.h"
+#include "wd_timer.h"
 
 /* Name of the OMAP hwmod for the MPU */
 #define MPU_INITIATOR_NAME              "mpu"
@@ -205,6 +208,20 @@ struct clkctrl_provider {
 static LIST_HEAD(clkctrl_providers);
 
 /**
+ * struct omap_hwmod_reset - IP specific reset functions
+ * @match: string to match against the module name
+ * @len: number of characters to match
+ * @reset: IP specific reset function
+ *
+ * Used only in cases where struct omap_hwmod is dynamically allocated.
+ */
+struct omap_hwmod_reset {
+        const char *match;
+        int len;
+        int (*reset)(struct omap_hwmod *oh);
+};
+
+/**
  * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
  * @enable_module: function to enable a module (via MODULEMODE)
  * @disable_module: function to disable a module (via MODULEMODE)
@@ -235,6 +252,7 @@ static struct omap_hwmod_soc_ops soc_ops;
 
 /* omap_hwmod_list contains all registered struct omap_hwmods */
 static LIST_HEAD(omap_hwmod_list);
+static DEFINE_MUTEX(list_lock);
 
 /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
 static struct omap_hwmod *mpu_oh;
@@ -2465,7 +2483,7 @@ static void _setup_iclk_autoidle(struct omap_hwmod *oh)
  */
 static int _setup_reset(struct omap_hwmod *oh)
 {
-        int r;
+        int r = 0;
 
         if (oh->_state != _HWMOD_STATE_INITIALIZED)
                 return -EINVAL;
@@ -2624,7 +2642,7 @@ static int _setup(struct omap_hwmod *oh, void *data)
  * that the copy process would be relatively complex due to the large number
  * of substructures.
  */
-static int __init _register(struct omap_hwmod *oh)
+static int _register(struct omap_hwmod *oh)
 {
         if (!oh || !oh->name || !oh->class || !oh->class->name ||
             (oh->_state != _HWMOD_STATE_UNKNOWN))
@@ -2663,7 +2681,7 @@ static int __init _register(struct omap_hwmod *oh)
  * locking in this code.  Changes to this assumption will require
  * additional locking.  Returns 0.
  */
-static int __init _add_link(struct omap_hwmod_ocp_if *oi)
+static int _add_link(struct omap_hwmod_ocp_if *oi)
 {
         pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name,
                  oi->slave->name);
@@ -3241,9 +3259,10 @@ static int omap_hwmod_init_regbits(struct device *dev,
  * @sysc_offs: sysc register offset
  * @syss_offs: syss register offset
  */
-int omap_hwmod_init_reg_offs(struct device *dev,
-                             const struct ti_sysc_module_data *data,
-                             s32 *rev_offs, s32 *sysc_offs, s32 *syss_offs)
+static int omap_hwmod_init_reg_offs(struct device *dev,
+                                    const struct ti_sysc_module_data *data,
+                                    s32 *rev_offs, s32 *sysc_offs,
+                                    s32 *syss_offs)
 {
         *rev_offs = -ENODEV;
         *sysc_offs = 0;
@@ -3267,9 +3286,9 @@ int omap_hwmod_init_reg_offs(struct device *dev,
  * @data: module data
  * @sysc_flags: module configuration
  */
-int omap_hwmod_init_sysc_flags(struct device *dev,
-                               const struct ti_sysc_module_data *data,
-                               u32 *sysc_flags)
+static int omap_hwmod_init_sysc_flags(struct device *dev,
+                                      const struct ti_sysc_module_data *data,
+                                      u32 *sysc_flags)
 {
         *sysc_flags = 0;
 
@@ -3341,9 +3360,9 @@ int omap_hwmod_init_sysc_flags(struct device *dev,
  * @data: module data
  * @idlemodes: module supported idle modes
  */
-int omap_hwmod_init_idlemodes(struct device *dev,
-                              const struct ti_sysc_module_data *data,
-                              u32 *idlemodes)
+static int omap_hwmod_init_idlemodes(struct device *dev,
+                                     const struct ti_sysc_module_data *data,
+                                     u32 *idlemodes)
 {
         *idlemodes = 0;
 
@@ -3434,14 +3453,18 @@ static int omap_hwmod_check_module(struct device *dev,
  *
  * Note that the allocations here cannot use devm as ti-sysc can rebind.
  */
-int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
-                               const struct ti_sysc_module_data *data,
-                               struct sysc_regbits *sysc_fields,
-                               s32 rev_offs, s32 sysc_offs, s32 syss_offs,
-                               u32 sysc_flags, u32 idlemodes)
+static int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
+                                      const struct ti_sysc_module_data *data,
+                                      struct sysc_regbits *sysc_fields,
+                                      s32 rev_offs, s32 sysc_offs,
+                                      s32 syss_offs, u32 sysc_flags,
+                                      u32 idlemodes)
 {
         struct omap_hwmod_class_sysconfig *sysc;
-        struct omap_hwmod_class *class;
+        struct omap_hwmod_class *class = NULL;
+        struct omap_hwmod_ocp_if *oi = NULL;
+        struct clockdomain *clkdm = NULL;
+        struct clk *clk = NULL;
         void __iomem *regs = NULL;
         unsigned long flags;
 
@@ -3465,26 +3488,128 @@ int omap_hwmod_allocate_module(struct device *dev, struct omap_hwmod *oh,
         }
 
         /*
-         * We need new oh->class as the other devices in the same class
+         * We may need a new oh->class as the other devices in the same class
          * may not yet have ioremapped their registers.
          */
-        class = kmemdup(oh->class, sizeof(*oh->class), GFP_KERNEL);
-        if (!class)
-                return -ENOMEM;
+        if (oh->class->name && strcmp(oh->class->name, data->name)) {
+                class = kmemdup(oh->class, sizeof(*oh->class), GFP_KERNEL);
+                if (!class)
+                        return -ENOMEM;
+        }
 
-        class->sysc = sysc;
+        if (list_empty(&oh->slave_ports)) {
+                oi = kcalloc(1, sizeof(*oi), GFP_KERNEL);
+                if (!oi)
+                        return -ENOMEM;
+
+                /*
+                 * Note that we assume interconnect interface clocks will be
+                 * managed by the interconnect driver for OCPIF_SWSUP_IDLE case
+                 * on omap24xx and omap3.
+                 */
+                oi->slave = oh;
+                oi->user = OCP_USER_MPU | OCP_USER_SDMA;
+        }
+
+        if (!oh->_clk) {
+                struct clk_hw_omap *hwclk;
+
+                clk = of_clk_get_by_name(dev->of_node, "fck");
+                if (!IS_ERR(clk))
+                        clk_prepare(clk);
+                else
+                        clk = NULL;
+
+                /*
+                 * Populate clockdomain based on dts clock. It is needed for
+                 * clkdm_deny_idle() and clkdm_allow_idle() until we have have
+                 * interconnect driver and reset driver capable of blocking
+                 * clockdomain idle during reset, enable and idle.
+                 */
+                if (clk) {
+                        hwclk = to_clk_hw_omap(__clk_get_hw(clk));
+                        if (hwclk && hwclk->clkdm_name)
+                                clkdm = clkdm_lookup(hwclk->clkdm_name);
+                }
+
+                /*
+                 * Note that we assume interconnect driver manages the clocks
+                 * and do not need to populate oh->_clk for dynamically
+                 * allocated modules.
+                 */
+                clk_unprepare(clk);
+                clk_put(clk);
+        }
 
         spin_lock_irqsave(&oh->_lock, flags);
         if (regs)
                 oh->_mpu_rt_va = regs;
-        oh->class = class;
+        if (class)
+                oh->class = class;
+        oh->class->sysc = sysc;
+        if (oi)
+                _add_link(oi);
+        if (clkdm)
+                oh->clkdm = clkdm;
         oh->_state = _HWMOD_STATE_INITIALIZED;
+        oh->_postsetup_state = _HWMOD_STATE_DEFAULT;
         _setup(oh, NULL);
         spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
 
+static const struct omap_hwmod_reset omap24xx_reset_quirks[] = {
+        { .match = "msdi", .len = 4, .reset = omap_msdi_reset, },
+};
+
+static const struct omap_hwmod_reset dra7_reset_quirks[] = {
+        { .match = "pcie", .len = 4, .reset = dra7xx_pciess_reset, },
+};
+
+static const struct omap_hwmod_reset omap_reset_quirks[] = {
+        { .match = "dss", .len = 3, .reset = omap_dss_reset, },
+        { .match = "hdq1w", .len = 5, .reset = omap_hdq1w_reset, },
+        { .match = "i2c", .len = 3, .reset = omap_i2c_reset, },
+        { .match = "wd_timer", .len = 8, .reset = omap2_wd_timer_reset, },
+};
+
+static void
+omap_hwmod_init_reset_quirk(struct device *dev, struct omap_hwmod *oh,
+                            const struct ti_sysc_module_data *data,
+                            const struct omap_hwmod_reset *quirks,
+                            int quirks_sz)
+{
+        const struct omap_hwmod_reset *quirk;
+        int i;
+
+        for (i = 0; i < quirks_sz; i++) {
+                quirk = &quirks[i];
+                if (!strncmp(data->name, quirk->match, quirk->len)) {
+                        oh->class->reset = quirk->reset;
+
+                        return;
+                }
+        }
+}
+
+static void
+omap_hwmod_init_reset_quirks(struct device *dev, struct omap_hwmod *oh,
+                             const struct ti_sysc_module_data *data)
+{
+        if (soc_is_omap24xx())
+                omap_hwmod_init_reset_quirk(dev, oh, data,
+                                            omap24xx_reset_quirks,
+                                            ARRAY_SIZE(omap24xx_reset_quirks));
+
+        if (soc_is_dra7xx())
+                omap_hwmod_init_reset_quirk(dev, oh, data, dra7_reset_quirks,
+                                            ARRAY_SIZE(dra7_reset_quirks));
+
+        omap_hwmod_init_reset_quirk(dev, oh, data, omap_reset_quirks,
+                                    ARRAY_SIZE(omap_reset_quirks));
+}
+
 /**
  * omap_hwmod_init_module - initialize new module
  * @dev: struct device
@@ -3505,8 +3630,31 @@ int omap_hwmod_init_module(struct device *dev,
                 return -EINVAL;
 
         oh = _lookup(data->name);
-        if (!oh)
-                return -ENODEV;
+        if (!oh) {
+                oh = kzalloc(sizeof(*oh), GFP_KERNEL);
+                if (!oh)
+                        return -ENOMEM;
+
+                oh->name = data->name;
+                oh->_state = _HWMOD_STATE_UNKNOWN;
+                lockdep_register_key(&oh->hwmod_key);
+
+                /* Unused, can be handled by PRM driver handling resets */
+                oh->prcm.omap4.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT;
+
+                oh->class = kzalloc(sizeof(*oh->class), GFP_KERNEL);
+                if (!oh->class) {
+                        kfree(oh);
+                        return -ENOMEM;
+                }
+
+                omap_hwmod_init_reset_quirks(dev, oh, data);
+
+                oh->class->name = data->name;
+                mutex_lock(&list_lock);
+                error = _register(oh);
+                mutex_unlock(&list_lock);
+        }
 
         cookie->data = oh;
 
@@ -3527,10 +3675,20 @@ int omap_hwmod_init_module(struct device *dev,
         if (error)
                 return error;
 
+        if (data->cfg->quirks & SYSC_QUIRK_NO_IDLE)
+                oh->flags |= HWMOD_NO_IDLE;
         if (data->cfg->quirks & SYSC_QUIRK_NO_IDLE_ON_INIT)
                 oh->flags |= HWMOD_INIT_NO_IDLE;
         if (data->cfg->quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
                 oh->flags |= HWMOD_INIT_NO_RESET;
+        if (data->cfg->quirks & SYSC_QUIRK_USE_CLOCKACT)
+                oh->flags |= HWMOD_SET_DEFAULT_CLOCKACT;
+        if (data->cfg->quirks & SYSC_QUIRK_SWSUP_SIDLE)
+                oh->flags |= HWMOD_SWSUP_SIDLE;
+        if (data->cfg->quirks & SYSC_QUIRK_SWSUP_SIDLE_ACT)
+                oh->flags |= HWMOD_SWSUP_SIDLE_ACT;
+        if (data->cfg->quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
+                oh->flags |= HWMOD_SWSUP_MSTANDBY;
 
         error = omap_hwmod_check_module(dev, oh, data, sysc_fields,
                                         rev_offs, sysc_offs, syss_offs,
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index b70cdc21f8a2..fca9e072154b 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -493,11 +493,16 @@ struct omap_hwmod_omap4_prcm {
 #define _HWMOD_STATE_IDLE                       5
 #define _HWMOD_STATE_DISABLED                   6
 
+#ifdef CONFIG_PM
+#define _HWMOD_STATE_DEFAULT                    _HWMOD_STATE_IDLE
+#else
+#define _HWMOD_STATE_DEFAULT                    _HWMOD_STATE_ENABLED
+#endif
+
 /**
  * struct omap_hwmod_class - the type of an IP block
  * @name: name of the hwmod_class
  * @sysc: device SYSCONFIG/SYSSTATUS register data
- * @rev: revision of the IP class
  * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
  * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
  * @enable_preprogram:  ptr to fn to be executed during device enable
@@ -523,7 +528,6 @@ struct omap_hwmod_omap4_prcm {
 struct omap_hwmod_class {
         const char                              *name;
         struct omap_hwmod_class_sysconfig       *sysc;
-        u32                                     rev;
         int                                     (*pre_shutdown)(struct omap_hwmod *oh);
         int                                     (*reset)(struct omap_hwmod *oh);
         int                                     (*enable_preprogram)(struct omap_hwmod *oh);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index d684fac8f592..8122c8d4b69a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -91,7 +91,6 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
 static struct omap_hwmod_class i2c_class = {
         .name           = "i2c",
         .sysc           = &i2c_sysc,
-        .rev            = OMAP_I2C_IP_VERSION_1,
         .reset          = &omap_i2c_reset,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index abef9f6f9bf5..f27cb60bde77 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -68,7 +68,6 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
 static struct omap_hwmod_class i2c_class = {
         .name           = "i2c",
         .sysc           = &i2c_sysc,
-        .rev            = OMAP_I2C_IP_VERSION_1,
         .reset          = &omap_i2c_reset,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 5345919a81f8..ed5f39d948de 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -96,7 +96,6 @@ static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
         .name = "gpio",
         .sysc = &omap2xxx_gpio_sysc,
-        .rev = 0,
 };
 
 /* system dma */
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
index 6f81d7a4fec1..aaa6092426ea 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
@@ -30,24 +30,16 @@ extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
 extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc;
 extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0;
 extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio1;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio2;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio3;
 extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2;
 extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c2;
-extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c3;
 extern struct omap_hwmod_ocp_if am33xx_l4_per__mailbox;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1;
-extern struct omap_hwmod_ocp_if am33xx_l3_s__mmc2;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1;
 extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2;
@@ -60,11 +52,6 @@ extern struct omap_hwmod_ocp_if am33xx_l3_main__tpcc;
 extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc0;
 extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc1;
 extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc2;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart2;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart3;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart4;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart5;
-extern struct omap_hwmod_ocp_if am33xx_l4_ls__uart6;
 extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
 extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0;
 extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0;
@@ -93,19 +80,10 @@ extern struct omap_hwmod am33xx_elm_hwmod;
 extern struct omap_hwmod am33xx_epwmss0_hwmod;
 extern struct omap_hwmod am33xx_epwmss1_hwmod;
 extern struct omap_hwmod am33xx_epwmss2_hwmod;
-extern struct omap_hwmod am33xx_gpio1_hwmod;
-extern struct omap_hwmod am33xx_gpio2_hwmod;
-extern struct omap_hwmod am33xx_gpio3_hwmod;
 extern struct omap_hwmod am33xx_gpmc_hwmod;
-extern struct omap_hwmod am33xx_i2c1_hwmod;
-extern struct omap_hwmod am33xx_i2c2_hwmod;
-extern struct omap_hwmod am33xx_i2c3_hwmod;
 extern struct omap_hwmod am33xx_mailbox_hwmod;
 extern struct omap_hwmod am33xx_mcasp0_hwmod;
 extern struct omap_hwmod am33xx_mcasp1_hwmod;
-extern struct omap_hwmod am33xx_mmc0_hwmod;
-extern struct omap_hwmod am33xx_mmc1_hwmod;
-extern struct omap_hwmod am33xx_mmc2_hwmod;
 extern struct omap_hwmod am33xx_rtc_hwmod;
 extern struct omap_hwmod am33xx_spi0_hwmod;
 extern struct omap_hwmod am33xx_spi1_hwmod;
@@ -121,19 +99,12 @@ extern struct omap_hwmod am33xx_tpcc_hwmod;
 extern struct omap_hwmod am33xx_tptc0_hwmod;
 extern struct omap_hwmod am33xx_tptc1_hwmod;
 extern struct omap_hwmod am33xx_tptc2_hwmod;
-extern struct omap_hwmod am33xx_uart1_hwmod;
-extern struct omap_hwmod am33xx_uart2_hwmod;
-extern struct omap_hwmod am33xx_uart3_hwmod;
-extern struct omap_hwmod am33xx_uart4_hwmod;
-extern struct omap_hwmod am33xx_uart5_hwmod;
-extern struct omap_hwmod am33xx_uart6_hwmod;
 extern struct omap_hwmod am33xx_wd_timer1_hwmod;
 
 extern struct omap_hwmod_class am33xx_emif_hwmod_class;
 extern struct omap_hwmod_class am33xx_l4_hwmod_class;
 extern struct omap_hwmod_class am33xx_wkup_m3_hwmod_class;
 extern struct omap_hwmod_class am33xx_control_hwmod_class;
-extern struct omap_hwmod_class am33xx_gpio_hwmod_class;
 extern struct omap_hwmod_class am33xx_timer_hwmod_class;
 extern struct omap_hwmod_class am33xx_epwmss_hwmod_class;
 extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class;
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
index e0001232bb4f..47a0e301b193 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
@@ -122,30 +122,6 @@ struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4 per/ls -> GPIO2 */
-struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_gpio1_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 per/ls -> gpio3 */
-struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_gpio2_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4 per/ls -> gpio4 */
-struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_gpio3_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
         .master         = &am33xx_cpgmac0_hwmod,
         .slave          = &am33xx_mdio_hwmod,
@@ -188,21 +164,6 @@ struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
         .user           = OCP_USER_MPU,
 };
 
-/* i2c2 */
-struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_i2c2_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_i2c3_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
 /* l4 ls -> mailbox */
 struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
         .master         = &am33xx_l4_ls_hwmod,
@@ -235,30 +196,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
         .user           = OCP_USER_MPU,
 };
 
-/* l4 ls -> mmc0 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_mmc0_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> mmc1 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_mmc1_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l3 s -> mmc2 */
-struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
-        .master         = &am33xx_l3_s_hwmod,
-        .slave          = &am33xx_mmc2_hwmod,
-        .clk            = "l3s_gclk",
-        .user           = OCP_USER_MPU,
-};
-
 /* l4 ls -> mcspi0 */
 struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
         .master         = &am33xx_l4_ls_hwmod,
@@ -355,46 +292,6 @@ struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
         .user           = OCP_USER_MPU,
 };
 
-/* l4 ls -> uart2 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_uart2_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> uart3 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_uart3_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> uart4 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_uart4_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> uart5 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_uart5_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
-/* l4 ls -> uart6 */
-struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am33xx_uart6_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU,
-};
-
 /* l3 main -> ocmc */
 struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
         .master         = &am33xx_l3_main_hwmod,
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index 9ded7bf972e7..4c3543bae562 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -16,9 +16,7 @@
 
 #include <linux/types.h>
 
-#include <linux/platform_data/hsmmc-omap.h>
 #include "omap_hwmod.h"
-#include "i2c.h"
 #include "wd_timer.h"
 #include "cm33xx.h"
 #include "prm33xx.h"
@@ -534,7 +532,6 @@ static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
         .name           = "gpio",
         .sysc           = &am33xx_gpio_sysc,
-        .rev            = 2,
 };
 
 /* gpio1 */
@@ -627,68 +624,6 @@ struct omap_hwmod am33xx_gpmc_hwmod = {
         },
 };
 
-/* 'i2c' class */
-static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
-        .rev_offs       = 0,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0090,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
-                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
-                          SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                          SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class i2c_class = {
-        .name           = "i2c",
-        .sysc           = &am33xx_i2c_sysc,
-        .rev            = OMAP_I2C_IP_VERSION_2,
-        .reset          = &omap_i2c_reset,
-};
-
-/* i2c1 */
-struct omap_hwmod am33xx_i2c1_hwmod = {
-        .name           = "i2c1",
-        .class          = &i2c_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
-        .prcm           = {
-                .omap4  = {
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c1 */
-struct omap_hwmod am33xx_i2c2_hwmod = {
-        .name           = "i2c2",
-        .class          = &i2c_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4 = {
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c3 */
-struct omap_hwmod am33xx_i2c3_hwmod = {
-        .name           = "i2c3",
-        .class          = &i2c_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
 /*
  * 'mailbox' class
  * mailbox module allowing communication between the on-chip processors using a
@@ -762,76 +697,6 @@ struct omap_hwmod am33xx_mcasp1_hwmod = {
         },
 };
 
-/* 'mmc' class */
-static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
-        .rev_offs       = 0x2fc,
-        .sysc_offs      = 0x110,
-        .syss_offs      = 0x114,
-        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-                          SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                          SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
-        .name           = "mmc",
-        .sysc           = &am33xx_mmc_sysc,
-};
-
-/* mmc0 */
-static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
-        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-};
-
-struct omap_hwmod am33xx_mmc0_hwmod = {
-        .name           = "mmc1",
-        .class          = &am33xx_mmc_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "mmc_clk",
-        .prcm           = {
-                .omap4  = {
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .dev_attr       = &am33xx_mmc0_dev_attr,
-};
-
-/* mmc1 */
-static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
-        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-};
-
-struct omap_hwmod am33xx_mmc1_hwmod = {
-        .name           = "mmc2",
-        .class          = &am33xx_mmc_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .main_clk       = "mmc_clk",
-        .prcm           = {
-                .omap4  = {
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .dev_attr       = &am33xx_mmc1_dev_attr,
-};
-
-/* mmc2 */
-static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
-        .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-};
-struct omap_hwmod am33xx_mmc2_hwmod = {
-        .name           = "mmc3",
-        .class          = &am33xx_mmc_hwmod_class,
-        .clkdm_name     = "l3s_clkdm",
-        .main_clk       = "mmc_clk",
-        .prcm           = {
-                .omap4  = {
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .dev_attr       = &am33xx_mmc2_dev_attr,
-};
-
 /*
  * 'rtc' class
  * rtc subsystem
@@ -1132,102 +997,6 @@ struct omap_hwmod am33xx_tptc2_hwmod = {
         },
 };
 
-/* 'uart' class */
-static struct omap_hwmod_class_sysconfig uart_sysc = {
-        .rev_offs       = 0x50,
-        .sysc_offs      = 0x54,
-        .syss_offs      = 0x58,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
-                          SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                          SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class uart_class = {
-        .name           = "uart",
-        .sysc           = &uart_sysc,
-};
-
-struct omap_hwmod am33xx_uart1_hwmod = {
-        .name           = "uart1",
-        .class          = &uart_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
-        .prcm           = {
-                .omap4  = {
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-struct omap_hwmod am33xx_uart2_hwmod = {
-        .name           = "uart2",
-        .class          = &uart_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart3 */
-struct omap_hwmod am33xx_uart3_hwmod = {
-        .name           = "uart3",
-        .class          = &uart_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-struct omap_hwmod am33xx_uart4_hwmod = {
-        .name           = "uart4",
-        .class          = &uart_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-struct omap_hwmod am33xx_uart5_hwmod = {
-        .name           = "uart5",
-        .class          = &uart_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-struct omap_hwmod am33xx_uart6_hwmod = {
-        .name           = "uart6",
-        .class          = &uart_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "dpll_per_m2_div4_ck",
-        .prcm           = {
-                .omap4  = {
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
 /* 'wd_timer' class */
 static struct omap_hwmod_class_sysconfig wdt_sysc = {
         .rev_offs       = 0x0,
@@ -1265,11 +1034,6 @@ struct omap_hwmod am33xx_wd_timer1_hwmod = {
 
 static void omap_hwmod_am33xx_clkctrl(void)
 {
-        CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
@@ -1279,13 +1043,9 @@ static void omap_hwmod_am33xx_clkctrl(void)
         CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
@@ -1299,13 +1059,10 @@ static void omap_hwmod_am33xx_clkctrl(void)
                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_smartreflex1_hwmod,
                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
         PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
@@ -1340,11 +1097,6 @@ void omap_hwmod_am33xx_reg(void)
 
 static void omap_hwmod_am43xx_clkctrl(void)
 {
-        CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
@@ -1354,13 +1106,9 @@ static void omap_hwmod_am43xx_clkctrl(void)
         CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
@@ -1374,12 +1122,9 @@ static void omap_hwmod_am43xx_clkctrl(void)
                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_smartreflex1_hwmod,
                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
-        CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index c9483bc06228..c965af275e34 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -14,8 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/platform_data/i2c-omap.h>
-
 #include "omap_hwmod.h"
 #include "omap_hwmod_common_data.h"
 
@@ -23,7 +21,6 @@
 #include "cm33xx.h"
 #include "prm33xx.h"
 #include "prm-regbits-33xx.h"
-#include "i2c.h"
 #include "wd_timer.h"
 #include "omap_hwmod_33xx_43xx_common_data.h"
 
@@ -230,27 +227,6 @@ static struct omap_hwmod am33xx_control_hwmod = {
         },
 };
 
-/* gpio0 */
-static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio0_dbclk" },
-};
-
-static struct omap_hwmod am33xx_gpio0_hwmod = {
-        .name           = "gpio1",
-        .class          = &am33xx_gpio_hwmod_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "dpll_core_m4_div2_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .opt_clks       = gpio0_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
-};
-
 /* lcdc */
 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
         .rev_offs       = 0x0,
@@ -388,22 +364,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
         .user           = OCP_USER_MPU,
 };
 
-/* L4 WKUP -> I2C1 */
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
-        .master         = &am33xx_l4_wkup_hwmod,
-        .slave          = &am33xx_i2c1_hwmod,
-        .clk            = "dpll_core_m4_div2_ck",
-        .user           = OCP_USER_MPU,
-};
-
-/* L4 WKUP -> GPIO1 */
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
-        .master         = &am33xx_l4_wkup_hwmod,
-        .slave          = &am33xx_gpio0_hwmod,
-        .clk            = "dpll_core_m4_div2_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* L4 WKUP -> ADC_TSC */
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
         .master         = &am33xx_l4_wkup_hwmod,
@@ -434,14 +394,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
         .user           = OCP_USER_MPU,
 };
 
-/* l4 wkup -> uart1 */
-static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
-        .master         = &am33xx_l4_wkup_hwmod,
-        .slave          = &am33xx_uart1_hwmod,
-        .clk            = "dpll_core_m4_div2_ck",
-        .user           = OCP_USER_MPU,
-};
-
 /* l4 wkup -> wd_timer1 */
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
         .master         = &am33xx_l4_wkup_hwmod,
@@ -479,27 +431,16 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l4_wkup__control,
         &am33xx_l4_wkup__smartreflex0,
         &am33xx_l4_wkup__smartreflex1,
-        &am33xx_l4_wkup__uart1,
         &am33xx_l4_wkup__timer1,
         &am33xx_l4_wkup__rtc,
-        &am33xx_l4_wkup__i2c1,
-        &am33xx_l4_wkup__gpio0,
         &am33xx_l4_wkup__adc_tsc,
         &am33xx_l4_wkup__wd_timer1,
         &am33xx_l4_hs__pruss,
         &am33xx_l4_per__dcan0,
         &am33xx_l4_per__dcan1,
-        &am33xx_l4_per__gpio1,
-        &am33xx_l4_per__gpio2,
-        &am33xx_l4_per__gpio3,
-        &am33xx_l4_per__i2c2,
-        &am33xx_l4_per__i2c3,
         &am33xx_l4_per__mailbox,
         &am33xx_l4_ls__mcasp0,
         &am33xx_l4_ls__mcasp1,
-        &am33xx_l4_ls__mmc0,
-        &am33xx_l4_ls__mmc1,
-        &am33xx_l3_s__mmc2,
         &am33xx_l4_ls__timer2,
         &am33xx_l4_ls__timer3,
         &am33xx_l4_ls__timer4,
@@ -507,11 +448,6 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l4_ls__timer6,
         &am33xx_l4_ls__timer7,
         &am33xx_l3_main__tpcc,
-        &am33xx_l4_ls__uart2,
-        &am33xx_l4_ls__uart3,
-        &am33xx_l4_ls__uart4,
-        &am33xx_l4_ls__uart5,
-        &am33xx_l4_ls__uart6,
         &am33xx_l4_ls__spinlock,
         &am33xx_l4_ls__elm,
         &am33xx_l4_ls__epwmss0,
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 23e6a41a18eb..edff39921bf8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -484,7 +484,6 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
 static struct omap_hwmod_class i2c_class = {
         .name   = "i2c",
         .sysc   = &i2c_sysc,
-        .rev    = OMAP_I2C_IP_VERSION_1,
         .reset  = &omap_i2c_reset,
 };
 
@@ -707,7 +706,6 @@ static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
         .name = "gpio",
         .sysc = &omap3xxx_gpio_sysc,
-        .rev = 1,
 };
 
 /* gpio1 */
@@ -1029,7 +1027,6 @@ static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
         .name = "smartreflex",
         .sysc = &omap34xx_sr_sysc,
-        .rev  = 1,
 };
 
 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
@@ -1044,7 +1041,6 @@ static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
         .name = "smartreflex",
         .sysc = &omap36xx_sr_sysc,
-        .rev  = 2,
 };
 
 /* SR1 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index aa271ac5ebac..69571abc14fd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -87,26 +87,6 @@ static struct omap_hwmod am43xx_control_hwmod = {
         },
 };
 
-static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio0_dbclk" },
-};
-
-static struct omap_hwmod am43xx_gpio0_hwmod = {
-        .name           = "gpio1",
-        .class          = &am33xx_gpio_hwmod_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "sys_clkin_ck",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-        .opt_clks       = gpio0_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio0_opt_clks),
-};
-
 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
         .rev_offs       = 0x0,
         .sysc_offs      = 0x4,
@@ -264,46 +244,6 @@ static struct omap_hwmod am43xx_spi4_hwmod = {
         },
 };
 
-static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio4_dbclk" },
-};
-
-static struct omap_hwmod am43xx_gpio4_hwmod = {
-        .name           = "gpio5",
-        .class          = &am33xx_gpio_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-        .opt_clks       = gpio4_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
-};
-
-static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio5_dbclk" },
-};
-
-static struct omap_hwmod am43xx_gpio5_hwmod = {
-        .name           = "gpio6",
-        .class          = &am33xx_gpio_hwmod_class,
-        .clkdm_name     = "l4ls_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4ls_gclk",
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-        .opt_clks       = gpio5_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
-};
-
 static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
         .name   = "ocp2scp",
 };
@@ -650,20 +590,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
-        .master         = &am33xx_l4_wkup_hwmod,
-        .slave          = &am33xx_i2c1_hwmod,
-        .clk            = "sys_clkin_ck",
-        .user           = OCP_USER_MPU,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
-        .master         = &am33xx_l4_wkup_hwmod,
-        .slave          = &am43xx_gpio0_hwmod,
-        .clk            = "sys_clkin_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
         .master         = &am33xx_l4_wkup_hwmod,
         .slave          = &am43xx_adc_tsc_hwmod,
@@ -685,13 +611,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
-        .master         = &am33xx_l4_wkup_hwmod,
-        .slave          = &am33xx_uart1_hwmod,
-        .clk            = "sys_clkin_ck",
-        .user           = OCP_USER_MPU,
-};
-
 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
         .master         = &am33xx_l4_wkup_hwmod,
         .slave          = &am33xx_wd_timer1_hwmod,
@@ -776,20 +695,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am43xx_gpio4_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
-        .master         = &am33xx_l4_ls_hwmod,
-        .slave          = &am43xx_gpio5_hwmod,
-        .clk            = "l4ls_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am43xx_ocp2scp0_hwmod,
@@ -907,8 +812,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
         &am43xx_l4_ls__mcspi2,
         &am43xx_l4_ls__mcspi3,
         &am43xx_l4_ls__mcspi4,
-        &am43xx_l4_ls__gpio4,
-        &am43xx_l4_ls__gpio5,
         &am43xx_l3_main__pruss,
         &am33xx_mpu__l3_main,
         &am33xx_mpu__prcm,
@@ -927,27 +830,16 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
         &am43xx_l4_wkup__control,
         &am43xx_l4_wkup__smartreflex0,
         &am43xx_l4_wkup__smartreflex1,
-        &am43xx_l4_wkup__uart1,
         &am43xx_l4_wkup__timer1,
-        &am43xx_l4_wkup__i2c1,
-        &am43xx_l4_wkup__gpio0,
         &am43xx_l4_wkup__wd_timer1,
         &am43xx_l4_wkup__adc_tsc,
         &am43xx_l3_s__qspi,
         &am33xx_l4_per__dcan0,
         &am33xx_l4_per__dcan1,
-        &am33xx_l4_per__gpio1,
-        &am33xx_l4_per__gpio2,
-        &am33xx_l4_per__gpio3,
-        &am33xx_l4_per__i2c2,
-        &am33xx_l4_per__i2c3,
         &am33xx_l4_per__mailbox,
         &am33xx_l4_per__rng,
         &am33xx_l4_ls__mcasp0,
         &am33xx_l4_ls__mcasp1,
-        &am33xx_l4_ls__mmc0,
-        &am33xx_l4_ls__mmc1,
-        &am33xx_l3_s__mmc2,
         &am33xx_l4_ls__timer2,
         &am33xx_l4_ls__timer3,
         &am33xx_l4_ls__timer4,
@@ -955,11 +847,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l4_ls__timer6,
         &am33xx_l4_ls__timer7,
         &am33xx_l3_main__tpcc,
-        &am33xx_l4_ls__uart2,
-        &am33xx_l4_ls__uart3,
-        &am33xx_l4_ls__uart4,
-        &am33xx_l4_ls__uart5,
-        &am33xx_l4_ls__uart6,
         &am33xx_l4_ls__spinlock,
         &am33xx_l4_ls__elm,
         &am33xx_l4_ls__epwmss0,
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index a95dbac57a81..b8de550a15b4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -21,9 +21,7 @@
  */
 
 #include <linux/io.h>
-#include <linux/platform_data/hsmmc-omap.h>
 #include <linux/power/smartreflex.h>
-#include <linux/platform_data/i2c-omap.h>
 
 #include <linux/omap-dma.h>
 
@@ -33,7 +31,6 @@
 #include "cm2_44xx.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
-#include "i2c.h"
 #include "wd_timer.h"
 
 /* Base offset for all OMAP4 interrupts external to MPUSS */
@@ -1056,160 +1053,6 @@ static struct omap_hwmod omap44xx_fdif_hwmod = {
 };
 
 /*
- * 'gpio' class
- * general purpose io module
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0114,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
-                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-                           SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
-        .name   = "gpio",
-        .sysc   = &omap44xx_gpio_sysc,
-        .rev    = 2,
-};
-
-/* gpio1 */
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio1_dbclk" },
-};
-
-static struct omap_hwmod omap44xx_gpio1_hwmod = {
-        .name           = "gpio1",
-        .class          = &omap44xx_gpio_hwmod_class,
-        .clkdm_name     = "l4_wkup_clkdm",
-        .main_clk       = "l4_wkup_clk_mux_ck",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio1_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
-};
-
-/* gpio2 */
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio2_dbclk" },
-};
-
-static struct omap_hwmod omap44xx_gpio2_hwmod = {
-        .name           = "gpio2",
-        .class          = &omap44xx_gpio_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4_div_ck",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio2_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
-};
-
-/* gpio3 */
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio3_dbclk" },
-};
-
-static struct omap_hwmod omap44xx_gpio3_hwmod = {
-        .name           = "gpio3",
-        .class          = &omap44xx_gpio_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4_div_ck",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio3_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
-};
-
-/* gpio4 */
-static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio4_dbclk" },
-};
-
-static struct omap_hwmod omap44xx_gpio4_hwmod = {
-        .name           = "gpio4",
-        .class          = &omap44xx_gpio_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4_div_ck",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio4_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
-};
-
-/* gpio5 */
-static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio5_dbclk" },
-};
-
-static struct omap_hwmod omap44xx_gpio5_hwmod = {
-        .name           = "gpio5",
-        .class          = &omap44xx_gpio_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4_div_ck",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio5_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
-};
-
-/* gpio6 */
-static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio6_dbclk" },
-};
-
-static struct omap_hwmod omap44xx_gpio6_hwmod = {
-        .name           = "gpio6",
-        .class          = &omap44xx_gpio_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4_div_ck",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio6_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
-};
-
-/*
  * 'gpmc' class
  * general purpose memory controller
  */
@@ -1355,94 +1198,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
 };
 
 /*
- * 'i2c' class
- * multimaster high-speed i2c controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
-        .rev_offs       = 0,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0090,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
-                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
-        .name   = "i2c",
-        .sysc   = &omap44xx_i2c_sysc,
-        .rev    = OMAP_I2C_IP_VERSION_2,
-        .reset  = &omap_i2c_reset,
-};
-
-/* i2c1 */
-static struct omap_hwmod omap44xx_i2c1_hwmod = {
-        .name           = "i2c1",
-        .class          = &omap44xx_i2c_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c2 */
-static struct omap_hwmod omap44xx_i2c2_hwmod = {
-        .name           = "i2c2",
-        .class          = &omap44xx_i2c_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c3 */
-static struct omap_hwmod omap44xx_i2c3_hwmod = {
-        .name           = "i2c3",
-        .class          = &omap44xx_i2c_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c4 */
-static struct omap_hwmod omap44xx_i2c4_hwmod = {
-        .name           = "i2c4",
-        .class          = &omap44xx_i2c_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
  * 'ipu' class
  * imaging processor unit
  */
@@ -1819,189 +1574,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
 };
 
 /*
- * 'mcspi' class
- * multichannel serial port interface (mcspi) / master/slave synchronous serial
- * bus
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
-                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
-        .name   = "mcspi",
-        .sysc   = &omap44xx_mcspi_sysc,
-};
-
-/* mcspi1 */
-static struct omap_hwmod omap44xx_mcspi1_hwmod = {
-        .name           = "mcspi1",
-        .class          = &omap44xx_mcspi_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* mcspi2 */
-static struct omap_hwmod omap44xx_mcspi2_hwmod = {
-        .name           = "mcspi2",
-        .class          = &omap44xx_mcspi_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* mcspi3 */
-static struct omap_hwmod omap44xx_mcspi3_hwmod = {
-        .name           = "mcspi3",
-        .class          = &omap44xx_mcspi_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* mcspi4 */
-static struct omap_hwmod omap44xx_mcspi4_hwmod = {
-        .name           = "mcspi4",
-        .class          = &omap44xx_mcspi_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
- * 'mmc' class
- * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
-                           SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_SOFTRESET),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
-        .name   = "mmc",
-        .sysc   = &omap44xx_mmc_sysc,
-};
-
-/* mmc1 */
-static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
-        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-};
-
-static struct omap_hwmod omap44xx_mmc1_hwmod = {
-        .name           = "mmc1",
-        .class          = &omap44xx_mmc_hwmod_class,
-        .clkdm_name     = "l3_init_clkdm",
-        .main_clk       = "hsmmc1_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-        .dev_attr       = &mmc1_dev_attr,
-};
-
-/* mmc2 */
-static struct omap_hwmod omap44xx_mmc2_hwmod = {
-        .name           = "mmc2",
-        .class          = &omap44xx_mmc_hwmod_class,
-        .clkdm_name     = "l3_init_clkdm",
-        .main_clk       = "hsmmc2_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* mmc3 */
-static struct omap_hwmod omap44xx_mmc3_hwmod = {
-        .name           = "mmc3",
-        .class          = &omap44xx_mmc_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* mmc4 */
-static struct omap_hwmod omap44xx_mmc4_hwmod = {
-        .name           = "mmc4",
-        .class          = &omap44xx_mmc_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* mmc5 */
-static struct omap_hwmod omap44xx_mmc5_hwmod = {
-        .name           = "mmc5",
-        .class          = &omap44xx_mmc_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
  * 'mmu' class
  * The memory management unit performs virtual to physical address translation
  * for its requestors.
@@ -2367,7 +1939,6 @@ static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
         .name   = "smartreflex",
         .sysc   = &omap44xx_smartreflex_sysc,
-        .rev    = 2,
 };
 
 /* smartreflex_core */
@@ -2673,92 +2244,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
 };
 
 /*
- * 'uart' class
- * universal asynchronous receiver/transmitter (uart)
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
-        .rev_offs       = 0x0050,
-        .sysc_offs      = 0x0054,
-        .syss_offs      = 0x0058,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
-                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-                           SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
-        .name   = "uart",
-        .sysc   = &omap44xx_uart_sysc,
-};
-
-/* uart1 */
-static struct omap_hwmod omap44xx_uart1_hwmod = {
-        .name           = "uart1",
-        .class          = &omap44xx_uart_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart2 */
-static struct omap_hwmod omap44xx_uart2_hwmod = {
-        .name           = "uart2",
-        .class          = &omap44xx_uart_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart3 */
-static struct omap_hwmod omap44xx_uart3_hwmod = {
-        .name           = "uart3",
-        .class          = &omap44xx_uart_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart4 */
-static struct omap_hwmod omap44xx_uart4_hwmod = {
-        .name           = "uart4",
-        .class          = &omap44xx_uart_hwmod_class,
-        .clkdm_name     = "l4_per_clkdm",
-        .flags          = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
  * 'usb_host_fs' class
  * full-speed usb host controller
  */
@@ -3082,22 +2567,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* mmc1 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
-        .master         = &omap44xx_mmc1_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mmc2 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
-        .master         = &omap44xx_mmc2_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* mpu -> l3_main_1 */
 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
         .master         = &omap44xx_mpu_hwmod,
@@ -3554,54 +3023,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
-        .master         = &omap44xx_l4_wkup_hwmod,
-        .slave          = &omap44xx_gpio1_hwmod,
-        .clk            = "l4_wkup_clk_mux_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio2_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio3_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio4_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio5_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio6 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio6_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l3_main_2 -> gpmc */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
         .master         = &omap44xx_l3_main_2_hwmod,
@@ -3634,38 +3055,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_per -> i2c1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_i2c1_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> i2c2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_i2c2_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> i2c3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_i2c3_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> i2c4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_i2c4_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l3_main_2 -> ipu */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
         .master         = &omap44xx_l3_main_2_hwmod,
@@ -3770,78 +3159,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_per -> mcspi1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcspi1_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mcspi2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcspi2_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mcspi3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcspi3_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mcspi4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcspi4_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mmc1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc1_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mmc2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc2_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mmc3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc3_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mmc4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc4_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mmc5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc5_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l3_main_2 -> ocmc_ram */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
         .master         = &omap44xx_l3_main_2_hwmod,
@@ -4050,38 +3367,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_per -> uart1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_uart1_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> uart2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_uart2_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> uart3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_uart3_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> uart4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_uart4_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_cfg -> usb_host_fs */
 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
         .master         = &omap44xx_l4_cfg_hwmod,
@@ -4164,8 +3449,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_dss__l3_main_1,
         &omap44xx_l3_main_2__l3_main_1,
         &omap44xx_l4_cfg__l3_main_1,
-        &omap44xx_mmc1__l3_main_1,
-        &omap44xx_mmc2__l3_main_1,
         &omap44xx_mpu__l3_main_1,
         &omap44xx_debugss__l3_main_2,
         &omap44xx_dma_system__l3_main_2,
@@ -4222,20 +3505,10 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_per__dss_venc,
         &omap44xx_l4_per__elm,
         &omap44xx_l4_cfg__fdif,
-        &omap44xx_l4_wkup__gpio1,
-        &omap44xx_l4_per__gpio2,
-        &omap44xx_l4_per__gpio3,
-        &omap44xx_l4_per__gpio4,
-        &omap44xx_l4_per__gpio5,
-        &omap44xx_l4_per__gpio6,
         &omap44xx_l3_main_2__gpmc,
         &omap44xx_l3_main_2__gpu,
         &omap44xx_l4_per__hdq1w,
         &omap44xx_l4_cfg__hsi,
-        &omap44xx_l4_per__i2c1,
-        &omap44xx_l4_per__i2c2,
-        &omap44xx_l4_per__i2c3,
-        &omap44xx_l4_per__i2c4,
         &omap44xx_l3_main_2__ipu,
         &omap44xx_l3_main_2__iss,
         /* &omap44xx_iva__sl2if, */
@@ -4249,15 +3522,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_abe__mcbsp3,
         &omap44xx_l4_per__mcbsp4,
         &omap44xx_l4_abe__mcpdm,
-        &omap44xx_l4_per__mcspi1,
-        &omap44xx_l4_per__mcspi2,
-        &omap44xx_l4_per__mcspi3,
-        &omap44xx_l4_per__mcspi4,
-        &omap44xx_l4_per__mmc1,
-        &omap44xx_l4_per__mmc2,
-        &omap44xx_l4_per__mmc3,
-        &omap44xx_l4_per__mmc4,
-        &omap44xx_l4_per__mmc5,
         &omap44xx_l3_main_2__mmu_ipu,
         &omap44xx_l4_cfg__mmu_dsp,
         &omap44xx_l3_main_2__ocmc_ram,
@@ -4286,10 +3550,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_per__timer9,
         &omap44xx_l4_per__timer10,
         &omap44xx_l4_per__timer11,
-        &omap44xx_l4_per__uart1,
-        &omap44xx_l4_per__uart2,
-        &omap44xx_l4_per__uart3,
-        &omap44xx_l4_per__uart4,
         /* &omap44xx_l4_cfg__usb_host_fs, */
         &omap44xx_l4_cfg__usb_host_hs,
         &omap44xx_l4_cfg__usb_otg_hs,
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 115473d441cd..29805cc9d74c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -18,9 +18,7 @@
  */
 
 #include <linux/io.h>
-#include <linux/platform_data/hsmmc-omap.h>
 #include <linux/power/smartreflex.h>
-#include <linux/platform_data/i2c-omap.h>
 
 #include <linux/omap-dma.h>
 
@@ -29,7 +27,6 @@
 #include "cm1_54xx.h"
 #include "cm2_54xx.h"
 #include "prm54xx.h"
-#include "i2c.h"
 #include "wd_timer.h"
 
 /* Base offset for all OMAP5 interrupts external to MPUSS */
@@ -601,308 +598,6 @@ static struct omap_hwmod omap54xx_emif2_hwmod = {
 };
 
 /*
- * 'gpio' class
- * general purpose io module
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0114,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
-                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-                           SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
-        .name   = "gpio",
-        .sysc   = &omap54xx_gpio_sysc,
-        .rev    = 2,
-};
-
-/* gpio1 */
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio1_dbclk" },
-};
-
-static struct omap_hwmod omap54xx_gpio1_hwmod = {
-        .name           = "gpio1",
-        .class          = &omap54xx_gpio_hwmod_class,
-        .clkdm_name     = "wkupaon_clkdm",
-        .main_clk       = "wkupaon_iclk_mux",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio1_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
-};
-
-/* gpio2 */
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio2_dbclk" },
-};
-
-static struct omap_hwmod omap54xx_gpio2_hwmod = {
-        .name           = "gpio2",
-        .class          = &omap54xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4_root_clk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio2_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
-};
-
-/* gpio3 */
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio3_dbclk" },
-};
-
-static struct omap_hwmod omap54xx_gpio3_hwmod = {
-        .name           = "gpio3",
-        .class          = &omap54xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4_root_clk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio3_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
-};
-
-/* gpio4 */
-static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio4_dbclk" },
-};
-
-static struct omap_hwmod omap54xx_gpio4_hwmod = {
-        .name           = "gpio4",
-        .class          = &omap54xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4_root_clk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio4_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
-};
-
-/* gpio5 */
-static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio5_dbclk" },
-};
-
-static struct omap_hwmod omap54xx_gpio5_hwmod = {
-        .name           = "gpio5",
-        .class          = &omap54xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4_root_clk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio5_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
-};
-
-/* gpio6 */
-static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio6_dbclk" },
-};
-
-static struct omap_hwmod omap54xx_gpio6_hwmod = {
-        .name           = "gpio6",
-        .class          = &omap54xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4_root_clk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio6_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
-};
-
-/* gpio7 */
-static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio7_dbclk" },
-};
-
-static struct omap_hwmod omap54xx_gpio7_hwmod = {
-        .name           = "gpio7",
-        .class          = &omap54xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4_root_clk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio7_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
-};
-
-/* gpio8 */
-static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio8_dbclk" },
-};
-
-static struct omap_hwmod omap54xx_gpio8_hwmod = {
-        .name           = "gpio8",
-        .class          = &omap54xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l4_root_clk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio8_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
-};
-
-/*
- * 'i2c' class
- * multimaster high-speed i2c controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
-        .rev_offs       = 0,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0090,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
-                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
-        .name   = "i2c",
-        .sysc   = &omap54xx_i2c_sysc,
-        .reset  = &omap_i2c_reset,
-        .rev    = OMAP_I2C_IP_VERSION_2,
-};
-
-/* i2c1 */
-static struct omap_hwmod omap54xx_i2c1_hwmod = {
-        .name           = "i2c1",
-        .class          = &omap54xx_i2c_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c2 */
-static struct omap_hwmod omap54xx_i2c2_hwmod = {
-        .name           = "i2c2",
-        .class          = &omap54xx_i2c_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c3 */
-static struct omap_hwmod omap54xx_i2c3_hwmod = {
-        .name           = "i2c3",
-        .class          = &omap54xx_i2c_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c4 */
-static struct omap_hwmod omap54xx_i2c4_hwmod = {
-        .name           = "i2c4",
-        .class          = &omap54xx_i2c_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c5 */
-static struct omap_hwmod omap54xx_i2c5_hwmod = {
-        .name           = "i2c5",
-        .class          = &omap54xx_i2c_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
  * 'kbd' class
  * keyboard controller
  */
@@ -1185,115 +880,6 @@ static struct omap_hwmod omap54xx_mcspi4_hwmod = {
 };
 
 /*
- * 'mmc' class
- * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
-                           SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_SOFTRESET),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
-        .name   = "mmc",
-        .sysc   = &omap54xx_mmc_sysc,
-};
-
-/* mmc1 */
-static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
-        { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
-};
-
-/* mmc1 dev_attr */
-static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
-        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-};
-
-static struct omap_hwmod omap54xx_mmc1_hwmod = {
-        .name           = "mmc1",
-        .class          = &omap54xx_mmc_hwmod_class,
-        .clkdm_name     = "l3init_clkdm",
-        .main_clk       = "mmc1_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-        .opt_clks       = mmc1_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
-        .dev_attr       = &mmc1_dev_attr,
-};
-
-/* mmc2 */
-static struct omap_hwmod omap54xx_mmc2_hwmod = {
-        .name           = "mmc2",
-        .class          = &omap54xx_mmc_hwmod_class,
-        .clkdm_name     = "l3init_clkdm",
-        .main_clk       = "mmc2_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* mmc3 */
-static struct omap_hwmod omap54xx_mmc3_hwmod = {
-        .name           = "mmc3",
-        .class          = &omap54xx_mmc_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* mmc4 */
-static struct omap_hwmod omap54xx_mmc4_hwmod = {
-        .name           = "mmc4",
-        .class          = &omap54xx_mmc_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* mmc5 */
-static struct omap_hwmod omap54xx_mmc5_hwmod = {
-        .name           = "mmc5",
-        .class          = &omap54xx_mmc_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
  * 'mmu' class
  * The memory management unit performs virtual to physical address translation
  * for its requestors.
@@ -1658,124 +1244,6 @@ static struct omap_hwmod omap54xx_timer11_hwmod = {
 };
 
 /*
- * 'uart' class
- * universal asynchronous receiver/transmitter (uart)
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
-        .rev_offs       = 0x0050,
-        .sysc_offs      = 0x0054,
-        .syss_offs      = 0x0058,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
-                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-                           SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
-        .name   = "uart",
-        .sysc   = &omap54xx_uart_sysc,
-};
-
-/* uart1 */
-static struct omap_hwmod omap54xx_uart1_hwmod = {
-        .name           = "uart1",
-        .class          = &omap54xx_uart_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart2 */
-static struct omap_hwmod omap54xx_uart2_hwmod = {
-        .name           = "uart2",
-        .class          = &omap54xx_uart_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart3 */
-static struct omap_hwmod omap54xx_uart3_hwmod = {
-        .name           = "uart3",
-        .class          = &omap54xx_uart_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart4 */
-static struct omap_hwmod omap54xx_uart4_hwmod = {
-        .name           = "uart4",
-        .class          = &omap54xx_uart_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart5 */
-static struct omap_hwmod omap54xx_uart5_hwmod = {
-        .name           = "uart5",
-        .class          = &omap54xx_uart_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart6 */
-static struct omap_hwmod omap54xx_uart6_hwmod = {
-        .name           = "uart6",
-        .class          = &omap54xx_uart_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .main_clk       = "func_48m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
-                        .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
  * 'usb_host_hs' class
  * high-speed multi-port usb host controller
  */
@@ -2274,110 +1742,6 @@ static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
-        .master         = &omap54xx_l4_wkup_hwmod,
-        .slave          = &omap54xx_gpio1_hwmod,
-        .clk            = "wkupaon_iclk_mux",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_gpio2_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_gpio3_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio4 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_gpio4_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio5 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_gpio5_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio6 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_gpio6_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio7 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_gpio7_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> gpio8 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_gpio8_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> i2c1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_i2c1_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> i2c2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_i2c2_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> i2c3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_i2c3_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> i2c4 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_i2c4_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> i2c5 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_i2c5_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_wkup -> kbd */
 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
         .master         = &omap54xx_l4_wkup_hwmod,
@@ -2458,46 +1822,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_per -> mmc1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_mmc1_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mmc2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_mmc2_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mmc3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_mmc3_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mmc4 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_mmc4_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> mmc5 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_mmc5_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_cfg -> mpu */
 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
         .master         = &omap54xx_l4_cfg_hwmod,
@@ -2610,54 +1934,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_per -> uart1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_uart1_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> uart2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_uart2_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> uart3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_uart3_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> uart4 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_uart4_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> uart5 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_uart5_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per -> uart6 */
-static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
-        .master         = &omap54xx_l4_per_hwmod,
-        .slave          = &omap54xx_uart6_hwmod,
-        .clk            = "l4_root_clk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_cfg -> usb_host_hs */
 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
         .master         = &omap54xx_l4_cfg_hwmod,
@@ -2719,19 +1995,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
         &omap54xx_l3_main_2__dss_rfbi,
         &omap54xx_mpu__emif1,
         &omap54xx_mpu__emif2,
-        &omap54xx_l4_wkup__gpio1,
-        &omap54xx_l4_per__gpio2,
-        &omap54xx_l4_per__gpio3,
-        &omap54xx_l4_per__gpio4,
-        &omap54xx_l4_per__gpio5,
-        &omap54xx_l4_per__gpio6,
-        &omap54xx_l4_per__gpio7,
-        &omap54xx_l4_per__gpio8,
-        &omap54xx_l4_per__i2c1,
-        &omap54xx_l4_per__i2c2,
-        &omap54xx_l4_per__i2c3,
-        &omap54xx_l4_per__i2c4,
-        &omap54xx_l4_per__i2c5,
         &omap54xx_l3_main_2__mmu_ipu,
         &omap54xx_l4_wkup__kbd,
         &omap54xx_l4_cfg__mailbox,
@@ -2743,11 +2006,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
         &omap54xx_l4_per__mcspi2,
         &omap54xx_l4_per__mcspi3,
         &omap54xx_l4_per__mcspi4,
-        &omap54xx_l4_per__mmc1,
-        &omap54xx_l4_per__mmc2,
-        &omap54xx_l4_per__mmc3,
-        &omap54xx_l4_per__mmc4,
-        &omap54xx_l4_per__mmc5,
         &omap54xx_l4_cfg__mpu,
         &omap54xx_l4_cfg__spinlock,
         &omap54xx_l4_cfg__ocp2scp1,
@@ -2762,12 +2020,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
         &omap54xx_l4_per__timer9,
         &omap54xx_l4_per__timer10,
         &omap54xx_l4_per__timer11,
-        &omap54xx_l4_per__uart1,
-        &omap54xx_l4_per__uart2,
-        &omap54xx_l4_per__uart3,
-        &omap54xx_l4_per__uart4,
-        &omap54xx_l4_per__uart5,
-        &omap54xx_l4_per__uart6,
         &omap54xx_l4_cfg__usb_host_hs,
         &omap54xx_l4_cfg__usb_tll_hs,
         &omap54xx_l4_cfg__usb_otg_ss,
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index e6c7061a8e73..7e85bd27ce9a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -18,9 +18,7 @@
  */
 
 #include <linux/io.h>
-#include <linux/platform_data/hsmmc-omap.h>
 #include <linux/power/smartreflex.h>
-#include <linux/platform_data/i2c-omap.h>
 
 #include <linux/omap-dma.h>
 
@@ -29,7 +27,6 @@
 #include "cm1_7xx.h"
 #include "cm2_7xx.h"
 #include "prm7xx.h"
-#include "i2c.h"
 #include "wd_timer.h"
 #include "soc.h"
 
@@ -693,7 +690,6 @@ static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
         .name   = "aes",
         .sysc   = &dra7xx_aes_sysc,
-        .rev    = 2,
 };
 
 /* AES1 */
@@ -737,7 +733,6 @@ static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
         .name           = "sham",
         .sysc           = &dra7xx_sha0_sysc,
-        .rev            = 2,
 };
 
 struct omap_hwmod dra7xx_sha0_hwmod = {
@@ -792,205 +787,6 @@ static struct omap_hwmod dra7xx_elm_hwmod = {
 };
 
 /*
- * 'gpio' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0114,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
-                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-                           SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
-        .name   = "gpio",
-        .sysc   = &dra7xx_gpio_sysc,
-        .rev    = 2,
-};
-
-/* gpio1 */
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio1_dbclk" },
-};
-
-static struct omap_hwmod dra7xx_gpio1_hwmod = {
-        .name           = "gpio1",
-        .class          = &dra7xx_gpio_hwmod_class,
-        .clkdm_name     = "wkupaon_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "wkupaon_iclk_mux",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio1_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
-};
-
-/* gpio2 */
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio2_dbclk" },
-};
-
-static struct omap_hwmod dra7xx_gpio2_hwmod = {
-        .name           = "gpio2",
-        .class          = &dra7xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l3_iclk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio2_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
-};
-
-/* gpio3 */
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio3_dbclk" },
-};
-
-static struct omap_hwmod dra7xx_gpio3_hwmod = {
-        .name           = "gpio3",
-        .class          = &dra7xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l3_iclk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio3_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
-};
-
-/* gpio4 */
-static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio4_dbclk" },
-};
-
-static struct omap_hwmod dra7xx_gpio4_hwmod = {
-        .name           = "gpio4",
-        .class          = &dra7xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l3_iclk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio4_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
-};
-
-/* gpio5 */
-static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio5_dbclk" },
-};
-
-static struct omap_hwmod dra7xx_gpio5_hwmod = {
-        .name           = "gpio5",
-        .class          = &dra7xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l3_iclk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio5_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
-};
-
-/* gpio6 */
-static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio6_dbclk" },
-};
-
-static struct omap_hwmod dra7xx_gpio6_hwmod = {
-        .name           = "gpio6",
-        .class          = &dra7xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l3_iclk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio6_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
-};
-
-/* gpio7 */
-static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio7_dbclk" },
-};
-
-static struct omap_hwmod dra7xx_gpio7_hwmod = {
-        .name           = "gpio7",
-        .class          = &dra7xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l3_iclk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio7_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
-};
-
-/* gpio8 */
-static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
-        { .role = "dbclk", .clk = "gpio8_dbclk" },
-};
-
-static struct omap_hwmod dra7xx_gpio8_hwmod = {
-        .name           = "gpio8",
-        .class          = &dra7xx_gpio_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .main_clk       = "l3_iclk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
-                },
-        },
-        .opt_clks       = gpio8_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
-};
-
-/*
  * 'gpmc' class
  *
  */
@@ -1065,110 +861,6 @@ static struct omap_hwmod dra7xx_hdq1w_hwmod = {
 };
 
 /*
- * 'i2c' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
-        .rev_offs       = 0,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0090,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
-                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
-        .name   = "i2c",
-        .sysc   = &dra7xx_i2c_sysc,
-        .reset  = &omap_i2c_reset,
-        .rev    = OMAP_I2C_IP_VERSION_2,
-};
-
-/* i2c1 */
-static struct omap_hwmod dra7xx_i2c1_hwmod = {
-        .name           = "i2c1",
-        .class          = &dra7xx_i2c_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c2 */
-static struct omap_hwmod dra7xx_i2c2_hwmod = {
-        .name           = "i2c2",
-        .class          = &dra7xx_i2c_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c3 */
-static struct omap_hwmod dra7xx_i2c3_hwmod = {
-        .name           = "i2c3",
-        .class          = &dra7xx_i2c_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c4 */
-static struct omap_hwmod dra7xx_i2c4_hwmod = {
-        .name           = "i2c4",
-        .class          = &dra7xx_i2c_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* i2c5 */
-static struct omap_hwmod dra7xx_i2c5_hwmod = {
-        .name           = "i2c5",
-        .class          = &dra7xx_i2c_hwmod_class,
-        .clkdm_name     = "ipu_clkdm",
-        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .main_clk       = "func_96m_fclk",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
  * 'mailbox' class
  *
  */
@@ -1632,118 +1324,6 @@ static struct omap_hwmod dra7xx_mcasp8_hwmod = {
 };
 
 /*
- * 'mmc' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
-                           SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_SOFTRESET),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
-        .name   = "mmc",
-        .sysc   = &dra7xx_mmc_sysc,
-};
-
-/* mmc1 */
-static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
-        { .role = "clk32k", .clk = "mmc1_clk32k" },
-};
-
-/* mmc1 dev_attr */
-static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
-        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
-};
-
-static struct omap_hwmod dra7xx_mmc1_hwmod = {
-        .name           = "mmc1",
-        .class          = &dra7xx_mmc_hwmod_class,
-        .clkdm_name     = "l3init_clkdm",
-        .main_clk       = "mmc1_fclk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-        .opt_clks       = mmc1_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
-        .dev_attr       = &mmc1_dev_attr,
-};
-
-/* mmc2 */
-static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
-        { .role = "clk32k", .clk = "mmc2_clk32k" },
-};
-
-static struct omap_hwmod dra7xx_mmc2_hwmod = {
-        .name           = "mmc2",
-        .class          = &dra7xx_mmc_hwmod_class,
-        .clkdm_name     = "l3init_clkdm",
-        .main_clk       = "mmc2_fclk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-        .opt_clks       = mmc2_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
-};
-
-/* mmc3 */
-static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
-        { .role = "clk32k", .clk = "mmc3_clk32k" },
-};
-
-static struct omap_hwmod dra7xx_mmc3_hwmod = {
-        .name           = "mmc3",
-        .class          = &dra7xx_mmc_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .main_clk       = "mmc3_gfclk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-        .opt_clks       = mmc3_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
-};
-
-/* mmc4 */
-static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
-        { .role = "clk32k", .clk = "mmc4_clk32k" },
-};
-
-static struct omap_hwmod dra7xx_mmc4_hwmod = {
-        .name           = "mmc4",
-        .class          = &dra7xx_mmc_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .main_clk       = "mmc4_gfclk_div",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-        .opt_clks       = mmc4_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
-};
-
-/*
  * 'mpu' class
  *
  */
@@ -1832,7 +1412,7 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
  * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
  * lines after asserting them.
  */
-static int dra7xx_pciess_reset(struct omap_hwmod *oh)
+int dra7xx_pciess_reset(struct omap_hwmod *oh)
 {
         int i;
 
@@ -2019,7 +1599,6 @@ static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
         .name   = "smartreflex",
         .sysc   = &dra7xx_smartreflex_sysc,
-        .rev    = 2,
 };
 
 /* smartreflex_core */
@@ -2375,188 +1954,6 @@ static struct omap_hwmod dra7xx_timer16_hwmod = {
         },
 };
 
-/*
- * 'uart' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
-        .rev_offs       = 0x0050,
-        .sysc_offs      = 0x0054,
-        .syss_offs      = 0x0058,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
-                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
-                           SYSS_HAS_RESET_STATUS),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
-        .name   = "uart",
-        .sysc   = &dra7xx_uart_sysc,
-};
-
-/* uart1 */
-static struct omap_hwmod dra7xx_uart1_hwmod = {
-        .name           = "uart1",
-        .class          = &dra7xx_uart_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .main_clk       = "uart1_gfclk_mux",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart2 */
-static struct omap_hwmod dra7xx_uart2_hwmod = {
-        .name           = "uart2",
-        .class          = &dra7xx_uart_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .main_clk       = "uart2_gfclk_mux",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart3 */
-static struct omap_hwmod dra7xx_uart3_hwmod = {
-        .name           = "uart3",
-        .class          = &dra7xx_uart_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .main_clk       = "uart3_gfclk_mux",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart4 */
-static struct omap_hwmod dra7xx_uart4_hwmod = {
-        .name           = "uart4",
-        .class          = &dra7xx_uart_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .main_clk       = "uart4_gfclk_mux",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart5 */
-static struct omap_hwmod dra7xx_uart5_hwmod = {
-        .name           = "uart5",
-        .class          = &dra7xx_uart_hwmod_class,
-        .clkdm_name     = "l4per_clkdm",
-        .main_clk       = "uart5_gfclk_mux",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart6 */
-static struct omap_hwmod dra7xx_uart6_hwmod = {
-        .name           = "uart6",
-        .class          = &dra7xx_uart_hwmod_class,
-        .clkdm_name     = "ipu_clkdm",
-        .main_clk       = "uart6_gfclk_mux",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart7 */
-static struct omap_hwmod dra7xx_uart7_hwmod = {
-        .name           = "uart7",
-        .class          = &dra7xx_uart_hwmod_class,
-        .clkdm_name     = "l4per2_clkdm",
-        .main_clk       = "uart7_gfclk_mux",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart8 */
-static struct omap_hwmod dra7xx_uart8_hwmod = {
-        .name           = "uart8",
-        .class          = &dra7xx_uart_hwmod_class,
-        .clkdm_name     = "l4per2_clkdm",
-        .main_clk       = "uart8_gfclk_mux",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart9 */
-static struct omap_hwmod dra7xx_uart9_hwmod = {
-        .name           = "uart9",
-        .class          = &dra7xx_uart_hwmod_class,
-        .clkdm_name     = "l4per2_clkdm",
-        .main_clk       = "uart9_gfclk_mux",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/* uart10 */
-static struct omap_hwmod dra7xx_uart10_hwmod = {
-        .name           = "uart10",
-        .class          = &dra7xx_uart_hwmod_class,
-        .clkdm_name     = "wkupaon_clkdm",
-        .main_clk       = "uart10_gfclk_mux",
-        .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
-                        .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
 /* DES (the 'P' (public) device) */
 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
         .rev_offs       = 0x0030,
@@ -3113,70 +2510,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
-        .master         = &dra7xx_l4_wkup_hwmod,
-        .slave          = &dra7xx_gpio1_hwmod,
-        .clk            = "wkupaon_iclk_mux",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> gpio2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_gpio2_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> gpio3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_gpio3_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> gpio4 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_gpio4_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> gpio5 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_gpio5_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> gpio6 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_gpio6_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> gpio7 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_gpio7_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> gpio8 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_gpio8_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l3_main_1 -> gpmc */
 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
         .master         = &dra7xx_l3_main_1_hwmod,
@@ -3193,46 +2526,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_per1 -> i2c1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_i2c1_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> i2c2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_i2c2_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> i2c3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_i2c3_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> i2c4 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_i2c4_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> i2c5 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_i2c5_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_cfg -> mailbox1 */
 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
         .master         = &dra7xx_l4_cfg_hwmod,
@@ -3369,38 +2662,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_per1 -> mmc1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_mmc1_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> mmc2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_mmc2_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> mmc3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_mmc3_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> mmc4 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_mmc4_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_cfg -> mpu */
 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
         .master         = &dra7xx_l4_cfg_hwmod,
@@ -3633,62 +2894,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_per1 -> uart1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_uart1_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> uart2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_uart2_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> uart3 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_uart3_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> uart4 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_uart4_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> uart5 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_uart5_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per1 -> uart6 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
-        .master         = &dra7xx_l4_per1_hwmod,
-        .slave          = &dra7xx_uart6_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> uart7 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
-        .master         = &dra7xx_l4_per2_hwmod,
-        .slave          = &dra7xx_uart7_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_per1 -> des */
 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
         .master         = &dra7xx_l4_per1_hwmod,
@@ -3697,30 +2902,6 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l4_per2 -> uart8 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
-        .master         = &dra7xx_l4_per2_hwmod,
-        .slave          = &dra7xx_uart8_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> uart9 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
-        .master         = &dra7xx_l4_per2_hwmod,
-        .slave          = &dra7xx_uart9_hwmod,
-        .clk            = "l3_iclk_div",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> uart10 */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
-        .master         = &dra7xx_l4_wkup_hwmod,
-        .slave          = &dra7xx_uart10_hwmod,
-        .clk            = "wkupaon_iclk_mux",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l4_per1 -> rng */
 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
         .master         = &dra7xx_l4_per1_hwmod,
@@ -3866,21 +3047,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
         &dra7xx_l3_main_1__aes2,
         &dra7xx_l3_main_1__sha0,
         &dra7xx_l4_per1__elm,
-        &dra7xx_l4_wkup__gpio1,
-        &dra7xx_l4_per1__gpio2,
-        &dra7xx_l4_per1__gpio3,
-        &dra7xx_l4_per1__gpio4,
-        &dra7xx_l4_per1__gpio5,
-        &dra7xx_l4_per1__gpio6,
-        &dra7xx_l4_per1__gpio7,
-        &dra7xx_l4_per1__gpio8,
         &dra7xx_l3_main_1__gpmc,
         &dra7xx_l4_per1__hdq1w,
-        &dra7xx_l4_per1__i2c1,
-        &dra7xx_l4_per1__i2c2,
-        &dra7xx_l4_per1__i2c3,
-        &dra7xx_l4_per1__i2c4,
-        &dra7xx_l4_per1__i2c5,
         &dra7xx_l4_cfg__mailbox1,
         &dra7xx_l4_per3__mailbox2,
         &dra7xx_l4_per3__mailbox3,
@@ -3898,10 +3066,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
         &dra7xx_l4_per1__mcspi2,
         &dra7xx_l4_per1__mcspi3,
         &dra7xx_l4_per1__mcspi4,
-        &dra7xx_l4_per1__mmc1,
-        &dra7xx_l4_per1__mmc2,
-        &dra7xx_l4_per1__mmc3,
-        &dra7xx_l4_per1__mmc4,
         &dra7xx_l4_cfg__mpu,
         &dra7xx_l4_cfg__ocp2scp1,
         &dra7xx_l4_cfg__ocp2scp3,
@@ -3929,16 +3093,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
         &dra7xx_l4_per3__timer14,
         &dra7xx_l4_per3__timer15,
         &dra7xx_l4_per3__timer16,
-        &dra7xx_l4_per1__uart1,
-        &dra7xx_l4_per1__uart2,
-        &dra7xx_l4_per1__uart3,
-        &dra7xx_l4_per1__uart4,
-        &dra7xx_l4_per1__uart5,
-        &dra7xx_l4_per1__uart6,
-        &dra7xx_l4_per2__uart7,
-        &dra7xx_l4_per2__uart8,
-        &dra7xx_l4_per2__uart9,
-        &dra7xx_l4_wkup__uart10,
         &dra7xx_l4_per1__des,
         &dra7xx_l4_per3__usb_otg_ss1,
         &dra7xx_l4_per3__usb_otg_ss2,
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index debcd88ab971..83230d9ce5ed 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -484,7 +484,6 @@ static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
         .name   = "gpio",
         .sysc   = &dm81xx_gpio_sysc,
-        .rev    = 2,
 };
 
 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c
index 724cf5774a6c..c93b6efd565f 100644
--- a/arch/arm/mach-omap2/pm33xx-core.c
+++ b/arch/arm/mach-omap2/pm33xx-core.c
@@ -51,10 +51,12 @@ static int amx3_common_init(void)
 
         /* CEFUSE domain can be turned off post bootup */
         cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
-        if (cefuse_pwrdm)
-                omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
-        else
+        if (!cefuse_pwrdm)
                 pr_err("PM: Failed to get cefuse_pwrdm\n");
+        else if (omap_type() != OMAP2_DEVICE_TYPE_GP)
+                pr_info("PM: Leaving EFUSE power domain active\n");
+        else
+                omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index 0854ed9ff379..248f6d9a1bb3 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -119,7 +119,10 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
         }
 
         sr_data->name = oh->name;
-        sr_data->ip_type = oh->class->rev;
+        if (cpu_is_omap343x())
+                sr_data->ip_type = 1;
+        else
+                sr_data->ip_type = 2;
         sr_data->senn_mod = 0x1;
         sr_data->senp_mod = 0x1;
 
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 51984a40b097..4675d9202000 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -245,6 +245,7 @@ static int __init rockchip_smp_prepare_pmu(void)
         }
 
         pmu_base = of_iomap(node, 0);
+        of_node_put(node);
         if (!pmu_base) {
                 pr_err("%s: could not map pmu registers\n", __func__);
                 return -ENOMEM;
diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index 0592534e0b88..065b09e6f1eb 100644
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -59,7 +59,7 @@ static inline u32 rk3288_l2_config(void)
         return l2ctlr;
 }
 
-static void rk3288_config_bootdata(void)
+static void __init rk3288_config_bootdata(void)
 {
         rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
         rkpm_bootdata_cpu_code = __pa_symbol(cpu_resume);
@@ -230,7 +230,7 @@ static void rk3288_suspend_finish(void)
                 pr_err("%s: Suspend finish failed\n", __func__);
 }
 
-static int rk3288_suspend_init(struct device_node *np)
+static int __init rk3288_suspend_init(struct device_node *np)
 {
         struct device_node *sram_np;
         struct resource res;
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 76c4855a03bc..937d0a83f8fd 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -328,6 +328,8 @@ static const struct {
         int num_i2c_devs;
         const struct spi_board_info *spi_devs;
         int num_spi_devs;
+
+        struct gpiod_lookup_table *gpiod_table;
 } gf_mods[] = {
         { .id = 0x01, .rev = 0xff, .name = "1250-EV1 Springbank" },
         { .id = 0x02, .rev = 0xff, .name = "1251-EV1 Jura" },
@@ -362,13 +364,16 @@ static const struct {
           .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
         { .id = 0x3c, .rev = 0xff, .name = "1273-EV1 Longmorn" },
         { .id = 0x3d, .rev = 0xff, .name = "1277-EV1 Littlemill",
-          .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) },
+          .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs),
+          .gpiod_table = &wm8994_gpiod_table },
         { .id = 0x3e, .rev = 0, .name = "WM5102-6271-EV1-CS127 Amrut",
           .spi_devs = wm5102_reva_spi_devs,
-          .num_spi_devs = ARRAY_SIZE(wm5102_reva_spi_devs) },
+          .num_spi_devs = ARRAY_SIZE(wm5102_reva_spi_devs),
+          .gpiod_table = &wm5102_reva_gpiod_table },
         { .id = 0x3e, .rev = -1, .name = "WM5102-6271-EV1-CS127 Amrut",
           .spi_devs = wm5102_spi_devs,
-          .num_spi_devs = ARRAY_SIZE(wm5102_spi_devs) },
+          .num_spi_devs = ARRAY_SIZE(wm5102_spi_devs),
+          .gpiod_table = &wm5102_gpiod_table },
         { .id = 0x3f, .rev = -1, .name = "WM2200-6271-CS90-M-REV1",
           .i2c_devs = wm2200_i2c, .num_i2c_devs = ARRAY_SIZE(wm2200_i2c) },
 };
@@ -408,6 +413,9 @@ static int wlf_gf_module_probe(struct i2c_client *i2c,
 
                 spi_register_board_info(gf_mods[i].spi_devs,
                                         gf_mods[i].num_spi_devs);
+
+                if (gf_mods[i].gpiod_table)
+                        gpiod_add_lookup_table(gf_mods[i].gpiod_table);
         } else {
                 dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n",
                          id, rev + 1);
diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index 8c2a20591524..e84599dd96f1 100644
--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -72,6 +72,7 @@ void __init rcar_gen2_pm_init(void)
         }
 
         error = of_address_to_resource(np, 0, &res);
+        of_node_put(np);
         if (error) {
                 pr_err("Failed to get smp-sram address: %d\n", error);
                 return;
diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
index dc526ef2e9b3..ee949255ced3 100644
--- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * R-Car Generation 2 da9063/da9210 regulator quirk
+ * R-Car Generation 2 da9063(L)/da9210 regulator quirk
  *
  * Certain Gen2 development boards have an da9063 and one or more da9210
  * regulators. All of these regulators have their interrupt request lines
@@ -65,6 +65,7 @@ static struct i2c_msg da9210_msg = {
 
 static const struct of_device_id rcar_gen2_quirk_match[] = {
         { .compatible = "dlg,da9063", .data = &da9063_msg },
+        { .compatible = "dlg,da9063l", .data = &da9063_msg },
         { .compatible = "dlg,da9210", .data = &da9210_msg },
         {},
 };
@@ -147,6 +148,7 @@ static int __init rcar_gen2_regulator_quirk(void)
 
         if (!of_machine_is_compatible("renesas,koelsch") &&
             !of_machine_is_compatible("renesas,lager") &&
+            !of_machine_is_compatible("renesas,porter") &&
             !of_machine_is_compatible("renesas,stout") &&
             !of_machine_is_compatible("renesas,gose"))
                 return -ENODEV;
@@ -210,7 +212,7 @@ static int __init rcar_gen2_regulator_quirk(void)
                 goto err_free;
         }
 
-        pr_info("IRQ2 is asserted, installing da9063/da9210 regulator quirk\n");
+        pr_info("IRQ2 is asserted, installing regulator quirk\n");
 
         bus_register_notifier(&i2c_bus_type, &regulator_quirk_nb);
         return 0;
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 713c068b953f..651bdf4f9c9e 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -4,6 +4,7 @@ menuconfig ARCH_STM32
         select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
         select ARM_GIC if ARCH_MULTI_V7
         select ARM_PSCI if ARCH_MULTI_V7
+        select ARM_AMBA
         select ARCH_HAS_RESET_CONTROLLER
         select CLKSRC_STM32
         select PINCTRL
@@ -18,22 +19,18 @@ if ARM_SINGLE_ARMV7M
 
 config MACH_STM32F429
         bool "STMicroelectronics STM32F429"
-        select ARM_AMBA
         default y
 
 config MACH_STM32F469
         bool "STMicroelectronics STM32F469"
-        select ARM_AMBA
         default y
 
 config MACH_STM32F746
         bool "STMicroelectronics STM32F746"
-        select ARM_AMBA
         default y
 
 config MACH_STM32F769
         bool "STMicroelectronics STM32F769"
-        select ARM_AMBA
         default y
 
 config MACH_STM32H743
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index b4037b603897..239084cf8192 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -89,6 +89,7 @@ static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
         struct device_node *node;
         int cpu = cluster * SUNXI_CPUS_PER_CLUSTER + core;
+        bool is_compatible;
 
         node = of_cpu_device_node_get(cpu);
 
@@ -107,7 +108,9 @@ static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
                 return false;
         }
 
-        return of_device_is_compatible(node, "arm,cortex-a15");
+        is_compatible = of_device_is_compatible(node, "arm,cortex-a15");
+        of_node_put(node);
+        return is_compatible;
 }
 
 static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster,
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index 8fb5088464db..bdde9ef3aaa9 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -50,6 +50,7 @@ static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
         }
 
         prcm_membase = of_iomap(node, 0);
+        of_node_put(node);
         if (!prcm_membase) {
                 pr_err("Couldn't map A31 PRCM registers\n");
                 return;
@@ -63,6 +64,7 @@ static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
         }
 
         cpucfg_membase = of_iomap(node, 0);
+        of_node_put(node);
         if (!cpucfg_membase)
                 pr_err("Couldn't map A31 CPU config registers\n");
 
@@ -133,6 +135,7 @@ static void __init sun8i_smp_prepare_cpus(unsigned int max_cpus)
         }
 
         prcm_membase = of_iomap(node, 0);
+        of_node_put(node);
         if (!prcm_membase) {
                 pr_err("Couldn't map A23 PRCM registers\n");
                 return;
@@ -146,6 +149,7 @@ static void __init sun8i_smp_prepare_cpus(unsigned int max_cpus)
         }
 
         cpucfg_membase = of_iomap(node, 0);
+        of_node_put(node);
         if (!cpucfg_membase)
                 pr_err("Couldn't map A23 CPU config registers\n");
 
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 7f3b83e0d324..63e89e75639b 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -2,7 +2,7 @@
 menuconfig ARCH_TEGRA
         bool "NVIDIA Tegra"
         depends on ARCH_MULTI_V7
-        select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS
+        select ARCH_HAS_RESET_CONTROLLER
         select ARM_AMBA
         select ARM_GIC
         select CLKSRC_MMIO
@@ -11,7 +11,6 @@ menuconfig ARCH_TEGRA
         select HAVE_ARM_TWD if SMP
         select PINCTRL
         select PM_OPP
-        select ARCH_HAS_RESET_CONTROLLER
         select RESET_CONTROLLER
         select SOC_BUS
         select ZONE_DMA if ARM_LPAE
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index e3fbcfedf845..43c695d83f03 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -21,6 +21,8 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 
+#include <linux/firmware/trusted_foundations.h>
+
 #include <asm/cpuidle.h>
 #include <asm/smp_plat.h>
 #include <asm/suspend.h>
@@ -46,7 +48,7 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
         tegra_set_cpu_in_lp2();
         cpu_pm_enter();
 
-        call_firmware_op(prepare_idle);
+        call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2);
 
         /* Do suspend by ourselves if the firmware does not implement it */
         if (call_firmware_op(do_idle, 0) == -ENOSYS)
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 1ad5719779b0..1b0ade06f204 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -27,12 +27,15 @@
 #include <linux/spinlock.h>
 #include <linux/suspend.h>
 
+#include <linux/firmware/trusted_foundations.h>
+
 #include <soc/tegra/flowctrl.h>
 #include <soc/tegra/fuse.h>
 #include <soc/tegra/pm.h>
 #include <soc/tegra/pmc.h>
 
 #include <asm/cacheflush.h>
+#include <asm/firmware.h>
 #include <asm/idmap.h>
 #include <asm/proc-fns.h>
 #include <asm/smp_plat.h>
@@ -159,6 +162,28 @@ int tegra_cpu_do_idle(void)
 
 static int tegra_sleep_cpu(unsigned long v2p)
 {
+        /*
+         * L2 cache disabling using kernel API only allowed when all
+         * secondary CPU's are offline. Cache have to be disabled with
+         * MMU-on if cache maintenance is done via Trusted Foundations
+         * firmware. Note that CPUIDLE won't ever enter powergate on Tegra30
+         * if any of secondary CPU's is online and this is the LP2-idle
+         * code-path only for Tegra20/30.
+         */
+        if (trusted_foundations_registered())
+                outer_disable();
+
+        /*
+         * Note that besides of setting up CPU reset vector this firmware
+         * call may also do the following, depending on the FW version:
+         *  1) Disable L2. But this doesn't matter since we already
+         *     disabled the L2.
+         *  2) Disable D-cache. This need to be taken into account in
+         *     particular by the tegra_disable_clean_inv_dcache() which
+         *     shall avoid the re-disable.
+         */
+        call_firmware_op(prepare_idle, TF_PM_MODE_LP2);
+
         setup_mm_for_reboot();
         tegra_sleep_cpu_finish(v2p);
 
@@ -197,6 +222,14 @@ void tegra_idle_lp2_last(void)
 
         cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
 
+        /*
+         * Resume L2 cache if it wasn't re-enabled early during resume,
+         * which is the case for Tegra30 that has to re-enable the cache
+         * via firmware call. In other cases cache is already enabled and
+         * hence re-enabling is a no-op. This is always a no-op on Tegra114+.
+         */
+        outer_resume();
+
         restore_cpu_complex();
         cpu_cluster_pm_exit();
 }
@@ -215,6 +248,15 @@ enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
 
 static int tegra_sleep_core(unsigned long v2p)
 {
+        /*
+         * Cache have to be disabled with MMU-on if cache maintenance is done
+         * via Trusted Foundations firmware. This is a no-op on Tegra114+.
+         */
+        if (trusted_foundations_registered())
+                outer_disable();
+
+        call_firmware_op(prepare_idle, TF_PM_MODE_LP1);
+
         setup_mm_for_reboot();
         tegra_sleep_core_finish(v2p);
 
@@ -342,6 +384,14 @@ static int tegra_suspend_enter(suspend_state_t state)
 
         cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
 
+        /*
+         * Resume L2 cache if it wasn't re-enabled early during resume,
+         * which is the case for Tegra30 that has to re-enable the cache
+         * via firmware call. In other cases cache is already enabled and
+         * hence re-enabling is a no-op.
+         */
+        outer_resume();
+
         switch (mode) {
         case TEGRA_SUSPEND_LP1:
                 tegra_suspend_exit_lp1();
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index e22ccf87eded..cd94d7c41fc0 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -20,6 +20,7 @@
 #include <soc/tegra/flowctrl.h>
 #include <soc/tegra/fuse.h>
 
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/cache.h>
 
@@ -29,8 +30,6 @@
 
 #define PMC_SCRATCH41   0x140
 
-#define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
-
 #ifdef CONFIG_PM_SLEEP
 /*
  *      tegra_resume
@@ -78,6 +77,7 @@ ENTRY(tegra_resume)
         orr     r1, r1, #1
         str     r1, [r0]
 #endif
+        bl      tegra_resume_trusted_foundations
 
 #ifdef CONFIG_CACHE_L2X0
         /* L2 cache resume & re-enable */
@@ -90,6 +90,30 @@ end_ca9_scu_l2_resume:
 
         b       cpu_resume
 ENDPROC(tegra_resume)
+
+/*
+ *      tegra_resume_trusted_foundations
+ *
+ *        Trusted Foundations firmware initialization.
+ *
+ *      Doesn't return if firmware presents.
+ *      Corrupted registers: r1, r2
+ */
+ENTRY(tegra_resume_trusted_foundations)
+        /* Check whether Trusted Foundations firmware presents. */
+        mov32   r2, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
+        ldr     r1, =__tegra_cpu_reset_handler_data_offset + \
+                                                        RESET_DATA(TF_PRESENT)
+        ldr     r1, [r2, r1]
+        cmp     r1, #0
+        reteq   lr
+
+ .arch_extension sec
+        /* First call after suspend wakes firmware. No arguments required. */
+        smc     #0
+
+        b       cpu_resume
+ENDPROC(tegra_resume_trusted_foundations)
 #endif
 
         .align L1_CACHE_SHIFT
@@ -115,12 +139,19 @@ ENTRY(__tegra_cpu_reset_handler_start)
  *       must be position-independent.
  */
 
+        .arm
         .align L1_CACHE_SHIFT
 ENTRY(__tegra_cpu_reset_handler)
 
         cpsid   aif, 0x13                       @ SVC mode, interrupts disabled
 
         tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
+
+        adr     r12, __tegra_cpu_reset_handler_data
+        ldr     r5, [r12, #RESET_DATA(TF_PRESENT)]
+        cmp     r5, #0
+        bne     after_errata
+
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 t20_check:
         cmp     r6, #TEGRA20
@@ -155,7 +186,6 @@ after_errata:
         and     r10, r10, #0x3                  @ R10 = CPU number
         mov     r11, #1
         mov     r11, r11, lsl r10               @ R11 = CPU mask
-        adr     r12, __tegra_cpu_reset_handler_data
 
 #ifdef CONFIG_SMP
         /* Does the OS know about this CPU? */
@@ -169,10 +199,9 @@ after_errata:
         cmp     r6, #TEGRA20
         bne     1f
         /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
-        mov32   r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
         mov     r0, #CPU_NOT_RESETTABLE
         cmp     r10, #0
-        strbne  r0, [r5, #__tegra20_cpu1_resettable_status_offset]
+        strbne  r0, [r12, #RESET_DATA(RESETTABLE_STATUS)]
 1:
 #endif
 
@@ -277,14 +306,13 @@ ENDPROC(__tegra_cpu_reset_handler)
         .align L1_CACHE_SHIFT
         .type   __tegra_cpu_reset_handler_data, %object
         .globl  __tegra_cpu_reset_handler_data
+        .globl  __tegra_cpu_reset_handler_data_offset
+        .equ    __tegra_cpu_reset_handler_data_offset, \
+                                        . - __tegra_cpu_reset_handler_start
 __tegra_cpu_reset_handler_data:
-        .rept   TEGRA_RESET_DATA_SIZE
-        .long   0
+        .rept   TEGRA_RESET_DATA_SIZE
+        .long   0
         .endr
-        .globl  __tegra20_cpu1_resettable_status_offset
-        .equ    __tegra20_cpu1_resettable_status_offset, \
-                                        . - __tegra_cpu_reset_handler_start
-        .byte   0
         .align L1_CACHE_SHIFT
 
 ENTRY(__tegra_cpu_reset_handler_end)
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index dc558892753c..35dc5d419b6f 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -19,6 +19,8 @@
 #include <linux/init.h>
 #include <linux/io.h>
 
+#include <linux/firmware/trusted_foundations.h>
+
 #include <soc/tegra/fuse.h>
 
 #include <asm/cacheflush.h>
@@ -89,6 +91,8 @@ static void __init tegra_cpu_reset_handler_enable(void)
 
 void __init tegra_cpu_reset_handler_init(void)
 {
+        __tegra_cpu_reset_handler_data[TEGRA_RESET_TF_PRESENT] =
+                trusted_foundations_registered();
 
 #ifdef CONFIG_SMP
         __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
index 9c479c7925b8..db0e6b3097ab 100644
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -25,7 +25,11 @@
 #define TEGRA_RESET_STARTUP_SECONDARY   3
 #define TEGRA_RESET_STARTUP_LP2         4
 #define TEGRA_RESET_STARTUP_LP1         5
-#define TEGRA_RESET_DATA_SIZE           6
+#define TEGRA_RESET_RESETTABLE_STATUS   6
+#define TEGRA_RESET_TF_PRESENT          7
+#define TEGRA_RESET_DATA_SIZE           8
+
+#define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
 
 #ifndef __ASSEMBLY__
 
@@ -49,7 +53,8 @@ void __tegra_cpu_reset_handler_end(void);
          (u32)__tegra_cpu_reset_handler_start)))
 #define tegra20_cpu1_resettable_status \
         (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
-         (u32)__tegra20_cpu1_resettable_status_offset))
+        ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \
+         (u32)__tegra_cpu_reset_handler_start)))
 #endif
 
 #define tegra_cpu_reset_handler_offset \
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index dedeebfccc55..50d51d3465f6 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -28,6 +28,7 @@
 #include <asm/cache.h>
 
 #include "irammap.h"
+#include "reset.h"
 #include "sleep.h"
 
 #define EMC_CFG                         0xc
@@ -53,6 +54,9 @@
 #define APB_MISC_XM2CFGCPADCTRL2        0x8e4
 #define APB_MISC_XM2CFGDPADCTRL2        0x8e8
 
+#define __tegra20_cpu1_resettable_status_offset \
+        (__tegra_cpu_reset_handler_data_offset + RESET_DATA(RESETTABLE_STATUS))
+
 .macro pll_enable, rd, r_car_base, pll_base
         ldr     \rd, [\r_car_base, #\pll_base]
         tst     \rd, #(1 << 30)
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 5e3496753df1..1735ded5a812 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -49,8 +49,9 @@ ENTRY(tegra_disable_clean_inv_dcache)
 
         /* Disable the D-cache */
         mrc     p15, 0, r2, c1, c0, 0
+        tst     r2, #CR_C                       @ see tegra_sleep_cpu()
         bic     r2, r2, #CR_C
-        mcr     p15, 0, r2, c1, c0, 0
+        mcrne   p15, 0, r2, c1, c0, 0
         isb
 
         /* Flush the D-cache */
@@ -132,10 +133,13 @@ ENTRY(tegra_shut_off_mmu)
 #ifdef CONFIG_CACHE_L2X0
         /* Disable L2 cache */
         check_cpu_part_num 0xc09, r9, r10
-        movweq  r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
-        movteq  r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
-        moveq   r3, #0
-        streq   r3, [r2, #L2X0_CTRL]
+        retne   r0
+
+        mov32   r2, TEGRA_ARM_PERIF_BASE + 0x3000
+        ldr     r3, [r2, #L2X0_CTRL]
+        tst     r3, #L2X0_CTRL_EN               @ see tegra_sleep_cpu()
+        mov     r3, #0
+        strne   r3, [r2, #L2X0_CTRL]
 #endif
         ret     r0
 ENDPROC(tegra_shut_off_mmu)
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index f9587be48235..3e88f67dd521 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -35,15 +35,17 @@
 #include <linux/sys_soc.h>
 #include <linux/usb/tegra_usb_phy.h>
 
+#include <linux/firmware/trusted_foundations.h>
+
 #include <soc/tegra/fuse.h>
 #include <soc/tegra/pmc.h>
 
+#include <asm/firmware.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
-#include <asm/trusted_foundations.h>
 
 #include "board.h"
 #include "common.h"
@@ -74,6 +76,7 @@ static void __init tegra_init_early(void)
 {
         of_register_trusted_foundations();
         tegra_cpu_reset_handler_init();
+        call_firmware_op(l2x0_init);
 }
 
 static void __init tegra_dt_init_irq(void)
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index 595b574c2c50..96ec72bd3928 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -130,3 +130,5 @@ static int __init u300_init_boardpower(void)
 }
 
 device_initcall(u300_init_boardpower);
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Linus Walleij");
diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c
index f51919974183..bf25f780c1c9 100644
--- a/arch/arm/plat-pxa/ssp.c
+++ b/arch/arm/plat-pxa/ssp.c
@@ -183,18 +183,12 @@ static int pxa_ssp_probe(struct platform_device *pdev)
 
 static int pxa_ssp_remove(struct platform_device *pdev)
 {
-        struct resource *res;
         struct ssp_device *ssp;
 
         ssp = platform_get_drvdata(pdev);
         if (ssp == NULL)
                 return -ENODEV;
 
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        release_mem_region(res->start, resource_size(res));
-
-        clk_put(ssp->clk);
-
         mutex_lock(&ssp_lock);
         list_del(&ssp->node);
         mutex_unlock(&ssp_lock);
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index 7793ebb5d2b8..0a56c0c23ba1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -104,7 +104,7 @@
 };
 
 &codec_analog {
-        hpvcc-supply = <&reg_eldo1>;
+        cpvdd-supply = <&reg_eldo1>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index c0b9cc7a6b3a..b7ac6374b178 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -80,7 +80,7 @@
 };
 
 &codec_analog {
-        hpvcc-supply = <&reg_eldo1>;
+        cpvdd-supply = <&reg_eldo1>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index d22736a62481..78c82a665c84 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -94,7 +94,7 @@
 };
 
 &codec_analog {
-        hpvcc-supply = <&reg_eldo1>;
+        cpvdd-supply = <&reg_eldo1>;
         status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
index d2651f284aa0..9d20e13f0c02 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
@@ -48,7 +48,7 @@
 #include <dt-bindings/gpio/gpio.h>
 
 &codec_analog {
-        hpvcc-supply = <&reg_eldo1>;
+        cpvdd-supply = <&reg_eldo1>;
 };
 
 &mmc0 {
diff --git a/drivers/ata/pata_ep93xx.c b/drivers/ata/pata_ep93xx.c
index cc6d06c1b2c7..db271b705529 100644
--- a/drivers/ata/pata_ep93xx.c
+++ b/drivers/ata/pata_ep93xx.c
@@ -44,7 +44,7 @@
 #include <linux/ktime.h>
 
 #include <linux/platform_data/dma-ep93xx.h>
-#include <mach/platform.h>
+#include <linux/soc/cirrus/ep93xx.h>
 
 #define DRV_NAME        "ep93xx-ide"
 #define DRV_VERSION     "1.0"
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
index d299ec79e4c3..308475ed4b32 100644
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -47,7 +47,10 @@ enum sysc_clocks {
         SYSC_MAX_CLOCKS,
 };
 
-static const char * const clock_names[SYSC_ICK + 1] = { "fck", "ick", };
+static const char * const clock_names[SYSC_MAX_CLOCKS] = {
+        "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
+        "opt5", "opt6", "opt7",
+};
 
 #define SYSC_IDLEMODE_MASK              3
 #define SYSC_CLOCKACTIVITY_MASK         3
@@ -75,6 +78,7 @@ struct sysc {
         u32 module_size;
         void __iomem *module_va;
         int offsets[SYSC_MAX_REGS];
+        struct ti_sysc_module_data *mdata;
         struct clk **clocks;
         const char **clock_roles;
         int nr_clocks;
@@ -94,7 +98,7 @@ struct sysc {
 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
                                   bool is_child);
 
-void sysc_write(struct sysc *ddata, int offset, u32 value)
+static void sysc_write(struct sysc *ddata, int offset, u32 value)
 {
         writel_relaxed(value, ddata->module_va + offset);
 }
@@ -128,6 +132,81 @@ static u32 sysc_read_revision(struct sysc *ddata)
         return sysc_read(ddata, offset);
 }
 
+static int sysc_add_named_clock_from_child(struct sysc *ddata,
+                                           const char *name,
+                                           const char *optfck_name)
+{
+        struct device_node *np = ddata->dev->of_node;
+        struct device_node *child;
+        struct clk_lookup *cl;
+        struct clk *clock;
+        const char *n;
+
+        if (name)
+                n = name;
+        else
+                n = optfck_name;
+
+        /* Does the clock alias already exist? */
+        clock = of_clk_get_by_name(np, n);
+        if (!IS_ERR(clock)) {
+                clk_put(clock);
+
+                return 0;
+        }
+
+        child = of_get_next_available_child(np, NULL);
+        if (!child)
+                return -ENODEV;
+
+        clock = devm_get_clk_from_child(ddata->dev, child, name);
+        if (IS_ERR(clock))
+                return PTR_ERR(clock);
+
+        /*
+         * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
+         * limit for clk_get(). If cl ever needs to be freed, it should be done
+         * with clkdev_drop().
+         */
+        cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
+        if (!cl)
+                return -ENOMEM;
+
+        cl->con_id = n;
+        cl->dev_id = dev_name(ddata->dev);
+        cl->clk = clock;
+        clkdev_add(cl);
+
+        clk_put(clock);
+
+        return 0;
+}
+
+static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
+{
+        const char *optfck_name;
+        int error, index;
+
+        if (ddata->nr_clocks < SYSC_OPTFCK0)
+                index = SYSC_OPTFCK0;
+        else
+                index = ddata->nr_clocks;
+
+        if (name)
+                optfck_name = name;
+        else
+                optfck_name = clock_names[index];
+
+        error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
+        if (error)
+                return error;
+
+        ddata->clock_roles[index] = optfck_name;
+        ddata->nr_clocks++;
+
+        return 0;
+}
+
 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
 {
         int error, i, index = -ENODEV;
@@ -199,6 +278,12 @@ static int sysc_get_clocks(struct sysc *ddata)
         if (ddata->nr_clocks < 1)
                 return 0;
 
+        if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
+                error = sysc_init_ext_opt_clock(ddata, NULL);
+                if (error)
+                        return error;
+        }
+
         if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
                 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
 
@@ -231,39 +316,125 @@ static int sysc_get_clocks(struct sysc *ddata)
         return 0;
 }
 
+static int sysc_enable_main_clocks(struct sysc *ddata)
+{
+        struct clk *clock;
+        int i, error;
+
+        if (!ddata->clocks)
+                return 0;
+
+        for (i = 0; i < SYSC_OPTFCK0; i++) {
+                clock = ddata->clocks[i];
+
+                /* Main clocks may not have ick */
+                if (IS_ERR_OR_NULL(clock))
+                        continue;
+
+                error = clk_enable(clock);
+                if (error)
+                        goto err_disable;
+        }
+
+        return 0;
+
+err_disable:
+        for (i--; i >= 0; i--) {
+                clock = ddata->clocks[i];
+
+                /* Main clocks may not have ick */
+                if (IS_ERR_OR_NULL(clock))
+                        continue;
+
+                clk_disable(clock);
+        }
+
+        return error;
+}
+
+static void sysc_disable_main_clocks(struct sysc *ddata)
+{
+        struct clk *clock;
+        int i;
+
+        if (!ddata->clocks)
+                return;
+
+        for (i = 0; i < SYSC_OPTFCK0; i++) {
+                clock = ddata->clocks[i];
+                if (IS_ERR_OR_NULL(clock))
+                        continue;
+
+                clk_disable(clock);
+        }
+}
+
+static int sysc_enable_opt_clocks(struct sysc *ddata)
+{
+        struct clk *clock;
+        int i, error;
+
+        if (!ddata->clocks)
+                return 0;
+
+        for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
+                clock = ddata->clocks[i];
+
+                /* Assume no holes for opt clocks */
+                if (IS_ERR_OR_NULL(clock))
+                        return 0;
+
+                error = clk_enable(clock);
+                if (error)
+                        goto err_disable;
+        }
+
+        return 0;
+
+err_disable:
+        for (i--; i >= 0; i--) {
+                clock = ddata->clocks[i];
+                if (IS_ERR_OR_NULL(clock))
+                        continue;
+
+                clk_disable(clock);
+        }
+
+        return error;
+}
+
+static void sysc_disable_opt_clocks(struct sysc *ddata)
+{
+        struct clk *clock;
+        int i;
+
+        if (!ddata->clocks)
+                return;
+
+        for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
+                clock = ddata->clocks[i];
+
+                /* Assume no holes for opt clocks */
+                if (IS_ERR_OR_NULL(clock))
+                        return;
+
+                clk_disable(clock);
+        }
+}
+
 /**
- * sysc_init_resets - reset module on init
+ * sysc_init_resets - init rstctrl reset line if configured
  * @ddata: device driver data
  *
- * A module can have both OCP softreset control and external rstctrl.
- * If more complicated rstctrl resets are needed, please handle these
- * directly from the child device driver and map only the module reset
- * for the parent interconnect target module device.
- *
- * Automatic reset of the module on init can be skipped with the
- * "ti,no-reset-on-init" device tree property.
+ * See sysc_rstctrl_reset_deassert().
  */
 static int sysc_init_resets(struct sysc *ddata)
 {
-        int error;
-
         ddata->rsts =
                 devm_reset_control_array_get_optional_exclusive(ddata->dev);
         if (IS_ERR(ddata->rsts))
                 return PTR_ERR(ddata->rsts);
 
-        if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
-                goto deassert;
-
-        error = reset_control_assert(ddata->rsts);
-        if (error)
-                return error;
-
-deassert:
-        error = reset_control_deassert(ddata->rsts);
-        if (error)
-                return error;
-
         return 0;
 }
 
@@ -622,91 +793,239 @@ static void sysc_show_registers(struct sysc *ddata)
                 buf);
 }
 
-static int __maybe_unused sysc_runtime_suspend(struct device *dev)
+#define SYSC_IDLE_MASK  (SYSC_NR_IDLEMODES - 1)
+
+static int sysc_enable_module(struct device *dev)
 {
-        struct ti_sysc_platform_data *pdata;
         struct sysc *ddata;
-        int error = 0, i;
+        const struct sysc_regbits *regbits;
+        u32 reg, idlemodes, best_mode;
 
         ddata = dev_get_drvdata(dev);
+        if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
+                return 0;
 
-        if (!ddata->enabled)
+        /*
+         * TODO: Need to prevent clockdomain autoidle?
+         * See clkdm_deny_idle() in arch/mach-omap2/omap_hwmod.c
+         */
+
+        regbits = ddata->cap->regbits;
+        reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
+
+        /* Set SIDLE mode */
+        idlemodes = ddata->cfg.sidlemodes;
+        if (!idlemodes || regbits->sidle_shift < 0)
+                goto set_midle;
+
+        best_mode = fls(ddata->cfg.sidlemodes) - 1;
+        if (best_mode > SYSC_IDLE_MASK) {
+                dev_err(dev, "%s: invalid sidlemode\n", __func__);
+                return -EINVAL;
+        }
+
+        reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
+        reg |= best_mode << regbits->sidle_shift;
+        sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
+
+set_midle:
+        /* Set MIDLE mode */
+        idlemodes = ddata->cfg.midlemodes;
+        if (!idlemodes || regbits->midle_shift < 0)
                 return 0;
 
-        if (ddata->legacy_mode) {
-                pdata = dev_get_platdata(ddata->dev);
-                if (!pdata)
-                        return 0;
+        best_mode = fls(ddata->cfg.midlemodes) - 1;
+        if (best_mode > SYSC_IDLE_MASK) {
+                dev_err(dev, "%s: invalid midlemode\n", __func__);
+                return -EINVAL;
+        }
 
-                if (!pdata->idle_module)
-                        return -ENODEV;
+        reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
+        reg |= best_mode << regbits->midle_shift;
+        sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
 
-                error = pdata->idle_module(dev, &ddata->cookie);
-                if (error)
-                        dev_err(dev, "%s: could not idle: %i\n",
-                                __func__, error);
+        return 0;
+}
+
+static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
+{
+        if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
+                *best_mode = SYSC_IDLE_SMART_WKUP;
+        else if (idlemodes & BIT(SYSC_IDLE_SMART))
+                *best_mode = SYSC_IDLE_SMART;
+        else if (idlemodes & SYSC_IDLE_FORCE)
+                *best_mode = SYSC_IDLE_FORCE;
+        else
+                return -EINVAL;
+
+        return 0;
+}
+
+static int sysc_disable_module(struct device *dev)
+{
+        struct sysc *ddata;
+        const struct sysc_regbits *regbits;
+        u32 reg, idlemodes, best_mode;
+        int ret;
 
-                goto idled;
+        ddata = dev_get_drvdata(dev);
+        if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
+                return 0;
+
+        /*
+         * TODO: Need to prevent clockdomain autoidle?
+         * See clkdm_deny_idle() in arch/mach-omap2/omap_hwmod.c
+         */
+
+        regbits = ddata->cap->regbits;
+        reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
+
+        /* Set MIDLE mode */
+        idlemodes = ddata->cfg.midlemodes;
+        if (!idlemodes || regbits->midle_shift < 0)
+                goto set_sidle;
+
+        ret = sysc_best_idle_mode(idlemodes, &best_mode);
+        if (ret) {
+                dev_err(dev, "%s: invalid midlemode\n", __func__);
+                return ret;
         }
 
-        for (i = 0; i < ddata->nr_clocks; i++) {
-                if (IS_ERR_OR_NULL(ddata->clocks[i]))
-                        continue;
+        reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
+        reg |= best_mode << regbits->midle_shift;
+        sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
 
-                if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata))
-                        break;
+set_sidle:
+        /* Set SIDLE mode */
+        idlemodes = ddata->cfg.sidlemodes;
+        if (!idlemodes || regbits->sidle_shift < 0)
+                return 0;
 
-                clk_disable(ddata->clocks[i]);
+        ret = sysc_best_idle_mode(idlemodes, &best_mode);
+        if (ret) {
+                dev_err(dev, "%s: invalid sidlemode\n", __func__);
+                return ret;
         }
 
-idled:
-        ddata->enabled = false;
+        reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
+        reg |= best_mode << regbits->sidle_shift;
+        sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
 
-        return error;
+        return 0;
 }
 
-static int __maybe_unused sysc_runtime_resume(struct device *dev)
+static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
+                                                      struct sysc *ddata)
 {
         struct ti_sysc_platform_data *pdata;
+        int error;
+
+        pdata = dev_get_platdata(ddata->dev);
+        if (!pdata)
+                return 0;
+
+        if (!pdata->idle_module)
+                return -ENODEV;
+
+        error = pdata->idle_module(dev, &ddata->cookie);
+        if (error)
+                dev_err(dev, "%s: could not idle: %i\n",
+                        __func__, error);
+
+        return 0;
+}
+
+static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
+                                                     struct sysc *ddata)
+{
+        struct ti_sysc_platform_data *pdata;
+        int error;
+
+        pdata = dev_get_platdata(ddata->dev);
+        if (!pdata)
+                return 0;
+
+        if (!pdata->enable_module)
+                return -ENODEV;
+
+        error = pdata->enable_module(dev, &ddata->cookie);
+        if (error)
+                dev_err(dev, "%s: could not enable: %i\n",
+                        __func__, error);
+
+        return 0;
+}
+
+static int __maybe_unused sysc_runtime_suspend(struct device *dev)
+{
         struct sysc *ddata;
-        int error = 0, i;
+        int error = 0;
 
         ddata = dev_get_drvdata(dev);
 
-        if (ddata->enabled)
+        if (!ddata->enabled)
                 return 0;
 
         if (ddata->legacy_mode) {
-                pdata = dev_get_platdata(ddata->dev);
-                if (!pdata)
-                        return 0;
+                error = sysc_runtime_suspend_legacy(dev, ddata);
+                if (error)
+                        return error;
+        } else {
+                error = sysc_disable_module(dev);
+                if (error)
+                        return error;
+        }
 
-                if (!pdata->enable_module)
-                        return -ENODEV;
+        sysc_disable_main_clocks(ddata);
 
-                error = pdata->enable_module(dev, &ddata->cookie);
-                if (error)
-                        dev_err(dev, "%s: could not enable: %i\n",
-                                __func__, error);
+        if (sysc_opt_clks_needed(ddata))
+                sysc_disable_opt_clocks(ddata);
 
-                goto awake;
-        }
+        ddata->enabled = false;
 
-        for (i = 0; i < ddata->nr_clocks; i++) {
-                if (IS_ERR_OR_NULL(ddata->clocks[i]))
-                        continue;
+        return error;
+}
 
-                if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata))
-                        break;
+static int __maybe_unused sysc_runtime_resume(struct device *dev)
+{
+        struct sysc *ddata;
+        int error = 0;
+
+        ddata = dev_get_drvdata(dev);
 
-                error = clk_enable(ddata->clocks[i]);
+        if (ddata->enabled)
+                return 0;
+
+        if (sysc_opt_clks_needed(ddata)) {
+                error = sysc_enable_opt_clocks(ddata);
                 if (error)
                         return error;
         }
 
-awake:
+        error = sysc_enable_main_clocks(ddata);
+        if (error)
+                goto err_opt_clocks;
+
+        if (ddata->legacy_mode) {
+                error = sysc_runtime_resume_legacy(dev, ddata);
+                if (error)
+                        goto err_main_clocks;
+        } else {
+                error = sysc_enable_module(dev);
+                if (error)
+                        goto err_main_clocks;
+        }
+
         ddata->enabled = true;
 
+        return 0;
+
+err_main_clocks:
+        sysc_disable_main_clocks(ddata);
+err_opt_clocks:
+        if (sysc_opt_clks_needed(ddata))
+                sysc_disable_opt_clocks(ddata);
+
         return error;
 }
 
@@ -788,12 +1107,17 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
         SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
                    0),
         SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
-                   SYSC_QUIRK_LEGACY_IDLE),
+                   SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
         /* Uarts on omap4 and later */
         SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
-                   SYSC_QUIRK_LEGACY_IDLE),
+                   SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
         SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
-                   SYSC_QUIRK_LEGACY_IDLE),
+                   SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
+
+        /* Quirks that need to be set based on the module address */
+        SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
+                   SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
+                   SYSC_QUIRK_SWSUP_SIDLE),
 
 #ifdef DEBUG
         SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
@@ -805,6 +1129,7 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
                    0xffff00f0, 0),
         SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0),
         SYSC_QUIRK("dcan", 0, 0, -1, -1, 0x00001401, 0xffffffff, 0),
+        SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
         SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
         SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
         SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
@@ -853,6 +1178,42 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
 #endif
 };
 
+/*
+ * Early quirks based on module base and register offsets only that are
+ * needed before the module revision can be read
+ */
+static void sysc_init_early_quirks(struct sysc *ddata)
+{
+        const struct sysc_revision_quirk *q;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
+                q = &sysc_revision_quirks[i];
+
+                if (!q->base)
+                        continue;
+
+                if (q->base != ddata->module_pa)
+                        continue;
+
+                if (q->rev_offset >= 0 &&
+                    q->rev_offset != ddata->offsets[SYSC_REVISION])
+                        continue;
+
+                if (q->sysc_offset >= 0 &&
+                    q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
+                        continue;
+
+                if (q->syss_offset >= 0 &&
+                    q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
+                        continue;
+
+                ddata->name = q->name;
+                ddata->cfg.quirks |= q->quirks;
+        }
+}
+
+/* Quirks that also consider the revision register value */
 static void sysc_init_revision_quirks(struct sysc *ddata)
 {
         const struct sysc_revision_quirk *q;
@@ -885,6 +1246,55 @@ static void sysc_init_revision_quirks(struct sysc *ddata)
         }
 }
 
+/*
+ * Note that pdata->init_module() typically does a reset first. After
+ * pdata->init_module() is done, PM runtime can be used for the interconnect
+ * target module.
+ */
+static int sysc_legacy_init(struct sysc *ddata)
+{
+        struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
+        int error;
+
+        if (!ddata->legacy_mode || !pdata || !pdata->init_module)
+                return 0;
+
+        error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
+        if (error == -EEXIST)
+                error = 0;
+
+        return error;
+}
+
+/**
+ * sysc_rstctrl_reset_deassert - deassert rstctrl reset
+ * @ddata: device driver data
+ * @reset: reset before deassert
+ *
+ * A module can have both OCP softreset control and external rstctrl.
+ * If more complicated rstctrl resets are needed, please handle these
+ * directly from the child device driver and map only the module reset
+ * for the parent interconnect target module device.
+ *
+ * Automatic reset of the module on init can be skipped with the
+ * "ti,no-reset-on-init" device tree property.
+ */
+static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
+{
+        int error;
+
+        if (!ddata->rsts)
+                return 0;
+
+        if (reset) {
+                error = reset_control_assert(ddata->rsts);
+                if (error)
+                        return error;
+        }
+
+        return reset_control_deassert(ddata->rsts);
+}
+
 static int sysc_reset(struct sysc *ddata)
 {
         int offset = ddata->offsets[SYSC_SYSCONFIG];
@@ -915,38 +1325,58 @@ static int sysc_reset(struct sysc *ddata)
                                   100, MAX_MODULE_SOFTRESET_WAIT);
 }
 
-/* At this point the module is configured enough to read the revision */
+/*
+ * At this point the module is configured enough to read the revision but
+ * module may not be completely configured yet to use PM runtime. Enable
+ * all clocks directly during init to configure the quirks needed for PM
+ * runtime based on the revision register.
+ */
 static int sysc_init_module(struct sysc *ddata)
 {
-        int error;
+        int error = 0;
+        bool manage_clocks = true;
+        bool reset = true;
 
-        if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE_ON_INIT) {
-                ddata->revision = sysc_read_revision(ddata);
-                goto rev_quirks;
-        }
+        if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
+                reset = false;
 
-        error = pm_runtime_get_sync(ddata->dev);
-        if (error < 0) {
-                pm_runtime_put_noidle(ddata->dev);
+        error = sysc_rstctrl_reset_deassert(ddata, reset);
+        if (error)
+                return error;
 
-                return 0;
-        }
+        if (ddata->cfg.quirks &
+            (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))
+                manage_clocks = false;
 
-        error = sysc_reset(ddata);
-        if (error) {
-                dev_err(ddata->dev, "Reset failed with %d\n", error);
-                pm_runtime_put_sync(ddata->dev);
+        if (manage_clocks) {
+                error = sysc_enable_opt_clocks(ddata);
+                if (error)
+                        return error;
 
-                return error;
+                error = sysc_enable_main_clocks(ddata);
+                if (error)
+                        goto err_opt_clocks;
         }
 
         ddata->revision = sysc_read_revision(ddata);
-        pm_runtime_put_sync(ddata->dev);
-
-rev_quirks:
         sysc_init_revision_quirks(ddata);
 
-        return 0;
+        error = sysc_legacy_init(ddata);
+        if (error)
+                goto err_main_clocks;
+
+        error = sysc_reset(ddata);
+        if (error)
+                dev_err(ddata->dev, "Reset failed with %d\n", error);
+
+err_main_clocks:
+        if (manage_clocks)
+                sysc_disable_main_clocks(ddata);
+err_opt_clocks:
+        if (manage_clocks)
+                sysc_disable_opt_clocks(ddata);
+
+        return error;
 }
 
 static int sysc_init_sysc_mask(struct sysc *ddata)
@@ -1208,7 +1638,7 @@ static int sysc_child_resume_noirq(struct device *dev)
 }
 #endif
 
-struct dev_pm_domain sysc_child_pm_domain = {
+static struct dev_pm_domain sysc_child_pm_domain = {
         .ops = {
                 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
                                    sysc_child_runtime_resume,
@@ -1281,6 +1711,8 @@ static const struct sysc_dts_quirk sysc_dts_quirks[] = {
           .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
         { .name = "ti,no-reset-on-init",
           .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
+        { .name = "ti,no-idle",
+          .mask = SYSC_QUIRK_NO_IDLE, },
 };
 
 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
@@ -1331,6 +1763,9 @@ static void sysc_unprepare(struct sysc *ddata)
 {
         int i;
 
+        if (!ddata->clocks)
+                return;
+
         for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
                 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
                         clk_unprepare(ddata->clocks[i]);
@@ -1576,28 +2011,26 @@ static const struct sysc_capabilities sysc_dra7_mcan = {
 static int sysc_init_pdata(struct sysc *ddata)
 {
         struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
-        struct ti_sysc_module_data mdata;
-        int error = 0;
+        struct ti_sysc_module_data *mdata;
 
         if (!pdata || !ddata->legacy_mode)
                 return 0;
 
-        mdata.name = ddata->legacy_mode;
-        mdata.module_pa = ddata->module_pa;
-        mdata.module_size = ddata->module_size;
-        mdata.offsets = ddata->offsets;
-        mdata.nr_offsets = SYSC_MAX_REGS;
-        mdata.cap = ddata->cap;
-        mdata.cfg = &ddata->cfg;
+        mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
+        if (!mdata)
+                return -ENOMEM;
 
-        if (!pdata->init_module)
-                return -ENODEV;
+        mdata->name = ddata->legacy_mode;
+        mdata->module_pa = ddata->module_pa;
+        mdata->module_size = ddata->module_size;
+        mdata->offsets = ddata->offsets;
+        mdata->nr_offsets = SYSC_MAX_REGS;
+        mdata->cap = ddata->cap;
+        mdata->cfg = &ddata->cfg;
 
-        error = pdata->init_module(ddata->dev, &mdata, &ddata->cookie);
-        if (error == -EEXIST)
-                error = 0;
+        ddata->mdata = mdata;
 
-        return error;
+        return 0;
 }
 
 static int sysc_init_match(struct sysc *ddata)
@@ -1651,10 +2084,6 @@ static int sysc_probe(struct platform_device *pdev)
         if (error)
                 goto unprepare;
 
-        error = sysc_get_clocks(ddata);
-        if (error)
-                return error;
-
         error = sysc_map_and_check_registers(ddata);
         if (error)
                 goto unprepare;
@@ -1675,15 +2104,21 @@ static int sysc_probe(struct platform_device *pdev)
         if (error)
                 goto unprepare;
 
+        sysc_init_early_quirks(ddata);
+
+        error = sysc_get_clocks(ddata);
+        if (error)
+                return error;
+
         error = sysc_init_resets(ddata);
         if (error)
                 return error;
 
-        pm_runtime_enable(ddata->dev);
         error = sysc_init_module(ddata);
         if (error)
                 goto unprepare;
 
+        pm_runtime_enable(ddata->dev);
         error = pm_runtime_get_sync(ddata->dev);
         if (error < 0) {
                 pm_runtime_put_noidle(ddata->dev);
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 4b3d143f0f8a..48321488f0fd 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -69,6 +69,13 @@ config FTTMR010_TIMER
           Enables support for the Faraday Technology timer block
           FTTMR010.
 
+config IXP4XX_TIMER
+        bool "Intel XScale IXP4xx timer driver" if COMPILE_TEST
+        depends on HAS_IOMEM
+        select CLKSRC_MMIO
+        help
+          Enables support for the Intel XScale IXP4xx SoC timer.
+
 config ROCKCHIP_TIMER
         bool "Rockchip timer driver" if COMPILE_TEST
         depends on ARM || ARM64
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index be6e0fbc7489..dba4eff880de 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_OMAP_DM_TIMER)	+= timer-ti-dm.o
 obj-$(CONFIG_DW_APB_TIMER)      += dw_apb_timer.o
 obj-$(CONFIG_DW_APB_TIMER_OF)   += dw_apb_timer_of.o
 obj-$(CONFIG_FTTMR010_TIMER)    += timer-fttmr010.o
+obj-$(CONFIG_IXP4XX_TIMER)      += timer-ixp4xx.o
 obj-$(CONFIG_ROCKCHIP_TIMER)      += timer-rockchip.o
 obj-$(CONFIG_CLKSRC_NOMADIK_MTU)        += nomadik-mtu.o
 obj-$(CONFIG_CLKSRC_DBX500_PRCMU)       += clksrc-dbx500-prcmu.o
diff --git a/drivers/clocksource/timer-ixp4xx.c b/drivers/clocksource/timer-ixp4xx.c
new file mode 100644
index 000000000000..5c2190b654cd
--- /dev/null
+++ b/drivers/clocksource/timer-ixp4xx.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IXP4 timer driver
+ * Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
+ *
+ * Based on arch/arm/mach-ixp4xx/common.c
+ * Copyright 2002 (C) Intel Corporation
+ * Copyright 2003-2004 (C) MontaVista, Software, Inc.
+ * Copyright (C) Deepak Saxena <dsaxena@plexity.net>
+ */
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/sched_clock.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+/* Goes away with OF conversion */
+#include <linux/platform_data/timer-ixp4xx.h>
+
+/*
+ * Constants to make it easy to access Timer Control/Status registers
+ */
+#define IXP4XX_OSTS_OFFSET      0x00  /* Continuous Timestamp */
+#define IXP4XX_OST1_OFFSET      0x04  /* Timer 1 Timestamp */
+#define IXP4XX_OSRT1_OFFSET     0x08  /* Timer 1 Reload */
+#define IXP4XX_OST2_OFFSET      0x0C  /* Timer 2 Timestamp */
+#define IXP4XX_OSRT2_OFFSET     0x10  /* Timer 2 Reload */
+#define IXP4XX_OSWT_OFFSET      0x14  /* Watchdog Timer */
+#define IXP4XX_OSWE_OFFSET      0x18  /* Watchdog Enable */
+#define IXP4XX_OSWK_OFFSET      0x1C  /* Watchdog Key */
+#define IXP4XX_OSST_OFFSET      0x20  /* Timer Status */
+
+/*
+ * Timer register values and bit definitions
+ */
+#define IXP4XX_OST_ENABLE               0x00000001
+#define IXP4XX_OST_ONE_SHOT             0x00000002
+/* Low order bits of reload value ignored */
+#define IXP4XX_OST_RELOAD_MASK          0x00000003
+#define IXP4XX_OST_DISABLED             0x00000000
+#define IXP4XX_OSST_TIMER_1_PEND        0x00000001
+#define IXP4XX_OSST_TIMER_2_PEND        0x00000002
+#define IXP4XX_OSST_TIMER_TS_PEND       0x00000004
+#define IXP4XX_OSST_TIMER_WDOG_PEND     0x00000008
+#define IXP4XX_OSST_TIMER_WARM_RESET    0x00000010
+
+#define IXP4XX_WDT_KEY                  0x0000482E
+#define IXP4XX_WDT_RESET_ENABLE         0x00000001
+#define IXP4XX_WDT_IRQ_ENABLE           0x00000002
+#define IXP4XX_WDT_COUNT_ENABLE         0x00000004
+
+struct ixp4xx_timer {
+        void __iomem *base;
+        unsigned int tick_rate;
+        u32 latch;
+        struct clock_event_device clkevt;
+#ifdef CONFIG_ARM
+        struct delay_timer delay_timer;
+#endif
+};
+
+/*
+ * A local singleton used by sched_clock and delay timer reads, which are
+ * fast and stateless
+ */
+static struct ixp4xx_timer *local_ixp4xx_timer;
+
+static inline struct ixp4xx_timer *
+to_ixp4xx_timer(struct clock_event_device *evt)
+{
+        return container_of(evt, struct ixp4xx_timer, clkevt);
+}
+
+static u64 notrace ixp4xx_read_sched_clock(void)
+{
+        return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET);
+}
+
+static u64 ixp4xx_clocksource_read(struct clocksource *c)
+{
+        return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET);
+}
+
+static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
+{
+        struct ixp4xx_timer *tmr = dev_id;
+        struct clock_event_device *evt = &tmr->clkevt;
+
+        /* Clear Pending Interrupt */
+        __raw_writel(IXP4XX_OSST_TIMER_1_PEND,
+                     tmr->base + IXP4XX_OSST_OFFSET);
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static int ixp4xx_set_next_event(unsigned long cycles,
+                                 struct clock_event_device *evt)
+{
+        struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
+        u32 val;
+
+        val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
+        /* Keep enable/oneshot bits */
+        val &= IXP4XX_OST_RELOAD_MASK;
+        __raw_writel((cycles & ~IXP4XX_OST_RELOAD_MASK) | val,
+                     tmr->base + IXP4XX_OSRT1_OFFSET);
+
+        return 0;
+}
+
+static int ixp4xx_shutdown(struct clock_event_device *evt)
+{
+        struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
+        u32 val;
+
+        val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
+        val &= ~IXP4XX_OST_ENABLE;
+        __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
+
+        return 0;
+}
+
+static int ixp4xx_set_oneshot(struct clock_event_device *evt)
+{
+        struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
+
+        __raw_writel(IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT,
+                     tmr->base + IXP4XX_OSRT1_OFFSET);
+
+        return 0;
+}
+
+static int ixp4xx_set_periodic(struct clock_event_device *evt)
+{
+        struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
+        u32 val;
+
+        val = tmr->latch & ~IXP4XX_OST_RELOAD_MASK;
+        val |= IXP4XX_OST_ENABLE;
+        __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
+
+        return 0;
+}
+
+static int ixp4xx_resume(struct clock_event_device *evt)
+{
+        struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
+        u32 val;
+
+        val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
+        val |= IXP4XX_OST_ENABLE;
+        __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
+
+        return 0;
+}
+
+/*
+ * IXP4xx timer tick
+ * We use OS timer1 on the CPU for the timer tick and the timestamp
+ * counter as a source of real clock ticks to account for missed jiffies.
+ */
+static __init int ixp4xx_timer_register(void __iomem *base,
+                                        int timer_irq,
+                                        unsigned int timer_freq)
+{
+        struct ixp4xx_timer *tmr;
+        int ret;
+
+        tmr = kzalloc(sizeof(*tmr), GFP_KERNEL);
+        if (!tmr)
+                return -ENOMEM;
+        tmr->base = base;
+        tmr->tick_rate = timer_freq;
+
+        /*
+         * The timer register doesn't allow to specify the two least
+         * significant bits of the timeout value and assumes them being zero.
+         * So make sure the latch is the best value with the two least
+         * significant bits unset.
+         */
+        tmr->latch = DIV_ROUND_CLOSEST(timer_freq,
+                                       (IXP4XX_OST_RELOAD_MASK + 1) * HZ)
+                * (IXP4XX_OST_RELOAD_MASK + 1);
+
+        local_ixp4xx_timer = tmr;
+
+        /* Reset/disable counter */
+        __raw_writel(0, tmr->base + IXP4XX_OSRT1_OFFSET);
+
+        /* Clear any pending interrupt on timer 1 */
+        __raw_writel(IXP4XX_OSST_TIMER_1_PEND,
+                     tmr->base + IXP4XX_OSST_OFFSET);
+
+        /* Reset time-stamp counter */
+        __raw_writel(0, tmr->base + IXP4XX_OSTS_OFFSET);
+
+        clocksource_mmio_init(NULL, "OSTS", timer_freq, 200, 32,
+                              ixp4xx_clocksource_read);
+
+        tmr->clkevt.name = "ixp4xx timer1";
+        tmr->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+        tmr->clkevt.rating = 200;
+        tmr->clkevt.set_state_shutdown = ixp4xx_shutdown;
+        tmr->clkevt.set_state_periodic = ixp4xx_set_periodic;
+        tmr->clkevt.set_state_oneshot = ixp4xx_set_oneshot;
+        tmr->clkevt.tick_resume = ixp4xx_resume;
+        tmr->clkevt.set_next_event = ixp4xx_set_next_event;
+        tmr->clkevt.cpumask = cpumask_of(0);
+        tmr->clkevt.irq = timer_irq;
+        ret = request_irq(timer_irq, ixp4xx_timer_interrupt,
+                          IRQF_TIMER, "IXP4XX-TIMER1", tmr);
+        if (ret) {
+                pr_crit("no timer IRQ\n");
+                return -ENODEV;
+        }
+        clockevents_config_and_register(&tmr->clkevt, timer_freq,
+                                        0xf, 0xfffffffe);
+
+        sched_clock_register(ixp4xx_read_sched_clock, 32, timer_freq);
+
+        return 0;
+}
+
+/**
+ * ixp4xx_timer_setup() - Timer setup function to be called from boardfiles
+ * @timerbase: physical base of timer block
+ * @timer_irq: Linux IRQ number for the timer
+ * @timer_freq: Fixed frequency of the timer
+ */
+void __init ixp4xx_timer_setup(resource_size_t timerbase,
+                               int timer_irq,
+                               unsigned int timer_freq)
+{
+        void __iomem *base;
+
+        base = ioremap(timerbase, 0x100);
+        if (!base) {
+                pr_crit("IXP4xx: can't remap timer\n");
+                return;
+        }
+        ixp4xx_timer_register(base, timer_irq, timer_freq);
+}
+EXPORT_SYMBOL_GPL(ixp4xx_timer_setup);
+
+#ifdef CONFIG_OF
+static __init int ixp4xx_of_timer_init(struct device_node *np)
+{
+        void __iomem *base;
+        int irq;
+        int ret;
+
+        base = of_iomap(np, 0);
+        if (!base) {
+                pr_crit("IXP4xx: can't remap timer\n");
+                return -ENODEV;
+        }
+
+        irq = irq_of_parse_and_map(np, 0);
+        if (irq <= 0) {
+                pr_err("Can't parse IRQ\n");
+                ret = -EINVAL;
+                goto out_unmap;
+        }
+
+        /* TODO: get some fixed clocks into the device tree */
+        ret = ixp4xx_timer_register(base, irq, 66666000);
+        if (ret)
+                goto out_unmap;
+        return 0;
+
+out_unmap:
+        iounmap(base);
+        return ret;
+}
+TIMER_OF_DECLARE(ixp4xx, "intel,ixp4xx-timer", ixp4xx_of_timer_init);
+#endif
diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c
index 9bbde2f26cac..f5414b6dfb55 100644
--- a/drivers/crypto/ixp4xx_crypto.c
+++ b/drivers/crypto/ixp4xx_crypto.c
@@ -30,8 +30,8 @@
 #include <crypto/authenc.h>
 #include <crypto/scatterwalk.h>
 
-#include <mach/npe.h>
-#include <mach/qmgr.h>
+#include <linux/soc/ixp4xx/npe.h>
+#include <linux/soc/ixp4xx/qmgr.h>
 
 #define MAX_KEYLEN 32
 
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index 7b655f6156fb..11fda9eb2466 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -253,6 +253,22 @@ config TI_SCI_PROTOCOL
           This protocol library is used by client drivers to use the features
           provided by the system controller.
 
+config TRUSTED_FOUNDATIONS
+        bool "Trusted Foundations secure monitor support"
+        depends on ARM
+        help
+          Some devices (including most early Tegra-based consumer devices on
+          the market) are booted with the Trusted Foundations secure monitor
+          active, requiring some core operations to be performed by the secure
+          monitor instead of the kernel.
+
+          This option allows the kernel to invoke the secure monitor whenever
+          required on devices using Trusted Foundations. See the functions and
+          comments in linux/firmware/trusted_foundations.h or the device tree
+          bindings for "tlm,trusted-foundations" for details on how to use it.
+
+          Choose N if you don't know what this is about.
+
 config HAVE_ARM_SMCCC
         bool
 
diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile
index 9a3909a22682..3fa0b34eb72f 100644
--- a/drivers/firmware/Makefile
+++ b/drivers/firmware/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SCM_64)	+= qcom_scm-64.o
 obj-$(CONFIG_QCOM_SCM_32)       += qcom_scm-32.o
 CFLAGS_qcom_scm-32.o :=$(call as-instr,.arch armv7-a\n.arch_extension sec,-DREQUIRES_SEC=1) -march=armv7-a
 obj-$(CONFIG_TI_SCI_PROTOCOL)   += ti_sci.o
+obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o
 
 obj-$(CONFIG_ARM_SCMI_PROTOCOL) += arm_scmi/
 obj-y                           += psci/
diff --git a/arch/arm/firmware/trusted_foundations.c b/drivers/firmware/trusted_foundations.c
index 689e6565abfc..fd4999388ff1 100644
--- a/arch/arm/firmware/trusted_foundations.c
+++ b/drivers/firmware/trusted_foundations.c
@@ -17,8 +17,17 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/of.h>
+
+#include <linux/firmware/trusted_foundations.h>
+
 #include <asm/firmware.h>
-#include <asm/trusted_foundations.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/outercache.h>
+
+#define TF_CACHE_MAINT          0xfffff100
+
+#define TF_CACHE_ENABLE         1
+#define TF_CACHE_DISABLE        2
 
 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
 
@@ -60,16 +69,75 @@ static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
         return 0;
 }
 
-static int tf_prepare_idle(void)
+static int tf_prepare_idle(unsigned long mode)
 {
-        tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2, cpu_boot_addr);
+        switch (mode) {
+        case TF_PM_MODE_LP0:
+                tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S3, cpu_boot_addr);
+                break;
+
+        case TF_PM_MODE_LP1:
+                tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2, cpu_boot_addr);
+                break;
+
+        case TF_PM_MODE_LP1_NO_MC_CLK:
+                tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2_NO_MC_CLK,
+                               cpu_boot_addr);
+                break;
+
+        case TF_PM_MODE_LP2:
+                tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1, cpu_boot_addr);
+                break;
+
+        case TF_PM_MODE_LP2_NOFLUSH_L2:
+                tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2,
+                               cpu_boot_addr);
+                break;
+
+        default:
+                return -EINVAL;
+        }
 
         return 0;
 }
 
+#ifdef CONFIG_CACHE_L2X0
+static void tf_cache_write_sec(unsigned long val, unsigned int reg)
+{
+        u32 l2x0_way_mask = 0xff;
+
+        switch (reg) {
+        case L2X0_CTRL:
+                if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
+                        l2x0_way_mask = 0xffff;
+
+                if (val == L2X0_CTRL_EN)
+                        tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_ENABLE,
+                                       l2x0_saved_regs.aux_ctrl);
+                else
+                        tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
+                                       l2x0_way_mask);
+                break;
+
+        default:
+                break;
+        }
+}
+
+static int tf_init_cache(void)
+{
+        outer_cache.write_sec = tf_cache_write_sec;
+
+        return 0;
+}
+#endif /* CONFIG_CACHE_L2X0 */
+
 static const struct firmware_ops trusted_foundations_ops = {
         .set_cpu_boot_addr = tf_set_cpu_boot_addr,
         .prepare_idle = tf_prepare_idle,
+#ifdef CONFIG_CACHE_L2X0
+        .l2x0_init = tf_init_cache,
+#endif
 };
 
 void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
@@ -101,3 +169,8 @@ void of_register_trusted_foundations(void)
                 panic("Trusted Foundation: missing version-minor property\n");
         register_trusted_foundations(&pdata);
 }
+
+bool trusted_foundations_registered(void)
+{
+        return firmware_ops == &trusted_foundations_ops;
+}
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 41f08362dad3..8023d03ec362 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -286,6 +286,19 @@ config GPIO_IOP
 
           If unsure, say N.
 
+config GPIO_IXP4XX
+        bool "Intel IXP4xx GPIO"
+        depends on ARM # For <asm/mach-types.h>
+        depends on ARCH_IXP4XX
+        select GPIO_GENERIC
+        select IRQ_DOMAIN
+        select IRQ_DOMAIN_HIERARCHY
+        help
+          Say yes here to support the GPIO functionality of a number of Intel
+          IXP4xx series of chips.
+
+          If unsure, say N.
+
 config GPIO_LOONGSON
         bool "Loongson-2/3 GPIO support"
         depends on CPU_LOONGSON2 || CPU_LOONGSON3
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index e19be766f6a6..6700eee860b7 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_GPIO_HLWD)		+= gpio-hlwd.o
 obj-$(CONFIG_HTC_EGPIO)         += gpio-htc-egpio.o
 obj-$(CONFIG_GPIO_ICH)          += gpio-ich.o
 obj-$(CONFIG_GPIO_IOP)          += gpio-iop.o
+obj-$(CONFIG_GPIO_IXP4XX)       += gpio-ixp4xx.o
 obj-$(CONFIG_GPIO_IT87)         += gpio-it87.o
 obj-$(CONFIG_GPIO_JANZ_TTL)     += gpio-janz-ttl.o
 obj-$(CONFIG_GPIO_KEMPLD)       += gpio-kempld.o
diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c
new file mode 100644
index 000000000000..4b1cf7ea858d
--- /dev/null
+++ b/drivers/gpio/gpio-ixp4xx.c
@@ -0,0 +1,474 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// IXP4 GPIO driver
+// Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
+//
+// based on previous work and know-how from:
+// Deepak Saxena <dsaxena@plexity.net>
+
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/bitops.h>
+/* Include that go away with DT transition */
+#include <linux/irqchip/irq-ixp4xx.h>
+
+#include <asm/mach-types.h>
+
+#define IXP4XX_REG_GPOUT        0x00
+#define IXP4XX_REG_GPOE         0x04
+#define IXP4XX_REG_GPIN         0x08
+#define IXP4XX_REG_GPIS         0x0C
+#define IXP4XX_REG_GPIT1        0x10
+#define IXP4XX_REG_GPIT2        0x14
+#define IXP4XX_REG_GPCLK        0x18
+#define IXP4XX_REG_GPDBSEL      0x1C
+
+/*
+ * The hardware uses 3 bits to indicate interrupt "style".
+ * we clear and set these three bits accordingly. The lower 24
+ * bits in two registers (GPIT1 and GPIT2) are used to set up
+ * the style for 8 lines each for a total of 16 GPIO lines.
+ */
+#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH   0x0
+#define IXP4XX_GPIO_STYLE_ACTIVE_LOW    0x1
+#define IXP4XX_GPIO_STYLE_RISING_EDGE   0x2
+#define IXP4XX_GPIO_STYLE_FALLING_EDGE  0x3
+#define IXP4XX_GPIO_STYLE_TRANSITIONAL  0x4
+#define IXP4XX_GPIO_STYLE_MASK          GENMASK(2, 0)
+#define IXP4XX_GPIO_STYLE_SIZE          3
+
+/**
+ * struct ixp4xx_gpio - IXP4 GPIO state container
+ * @dev: containing device for this instance
+ * @fwnode: the fwnode for this GPIO chip
+ * @gc: gpiochip for this instance
+ * @domain: irqdomain for this chip instance
+ * @base: remapped I/O-memory base
+ * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
+ * 0: level triggered
+ */
+struct ixp4xx_gpio {
+        struct device *dev;
+        struct fwnode_handle *fwnode;
+        struct gpio_chip gc;
+        struct irq_domain *domain;
+        void __iomem *base;
+        unsigned long long irq_edge;
+};
+
+/**
+ * struct ixp4xx_gpio_map - IXP4 GPIO to parent IRQ map
+ * @gpio_offset: offset of the IXP4 GPIO line
+ * @parent_hwirq: hwirq on the parent IRQ controller
+ */
+struct ixp4xx_gpio_map {
+        int gpio_offset;
+        int parent_hwirq;
+};
+
+/* GPIO lines 0..12 have corresponding IRQs, GPIOs 13..15 have no IRQs */
+const struct ixp4xx_gpio_map ixp4xx_gpiomap[] = {
+        { .gpio_offset = 0, .parent_hwirq = 6 },
+        { .gpio_offset = 1, .parent_hwirq = 7 },
+        { .gpio_offset = 2, .parent_hwirq = 19 },
+        { .gpio_offset = 3, .parent_hwirq = 20 },
+        { .gpio_offset = 4, .parent_hwirq = 21 },
+        { .gpio_offset = 5, .parent_hwirq = 22 },
+        { .gpio_offset = 6, .parent_hwirq = 23 },
+        { .gpio_offset = 7, .parent_hwirq = 24 },
+        { .gpio_offset = 8, .parent_hwirq = 25 },
+        { .gpio_offset = 9, .parent_hwirq = 26 },
+        { .gpio_offset = 10, .parent_hwirq = 27 },
+        { .gpio_offset = 11, .parent_hwirq = 28 },
+        { .gpio_offset = 12, .parent_hwirq = 29 },
+};
+
+static void ixp4xx_gpio_irq_ack(struct irq_data *d)
+{
+        struct ixp4xx_gpio *g = irq_data_get_irq_chip_data(d);
+
+        __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
+}
+
+static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
+{
+        struct ixp4xx_gpio *g = irq_data_get_irq_chip_data(d);
+
+        /* ACK when unmasking if not edge-triggered */
+        if (!(g->irq_edge & BIT(d->hwirq)))
+                ixp4xx_gpio_irq_ack(d);
+
+        irq_chip_unmask_parent(d);
+}
+
+static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+{
+        struct ixp4xx_gpio *g = irq_data_get_irq_chip_data(d);
+        int line = d->hwirq;
+        unsigned long flags;
+        u32 int_style;
+        u32 int_reg;
+        u32 val;
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_BOTH:
+                irq_set_handler_locked(d, handle_edge_irq);
+                int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
+                g->irq_edge |= BIT(d->hwirq);
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+                irq_set_handler_locked(d, handle_edge_irq);
+                int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
+                g->irq_edge |= BIT(d->hwirq);
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                irq_set_handler_locked(d, handle_edge_irq);
+                int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
+                g->irq_edge |= BIT(d->hwirq);
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                irq_set_handler_locked(d, handle_level_irq);
+                int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
+                g->irq_edge &= ~BIT(d->hwirq);
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                irq_set_handler_locked(d, handle_level_irq);
+                int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
+                g->irq_edge &= ~BIT(d->hwirq);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        if (line >= 8) {
+                /* pins 8-15 */
+                line -= 8;
+                int_reg = IXP4XX_REG_GPIT2;
+        } else {
+                /* pins 0-7 */
+                int_reg = IXP4XX_REG_GPIT1;
+        }
+
+        spin_lock_irqsave(&g->gc.bgpio_lock, flags);
+
+        /* Clear the style for the appropriate pin */
+        val = __raw_readl(g->base + int_reg);
+        val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE));
+        __raw_writel(val, g->base + int_reg);
+
+        __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS);
+
+        /* Set the new style */
+        val = __raw_readl(g->base + int_reg);
+        val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
+        __raw_writel(val, g->base + int_reg);
+
+        /* Force-configure this line as an input */
+        val = __raw_readl(g->base + IXP4XX_REG_GPOE);
+        val |= BIT(d->hwirq);
+        __raw_writel(val, g->base + IXP4XX_REG_GPOE);
+
+        spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);
+
+        /* This parent only accept level high (asserted) */
+        return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
+}
+
+static struct irq_chip ixp4xx_gpio_irqchip = {
+        .name = "IXP4GPIO",
+        .irq_ack = ixp4xx_gpio_irq_ack,
+        .irq_mask = irq_chip_mask_parent,
+        .irq_unmask = ixp4xx_gpio_irq_unmask,
+        .irq_set_type = ixp4xx_gpio_irq_set_type,
+};
+
+static int ixp4xx_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
+{
+        struct ixp4xx_gpio *g = gpiochip_get_data(gc);
+        struct irq_fwspec fwspec;
+
+        fwspec.fwnode = g->fwnode;
+        fwspec.param_count = 2;
+        fwspec.param[0] = offset;
+        fwspec.param[1] = IRQ_TYPE_NONE;
+
+        return irq_create_fwspec_mapping(&fwspec);
+}
+
+static int ixp4xx_gpio_irq_domain_translate(struct irq_domain *domain,
+                                            struct irq_fwspec *fwspec,
+                                            unsigned long *hwirq,
+                                            unsigned int *type)
+{
+
+        /* We support standard DT translation */
+        if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
+                *hwirq = fwspec->param[0];
+                *type = fwspec->param[1];
+                return 0;
+        }
+
+        /* This goes away when we transition to DT */
+        if (is_fwnode_irqchip(fwspec->fwnode)) {
+                if (fwspec->param_count != 2)
+                        return -EINVAL;
+                *hwirq = fwspec->param[0];
+                *type = fwspec->param[1];
+                WARN_ON(*type == IRQ_TYPE_NONE);
+                return 0;
+        }
+        return -EINVAL;
+}
+
+static int ixp4xx_gpio_irq_domain_alloc(struct irq_domain *d,
+                                        unsigned int irq, unsigned int nr_irqs,
+                                        void *data)
+{
+        struct ixp4xx_gpio *g = d->host_data;
+        irq_hw_number_t hwirq;
+        unsigned int type = IRQ_TYPE_NONE;
+        struct irq_fwspec *fwspec = data;
+        int ret;
+        int i;
+
+        ret = ixp4xx_gpio_irq_domain_translate(d, fwspec, &hwirq, &type);
+        if (ret)
+                return ret;
+
+        dev_dbg(g->dev, "allocate IRQ %d..%d, hwirq %lu..%lu\n",
+                irq, irq + nr_irqs - 1,
+                hwirq, hwirq + nr_irqs - 1);
+
+        for (i = 0; i < nr_irqs; i++) {
+                struct irq_fwspec parent_fwspec;
+                const struct ixp4xx_gpio_map *map;
+                int j;
+
+                /* Not all lines support IRQs */
+                for (j = 0; j < ARRAY_SIZE(ixp4xx_gpiomap); j++) {
+                        map = &ixp4xx_gpiomap[j];
+                        if (map->gpio_offset == hwirq)
+                                break;
+                }
+                if (j == ARRAY_SIZE(ixp4xx_gpiomap)) {
+                        dev_err(g->dev, "can't look up hwirq %lu\n", hwirq);
+                        return -EINVAL;
+                }
+                dev_dbg(g->dev, "found parent hwirq %u\n", map->parent_hwirq);
+
+                /*
+                 * We set handle_bad_irq because the .set_type() should
+                 * always be invoked and set the right type of handler.
+                 */
+                irq_domain_set_info(d,
+                                    irq + i,
+                                    hwirq + i,
+                                    &ixp4xx_gpio_irqchip,
+                                    g,
+                                    handle_bad_irq,
+                                    NULL, NULL);
+                irq_set_probe(irq + i);
+
+                /*
+                 * Create a IRQ fwspec to send up to the parent irqdomain:
+                 * specify the hwirq we address on the parent and tie it
+                 * all together up the chain.
+                 */
+                parent_fwspec.fwnode = d->parent->fwnode;
+                parent_fwspec.param_count = 2;
+                parent_fwspec.param[0] = map->parent_hwirq;
+                /* This parent only handles asserted level IRQs */
+                parent_fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
+                dev_dbg(g->dev, "alloc_irqs_parent for %d parent hwirq %d\n",
+                        irq + i, map->parent_hwirq);
+                ret = irq_domain_alloc_irqs_parent(d, irq + i, 1,
+                                                   &parent_fwspec);
+                if (ret)
+                        dev_err(g->dev,
+                                "failed to allocate parent hwirq %d for hwirq %lu\n",
+                                map->parent_hwirq, hwirq);
+        }
+
+        return 0;
+}
+
+static const struct irq_domain_ops ixp4xx_gpio_irqdomain_ops = {
+        .translate = ixp4xx_gpio_irq_domain_translate,
+        .alloc = ixp4xx_gpio_irq_domain_alloc,
+        .free = irq_domain_free_irqs_common,
+};
+
+static int ixp4xx_gpio_probe(struct platform_device *pdev)
+{
+        unsigned long flags;
+        struct device *dev = &pdev->dev;
+        struct device_node *np = dev->of_node;
+        struct irq_domain *parent;
+        struct resource *res;
+        struct ixp4xx_gpio *g;
+        int ret;
+        int i;
+
+        g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
+        if (!g)
+                return -ENOMEM;
+        g->dev = dev;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        g->base = devm_ioremap_resource(dev, res);
+        if (IS_ERR(g->base)) {
+                dev_err(dev, "ioremap error\n");
+                return PTR_ERR(g->base);
+        }
+
+        /*
+         * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on
+         * specific machines.
+         */
+        if (machine_is_dsmg600() || machine_is_nas100d())
+                __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
+
+        /*
+         * This is a very special big-endian ARM issue: when the IXP4xx is
+         * run in big endian mode, all registers in the machine are switched
+         * around to the CPU-native endianness. As you see mostly in the
+         * driver we use __raw_readl()/__raw_writel() to access the registers
+         * in the appropriate order. With the GPIO library we need to specify
+         * byte order explicitly, so this flag needs to be set when compiling
+         * for big endian.
+         */
+#if defined(CONFIG_CPU_BIG_ENDIAN)
+        flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
+#else
+        flags = 0;
+#endif
+
+        /* Populate and register gpio chip */
+        ret = bgpio_init(&g->gc, dev, 4,
+                         g->base + IXP4XX_REG_GPIN,
+                         g->base + IXP4XX_REG_GPOUT,
+                         NULL,
+                         NULL,
+                         g->base + IXP4XX_REG_GPOE,
+                         flags);
+        if (ret) {
+                dev_err(dev, "unable to init generic GPIO\n");
+                return ret;
+        }
+        g->gc.to_irq = ixp4xx_gpio_to_irq;
+        g->gc.ngpio = 16;
+        g->gc.label = "IXP4XX_GPIO_CHIP";
+        /*
+         * TODO: when we have migrated to device tree and all GPIOs
+         * are fetched using phandles, set this to -1 to get rid of
+         * the fixed gpiochip base.
+         */
+        g->gc.base = 0;
+        g->gc.parent = &pdev->dev;
+        g->gc.owner = THIS_MODULE;
+
+        ret = devm_gpiochip_add_data(dev, &g->gc, g);
+        if (ret) {
+                dev_err(dev, "failed to add SoC gpiochip\n");
+                return ret;
+        }
+
+        /*
+         * When we convert to device tree we will simply look up the
+         * parent irqdomain using irq_find_host(parent) as parent comes
+         * from IRQCHIP_DECLARE(), then use of_node_to_fwnode() to get
+         * the fwnode. For now we need this boardfile style code.
+         */
+        if (np) {
+                struct device_node *irq_parent;
+
+                irq_parent = of_irq_find_parent(np);
+                if (!irq_parent) {
+                        dev_err(dev, "no IRQ parent node\n");
+                        return -ENODEV;
+                }
+                parent = irq_find_host(irq_parent);
+                if (!parent) {
+                        dev_err(dev, "no IRQ parent domain\n");
+                        return -ENODEV;
+                }
+                g->fwnode = of_node_to_fwnode(np);
+        } else {
+                parent = ixp4xx_get_irq_domain();
+                g->fwnode = irq_domain_alloc_fwnode(g->base);
+                if (!g->fwnode) {
+                        dev_err(dev, "no domain base\n");
+                        return -ENODEV;
+                }
+        }
+        g->domain = irq_domain_create_hierarchy(parent,
+                                                IRQ_DOMAIN_FLAG_HIERARCHY,
+                                                ARRAY_SIZE(ixp4xx_gpiomap),
+                                                g->fwnode,
+                                                &ixp4xx_gpio_irqdomain_ops,
+                                                g);
+        if (!g->domain) {
+                irq_domain_free_fwnode(g->fwnode);
+                dev_err(dev, "no hierarchical irq domain\n");
+                return ret;
+        }
+
+        /*
+         * After adding OF support, this is no longer needed: irqs
+         * will be allocated for the respective fwnodes.
+         */
+        if (!np) {
+                for (i = 0; i < ARRAY_SIZE(ixp4xx_gpiomap); i++) {
+                        const struct ixp4xx_gpio_map *map = &ixp4xx_gpiomap[i];
+                        struct irq_fwspec fwspec;
+
+                        fwspec.fwnode = g->fwnode;
+                        /* This is the hwirq for the GPIO line side of things */
+                        fwspec.param[0] = map->gpio_offset;
+                        fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
+                        fwspec.param_count = 2;
+                        ret = __irq_domain_alloc_irqs(g->domain,
+                                                      -1, /* just pick something */
+                                                      1,
+                                                      NUMA_NO_NODE,
+                                                      &fwspec,
+                                                      false,
+                                                      NULL);
+                        if (ret < 0) {
+                                irq_domain_free_fwnode(g->fwnode);
+                                dev_err(dev,
+                                        "can not allocate irq for GPIO line %d parent hwirq %d in hierarchy domain: %d\n",
+                                        map->gpio_offset, map->parent_hwirq,
+                                        ret);
+                                return ret;
+                        }
+                }
+        }
+
+        platform_set_drvdata(pdev, g);
+        dev_info(dev, "IXP4 GPIO @%p registered\n", g->base);
+
+        return 0;
+}
+
+static const struct of_device_id ixp4xx_gpio_of_match[] = {
+        {
+                .compatible = "intel,ixp4xx-gpio",
+        },
+        {},
+};
+
+
+static struct platform_driver ixp4xx_gpio_driver = {
+        .driver = {
+                .name           = "ixp4xx-gpio",
+                .of_match_table = of_match_ptr(ixp4xx_gpio_of_match),
+        },
+        .probe = ixp4xx_gpio_probe,
+};
+builtin_platform_driver(ixp4xx_gpio_driver);
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index 1fe039d7326b..82398827b64f 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -205,7 +205,7 @@ config KEYBOARD_LKKBD
 
 config KEYBOARD_EP93XX
         tristate "EP93xx Matrix Keypad support"
-        depends on ARCH_EP93XX
+        depends on ARCH_EP93XX || COMPILE_TEST
         select INPUT_MATRIXKMAP
         help
           Say Y here to enable the matrix keypad on the Cirrus EP93XX.
diff --git a/drivers/input/keyboard/ep93xx_keypad.c b/drivers/input/keyboard/ep93xx_keypad.c
index f77b295e0123..575dac52f7b4 100644
--- a/drivers/input/keyboard/ep93xx_keypad.c
+++ b/drivers/input/keyboard/ep93xx_keypad.c
@@ -27,8 +27,7 @@
 #include <linux/io.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/slab.h>
-
-#include <mach/hardware.h>
+#include <linux/soc/cirrus/ep93xx.h>
 #include <linux/platform_data/keypad-ep93xx.h>
 
 /*
@@ -137,10 +136,7 @@ static void ep93xx_keypad_config(struct ep93xx_keypad *keypad)
         struct ep93xx_keypad_platform_data *pdata = keypad->pdata;
         unsigned int val = 0;
 
-        if (pdata->flags & EP93XX_KEYPAD_KDIV)
-                clk_set_rate(keypad->clk, EP93XX_KEYTCHCLK_DIV4);
-        else
-                clk_set_rate(keypad->clk, EP93XX_KEYTCHCLK_DIV16);
+        clk_set_rate(keypad->clk, pdata->clk_rate);
 
         if (pdata->flags & EP93XX_KEYPAD_DISABLE_3_KEY)
                 val |= KEY_INIT_DIS3KY;
diff --git a/drivers/input/misc/ixp4xx-beeper.c b/drivers/input/misc/ixp4xx-beeper.c
index 1fe149f3def2..4776273fa10b 100644
--- a/drivers/input/misc/ixp4xx-beeper.c
+++ b/drivers/input/misc/ixp4xx-beeper.c
@@ -30,6 +30,8 @@ MODULE_ALIAS("platform:ixp4xx-beeper");
 
 static DEFINE_SPINLOCK(beep_lock);
 
+static int ixp4xx_timer2_irq;
+
 static void ixp4xx_spkr_control(unsigned int pin, unsigned int count)
 {
         unsigned long flags;
@@ -90,6 +92,7 @@ static irqreturn_t ixp4xx_spkr_interrupt(int irq, void *dev_id)
 static int ixp4xx_spkr_probe(struct platform_device *dev)
 {
         struct input_dev *input_dev;
+        int irq;
         int err;
 
         input_dev = input_allocate_device();
@@ -110,15 +113,22 @@ static int ixp4xx_spkr_probe(struct platform_device *dev)
         input_dev->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
         input_dev->event = ixp4xx_spkr_event;
 
+        irq = platform_get_irq(dev, 0);
+        if (irq < 0) {
+                err = irq;
+                goto err_free_device;
+        }
+
         err = gpio_request(dev->id, "ixp4-beeper");
         if (err)
                 goto err_free_device;
 
-        err = request_irq(IRQ_IXP4XX_TIMER2, &ixp4xx_spkr_interrupt,
+        err = request_irq(irq, &ixp4xx_spkr_interrupt,
                           IRQF_NO_SUSPEND, "ixp4xx-beeper",
                           (void *) dev->id);
         if (err)
                 goto err_free_gpio;
+        ixp4xx_timer2_irq = irq;
 
         err = input_register_device(input_dev);
         if (err)
@@ -129,7 +139,7 @@ static int ixp4xx_spkr_probe(struct platform_device *dev)
         return 0;
 
  err_free_irq:
-        free_irq(IRQ_IXP4XX_TIMER2, (void *)dev->id);
+        free_irq(irq, (void *)dev->id);
  err_free_gpio:
         gpio_free(dev->id);
  err_free_device:
@@ -146,10 +156,10 @@ static int ixp4xx_spkr_remove(struct platform_device *dev)
         input_unregister_device(input_dev);
 
         /* turn the speaker off */
-        disable_irq(IRQ_IXP4XX_TIMER2);
+        disable_irq(ixp4xx_timer2_irq);
         ixp4xx_spkr_control(pin, 0);
 
-        free_irq(IRQ_IXP4XX_TIMER2, (void *)dev->id);
+        free_irq(ixp4xx_timer2_irq, (void *)dev->id);
         gpio_free(dev->id);
 
         return 0;
@@ -161,7 +171,7 @@ static void ixp4xx_spkr_shutdown(struct platform_device *dev)
         unsigned int pin = (unsigned int) input_get_drvdata(input_dev);
 
         /* turn off the speaker */
-        disable_irq(IRQ_IXP4XX_TIMER2);
+        disable_irq(ixp4xx_timer2_irq);
         ixp4xx_spkr_control(pin, 0);
 }
 
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 5438abb1baba..cf7984991062 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -160,6 +160,12 @@ config IMGPDC_IRQ
         select GENERIC_IRQ_CHIP
         select IRQ_DOMAIN
 
+config IXP4XX_IRQ
+        bool
+        select IRQ_DOMAIN
+        select GENERIC_IRQ_MULTI_HANDLER
+        select SPARSE_IRQ
+
 config MADERA_IRQ
         tristate
 
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 85972ae1bd7f..f8c66e958a64 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_ATMEL_AIC5_IRQ)	+= irq-atmel-aic-common.o irq-atmel-aic5.o
 obj-$(CONFIG_I8259)                     += irq-i8259.o
 obj-$(CONFIG_IMGPDC_IRQ)                += irq-imgpdc.o
 obj-$(CONFIG_IRQ_MIPS_CPU)              += irq-mips-cpu.o
+obj-$(CONFIG_IXP4XX_IRQ)                += irq-ixp4xx.o
 obj-$(CONFIG_SIRF_IRQ)                  += irq-sirfsoc.o
 obj-$(CONFIG_JCORE_AIC)                 += irq-jcore-aic.o
 obj-$(CONFIG_RDA_INTC)                  += irq-rda-intc.o
diff --git a/drivers/irqchip/irq-ixp4xx.c b/drivers/irqchip/irq-ixp4xx.c
new file mode 100644
index 000000000000..d576809429ac
--- /dev/null
+++ b/drivers/irqchip/irq-ixp4xx.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * irqchip for the IXP4xx interrupt controller
+ * Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
+ *
+ * Based on arch/arm/mach-ixp4xx/common.c
+ * Copyright 2002 (C) Intel Corporation
+ * Copyright 2003-2004 (C) MontaVista, Software, Inc.
+ * Copyright (C) Deepak Saxena <dsaxena@plexity.net>
+ */
+#include <linux/bitops.h>
+#include <linux/gpio/driver.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/irq-ixp4xx.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/cpu.h>
+
+#include <asm/exception.h>
+#include <asm/mach/irq.h>
+
+#define IXP4XX_ICPR     0x00 /* Interrupt Status */
+#define IXP4XX_ICMR     0x04 /* Interrupt Enable */
+#define IXP4XX_ICLR     0x08 /* Interrupt IRQ/FIQ Select */
+#define IXP4XX_ICIP     0x0C /* IRQ Status */
+#define IXP4XX_ICFP     0x10 /* FIQ Status */
+#define IXP4XX_ICHR     0x14 /* Interrupt Priority */
+#define IXP4XX_ICIH     0x18 /* IRQ Highest Pri Int */
+#define IXP4XX_ICFH     0x1C /* FIQ Highest Pri Int */
+
+/* IXP43x and IXP46x-only */
+#define IXP4XX_ICPR2    0x20 /* Interrupt Status 2 */
+#define IXP4XX_ICMR2    0x24 /* Interrupt Enable 2 */
+#define IXP4XX_ICLR2    0x28 /* Interrupt IRQ/FIQ Select 2 */
+#define IXP4XX_ICIP2    0x2C /* IRQ Status */
+#define IXP4XX_ICFP2    0x30 /* FIQ Status */
+#define IXP4XX_ICEEN    0x34 /* Error High Pri Enable */
+
+/**
+ * struct ixp4xx_irq - state container for the Faraday IRQ controller
+ * @irqbase: IRQ controller memory base in virtual memory
+ * @is_356: if this is an IXP43x, IXP45x or IX46x SoC (with 64 IRQs)
+ * @irqchip: irqchip for this instance
+ * @domain: IRQ domain for this instance
+ */
+struct ixp4xx_irq {
+        void __iomem *irqbase;
+        bool is_356;
+        struct irq_chip irqchip;
+        struct irq_domain *domain;
+};
+
+/* Local static state container */
+static struct ixp4xx_irq ixirq;
+
+/* GPIO Clocks */
+#define IXP4XX_GPIO_CLK_0               14
+#define IXP4XX_GPIO_CLK_1               15
+
+static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
+{
+        /* All are level active high (asserted) here */
+        if (type != IRQ_TYPE_LEVEL_HIGH)
+                return -EINVAL;
+        return 0;
+}
+
+static void ixp4xx_irq_mask(struct irq_data *d)
+{
+        struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
+        u32 val;
+
+        if (ixi->is_356 && d->hwirq >= 32) {
+                val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
+                val &= ~BIT(d->hwirq - 32);
+                __raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
+        } else {
+                val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
+                val &= ~BIT(d->hwirq);
+                __raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
+        }
+}
+
+/*
+ * Level triggered interrupts on GPIO lines can only be cleared when the
+ * interrupt condition disappears.
+ */
+static void ixp4xx_irq_unmask(struct irq_data *d)
+{
+        struct ixp4xx_irq *ixi = irq_data_get_irq_chip_data(d);
+        u32 val;
+
+        if (ixi->is_356 && d->hwirq >= 32) {
+                val = __raw_readl(ixi->irqbase + IXP4XX_ICMR2);
+                val |= BIT(d->hwirq - 32);
+                __raw_writel(val, ixi->irqbase + IXP4XX_ICMR2);
+        } else {
+                val = __raw_readl(ixi->irqbase + IXP4XX_ICMR);
+                val |= BIT(d->hwirq);
+                __raw_writel(val, ixi->irqbase + IXP4XX_ICMR);
+        }
+}
+
+asmlinkage void __exception_irq_entry ixp4xx_handle_irq(struct pt_regs *regs)
+{
+        struct ixp4xx_irq *ixi = &ixirq;
+        unsigned long status;
+        int i;
+
+        status = __raw_readl(ixi->irqbase + IXP4XX_ICIP);
+        for_each_set_bit(i, &status, 32)
+                handle_domain_irq(ixi->domain, i, regs);
+
+        /*
+         * IXP465/IXP435 has an upper IRQ status register
+         */
+        if (ixi->is_356) {
+                status = __raw_readl(ixi->irqbase + IXP4XX_ICIP2);
+                for_each_set_bit(i, &status, 32)
+                        handle_domain_irq(ixi->domain, i + 32, regs);
+        }
+}
+
+static int ixp4xx_irq_domain_translate(struct irq_domain *domain,
+                                       struct irq_fwspec *fwspec,
+                                       unsigned long *hwirq,
+                                       unsigned int *type)
+{
+        /* We support standard DT translation */
+        if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
+                *hwirq = fwspec->param[0];
+                *type = fwspec->param[1];
+                return 0;
+        }
+
+        if (is_fwnode_irqchip(fwspec->fwnode)) {
+                if (fwspec->param_count != 2)
+                        return -EINVAL;
+                *hwirq = fwspec->param[0];
+                *type = fwspec->param[1];
+                WARN_ON(*type == IRQ_TYPE_NONE);
+                return 0;
+        }
+
+        return -EINVAL;
+}
+
+static int ixp4xx_irq_domain_alloc(struct irq_domain *d,
+                                   unsigned int irq, unsigned int nr_irqs,
+                                   void *data)
+{
+        struct ixp4xx_irq *ixi = d->host_data;
+        irq_hw_number_t hwirq;
+        unsigned int type = IRQ_TYPE_NONE;
+        struct irq_fwspec *fwspec = data;
+        int ret;
+        int i;
+
+        ret = ixp4xx_irq_domain_translate(d, fwspec, &hwirq, &type);
+        if (ret)
+                return ret;
+
+        for (i = 0; i < nr_irqs; i++) {
+                /*
+                 * TODO: after converting IXP4xx to only device tree, set
+                 * handle_bad_irq as default handler and assume all consumers
+                 * call .set_type() as this is provided in the second cell in
+                 * the device tree phandle.
+                 */
+                irq_domain_set_info(d,
+                                    irq + i,
+                                    hwirq + i,
+                                    &ixi->irqchip,
+                                    ixi,
+                                    handle_level_irq,
+                                    NULL, NULL);
+                irq_set_probe(irq + i);
+        }
+
+        return 0;
+}
+
+/*
+ * This needs to be a hierarchical irqdomain to work well with the
+ * GPIO irqchip (which is lower in the hierarchy)
+ */
+static const struct irq_domain_ops ixp4xx_irqdomain_ops = {
+        .translate = ixp4xx_irq_domain_translate,
+        .alloc = ixp4xx_irq_domain_alloc,
+        .free = irq_domain_free_irqs_common,
+};
+
+/**
+ * ixp4xx_get_irq_domain() - retrieve the ixp4xx irq domain
+ *
+ * This function will go away when we transition to DT probing.
+ */
+struct irq_domain *ixp4xx_get_irq_domain(void)
+{
+        struct ixp4xx_irq *ixi = &ixirq;
+
+        return ixi->domain;
+}
+EXPORT_SYMBOL_GPL(ixp4xx_get_irq_domain);
+
+/*
+ * This is the Linux IRQ to hwirq mapping table. This goes away when
+ * we have DT support as all IRQ resources are defined in the device
+ * tree. It will register all the IRQs that are not used by the hierarchical
+ * GPIO IRQ chip. The "holes" inbetween these IRQs will be requested by
+ * the GPIO driver using . This is a step-gap solution.
+ */
+struct ixp4xx_irq_chunk {
+        int irq;
+        int hwirq;
+        int nr_irqs;
+};
+
+static const struct ixp4xx_irq_chunk ixp4xx_irq_chunks[] = {
+        {
+                .irq = 16,
+                .hwirq = 0,
+                .nr_irqs = 6,
+        },
+        {
+                .irq = 24,
+                .hwirq = 8,
+                .nr_irqs = 11,
+        },
+        {
+                .irq = 46,
+                .hwirq = 30,
+                .nr_irqs = 2,
+        },
+        /* Only on the 436 variants */
+        {
+                .irq = 48,
+                .hwirq = 32,
+                .nr_irqs = 10,
+        },
+};
+
+/**
+ * ixp4x_irq_setup() - Common setup code for the IXP4xx interrupt controller
+ * @ixi: State container
+ * @irqbase: Virtual memory base for the interrupt controller
+ * @fwnode: Corresponding fwnode abstraction for this controller
+ * @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
+ */
+static int ixp4xx_irq_setup(struct ixp4xx_irq *ixi,
+                            void __iomem *irqbase,
+                            struct fwnode_handle *fwnode,
+                            bool is_356)
+{
+        int nr_irqs;
+
+        ixi->irqbase = irqbase;
+        ixi->is_356 = is_356;
+
+        /* Route all sources to IRQ instead of FIQ */
+        __raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR);
+
+        /* Disable all interrupts */
+        __raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR);
+
+        if (is_356) {
+                /* Route upper 32 sources to IRQ instead of FIQ */
+                __raw_writel(0x0, ixi->irqbase + IXP4XX_ICLR2);
+
+                /* Disable upper 32 interrupts */
+                __raw_writel(0x0, ixi->irqbase + IXP4XX_ICMR2);
+
+                nr_irqs = 64;
+        } else {
+                nr_irqs = 32;
+        }
+
+        ixi->irqchip.name = "IXP4xx";
+        ixi->irqchip.irq_mask = ixp4xx_irq_mask;
+        ixi->irqchip.irq_unmask = ixp4xx_irq_unmask;
+        ixi->irqchip.irq_set_type = ixp4xx_set_irq_type;
+
+        ixi->domain = irq_domain_create_linear(fwnode, nr_irqs,
+                                               &ixp4xx_irqdomain_ops,
+                                               ixi);
+        if (!ixi->domain) {
+                pr_crit("IXP4XX: can not add primary irqdomain\n");
+                return -ENODEV;
+        }
+
+        set_handle_irq(ixp4xx_handle_irq);
+
+        return 0;
+}
+
+/**
+ * ixp4xx_irq_init() - Function to initialize the irqchip from boardfiles
+ * @irqbase: physical base for the irq controller
+ * @is_356: if this is an IXP43x, IXP45x or IXP46x SoC variant
+ */
+void __init ixp4xx_irq_init(resource_size_t irqbase,
+                            bool is_356)
+{
+        struct ixp4xx_irq *ixi = &ixirq;
+        void __iomem *base;
+        struct fwnode_handle *fwnode;
+        struct irq_fwspec fwspec;
+        int nr_chunks;
+        int ret;
+        int i;
+
+        base = ioremap(irqbase, 0x100);
+        if (!base) {
+                pr_crit("IXP4XX: could not ioremap interrupt controller\n");
+                return;
+        }
+        fwnode = irq_domain_alloc_fwnode(base);
+        if (!fwnode) {
+                pr_crit("IXP4XX: no domain handle\n");
+                return;
+        }
+        ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
+        if (ret) {
+                pr_crit("IXP4XX: failed to set up irqchip\n");
+                irq_domain_free_fwnode(fwnode);
+        }
+
+        nr_chunks = ARRAY_SIZE(ixp4xx_irq_chunks);
+        if (!is_356)
+                nr_chunks--;
+
+        /*
+         * After adding OF support, this is no longer needed: irqs
+         * will be allocated for the respective fwnodes.
+         */
+        for (i = 0; i < nr_chunks; i++) {
+                const struct ixp4xx_irq_chunk *chunk = &ixp4xx_irq_chunks[i];
+
+                pr_info("Allocate Linux IRQs %d..%d HW IRQs %d..%d\n",
+                        chunk->irq, chunk->irq + chunk->nr_irqs - 1,
+                        chunk->hwirq, chunk->hwirq + chunk->nr_irqs - 1);
+                fwspec.fwnode = fwnode;
+                fwspec.param[0] = chunk->hwirq;
+                fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH;
+                fwspec.param_count = 2;
+                ret = __irq_domain_alloc_irqs(ixi->domain,
+                                              chunk->irq,
+                                              chunk->nr_irqs,
+                                              NUMA_NO_NODE,
+                                              &fwspec,
+                                              false,
+                                              NULL);
+                if (ret < 0) {
+                        pr_crit("IXP4XX: can not allocate irqs in hierarchy %d\n",
+                                ret);
+                        return;
+                }
+        }
+}
+EXPORT_SYMBOL_GPL(ixp4xx_irq_init);
+
+#ifdef CONFIG_OF
+int __init ixp4xx_of_init_irq(struct device_node *np,
+                              struct device_node *parent)
+{
+        struct ixp4xx_irq *ixi = &ixirq;
+        void __iomem *base;
+        struct fwnode_handle *fwnode;
+        bool is_356;
+        int ret;
+
+        base = of_iomap(np, 0);
+        if (!base) {
+                pr_crit("IXP4XX: could not ioremap interrupt controller\n");
+                return -ENODEV;
+        }
+        fwnode = of_node_to_fwnode(np);
+
+        /* These chip variants have 64 interrupts */
+        is_356 = of_device_is_compatible(np, "intel,ixp43x-interrupt") ||
+                of_device_is_compatible(np, "intel,ixp45x-interrupt") ||
+                of_device_is_compatible(np, "intel,ixp46x-interrupt");
+
+        ret = ixp4xx_irq_setup(ixi, base, fwnode, is_356);
+        if (ret)
+                pr_crit("IXP4XX: failed to set up irqchip\n");
+
+        return ret;
+}
+IRQCHIP_DECLARE(ixp42x, "intel,ixp42x-interrupt",
+                ixp4xx_of_init_irq);
+IRQCHIP_DECLARE(ixp43x, "intel,ixp43x-interrupt",
+                ixp4xx_of_init_irq);
+IRQCHIP_DECLARE(ixp45x, "intel,ixp45x-interrupt",
+                ixp4xx_of_init_irq);
+IRQCHIP_DECLARE(ixp46x, "intel,ixp46x-interrupt",
+                ixp4xx_of_init_irq);
+#endif
diff --git a/drivers/net/ethernet/cirrus/Kconfig b/drivers/net/ethernet/cirrus/Kconfig
index e9a0213b08c4..6238e6951336 100644
--- a/drivers/net/ethernet/cirrus/Kconfig
+++ b/drivers/net/ethernet/cirrus/Kconfig
@@ -41,7 +41,7 @@ config CS89x0_PLATFORM
 
 config EP93XX_ETH
         tristate "EP93xx Ethernet support"
-        depends on ARM && ARCH_EP93XX
+        depends on (ARM && ARCH_EP93XX) || COMPILE_TEST
         select MII
         help
           This is a driver for the ethernet hardware included in EP93xx CPUs.
diff --git a/drivers/net/ethernet/cirrus/ep93xx_eth.c b/drivers/net/ethernet/cirrus/ep93xx_eth.c
index 13dfdfca49fc..a6da9873570b 100644
--- a/drivers/net/ethernet/cirrus/ep93xx_eth.c
+++ b/drivers/net/ethernet/cirrus/ep93xx_eth.c
@@ -25,7 +25,7 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
-#include <mach/hardware.h>
+#include <linux/platform_data/eth-ep93xx.h>
 
 #define DRV_MODULE_NAME         "ep93xx-eth"
 #define DRV_MODULE_VERSION      "0.1"
diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c
index ed6623a9801e..319db3ece263 100644
--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
+++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
@@ -31,14 +31,15 @@
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/net_tstamp.h>
+#include <linux/of.h>
 #include <linux/phy.h>
 #include <linux/platform_device.h>
 #include <linux/ptp_classify.h>
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <mach/ixp46x_ts.h>
-#include <mach/npe.h>
-#include <mach/qmgr.h>
+#include <linux/soc/ixp4xx/npe.h>
+#include <linux/soc/ixp4xx/qmgr.h>
 
 #define DEBUG_DESC              0
 #define DEBUG_RX                0
@@ -1497,6 +1498,15 @@ static struct platform_driver ixp4xx_eth_driver = {
 static int __init eth_init_module(void)
 {
         int err;
+
+        /*
+         * FIXME: we bail out on device tree boot but this really needs
+         * to be fixed in a nicer way: this registers the MDIO bus before
+         * even matching the driver infrastructure, we should only probe
+         * detected hardware.
+         */
+        if (of_have_populated_dt())
+                return -ENODEV;
         if ((err = ixp4xx_mdio_register()))
                 return err;
         return platform_driver_register(&ixp4xx_eth_driver);
diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c
index 5c60dc60a8e6..46a05b6540b8 100644
--- a/drivers/net/wan/ixp4xx_hss.c
+++ b/drivers/net/wan/ixp4xx_hss.c
@@ -22,8 +22,8 @@
 #include <linux/platform_device.h>
 #include <linux/poll.h>
 #include <linux/slab.h>
-#include <mach/npe.h>
-#include <mach/qmgr.h>
+#include <linux/soc/ixp4xx/npe.h>
+#include <linux/soc/ixp4xx/qmgr.h>
 
 #define DEBUG_DESC              0
 #define DEBUG_RX                0
diff --git a/drivers/pwm/pwm-ep93xx.c b/drivers/pwm/pwm-ep93xx.c
index bbf10ae02f0e..fa168581e6b8 100644
--- a/drivers/pwm/pwm-ep93xx.c
+++ b/drivers/pwm/pwm-ep93xx.c
@@ -35,7 +35,7 @@
 
 #include <asm/div64.h>
 
-#include <mach/platform.h>      /* for ep93xx_pwm_{acquire,release}_gpio() */
+#include <linux/soc/cirrus/ep93xx.h>    /* for ep93xx_pwm_{acquire,release}_gpio() */
 
 #define EP93XX_PWMx_TERM_COUNT  0x00
 #define EP93XX_PWMx_DUTY_CYCLE  0x04
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index c07b4a85253f..ae9bf20b26fa 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -6,6 +6,7 @@ source "drivers/soc/atmel/Kconfig"
 source "drivers/soc/bcm/Kconfig"
 source "drivers/soc/fsl/Kconfig"
 source "drivers/soc/imx/Kconfig"
+source "drivers/soc/ixp4xx/Kconfig"
 source "drivers/soc/mediatek/Kconfig"
 source "drivers/soc/qcom/Kconfig"
 source "drivers/soc/renesas/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 90b686e586c6..c7c1a139ad8d 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_MACH_DOVE)		+= dove/
 obj-y                           += fsl/
 obj-$(CONFIG_ARCH_GEMINI)       += gemini/
 obj-$(CONFIG_ARCH_MXC)          += imx/
+obj-$(CONFIG_ARCH_IXP4XX)       += ixp4xx/
 obj-$(CONFIG_SOC_XWAY)          += lantiq/
 obj-y                           += mediatek/
 obj-y                           += amlogic/
diff --git a/drivers/soc/ixp4xx/Kconfig b/drivers/soc/ixp4xx/Kconfig
new file mode 100644
index 000000000000..de6becdc78a2
--- /dev/null
+++ b/drivers/soc/ixp4xx/Kconfig
@@ -0,0 +1,16 @@
+menu "IXP4xx SoC drivers"
+
+config IXP4XX_QMGR
+        tristate "IXP4xx Queue Manager support"
+        help
+          This driver supports IXP4xx built-in hardware queue manager
+          and is automatically selected by Ethernet and HSS drivers.
+
+config IXP4XX_NPE
+        tristate "IXP4xx Network Processor Engine support"
+        select FW_LOADER
+        help
+          This driver supports IXP4xx built-in network coprocessors
+          and is automatically selected by Ethernet and HSS drivers.
+
+endmenu
diff --git a/drivers/soc/ixp4xx/Makefile b/drivers/soc/ixp4xx/Makefile
new file mode 100644
index 000000000000..d20d99e6df65
--- /dev/null
+++ b/drivers/soc/ixp4xx/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_IXP4XX_QMGR)       += ixp4xx-qmgr.o
+obj-$(CONFIG_IXP4XX_NPE)        += ixp4xx-npe.o
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/drivers/soc/ixp4xx/ixp4xx-npe.c
index d4eb09a62863..15979d4376ab 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+++ b/drivers/soc/ixp4xx/ixp4xx-npe.c
@@ -20,7 +20,9 @@
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <mach/npe.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/soc/ixp4xx/npe.h>
 
 #define DEBUG_MSG                       0
 #define DEBUG_FW                        0
@@ -153,16 +155,10 @@ static struct {
 static struct npe npe_tab[NPE_COUNT] = {
         {
                 .id     = 0,
-                .regs   = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT,
-                .regs_phys = IXP4XX_NPEA_BASE_PHYS,
         }, {
                 .id     = 1,
-                .regs   = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT,
-                .regs_phys = IXP4XX_NPEB_BASE_PHYS,
         }, {
                 .id     = 2,
-                .regs   = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT,
-                .regs_phys = IXP4XX_NPEC_BASE_PHYS,
         }
 };
 
@@ -682,28 +678,37 @@ void npe_release(struct npe *npe)
         module_put(THIS_MODULE);
 }
 
-
-static int __init npe_init_module(void)
+static int ixp4xx_npe_probe(struct platform_device *pdev)
 {
-
         int i, found = 0;
+        struct device *dev = &pdev->dev;
+        struct resource *res;
 
         for (i = 0; i < NPE_COUNT; i++) {
                 struct npe *npe = &npe_tab[i];
+
+                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+                if (!res)
+                        return -ENODEV;
+
                 if (!(ixp4xx_read_feature_bits() &
-                      (IXP4XX_FEATURE_RESET_NPEA << i)))
+                      (IXP4XX_FEATURE_RESET_NPEA << i))) {
+                        dev_info(dev, "NPE%d at 0x%08x-0x%08x not available\n",
+                                 i, res->start, res->end);
                         continue; /* NPE already disabled or not present */
-                if (!(npe->mem_res = request_mem_region(npe->regs_phys,
-                                                        REGS_SIZE,
-                                                        npe_name(npe)))) {
-                        print_npe(KERN_ERR, npe,
-                                  "failed to request memory region\n");
-                        continue;
                 }
+                npe->regs = devm_ioremap_resource(dev, res);
+                if (!npe->regs)
+                        return -ENOMEM;
 
-                if (npe_reset(npe))
+                if (npe_reset(npe)) {
+                        dev_info(dev, "NPE%d at 0x%08x-0x%08x does not reset\n",
+                                 i, res->start, res->end);
                         continue;
+                }
                 npe->valid = 1;
+                dev_info(dev, "NPE%d at 0x%08x-0x%08x registered\n",
+                         i, res->start, res->end);
                 found++;
         }
 
@@ -712,19 +717,34 @@ static int __init npe_init_module(void)
         return 0;
 }
 
-static void __exit npe_cleanup_module(void)
+static int ixp4xx_npe_remove(struct platform_device *pdev)
 {
         int i;
 
         for (i = 0; i < NPE_COUNT; i++)
-                if (npe_tab[i].mem_res) {
+                if (npe_tab[i].regs) {
                         npe_reset(&npe_tab[i]);
-                        release_resource(npe_tab[i].mem_res);
                 }
+
+        return 0;
 }
 
-module_init(npe_init_module);
-module_exit(npe_cleanup_module);
+static const struct of_device_id ixp4xx_npe_of_match[] = {
+        {
+                .compatible = "intel,ixp4xx-network-processing-engine",
+        },
+        {},
+};
+
+static struct platform_driver ixp4xx_npe_driver = {
+        .driver = {
+                .name           = "ixp4xx-npe",
+                .of_match_table = of_match_ptr(ixp4xx_npe_of_match),
+        },
+        .probe = ixp4xx_npe_probe,
+        .remove = ixp4xx_npe_remove,
+};
+module_platform_driver(ixp4xx_npe_driver);
 
 MODULE_AUTHOR("Krzysztof Halasa");
 MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/drivers/soc/ixp4xx/ixp4xx-qmgr.c
index 9d1b6b7c394c..13a8a13c9b01 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
+++ b/drivers/soc/ixp4xx/ixp4xx-qmgr.c
@@ -12,10 +12,13 @@
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <mach/qmgr.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/soc/ixp4xx/qmgr.h>
 
-static struct qmgr_regs __iomem *qmgr_regs = IXP4XX_QMGR_BASE_VIRT;
-static struct resource *mem_res;
+static struct qmgr_regs __iomem *qmgr_regs;
+static int qmgr_irq_1;
+static int qmgr_irq_2;
 static spinlock_t qmgr_lock;
 static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
 static void (*irq_handlers[QUEUES])(void *pdev);
@@ -25,6 +28,94 @@ static void *irq_pdevs[QUEUES];
 char qmgr_queue_descs[QUEUES][32];
 #endif
 
+void qmgr_put_entry(unsigned int queue, u32 val)
+{
+#if DEBUG_QMGR
+        BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
+
+        printk(KERN_DEBUG "Queue %s(%i) put %X\n",
+               qmgr_queue_descs[queue], queue, val);
+#endif
+        __raw_writel(val, &qmgr_regs->acc[queue][0]);
+}
+
+u32 qmgr_get_entry(unsigned int queue)
+{
+        u32 val;
+        val = __raw_readl(&qmgr_regs->acc[queue][0]);
+#if DEBUG_QMGR
+        BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
+
+        printk(KERN_DEBUG "Queue %s(%i) get %X\n",
+               qmgr_queue_descs[queue], queue, val);
+#endif
+        return val;
+}
+
+static int __qmgr_get_stat1(unsigned int queue)
+{
+        return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
+                >> ((queue & 7) << 2)) & 0xF;
+}
+
+static int __qmgr_get_stat2(unsigned int queue)
+{
+        BUG_ON(queue >= HALF_QUEUES);
+        return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
+                >> ((queue & 0xF) << 1)) & 0x3;
+}
+
+/**
+ * qmgr_stat_empty() - checks if a hardware queue is empty
+ * @queue:      queue number
+ *
+ * Returns non-zero value if the queue is empty.
+ */
+int qmgr_stat_empty(unsigned int queue)
+{
+        BUG_ON(queue >= HALF_QUEUES);
+        return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY;
+}
+
+/**
+ * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
+ * @queue:      queue number
+ *
+ * Returns non-zero value if the queue is below low watermark.
+ */
+int qmgr_stat_below_low_watermark(unsigned int queue)
+{
+        if (queue >= HALF_QUEUES)
+                return (__raw_readl(&qmgr_regs->statne_h) >>
+                        (queue - HALF_QUEUES)) & 0x01;
+        return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY;
+}
+
+/**
+ * qmgr_stat_full() - checks if a hardware queue is full
+ * @queue:      queue number
+ *
+ * Returns non-zero value if the queue is full.
+ */
+int qmgr_stat_full(unsigned int queue)
+{
+        if (queue >= HALF_QUEUES)
+                return (__raw_readl(&qmgr_regs->statf_h) >>
+                        (queue - HALF_QUEUES)) & 0x01;
+        return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL;
+}
+
+/**
+ * qmgr_stat_overflow() - checks if a hardware queue experienced overflow
+ * @queue:      queue number
+ *
+ * Returns non-zero value if the queue experienced overflow.
+ */
+int qmgr_stat_overflow(unsigned int queue)
+{
+        return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW;
+}
+
 void qmgr_set_irq(unsigned int queue, int src,
                   void (*handler)(void *pdev), void *pdev)
 {
@@ -95,7 +186,7 @@ static irqreturn_t qmgr_irq2_a0(int irq, void *pdev)
 
 static irqreturn_t qmgr_irq(int irq, void *pdev)
 {
-        int i, half = (irq == IRQ_IXP4XX_QM1 ? 0 : 1);
+        int i, half = (irq == qmgr_irq_1 ? 0 : 1);
         u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]);
 
         if (!req_bitmap)
@@ -282,16 +373,29 @@ void qmgr_release_queue(unsigned int queue)
         module_put(THIS_MODULE);
 }
 
-static int qmgr_init(void)
+static int ixp4xx_qmgr_probe(struct platform_device *pdev)
 {
         int i, err;
         irq_handler_t handler1, handler2;
+        struct device *dev = &pdev->dev;
+        struct resource *res;
+        int irq1, irq2;
 
-        mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS,
-                                     IXP4XX_QMGR_REGION_SIZE,
-                                     "IXP4xx Queue Manager");
-        if (mem_res == NULL)
-                return -EBUSY;
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                return -ENODEV;
+        qmgr_regs = devm_ioremap_resource(dev, res);
+        if (!qmgr_regs)
+                return -ENOMEM;
+
+        irq1 = platform_get_irq(pdev, 0);
+        if (irq1 <= 0)
+                return irq1 ? irq1 : -EINVAL;
+        qmgr_irq_1 = irq1;
+        irq2 = platform_get_irq(pdev, 1);
+        if (irq2 <= 0)
+                return irq2 ? irq2 : -EINVAL;
+        qmgr_irq_2 = irq2;
 
         /* reset qmgr registers */
         for (i = 0; i < 4; i++) {
@@ -316,50 +420,62 @@ static int qmgr_init(void)
         } else
                 handler1 = handler2 = qmgr_irq;
 
-        err = request_irq(IRQ_IXP4XX_QM1, handler1, 0, "IXP4xx Queue Manager",
-                          NULL);
+        err = devm_request_irq(dev, irq1, handler1, 0, "IXP4xx Queue Manager",
+                               NULL);
         if (err) {
-                printk(KERN_ERR "qmgr: failed to request IRQ%i (%i)\n",
-                       IRQ_IXP4XX_QM1, err);
-                goto error_irq;
+                dev_err(dev, "failed to request IRQ%i (%i)\n",
+                        irq1, err);
+                return err;
         }
 
-        err = request_irq(IRQ_IXP4XX_QM2, handler2, 0, "IXP4xx Queue Manager",
-                          NULL);
+        err = devm_request_irq(dev, irq2, handler2, 0, "IXP4xx Queue Manager",
+                               NULL);
         if (err) {
-                printk(KERN_ERR "qmgr: failed to request IRQ%i (%i)\n",
-                       IRQ_IXP4XX_QM2, err);
-                goto error_irq2;
+                dev_err(dev, "failed to request IRQ%i (%i)\n",
+                        irq2, err);
+                return err;
         }
 
         used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
         spin_lock_init(&qmgr_lock);
 
-        printk(KERN_INFO "IXP4xx Queue Manager initialized.\n");
+        dev_info(dev, "IXP4xx Queue Manager initialized.\n");
         return 0;
-
-error_irq2:
-        free_irq(IRQ_IXP4XX_QM1, NULL);
-error_irq:
-        release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
-        return err;
 }
 
-static void qmgr_remove(void)
+static int ixp4xx_qmgr_remove(struct platform_device *pdev)
 {
-        free_irq(IRQ_IXP4XX_QM1, NULL);
-        free_irq(IRQ_IXP4XX_QM2, NULL);
-        synchronize_irq(IRQ_IXP4XX_QM1);
-        synchronize_irq(IRQ_IXP4XX_QM2);
-        release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
+        synchronize_irq(qmgr_irq_1);
+        synchronize_irq(qmgr_irq_2);
+        return 0;
 }
 
-module_init(qmgr_init);
-module_exit(qmgr_remove);
+static const struct of_device_id ixp4xx_qmgr_of_match[] = {
+        {
+                .compatible = "intel,ixp4xx-ahb-queue-manager",
+        },
+        {},
+};
+
+static struct platform_driver ixp4xx_qmgr_driver = {
+        .driver = {
+                .name           = "ixp4xx-qmgr",
+                .of_match_table = of_match_ptr(ixp4xx_qmgr_of_match),
+        },
+        .probe = ixp4xx_qmgr_probe,
+        .remove = ixp4xx_qmgr_remove,
+};
+module_platform_driver(ixp4xx_qmgr_driver);
 
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Krzysztof Halasa");
 
+EXPORT_SYMBOL(qmgr_put_entry);
+EXPORT_SYMBOL(qmgr_get_entry);
+EXPORT_SYMBOL(qmgr_stat_empty);
+EXPORT_SYMBOL(qmgr_stat_below_low_watermark);
+EXPORT_SYMBOL(qmgr_stat_full);
+EXPORT_SYMBOL(qmgr_stat_overflow);
 EXPORT_SYMBOL(qmgr_set_irq);
 EXPORT_SYMBOL(qmgr_enable_irq);
 EXPORT_SYMBOL(qmgr_disable_irq);
diff --git a/drivers/usb/host/ohci-da8xx.c b/drivers/usb/host/ohci-da8xx.c
index ca8a94f15ac0..38183ac438c6 100644
--- a/drivers/usb/host/ohci-da8xx.c
+++ b/drivers/usb/host/ohci-da8xx.c
@@ -40,8 +40,6 @@ struct da8xx_ohci_hcd {
         struct phy *usb11_phy;
         struct regulator *vbus_reg;
         struct notifier_block nb;
-        unsigned int reg_enabled;
-        struct gpio_desc *vbus_gpio;
         struct gpio_desc *oc_gpio;
 };
 
@@ -92,29 +90,21 @@ static int ohci_da8xx_set_power(struct usb_hcd *hcd, int on)
         struct device *dev = hcd->self.controller;
         int ret;
 
-        if (da8xx_ohci->vbus_gpio) {
-                gpiod_set_value_cansleep(da8xx_ohci->vbus_gpio, on);
-                return 0;
-        }
-
         if (!da8xx_ohci->vbus_reg)
                 return 0;
 
-        if (on && !da8xx_ohci->reg_enabled) {
+        if (on) {
                 ret = regulator_enable(da8xx_ohci->vbus_reg);
                 if (ret) {
                         dev_err(dev, "Failed to enable regulator: %d\n", ret);
                         return ret;
                 }
-                da8xx_ohci->reg_enabled = 1;
-
-        } else if (!on && da8xx_ohci->reg_enabled) {
+        } else {
                 ret = regulator_disable(da8xx_ohci->vbus_reg);
                 if (ret) {
                         dev_err(dev, "Failed  to disable regulator: %d\n", ret);
                         return ret;
                 }
-                da8xx_ohci->reg_enabled = 0;
         }
 
         return 0;
@@ -124,9 +114,6 @@ static int ohci_da8xx_get_power(struct usb_hcd *hcd)
 {
         struct da8xx_ohci_hcd *da8xx_ohci = to_da8xx_ohci(hcd);
 
-        if (da8xx_ohci->vbus_gpio)
-                return gpiod_get_value_cansleep(da8xx_ohci->vbus_gpio);
-
         if (da8xx_ohci->vbus_reg)
                 return regulator_is_enabled(da8xx_ohci->vbus_reg);
 
@@ -159,9 +146,6 @@ static int ohci_da8xx_has_set_power(struct usb_hcd *hcd)
 {
         struct da8xx_ohci_hcd *da8xx_ohci = to_da8xx_ohci(hcd);
 
-        if (da8xx_ohci->vbus_gpio)
-                return 1;
-
         if (da8xx_ohci->vbus_reg)
                 return 1;
 
@@ -206,12 +190,18 @@ static int ohci_da8xx_regulator_event(struct notifier_block *nb,
         return 0;
 }
 
-static irqreturn_t ohci_da8xx_oc_handler(int irq, void *data)
+static irqreturn_t ohci_da8xx_oc_thread(int irq, void *data)
 {
         struct da8xx_ohci_hcd *da8xx_ohci = data;
+        struct device *dev = da8xx_ohci->hcd->self.controller;
+        int ret;
 
-        if (gpiod_get_value(da8xx_ohci->oc_gpio))
-                gpiod_set_value(da8xx_ohci->vbus_gpio, 0);
+        if (gpiod_get_value_cansleep(da8xx_ohci->oc_gpio) &&
+            da8xx_ohci->vbus_reg) {
+                ret = regulator_disable(da8xx_ohci->vbus_reg);
+                if (ret)
+                        dev_err(dev, "Failed to disable regulator: %d\n", ret);
+        }
 
         return IRQ_HANDLED;
 }
@@ -424,11 +414,6 @@ static int ohci_da8xx_probe(struct platform_device *pdev)
                 }
         }
 
-        da8xx_ohci->vbus_gpio = devm_gpiod_get_optional(dev, "vbus",
-                                                        GPIOD_OUT_HIGH);
-        if (IS_ERR(da8xx_ohci->vbus_gpio))
-                goto err;
-
         da8xx_ohci->oc_gpio = devm_gpiod_get_optional(dev, "oc", GPIOD_IN);
         if (IS_ERR(da8xx_ohci->oc_gpio))
                 goto err;
@@ -438,8 +423,9 @@ static int ohci_da8xx_probe(struct platform_device *pdev)
                 if (oc_irq < 0)
                         goto err;
 
-                error = devm_request_irq(dev, oc_irq, ohci_da8xx_oc_handler,
-                                IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+                error = devm_request_threaded_irq(dev, oc_irq, NULL,
+                                ohci_da8xx_oc_thread, IRQF_TRIGGER_RISING |
+                                IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
                                 "OHCI over-current indicator", da8xx_ohci);
                 if (error)
                         goto err;
diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c
index dd139cda936c..9067998759e3 100644
--- a/drivers/watchdog/ixp4xx_wdt.c
+++ b/drivers/watchdog/ixp4xx_wdt.c
@@ -21,6 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/fs.h>
 #include <linux/miscdevice.h>
+#include <linux/of.h>
 #include <linux/watchdog.h>
 #include <linux/init.h>
 #include <linux/bitops.h>
@@ -176,6 +177,14 @@ static int __init ixp4xx_wdt_init(void)
 {
         int ret;
 
+        /*
+         * FIXME: we bail out on device tree boot but this really needs
+         * to be fixed in a nicer way: this registers the MDIO bus before
+         * even matching the driver infrastructure, we should only probe
+         * detected hardware.
+         */
+        if (of_have_populated_dt())
+                return -ENODEV;
         if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) {
                 pr_err("Rev. A0 IXP42x CPU detected - watchdog disabled\n");
 
diff --git a/arch/arm/include/asm/trusted_foundations.h b/include/linux/firmware/trusted_foundations.h
index 00748350cf72..4064e7c74715 100644
--- a/arch/arm/include/asm/trusted_foundations.h
+++ b/include/linux/firmware/trusted_foundations.h
@@ -23,14 +23,24 @@
  * PSCI standard.
  */
 
-#ifndef __ASM_ARM_TRUSTED_FOUNDATIONS_H
-#define __ASM_ARM_TRUSTED_FOUNDATIONS_H
+#ifndef __FIRMWARE_TRUSTED_FOUNDATIONS_H
+#define __FIRMWARE_TRUSTED_FOUNDATIONS_H
 
 #include <linux/printk.h>
 #include <linux/bug.h>
 #include <linux/of.h>
 #include <linux/cpu.h>
 #include <linux/smp.h>
+#include <linux/types.h>
+
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/outercache.h>
+
+#define TF_PM_MODE_LP0                  0
+#define TF_PM_MODE_LP1                  1
+#define TF_PM_MODE_LP1_NO_MC_CLK        2
+#define TF_PM_MODE_LP2                  3
+#define TF_PM_MODE_LP2_NOFLUSH_L2       4
 
 struct trusted_foundations_platform_data {
         unsigned int version_major;
@@ -41,8 +51,12 @@ struct trusted_foundations_platform_data {
 
 void register_trusted_foundations(struct trusted_foundations_platform_data *pd);
 void of_register_trusted_foundations(void);
+bool trusted_foundations_registered(void);
 
 #else /* CONFIG_TRUSTED_FOUNDATIONS */
+static inline void tf_dummy_write_sec(unsigned long val, unsigned int reg)
+{
+}
 
 static inline void register_trusted_foundations(
                                    struct trusted_foundations_platform_data *pd)
@@ -53,6 +67,10 @@ static inline void register_trusted_foundations(
          */
         pr_err("No support for Trusted Foundations, continuing in degraded mode.\n");
         pr_err("Secondary processors as well as CPU PM will be disabled.\n");
+#if IS_ENABLED(CONFIG_CACHE_L2X0)
+        pr_err("L2X0 cache will be kept disabled.\n");
+        outer_cache.write_sec = tf_dummy_write_sec;
+#endif
 #if IS_ENABLED(CONFIG_SMP)
         setup_max_cpus = 0;
 #endif
@@ -68,6 +86,11 @@ static inline void of_register_trusted_foundations(void)
         if (of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations"))
                 register_trusted_foundations(NULL);
 }
+
+static inline bool trusted_foundations_registered(void)
+{
+        return false;
+}
 #endif /* CONFIG_TRUSTED_FOUNDATIONS */
 
 #endif
diff --git a/include/linux/irqchip/irq-ixp4xx.h b/include/linux/irqchip/irq-ixp4xx.h
new file mode 100644
index 000000000000..9395917d6936
--- /dev/null
+++ b/include/linux/irqchip/irq-ixp4xx.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __IRQ_IXP4XX_H
+#define __IRQ_IXP4XX_H
+
+#include <linux/ioport.h>
+struct irq_domain;
+
+void ixp4xx_irq_init(resource_size_t irqbase,
+                     bool is_356);
+struct irq_domain *ixp4xx_get_irq_domain(void);
+
+#endif /* __IRQ_IXP4XX_H */
diff --git a/include/linux/platform_data/eth-ep93xx.h b/include/linux/platform_data/eth-ep93xx.h
new file mode 100644
index 000000000000..8eef637a804d
--- /dev/null
+++ b/include/linux/platform_data/eth-ep93xx.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _LINUX_PLATFORM_DATA_ETH_EP93XX
+#define _LINUX_PLATFORM_DATA_ETH_EP93XX
+
+struct ep93xx_eth_data {
+        unsigned char   dev_addr[6];
+        unsigned char   phy_id;
+};
+
+#endif
diff --git a/include/linux/platform_data/keypad-ep93xx.h b/include/linux/platform_data/keypad-ep93xx.h
index 0e36818e3680..3054fced8509 100644
--- a/include/linux/platform_data/keypad-ep93xx.h
+++ b/include/linux/platform_data/keypad-ep93xx.h
@@ -9,8 +9,7 @@ struct matrix_keymap_data;
 #define EP93XX_KEYPAD_DIAG_MODE         (1<<1)  /* diagnostic mode */
 #define EP93XX_KEYPAD_BACK_DRIVE        (1<<2)  /* back driving mode */
 #define EP93XX_KEYPAD_TEST_MODE         (1<<3)  /* scan only column 0 */
-#define EP93XX_KEYPAD_KDIV              (1<<4)  /* 1/4 clock or 1/16 clock */
-#define EP93XX_KEYPAD_AUTOREPEAT        (1<<5)  /* enable key autorepeat */
+#define EP93XX_KEYPAD_AUTOREPEAT        (1<<4)  /* enable key autorepeat */
 
 /**
  * struct ep93xx_keypad_platform_data - platform specific device structure
@@ -24,6 +23,7 @@ struct ep93xx_keypad_platform_data {
         unsigned int    debounce;
         unsigned int    prescale;
         unsigned int    flags;
+        unsigned int    clk_rate;
 };
 
 #define EP93XX_MATRIX_ROWS              (8)
diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h
index 1ea3aab972b4..9256c0305968 100644
--- a/include/linux/platform_data/ti-sysc.h
+++ b/include/linux/platform_data/ti-sysc.h
@@ -46,8 +46,13 @@ struct sysc_regbits {
         s8 emufree_shift;
 };
 
-#define SYSC_QUIRK_LEGACY_IDLE          BIT(8)
-#define SYSC_QUIRK_RESET_STATUS         BIT(7)
+#define SYSC_QUIRK_SWSUP_MSTANDBY       BIT(13)
+#define SYSC_QUIRK_SWSUP_SIDLE_ACT      BIT(12)
+#define SYSC_QUIRK_SWSUP_SIDLE          BIT(11)
+#define SYSC_QUIRK_EXT_OPT_CLOCK        BIT(10)
+#define SYSC_QUIRK_LEGACY_IDLE          BIT(9)
+#define SYSC_QUIRK_RESET_STATUS         BIT(8)
+#define SYSC_QUIRK_NO_IDLE              BIT(7)
 #define SYSC_QUIRK_NO_IDLE_ON_INIT      BIT(6)
 #define SYSC_QUIRK_NO_RESET_ON_INIT     BIT(5)
 #define SYSC_QUIRK_OPT_CLKS_NEEDED      BIT(4)
diff --git a/include/linux/platform_data/timer-ixp4xx.h b/include/linux/platform_data/timer-ixp4xx.h
new file mode 100644
index 000000000000..ee92ae7edaed
--- /dev/null
+++ b/include/linux/platform_data/timer-ixp4xx.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __TIMER_IXP4XX_H
+#define __TIMER_IXP4XX_H
+
+#include <linux/ioport.h>
+
+void __init ixp4xx_timer_setup(resource_size_t timerbase,
+                               int timer_irq,
+                               unsigned int timer_freq);
+
+#endif
diff --git a/include/linux/soc/cirrus/ep93xx.h b/include/linux/soc/cirrus/ep93xx.h
new file mode 100644
index 000000000000..56fbe2dc59b1
--- /dev/null
+++ b/include/linux/soc/cirrus/ep93xx.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _SOC_EP93XX_H
+#define _SOC_EP93XX_H
+
+struct platform_device;
+
+#define EP93XX_CHIP_REV_D0      3
+#define EP93XX_CHIP_REV_D1      4
+#define EP93XX_CHIP_REV_E0      5
+#define EP93XX_CHIP_REV_E1      6
+#define EP93XX_CHIP_REV_E2      7
+
+#ifdef CONFIG_ARCH_EP93XX
+int ep93xx_pwm_acquire_gpio(struct platform_device *pdev);
+void ep93xx_pwm_release_gpio(struct platform_device *pdev);
+int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
+void ep93xx_ide_release_gpio(struct platform_device *pdev);
+int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
+void ep93xx_keypad_release_gpio(struct platform_device *pdev);
+int ep93xx_i2s_acquire(void);
+void ep93xx_i2s_release(void);
+unsigned int ep93xx_chip_revision(void);
+
+#else
+static inline int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) { return 0; }
+static inline void ep93xx_pwm_release_gpio(struct platform_device *pdev) {}
+static inline int ep93xx_ide_acquire_gpio(struct platform_device *pdev) { return 0; }
+static inline void ep93xx_ide_release_gpio(struct platform_device *pdev) {}
+static inline int ep93xx_keypad_acquire_gpio(struct platform_device *pdev) { return 0; }
+static inline void ep93xx_keypad_release_gpio(struct platform_device *pdev) {}
+static inline int ep93xx_i2s_acquire(void) { return 0; }
+static inline void ep93xx_i2s_release(void) {}
+static inline unsigned int ep93xx_chip_revision(void) { return 0; }
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/npe.h b/include/linux/soc/ixp4xx/npe.h
index 3a980845e557..2a91f465d456 100644
--- a/arch/arm/mach-ixp4xx/include/mach/npe.h
+++ b/include/linux/soc/ixp4xx/npe.h
@@ -16,9 +16,7 @@ struct npe_regs {
 };
 
 struct npe {
-        struct resource *mem_res;
         struct npe_regs __iomem *regs;
-        u32 regs_phys;
         int id;
         int valid;
 };
diff --git a/include/linux/soc/ixp4xx/qmgr.h b/include/linux/soc/ixp4xx/qmgr.h
new file mode 100644
index 000000000000..bed8ee94fa57
--- /dev/null
+++ b/include/linux/soc/ixp4xx/qmgr.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef IXP4XX_QMGR_H
+#define IXP4XX_QMGR_H
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#define DEBUG_QMGR      0
+
+#define HALF_QUEUES     32
+#define QUEUES          64
+#define MAX_QUEUE_LENGTH 4      /* in dwords */
+
+#define QUEUE_STAT1_EMPTY               1 /* queue status bits */
+#define QUEUE_STAT1_NEARLY_EMPTY        2
+#define QUEUE_STAT1_NEARLY_FULL         4
+#define QUEUE_STAT1_FULL                8
+#define QUEUE_STAT2_UNDERFLOW           1
+#define QUEUE_STAT2_OVERFLOW            2
+
+#define QUEUE_WATERMARK_0_ENTRIES       0
+#define QUEUE_WATERMARK_1_ENTRY         1
+#define QUEUE_WATERMARK_2_ENTRIES       2
+#define QUEUE_WATERMARK_4_ENTRIES       3
+#define QUEUE_WATERMARK_8_ENTRIES       4
+#define QUEUE_WATERMARK_16_ENTRIES      5
+#define QUEUE_WATERMARK_32_ENTRIES      6
+#define QUEUE_WATERMARK_64_ENTRIES      7
+
+/* queue interrupt request conditions */
+#define QUEUE_IRQ_SRC_EMPTY             0
+#define QUEUE_IRQ_SRC_NEARLY_EMPTY      1
+#define QUEUE_IRQ_SRC_NEARLY_FULL       2
+#define QUEUE_IRQ_SRC_FULL              3
+#define QUEUE_IRQ_SRC_NOT_EMPTY         4
+#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY  5
+#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL   6
+#define QUEUE_IRQ_SRC_NOT_FULL          7
+
+struct qmgr_regs {
+        u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
+        u32 stat1[4];           /* 0x400 - 0x40F */
+        u32 stat2[2];           /* 0x410 - 0x417 */
+        u32 statne_h;           /* 0x418 - queue nearly empty */
+        u32 statf_h;            /* 0x41C - queue full */
+        u32 irqsrc[4];          /* 0x420 - 0x42F IRC source */
+        u32 irqen[2];           /* 0x430 - 0x437 IRQ enabled */
+        u32 irqstat[2];         /* 0x438 - 0x43F - IRQ access only */
+        u32 reserved[1776];
+        u32 sram[2048];         /* 0x2000 - 0x3FFF - config and buffer */
+};
+
+void qmgr_put_entry(unsigned int queue, u32 val);
+u32 qmgr_get_entry(unsigned int queue);
+int qmgr_stat_empty(unsigned int queue);
+int qmgr_stat_below_low_watermark(unsigned int queue);
+int qmgr_stat_full(unsigned int queue);
+int qmgr_stat_overflow(unsigned int queue);
+void qmgr_release_queue(unsigned int queue);
+void qmgr_set_irq(unsigned int queue, int src,
+                  void (*handler)(void *pdev), void *pdev);
+void qmgr_enable_irq(unsigned int queue);
+void qmgr_disable_irq(unsigned int queue);
+
+/* request_ and release_queue() must be called from non-IRQ context */
+
+#if DEBUG_QMGR
+extern char qmgr_queue_descs[QUEUES][32];
+
+int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
+                       unsigned int nearly_empty_watermark,
+                       unsigned int nearly_full_watermark,
+                       const char *desc_format, const char* name);
+#else
+int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
+                         unsigned int nearly_empty_watermark,
+                         unsigned int nearly_full_watermark);
+#define qmgr_request_queue(queue, len, nearly_empty_watermark,          \
+                           nearly_full_watermark, desc_format, name)    \
+        __qmgr_request_queue(queue, len, nearly_empty_watermark,        \
+                             nearly_full_watermark)
+#endif
+
+#endif
diff --git a/sound/soc/cirrus/edb93xx.c b/sound/soc/cirrus/edb93xx.c
index 3d011abaa266..f678b4c1514a 100644
--- a/sound/soc/cirrus/edb93xx.c
+++ b/sound/soc/cirrus/edb93xx.c
@@ -22,11 +22,11 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/module.h>
+#include <linux/soc/cirrus/ep93xx.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/soc.h>
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
 
 static int edb93xx_hw_params(struct snd_pcm_substream *substream,
                              struct snd_pcm_hw_params *params)
diff --git a/sound/soc/cirrus/ep93xx-ac97.c b/sound/soc/cirrus/ep93xx-ac97.c
index cd5a939ad608..c6bc447429af 100644
--- a/sound/soc/cirrus/ep93xx-ac97.c
+++ b/sound/soc/cirrus/ep93xx-ac97.c
@@ -24,6 +24,7 @@
 #include <sound/soc.h>
 
 #include <linux/platform_data/dma-ep93xx.h>
+#include <linux/soc/cirrus/ep93xx.h>
 
 #include "ep93xx-pcm.h"
 
diff --git a/sound/soc/cirrus/ep93xx-i2s.c b/sound/soc/cirrus/ep93xx-i2s.c
index 0918c5da575a..beab7c516855 100644
--- a/sound/soc/cirrus/ep93xx-i2s.c
+++ b/sound/soc/cirrus/ep93xx-i2s.c
@@ -27,9 +27,8 @@
 #include <sound/initval.h>
 #include <sound/soc.h>
 
-#include <mach/hardware.h>
-#include <mach/ep93xx-regs.h>
 #include <linux/platform_data/dma-ep93xx.h>
+#include <linux/soc/cirrus/ep93xx.h>
 
 #include "ep93xx-pcm.h"
 
diff --git a/sound/soc/cirrus/simone.c b/sound/soc/cirrus/simone.c
index 1ec661834e5a..cb850530331b 100644
--- a/sound/soc/cirrus/simone.c
+++ b/sound/soc/cirrus/simone.c
@@ -13,13 +13,13 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/soc/cirrus/ep93xx.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/soc.h>
 
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
 
 static struct snd_soc_dai_link simone_dai = {
         .name           = "AC97",
diff --git a/sound/soc/cirrus/snappercl15.c b/sound/soc/cirrus/snappercl15.c
index 11ff7b2672b2..dea4909154c8 100644
--- a/sound/soc/cirrus/snappercl15.c
+++ b/sound/soc/cirrus/snappercl15.c
@@ -13,12 +13,12 @@
 
 #include <linux/platform_device.h>
 #include <linux/module.h>
+#include <linux/soc/cirrus/ep93xx.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
 #include <sound/soc.h>
 
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
 
 #include "../codecs/tlv320aic23.h"