2 files changed, 12 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e69fe05228fb..9b76d63cc1ac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7215,6 +7215,10 @@ enum {
 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
 #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
 
+/* Display Internal Timeout Register */
+#define RM_TIMEOUT              _MMIO(0x42060)
+#define  MMIO_TIMEOUT_US(us)    ((us) << 0)
+
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 75ee027abb80..b5903ee25dea 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -126,6 +126,14 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
          */
         I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
                    PWM1_GATING_DIS | PWM2_GATING_DIS);
+
+        /*
+         * Lower the display internal timeout.
+         * This is needed to avoid any hard hangs when DSI port PLL
+         * is off and a MMIO access is attempted by any privilege
+         * application, using batch buffers or any other means.
+         */
+        I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950));
 }
 
 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)