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-rw-r--r--tools/arch/x86/include/asm/inat.h2
-rw-r--r--tools/arch/x86/include/asm/insn.h2
-rw-r--r--tools/arch/x86/lib/inat.c2
-rw-r--r--tools/arch/x86/lib/insn.c4
-rw-r--r--tools/perf/arch/x86/tests/insn-x86.c2
-rw-r--r--tools/perf/arch/x86/util/archinsn.c2
-rwxr-xr-xtools/perf/check-headers.sh11
-rw-r--r--tools/perf/util/intel-pt-decoder/Build20
-rw-r--r--tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk392
-rw-r--r--tools/perf/util/intel-pt-decoder/inat.c82
-rw-r--r--tools/perf/util/intel-pt-decoder/inat.h230
-rw-r--r--tools/perf/util/intel-pt-decoder/inat_types.h15
-rw-r--r--tools/perf/util/intel-pt-decoder/insn.c593
-rw-r--r--tools/perf/util/intel-pt-decoder/insn.h216
-rw-r--r--tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c10
-rw-r--r--tools/perf/util/intel-pt-decoder/x86-opcode-map.txt1072
16 files changed, 23 insertions, 2632 deletions
diff --git a/tools/arch/x86/include/asm/inat.h b/tools/arch/x86/include/asm/inat.h
index 4cf2ad521f65..877827b7c2c3 100644
--- a/tools/arch/x86/include/asm/inat.h
+++ b/tools/arch/x86/include/asm/inat.h
@@ -6,7 +6,7 @@
6 * 6 *
7 * Written by Masami Hiramatsu <mhiramat@redhat.com> 7 * Written by Masami Hiramatsu <mhiramat@redhat.com>
8 */ 8 */
9#include <asm/inat_types.h> 9#include "inat_types.h"
10 10
11/* 11/*
12 * Internal bits. Don't use bitmasks directly, because these bits are 12 * Internal bits. Don't use bitmasks directly, because these bits are
diff --git a/tools/arch/x86/include/asm/insn.h b/tools/arch/x86/include/asm/insn.h
index 154f27be8bfc..37a4c390750b 100644
--- a/tools/arch/x86/include/asm/insn.h
+++ b/tools/arch/x86/include/asm/insn.h
@@ -8,7 +8,7 @@
8 */ 8 */
9 9
10/* insn_attr_t is defined in inat.h */ 10/* insn_attr_t is defined in inat.h */
11#include <asm/inat.h> 11#include "inat.h"
12 12
13struct insn_field { 13struct insn_field {
14 union { 14 union {
diff --git a/tools/arch/x86/lib/inat.c b/tools/arch/x86/lib/inat.c
index 12539fca75c4..4f5ed49e1b4e 100644
--- a/tools/arch/x86/lib/inat.c
+++ b/tools/arch/x86/lib/inat.c
@@ -4,7 +4,7 @@
4 * 4 *
5 * Written by Masami Hiramatsu <mhiramat@redhat.com> 5 * Written by Masami Hiramatsu <mhiramat@redhat.com>
6 */ 6 */
7#include <asm/insn.h> 7#include "../include/asm/insn.h"
8 8
9/* Attribute tables are generated from opcode map */ 9/* Attribute tables are generated from opcode map */
10#include "inat-tables.c" 10#include "inat-tables.c"
diff --git a/tools/arch/x86/lib/insn.c b/tools/arch/x86/lib/insn.c
index 0b5862ba6a75..79e048f1d902 100644
--- a/tools/arch/x86/lib/insn.c
+++ b/tools/arch/x86/lib/insn.c
@@ -10,8 +10,8 @@
10#else 10#else
11#include <string.h> 11#include <string.h>
12#endif 12#endif
13#include <asm/inat.h> 13#include "../include/asm/inat.h"
14#include <asm/insn.h> 14#include "../include/asm/insn.h"
15 15
16/* Verify next sizeof(t) bytes can be on the same instruction */ 16/* Verify next sizeof(t) bytes can be on the same instruction */
17#define validate_next(t, insn, n) \ 17#define validate_next(t, insn, n) \
diff --git a/tools/perf/arch/x86/tests/insn-x86.c b/tools/perf/arch/x86/tests/insn-x86.c
index d67bc0ffb70a..745f29adb14b 100644
--- a/tools/perf/arch/x86/tests/insn-x86.c
+++ b/tools/perf/arch/x86/tests/insn-x86.c
@@ -1,12 +1,12 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2#include <linux/types.h> 2#include <linux/types.h>
3#include "../../../../arch/x86/include/asm/insn.h"
3#include <string.h> 4#include <string.h>
4 5
5#include "debug.h" 6#include "debug.h"
6#include "tests/tests.h" 7#include "tests/tests.h"
7#include "arch-tests.h" 8#include "arch-tests.h"
8 9
9#include "intel-pt-decoder/insn.h"
10#include "intel-pt-decoder/intel-pt-insn-decoder.h" 10#include "intel-pt-decoder/intel-pt-insn-decoder.h"
11 11
12struct test_data { 12struct test_data {
diff --git a/tools/perf/arch/x86/util/archinsn.c b/tools/perf/arch/x86/util/archinsn.c
index 62e8e1820132..9876c7a7ed7c 100644
--- a/tools/perf/arch/x86/util/archinsn.c
+++ b/tools/perf/arch/x86/util/archinsn.c
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2#include "../../../../arch/x86/include/asm/insn.h"
2#include "archinsn.h" 3#include "archinsn.h"
3#include "util/intel-pt-decoder/insn.h"
4#include "machine.h" 4#include "machine.h"
5#include "thread.h" 5#include "thread.h"
6#include "symbol.h" 6#include "symbol.h"
diff --git a/tools/perf/check-headers.sh b/tools/perf/check-headers.sh
index 5308b3836278..cbcc3590098c 100755
--- a/tools/perf/check-headers.sh
+++ b/tools/perf/check-headers.sh
@@ -1,7 +1,7 @@
1#!/bin/sh 1#!/bin/sh
2# SPDX-License-Identifier: GPL-2.0 2# SPDX-License-Identifier: GPL-2.0
3 3
4HEADERS=' 4FILES='
5include/uapi/linux/const.h 5include/uapi/linux/const.h
6include/uapi/drm/drm.h 6include/uapi/drm/drm.h
7include/uapi/drm/i915_drm.h 7include/uapi/drm/i915_drm.h
@@ -26,7 +26,14 @@ include/uapi/linux/hw_breakpoint.h
26arch/x86/include/asm/disabled-features.h 26arch/x86/include/asm/disabled-features.h
27arch/x86/include/asm/required-features.h 27arch/x86/include/asm/required-features.h
28arch/x86/include/asm/cpufeatures.h 28arch/x86/include/asm/cpufeatures.h
29arch/x86/include/asm/inat.h
30arch/x86/include/asm/inat_types.h
31arch/x86/include/asm/insn.h
29arch/x86/include/uapi/asm/prctl.h 32arch/x86/include/uapi/asm/prctl.h
33arch/x86/lib/inat.c
34arch/x86/lib/insn.c
35arch/x86/lib/x86-opcode-map.txt
36arch/x86/tools/gen-insn-attr-x86.awk
30arch/arm/include/uapi/asm/perf_regs.h 37arch/arm/include/uapi/asm/perf_regs.h
31arch/arm64/include/uapi/asm/perf_regs.h 38arch/arm64/include/uapi/asm/perf_regs.h
32arch/powerpc/include/uapi/asm/perf_regs.h 39arch/powerpc/include/uapi/asm/perf_regs.h
@@ -98,7 +105,7 @@ test -d ../../include || exit 0
98cd ../.. 105cd ../..
99 106
100# simple diff check 107# simple diff check
101for i in $HEADERS; do 108for i in $FILES; do
102 check $i -B 109 check $i -B
103done 110done
104 111
diff --git a/tools/perf/util/intel-pt-decoder/Build b/tools/perf/util/intel-pt-decoder/Build
index acb18a3463c3..bc629359826f 100644
--- a/tools/perf/util/intel-pt-decoder/Build
+++ b/tools/perf/util/intel-pt-decoder/Build
@@ -1,7 +1,7 @@
1perf-$(CONFIG_AUXTRACE) += intel-pt-pkt-decoder.o intel-pt-insn-decoder.o intel-pt-log.o intel-pt-decoder.o 1perf-$(CONFIG_AUXTRACE) += intel-pt-pkt-decoder.o intel-pt-insn-decoder.o intel-pt-log.o intel-pt-decoder.o
2 2
3inat_tables_script = util/intel-pt-decoder/gen-insn-attr-x86.awk 3inat_tables_script = $(srctree)/tools/arch/x86/tools/gen-insn-attr-x86.awk
4inat_tables_maps = util/intel-pt-decoder/x86-opcode-map.txt 4inat_tables_maps = $(srctree)/tools/arch/x86/lib/x86-opcode-map.txt
5 5
6$(OUTPUT)util/intel-pt-decoder/inat-tables.c: $(inat_tables_script) $(inat_tables_maps) 6$(OUTPUT)util/intel-pt-decoder/inat-tables.c: $(inat_tables_script) $(inat_tables_maps)
7 $(call rule_mkdir) 7 $(call rule_mkdir)
@@ -10,22 +10,6 @@ $(OUTPUT)util/intel-pt-decoder/inat-tables.c: $(inat_tables_script) $(inat_table
10# Busybox's diff doesn't have -I, avoid warning in the case 10# Busybox's diff doesn't have -I, avoid warning in the case
11 11
12$(OUTPUT)util/intel-pt-decoder/intel-pt-insn-decoder.o: util/intel-pt-decoder/intel-pt-insn-decoder.c $(OUTPUT)util/intel-pt-decoder/inat-tables.c 12$(OUTPUT)util/intel-pt-decoder/intel-pt-insn-decoder.o: util/intel-pt-decoder/intel-pt-insn-decoder.c $(OUTPUT)util/intel-pt-decoder/inat-tables.c
13 @(diff -I 2>&1 | grep -q 'option requires an argument' && \
14 test -d ../../kernel -a -d ../../tools -a -d ../perf && ( \
15 ((diff -B -I'^#include' util/intel-pt-decoder/insn.c ../../arch/x86/lib/insn.c >/dev/null) || \
16 (echo "Warning: Intel PT: x86 instruction decoder C file at 'tools/perf/util/intel-pt-decoder/insn.c' differs from latest version at 'arch/x86/lib/insn.c'" >&2)) && \
17 ((diff -B -I'^#include' util/intel-pt-decoder/inat.c ../../arch/x86/lib/inat.c >/dev/null) || \
18 (echo "Warning: Intel PT: x86 instruction decoder C file at 'tools/perf/util/intel-pt-decoder/inat.c' differs from latest version at 'arch/x86/lib/inat.c'" >&2)) && \
19 ((diff -B util/intel-pt-decoder/x86-opcode-map.txt ../../arch/x86/lib/x86-opcode-map.txt >/dev/null) || \
20 (echo "Warning: Intel PT: x86 instruction decoder map file at 'tools/perf/util/intel-pt-decoder/x86-opcode-map.txt' differs from latest version at 'arch/x86/lib/x86-opcode-map.txt'" >&2)) && \
21 ((diff -B util/intel-pt-decoder/gen-insn-attr-x86.awk ../../arch/x86/tools/gen-insn-attr-x86.awk >/dev/null) || \
22 (echo "Warning: Intel PT: x86 instruction decoder script at 'tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk' differs from latest version at 'arch/x86/tools/gen-insn-attr-x86.awk'" >&2)) && \
23 ((diff -B -I'^#include' util/intel-pt-decoder/insn.h ../../arch/x86/include/asm/insn.h >/dev/null) || \
24 (echo "Warning: Intel PT: x86 instruction decoder header at 'tools/perf/util/intel-pt-decoder/insn.h' differs from latest version at 'arch/x86/include/asm/insn.h'" >&2)) && \
25 ((diff -B -I'^#include' util/intel-pt-decoder/inat.h ../../arch/x86/include/asm/inat.h >/dev/null) || \
26 (echo "Warning: Intel PT: x86 instruction decoder header at 'tools/perf/util/intel-pt-decoder/inat.h' differs from latest version at 'arch/x86/include/asm/inat.h'" >&2)) && \
27 ((diff -B -I'^#include' util/intel-pt-decoder/inat_types.h ../../arch/x86/include/asm/inat_types.h >/dev/null) || \
28 (echo "Warning: Intel PT: x86 instruction decoder header at 'tools/perf/util/intel-pt-decoder/inat_types.h' differs from latest version at 'arch/x86/include/asm/inat_types.h'" >&2)))) || true
29 $(call rule_mkdir) 13 $(call rule_mkdir)
30 $(call if_changed_dep,cc_o_c) 14 $(call if_changed_dep,cc_o_c)
31 15
diff --git a/tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk b/tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk
deleted file mode 100644
index ddd5c4c21129..000000000000
--- a/tools/perf/util/intel-pt-decoder/gen-insn-attr-x86.awk
+++ /dev/null
@@ -1,392 +0,0 @@
1#!/bin/awk -f
2# SPDX-License-Identifier: GPL-2.0
3# gen-insn-attr-x86.awk: Instruction attribute table generator
4# Written by Masami Hiramatsu <mhiramat@redhat.com>
5#
6# Usage: awk -f gen-insn-attr-x86.awk x86-opcode-map.txt > inat-tables.c
7
8# Awk implementation sanity check
9function check_awk_implement() {
10 if (sprintf("%x", 0) != "0")
11 return "Your awk has a printf-format problem."
12 return ""
13}
14
15# Clear working vars
16function clear_vars() {
17 delete table
18 delete lptable2
19 delete lptable1
20 delete lptable3
21 eid = -1 # escape id
22 gid = -1 # group id
23 aid = -1 # AVX id
24 tname = ""
25}
26
27BEGIN {
28 # Implementation error checking
29 awkchecked = check_awk_implement()
30 if (awkchecked != "") {
31 print "Error: " awkchecked > "/dev/stderr"
32 print "Please try to use gawk." > "/dev/stderr"
33 exit 1
34 }
35
36 # Setup generating tables
37 print "/* x86 opcode map generated from x86-opcode-map.txt */"
38 print "/* Do not change this code. */\n"
39 ggid = 1
40 geid = 1
41 gaid = 0
42 delete etable
43 delete gtable
44 delete atable
45
46 opnd_expr = "^[A-Za-z/]"
47 ext_expr = "^\\("
48 sep_expr = "^\\|$"
49 group_expr = "^Grp[0-9A-Za-z]+"
50
51 imm_expr = "^[IJAOL][a-z]"
52 imm_flag["Ib"] = "INAT_MAKE_IMM(INAT_IMM_BYTE)"
53 imm_flag["Jb"] = "INAT_MAKE_IMM(INAT_IMM_BYTE)"
54 imm_flag["Iw"] = "INAT_MAKE_IMM(INAT_IMM_WORD)"
55 imm_flag["Id"] = "INAT_MAKE_IMM(INAT_IMM_DWORD)"
56 imm_flag["Iq"] = "INAT_MAKE_IMM(INAT_IMM_QWORD)"
57 imm_flag["Ap"] = "INAT_MAKE_IMM(INAT_IMM_PTR)"
58 imm_flag["Iz"] = "INAT_MAKE_IMM(INAT_IMM_VWORD32)"
59 imm_flag["Jz"] = "INAT_MAKE_IMM(INAT_IMM_VWORD32)"
60 imm_flag["Iv"] = "INAT_MAKE_IMM(INAT_IMM_VWORD)"
61 imm_flag["Ob"] = "INAT_MOFFSET"
62 imm_flag["Ov"] = "INAT_MOFFSET"
63 imm_flag["Lx"] = "INAT_MAKE_IMM(INAT_IMM_BYTE)"
64
65 modrm_expr = "^([CDEGMNPQRSUVW/][a-z]+|NTA|T[012])"
66 force64_expr = "\\([df]64\\)"
67 rex_expr = "^REX(\\.[XRWB]+)*"
68 fpu_expr = "^ESC" # TODO
69
70 lprefix1_expr = "\\((66|!F3)\\)"
71 lprefix2_expr = "\\(F3\\)"
72 lprefix3_expr = "\\((F2|!F3|66\\&F2)\\)"
73 lprefix_expr = "\\((66|F2|F3)\\)"
74 max_lprefix = 4
75
76 # All opcodes starting with lower-case 'v', 'k' or with (v1) superscript
77 # accepts VEX prefix
78 vexok_opcode_expr = "^[vk].*"
79 vexok_expr = "\\(v1\\)"
80 # All opcodes with (v) superscript supports *only* VEX prefix
81 vexonly_expr = "\\(v\\)"
82 # All opcodes with (ev) superscript supports *only* EVEX prefix
83 evexonly_expr = "\\(ev\\)"
84
85 prefix_expr = "\\(Prefix\\)"
86 prefix_num["Operand-Size"] = "INAT_PFX_OPNDSZ"
87 prefix_num["REPNE"] = "INAT_PFX_REPNE"
88 prefix_num["REP/REPE"] = "INAT_PFX_REPE"
89 prefix_num["XACQUIRE"] = "INAT_PFX_REPNE"
90 prefix_num["XRELEASE"] = "INAT_PFX_REPE"
91 prefix_num["LOCK"] = "INAT_PFX_LOCK"
92 prefix_num["SEG=CS"] = "INAT_PFX_CS"
93 prefix_num["SEG=DS"] = "INAT_PFX_DS"
94 prefix_num["SEG=ES"] = "INAT_PFX_ES"
95 prefix_num["SEG=FS"] = "INAT_PFX_FS"
96 prefix_num["SEG=GS"] = "INAT_PFX_GS"
97 prefix_num["SEG=SS"] = "INAT_PFX_SS"
98 prefix_num["Address-Size"] = "INAT_PFX_ADDRSZ"
99 prefix_num["VEX+1byte"] = "INAT_PFX_VEX2"
100 prefix_num["VEX+2byte"] = "INAT_PFX_VEX3"
101 prefix_num["EVEX"] = "INAT_PFX_EVEX"
102
103 clear_vars()
104}
105
106function semantic_error(msg) {
107 print "Semantic error at " NR ": " msg > "/dev/stderr"
108 exit 1
109}
110
111function debug(msg) {
112 print "DEBUG: " msg
113}
114
115function array_size(arr, i,c) {
116 c = 0
117 for (i in arr)
118 c++
119 return c
120}
121
122/^Table:/ {
123 print "/* " $0 " */"
124 if (tname != "")
125 semantic_error("Hit Table: before EndTable:.");
126}
127
128/^Referrer:/ {
129 if (NF != 1) {
130 # escape opcode table
131 ref = ""
132 for (i = 2; i <= NF; i++)
133 ref = ref $i
134 eid = escape[ref]
135 tname = sprintf("inat_escape_table_%d", eid)
136 }
137}
138
139/^AVXcode:/ {
140 if (NF != 1) {
141 # AVX/escape opcode table
142 aid = $2
143 if (gaid <= aid)
144 gaid = aid + 1
145 if (tname == "") # AVX only opcode table
146 tname = sprintf("inat_avx_table_%d", $2)
147 }
148 if (aid == -1 && eid == -1) # primary opcode table
149 tname = "inat_primary_table"
150}
151
152/^GrpTable:/ {
153 print "/* " $0 " */"
154 if (!($2 in group))
155 semantic_error("No group: " $2 )
156 gid = group[$2]
157 tname = "inat_group_table_" gid
158}
159
160function print_table(tbl,name,fmt,n)
161{
162 print "const insn_attr_t " name " = {"
163 for (i = 0; i < n; i++) {
164 id = sprintf(fmt, i)
165 if (tbl[id])
166 print " [" id "] = " tbl[id] ","
167 }
168 print "};"
169}
170
171/^EndTable/ {
172 if (gid != -1) {
173 # print group tables
174 if (array_size(table) != 0) {
175 print_table(table, tname "[INAT_GROUP_TABLE_SIZE]",
176 "0x%x", 8)
177 gtable[gid,0] = tname
178 }
179 if (array_size(lptable1) != 0) {
180 print_table(lptable1, tname "_1[INAT_GROUP_TABLE_SIZE]",
181 "0x%x", 8)
182 gtable[gid,1] = tname "_1"
183 }
184 if (array_size(lptable2) != 0) {
185 print_table(lptable2, tname "_2[INAT_GROUP_TABLE_SIZE]",
186 "0x%x", 8)
187 gtable[gid,2] = tname "_2"
188 }
189 if (array_size(lptable3) != 0) {
190 print_table(lptable3, tname "_3[INAT_GROUP_TABLE_SIZE]",
191 "0x%x", 8)
192 gtable[gid,3] = tname "_3"
193 }
194 } else {
195 # print primary/escaped tables
196 if (array_size(table) != 0) {
197 print_table(table, tname "[INAT_OPCODE_TABLE_SIZE]",
198 "0x%02x", 256)
199 etable[eid,0] = tname
200 if (aid >= 0)
201 atable[aid,0] = tname
202 }
203 if (array_size(lptable1) != 0) {
204 print_table(lptable1,tname "_1[INAT_OPCODE_TABLE_SIZE]",
205 "0x%02x", 256)
206 etable[eid,1] = tname "_1"
207 if (aid >= 0)
208 atable[aid,1] = tname "_1"
209 }
210 if (array_size(lptable2) != 0) {
211 print_table(lptable2,tname "_2[INAT_OPCODE_TABLE_SIZE]",
212 "0x%02x", 256)
213 etable[eid,2] = tname "_2"
214 if (aid >= 0)
215 atable[aid,2] = tname "_2"
216 }
217 if (array_size(lptable3) != 0) {
218 print_table(lptable3,tname "_3[INAT_OPCODE_TABLE_SIZE]",
219 "0x%02x", 256)
220 etable[eid,3] = tname "_3"
221 if (aid >= 0)
222 atable[aid,3] = tname "_3"
223 }
224 }
225 print ""
226 clear_vars()
227}
228
229function add_flags(old,new) {
230 if (old && new)
231 return old " | " new
232 else if (old)
233 return old
234 else
235 return new
236}
237
238# convert operands to flags.
239function convert_operands(count,opnd, i,j,imm,mod)
240{
241 imm = null
242 mod = null
243 for (j = 1; j <= count; j++) {
244 i = opnd[j]
245 if (match(i, imm_expr) == 1) {
246 if (!imm_flag[i])
247 semantic_error("Unknown imm opnd: " i)
248 if (imm) {
249 if (i != "Ib")
250 semantic_error("Second IMM error")
251 imm = add_flags(imm, "INAT_SCNDIMM")
252 } else
253 imm = imm_flag[i]
254 } else if (match(i, modrm_expr))
255 mod = "INAT_MODRM"
256 }
257 return add_flags(imm, mod)
258}
259
260/^[0-9a-f]+\:/ {
261 if (NR == 1)
262 next
263 # get index
264 idx = "0x" substr($1, 1, index($1,":") - 1)
265 if (idx in table)
266 semantic_error("Redefine " idx " in " tname)
267
268 # check if escaped opcode
269 if ("escape" == $2) {
270 if ($3 != "#")
271 semantic_error("No escaped name")
272 ref = ""
273 for (i = 4; i <= NF; i++)
274 ref = ref $i
275 if (ref in escape)
276 semantic_error("Redefine escape (" ref ")")
277 escape[ref] = geid
278 geid++
279 table[idx] = "INAT_MAKE_ESCAPE(" escape[ref] ")"
280 next
281 }
282
283 variant = null
284 # converts
285 i = 2
286 while (i <= NF) {
287 opcode = $(i++)
288 delete opnds
289 ext = null
290 flags = null
291 opnd = null
292 # parse one opcode
293 if (match($i, opnd_expr)) {
294 opnd = $i
295 count = split($(i++), opnds, ",")
296 flags = convert_operands(count, opnds)
297 }
298 if (match($i, ext_expr))
299 ext = $(i++)
300 if (match($i, sep_expr))
301 i++
302 else if (i < NF)
303 semantic_error($i " is not a separator")
304
305 # check if group opcode
306 if (match(opcode, group_expr)) {
307 if (!(opcode in group)) {
308 group[opcode] = ggid
309 ggid++
310 }
311 flags = add_flags(flags, "INAT_MAKE_GROUP(" group[opcode] ")")
312 }
313 # check force(or default) 64bit
314 if (match(ext, force64_expr))
315 flags = add_flags(flags, "INAT_FORCE64")
316
317 # check REX prefix
318 if (match(opcode, rex_expr))
319 flags = add_flags(flags, "INAT_MAKE_PREFIX(INAT_PFX_REX)")
320
321 # check coprocessor escape : TODO
322 if (match(opcode, fpu_expr))
323 flags = add_flags(flags, "INAT_MODRM")
324
325 # check VEX codes
326 if (match(ext, evexonly_expr))
327 flags = add_flags(flags, "INAT_VEXOK | INAT_EVEXONLY")
328 else if (match(ext, vexonly_expr))
329 flags = add_flags(flags, "INAT_VEXOK | INAT_VEXONLY")
330 else if (match(ext, vexok_expr) || match(opcode, vexok_opcode_expr))
331 flags = add_flags(flags, "INAT_VEXOK")
332
333 # check prefixes
334 if (match(ext, prefix_expr)) {
335 if (!prefix_num[opcode])
336 semantic_error("Unknown prefix: " opcode)
337 flags = add_flags(flags, "INAT_MAKE_PREFIX(" prefix_num[opcode] ")")
338 }
339 if (length(flags) == 0)
340 continue
341 # check if last prefix
342 if (match(ext, lprefix1_expr)) {
343 lptable1[idx] = add_flags(lptable1[idx],flags)
344 variant = "INAT_VARIANT"
345 }
346 if (match(ext, lprefix2_expr)) {
347 lptable2[idx] = add_flags(lptable2[idx],flags)
348 variant = "INAT_VARIANT"
349 }
350 if (match(ext, lprefix3_expr)) {
351 lptable3[idx] = add_flags(lptable3[idx],flags)
352 variant = "INAT_VARIANT"
353 }
354 if (!match(ext, lprefix_expr)){
355 table[idx] = add_flags(table[idx],flags)
356 }
357 }
358 if (variant)
359 table[idx] = add_flags(table[idx],variant)
360}
361
362END {
363 if (awkchecked != "")
364 exit 1
365 # print escape opcode map's array
366 print "/* Escape opcode map array */"
367 print "const insn_attr_t * const inat_escape_tables[INAT_ESC_MAX + 1]" \
368 "[INAT_LSTPFX_MAX + 1] = {"
369 for (i = 0; i < geid; i++)
370 for (j = 0; j < max_lprefix; j++)
371 if (etable[i,j])
372 print " ["i"]["j"] = "etable[i,j]","
373 print "};\n"
374 # print group opcode map's array
375 print "/* Group opcode map array */"
376 print "const insn_attr_t * const inat_group_tables[INAT_GRP_MAX + 1]"\
377 "[INAT_LSTPFX_MAX + 1] = {"
378 for (i = 0; i < ggid; i++)
379 for (j = 0; j < max_lprefix; j++)
380 if (gtable[i,j])
381 print " ["i"]["j"] = "gtable[i,j]","
382 print "};\n"
383 # print AVX opcode map's array
384 print "/* AVX opcode map array */"
385 print "const insn_attr_t * const inat_avx_tables[X86_VEX_M_MAX + 1]"\
386 "[INAT_LSTPFX_MAX + 1] = {"
387 for (i = 0; i < gaid; i++)
388 for (j = 0; j < max_lprefix; j++)
389 if (atable[i,j])
390 print " ["i"]["j"] = "atable[i,j]","
391 print "};"
392}
diff --git a/tools/perf/util/intel-pt-decoder/inat.c b/tools/perf/util/intel-pt-decoder/inat.c
deleted file mode 100644
index 446c0413a27c..000000000000
--- a/tools/perf/util/intel-pt-decoder/inat.c
+++ /dev/null
@@ -1,82 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * x86 instruction attribute tables
4 *
5 * Written by Masami Hiramatsu <mhiramat@redhat.com>
6 */
7#include "insn.h"
8
9/* Attribute tables are generated from opcode map */
10#include "inat-tables.c"
11
12/* Attribute search APIs */
13insn_attr_t inat_get_opcode_attribute(insn_byte_t opcode)
14{
15 return inat_primary_table[opcode];
16}
17
18int inat_get_last_prefix_id(insn_byte_t last_pfx)
19{
20 insn_attr_t lpfx_attr;
21
22 lpfx_attr = inat_get_opcode_attribute(last_pfx);
23 return inat_last_prefix_id(lpfx_attr);
24}
25
26insn_attr_t inat_get_escape_attribute(insn_byte_t opcode, int lpfx_id,
27 insn_attr_t esc_attr)
28{
29 const insn_attr_t *table;
30 int n;
31
32 n = inat_escape_id(esc_attr);
33
34 table = inat_escape_tables[n][0];
35 if (!table)
36 return 0;
37 if (inat_has_variant(table[opcode]) && lpfx_id) {
38 table = inat_escape_tables[n][lpfx_id];
39 if (!table)
40 return 0;
41 }
42 return table[opcode];
43}
44
45insn_attr_t inat_get_group_attribute(insn_byte_t modrm, int lpfx_id,
46 insn_attr_t grp_attr)
47{
48 const insn_attr_t *table;
49 int n;
50
51 n = inat_group_id(grp_attr);
52
53 table = inat_group_tables[n][0];
54 if (!table)
55 return inat_group_common_attribute(grp_attr);
56 if (inat_has_variant(table[X86_MODRM_REG(modrm)]) && lpfx_id) {
57 table = inat_group_tables[n][lpfx_id];
58 if (!table)
59 return inat_group_common_attribute(grp_attr);
60 }
61 return table[X86_MODRM_REG(modrm)] |
62 inat_group_common_attribute(grp_attr);
63}
64
65insn_attr_t inat_get_avx_attribute(insn_byte_t opcode, insn_byte_t vex_m,
66 insn_byte_t vex_p)
67{
68 const insn_attr_t *table;
69 if (vex_m > X86_VEX_M_MAX || vex_p > INAT_LSTPFX_MAX)
70 return 0;
71 /* At first, this checks the master table */
72 table = inat_avx_tables[vex_m][0];
73 if (!table)
74 return 0;
75 if (!inat_is_group(table[opcode]) && vex_p) {
76 /* If this is not a group, get attribute directly */
77 table = inat_avx_tables[vex_m][vex_p];
78 if (!table)
79 return 0;
80 }
81 return table[opcode];
82}
diff --git a/tools/perf/util/intel-pt-decoder/inat.h b/tools/perf/util/intel-pt-decoder/inat.h
deleted file mode 100644
index 877827b7c2c3..000000000000
--- a/tools/perf/util/intel-pt-decoder/inat.h
+++ /dev/null
@@ -1,230 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2#ifndef _ASM_X86_INAT_H
3#define _ASM_X86_INAT_H
4/*
5 * x86 instruction attributes
6 *
7 * Written by Masami Hiramatsu <mhiramat@redhat.com>
8 */
9#include "inat_types.h"
10
11/*
12 * Internal bits. Don't use bitmasks directly, because these bits are
13 * unstable. You should use checking functions.
14 */
15
16#define INAT_OPCODE_TABLE_SIZE 256
17#define INAT_GROUP_TABLE_SIZE 8
18
19/* Legacy last prefixes */
20#define INAT_PFX_OPNDSZ 1 /* 0x66 */ /* LPFX1 */
21#define INAT_PFX_REPE 2 /* 0xF3 */ /* LPFX2 */
22#define INAT_PFX_REPNE 3 /* 0xF2 */ /* LPFX3 */
23/* Other Legacy prefixes */
24#define INAT_PFX_LOCK 4 /* 0xF0 */
25#define INAT_PFX_CS 5 /* 0x2E */
26#define INAT_PFX_DS 6 /* 0x3E */
27#define INAT_PFX_ES 7 /* 0x26 */
28#define INAT_PFX_FS 8 /* 0x64 */
29#define INAT_PFX_GS 9 /* 0x65 */
30#define INAT_PFX_SS 10 /* 0x36 */
31#define INAT_PFX_ADDRSZ 11 /* 0x67 */
32/* x86-64 REX prefix */
33#define INAT_PFX_REX 12 /* 0x4X */
34/* AVX VEX prefixes */
35#define INAT_PFX_VEX2 13 /* 2-bytes VEX prefix */
36#define INAT_PFX_VEX3 14 /* 3-bytes VEX prefix */
37#define INAT_PFX_EVEX 15 /* EVEX prefix */
38
39#define INAT_LSTPFX_MAX 3
40#define INAT_LGCPFX_MAX 11
41
42/* Immediate size */
43#define INAT_IMM_BYTE 1
44#define INAT_IMM_WORD 2
45#define INAT_IMM_DWORD 3
46#define INAT_IMM_QWORD 4
47#define INAT_IMM_PTR 5
48#define INAT_IMM_VWORD32 6
49#define INAT_IMM_VWORD 7
50
51/* Legacy prefix */
52#define INAT_PFX_OFFS 0
53#define INAT_PFX_BITS 4
54#define INAT_PFX_MAX ((1 << INAT_PFX_BITS) - 1)
55#define INAT_PFX_MASK (INAT_PFX_MAX << INAT_PFX_OFFS)
56/* Escape opcodes */
57#define INAT_ESC_OFFS (INAT_PFX_OFFS + INAT_PFX_BITS)
58#define INAT_ESC_BITS 2
59#define INAT_ESC_MAX ((1 << INAT_ESC_BITS) - 1)
60#define INAT_ESC_MASK (INAT_ESC_MAX << INAT_ESC_OFFS)
61/* Group opcodes (1-16) */
62#define INAT_GRP_OFFS (INAT_ESC_OFFS + INAT_ESC_BITS)
63#define INAT_GRP_BITS 5
64#define INAT_GRP_MAX ((1 << INAT_GRP_BITS) - 1)
65#define INAT_GRP_MASK (INAT_GRP_MAX << INAT_GRP_OFFS)
66/* Immediates */
67#define INAT_IMM_OFFS (INAT_GRP_OFFS + INAT_GRP_BITS)
68#define INAT_IMM_BITS 3
69#define INAT_IMM_MASK (((1 << INAT_IMM_BITS) - 1) << INAT_IMM_OFFS)
70/* Flags */
71#define INAT_FLAG_OFFS (INAT_IMM_OFFS + INAT_IMM_BITS)
72#define INAT_MODRM (1 << (INAT_FLAG_OFFS))
73#define INAT_FORCE64 (1 << (INAT_FLAG_OFFS + 1))
74#define INAT_SCNDIMM (1 << (INAT_FLAG_OFFS + 2))
75#define INAT_MOFFSET (1 << (INAT_FLAG_OFFS + 3))
76#define INAT_VARIANT (1 << (INAT_FLAG_OFFS + 4))
77#define INAT_VEXOK (1 << (INAT_FLAG_OFFS + 5))
78#define INAT_VEXONLY (1 << (INAT_FLAG_OFFS + 6))
79#define INAT_EVEXONLY (1 << (INAT_FLAG_OFFS + 7))
80/* Attribute making macros for attribute tables */
81#define INAT_MAKE_PREFIX(pfx) (pfx << INAT_PFX_OFFS)
82#define INAT_MAKE_ESCAPE(esc) (esc << INAT_ESC_OFFS)
83#define INAT_MAKE_GROUP(grp) ((grp << INAT_GRP_OFFS) | INAT_MODRM)
84#define INAT_MAKE_IMM(imm) (imm << INAT_IMM_OFFS)
85
86/* Identifiers for segment registers */
87#define INAT_SEG_REG_IGNORE 0
88#define INAT_SEG_REG_DEFAULT 1
89#define INAT_SEG_REG_CS 2
90#define INAT_SEG_REG_SS 3
91#define INAT_SEG_REG_DS 4
92#define INAT_SEG_REG_ES 5
93#define INAT_SEG_REG_FS 6
94#define INAT_SEG_REG_GS 7
95
96/* Attribute search APIs */
97extern insn_attr_t inat_get_opcode_attribute(insn_byte_t opcode);
98extern int inat_get_last_prefix_id(insn_byte_t last_pfx);
99extern insn_attr_t inat_get_escape_attribute(insn_byte_t opcode,
100 int lpfx_id,
101 insn_attr_t esc_attr);
102extern insn_attr_t inat_get_group_attribute(insn_byte_t modrm,
103 int lpfx_id,
104 insn_attr_t esc_attr);
105extern insn_attr_t inat_get_avx_attribute(insn_byte_t opcode,
106 insn_byte_t vex_m,
107 insn_byte_t vex_pp);
108
109/* Attribute checking functions */
110static inline int inat_is_legacy_prefix(insn_attr_t attr)
111{
112 attr &= INAT_PFX_MASK;
113 return attr && attr <= INAT_LGCPFX_MAX;
114}
115
116static inline int inat_is_address_size_prefix(insn_attr_t attr)
117{
118 return (attr & INAT_PFX_MASK) == INAT_PFX_ADDRSZ;
119}
120
121static inline int inat_is_operand_size_prefix(insn_attr_t attr)
122{
123 return (attr & INAT_PFX_MASK) == INAT_PFX_OPNDSZ;
124}
125
126static inline int inat_is_rex_prefix(insn_attr_t attr)
127{
128 return (attr & INAT_PFX_MASK) == INAT_PFX_REX;
129}
130
131static inline int inat_last_prefix_id(insn_attr_t attr)
132{
133 if ((attr & INAT_PFX_MASK) > INAT_LSTPFX_MAX)
134 return 0;
135 else
136 return attr & INAT_PFX_MASK;
137}
138
139static inline int inat_is_vex_prefix(insn_attr_t attr)
140{
141 attr &= INAT_PFX_MASK;
142 return attr == INAT_PFX_VEX2 || attr == INAT_PFX_VEX3 ||
143 attr == INAT_PFX_EVEX;
144}
145
146static inline int inat_is_evex_prefix(insn_attr_t attr)
147{
148 return (attr & INAT_PFX_MASK) == INAT_PFX_EVEX;
149}
150
151static inline int inat_is_vex3_prefix(insn_attr_t attr)
152{
153 return (attr & INAT_PFX_MASK) == INAT_PFX_VEX3;
154}
155
156static inline int inat_is_escape(insn_attr_t attr)
157{
158 return attr & INAT_ESC_MASK;
159}
160
161static inline int inat_escape_id(insn_attr_t attr)
162{
163 return (attr & INAT_ESC_MASK) >> INAT_ESC_OFFS;
164}
165
166static inline int inat_is_group(insn_attr_t attr)
167{
168 return attr & INAT_GRP_MASK;
169}
170
171static inline int inat_group_id(insn_attr_t attr)
172{
173 return (attr & INAT_GRP_MASK) >> INAT_GRP_OFFS;
174}
175
176static inline int inat_group_common_attribute(insn_attr_t attr)
177{
178 return attr & ~INAT_GRP_MASK;
179}
180
181static inline int inat_has_immediate(insn_attr_t attr)
182{
183 return attr & INAT_IMM_MASK;
184}
185
186static inline int inat_immediate_size(insn_attr_t attr)
187{
188 return (attr & INAT_IMM_MASK) >> INAT_IMM_OFFS;
189}
190
191static inline int inat_has_modrm(insn_attr_t attr)
192{
193 return attr & INAT_MODRM;
194}
195
196static inline int inat_is_force64(insn_attr_t attr)
197{
198 return attr & INAT_FORCE64;
199}
200
201static inline int inat_has_second_immediate(insn_attr_t attr)
202{
203 return attr & INAT_SCNDIMM;
204}
205
206static inline int inat_has_moffset(insn_attr_t attr)
207{
208 return attr & INAT_MOFFSET;
209}
210
211static inline int inat_has_variant(insn_attr_t attr)
212{
213 return attr & INAT_VARIANT;
214}
215
216static inline int inat_accept_vex(insn_attr_t attr)
217{
218 return attr & INAT_VEXOK;
219}
220
221static inline int inat_must_vex(insn_attr_t attr)
222{
223 return attr & (INAT_VEXONLY | INAT_EVEXONLY);
224}
225
226static inline int inat_must_evex(insn_attr_t attr)
227{
228 return attr & INAT_EVEXONLY;
229}
230#endif
diff --git a/tools/perf/util/intel-pt-decoder/inat_types.h b/tools/perf/util/intel-pt-decoder/inat_types.h
deleted file mode 100644
index b047efa9ddc2..000000000000
--- a/tools/perf/util/intel-pt-decoder/inat_types.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2#ifndef _ASM_X86_INAT_TYPES_H
3#define _ASM_X86_INAT_TYPES_H
4/*
5 * x86 instruction attributes
6 *
7 * Written by Masami Hiramatsu <mhiramat@redhat.com>
8 */
9
10/* Instruction attributes */
11typedef unsigned int insn_attr_t;
12typedef unsigned char insn_byte_t;
13typedef signed int insn_value_t;
14
15#endif
diff --git a/tools/perf/util/intel-pt-decoder/insn.c b/tools/perf/util/intel-pt-decoder/insn.c
deleted file mode 100644
index 82783bf43b74..000000000000
--- a/tools/perf/util/intel-pt-decoder/insn.c
+++ /dev/null
@@ -1,593 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * x86 instruction analysis
4 *
5 * Copyright (C) IBM Corporation, 2002, 2004, 2009
6 */
7
8#ifdef __KERNEL__
9#include <linux/string.h>
10#else
11#include <string.h>
12#endif
13#include "inat.h"
14#include "insn.h"
15
16/* Verify next sizeof(t) bytes can be on the same instruction */
17#define validate_next(t, insn, n) \
18 ((insn)->next_byte + sizeof(t) + n <= (insn)->end_kaddr)
19
20#define __get_next(t, insn) \
21 ({ t r = *(t*)insn->next_byte; insn->next_byte += sizeof(t); r; })
22
23#define __peek_nbyte_next(t, insn, n) \
24 ({ t r = *(t*)((insn)->next_byte + n); r; })
25
26#define get_next(t, insn) \
27 ({ if (unlikely(!validate_next(t, insn, 0))) goto err_out; __get_next(t, insn); })
28
29#define peek_nbyte_next(t, insn, n) \
30 ({ if (unlikely(!validate_next(t, insn, n))) goto err_out; __peek_nbyte_next(t, insn, n); })
31
32#define peek_next(t, insn) peek_nbyte_next(t, insn, 0)
33
34/**
35 * insn_init() - initialize struct insn
36 * @insn: &struct insn to be initialized
37 * @kaddr: address (in kernel memory) of instruction (or copy thereof)
38 * @x86_64: !0 for 64-bit kernel or 64-bit app
39 */
40void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64)
41{
42 /*
43 * Instructions longer than MAX_INSN_SIZE (15 bytes) are invalid
44 * even if the input buffer is long enough to hold them.
45 */
46 if (buf_len > MAX_INSN_SIZE)
47 buf_len = MAX_INSN_SIZE;
48
49 memset(insn, 0, sizeof(*insn));
50 insn->kaddr = kaddr;
51 insn->end_kaddr = kaddr + buf_len;
52 insn->next_byte = kaddr;
53 insn->x86_64 = x86_64 ? 1 : 0;
54 insn->opnd_bytes = 4;
55 if (x86_64)
56 insn->addr_bytes = 8;
57 else
58 insn->addr_bytes = 4;
59}
60
61/**
62 * insn_get_prefixes - scan x86 instruction prefix bytes
63 * @insn: &struct insn containing instruction
64 *
65 * Populates the @insn->prefixes bitmap, and updates @insn->next_byte
66 * to point to the (first) opcode. No effect if @insn->prefixes.got
67 * is already set.
68 */
69void insn_get_prefixes(struct insn *insn)
70{
71 struct insn_field *prefixes = &insn->prefixes;
72 insn_attr_t attr;
73 insn_byte_t b, lb;
74 int i, nb;
75
76 if (prefixes->got)
77 return;
78
79 nb = 0;
80 lb = 0;
81 b = peek_next(insn_byte_t, insn);
82 attr = inat_get_opcode_attribute(b);
83 while (inat_is_legacy_prefix(attr)) {
84 /* Skip if same prefix */
85 for (i = 0; i < nb; i++)
86 if (prefixes->bytes[i] == b)
87 goto found;
88 if (nb == 4)
89 /* Invalid instruction */
90 break;
91 prefixes->bytes[nb++] = b;
92 if (inat_is_address_size_prefix(attr)) {
93 /* address size switches 2/4 or 4/8 */
94 if (insn->x86_64)
95 insn->addr_bytes ^= 12;
96 else
97 insn->addr_bytes ^= 6;
98 } else if (inat_is_operand_size_prefix(attr)) {
99 /* oprand size switches 2/4 */
100 insn->opnd_bytes ^= 6;
101 }
102found:
103 prefixes->nbytes++;
104 insn->next_byte++;
105 lb = b;
106 b = peek_next(insn_byte_t, insn);
107 attr = inat_get_opcode_attribute(b);
108 }
109 /* Set the last prefix */
110 if (lb && lb != insn->prefixes.bytes[3]) {
111 if (unlikely(insn->prefixes.bytes[3])) {
112 /* Swap the last prefix */
113 b = insn->prefixes.bytes[3];
114 for (i = 0; i < nb; i++)
115 if (prefixes->bytes[i] == lb)
116 prefixes->bytes[i] = b;
117 }
118 insn->prefixes.bytes[3] = lb;
119 }
120
121 /* Decode REX prefix */
122 if (insn->x86_64) {
123 b = peek_next(insn_byte_t, insn);
124 attr = inat_get_opcode_attribute(b);
125 if (inat_is_rex_prefix(attr)) {
126 insn->rex_prefix.value = b;
127 insn->rex_prefix.nbytes = 1;
128 insn->next_byte++;
129 if (X86_REX_W(b))
130 /* REX.W overrides opnd_size */
131 insn->opnd_bytes = 8;
132 }
133 }
134 insn->rex_prefix.got = 1;
135
136 /* Decode VEX prefix */
137 b = peek_next(insn_byte_t, insn);
138 attr = inat_get_opcode_attribute(b);
139 if (inat_is_vex_prefix(attr)) {
140 insn_byte_t b2 = peek_nbyte_next(insn_byte_t, insn, 1);
141 if (!insn->x86_64) {
142 /*
143 * In 32-bits mode, if the [7:6] bits (mod bits of
144 * ModRM) on the second byte are not 11b, it is
145 * LDS or LES or BOUND.
146 */
147 if (X86_MODRM_MOD(b2) != 3)
148 goto vex_end;
149 }
150 insn->vex_prefix.bytes[0] = b;
151 insn->vex_prefix.bytes[1] = b2;
152 if (inat_is_evex_prefix(attr)) {
153 b2 = peek_nbyte_next(insn_byte_t, insn, 2);
154 insn->vex_prefix.bytes[2] = b2;
155 b2 = peek_nbyte_next(insn_byte_t, insn, 3);
156 insn->vex_prefix.bytes[3] = b2;
157 insn->vex_prefix.nbytes = 4;
158 insn->next_byte += 4;
159 if (insn->x86_64 && X86_VEX_W(b2))
160 /* VEX.W overrides opnd_size */
161 insn->opnd_bytes = 8;
162 } else if (inat_is_vex3_prefix(attr)) {
163 b2 = peek_nbyte_next(insn_byte_t, insn, 2);
164 insn->vex_prefix.bytes[2] = b2;
165 insn->vex_prefix.nbytes = 3;
166 insn->next_byte += 3;
167 if (insn->x86_64 && X86_VEX_W(b2))
168 /* VEX.W overrides opnd_size */
169 insn->opnd_bytes = 8;
170 } else {
171 /*
172 * For VEX2, fake VEX3-like byte#2.
173 * Makes it easier to decode vex.W, vex.vvvv,
174 * vex.L and vex.pp. Masking with 0x7f sets vex.W == 0.
175 */
176 insn->vex_prefix.bytes[2] = b2 & 0x7f;
177 insn->vex_prefix.nbytes = 2;
178 insn->next_byte += 2;
179 }
180 }
181vex_end:
182 insn->vex_prefix.got = 1;
183
184 prefixes->got = 1;
185
186err_out:
187 return;
188}
189
190/**
191 * insn_get_opcode - collect opcode(s)
192 * @insn: &struct insn containing instruction
193 *
194 * Populates @insn->opcode, updates @insn->next_byte to point past the
195 * opcode byte(s), and set @insn->attr (except for groups).
196 * If necessary, first collects any preceding (prefix) bytes.
197 * Sets @insn->opcode.value = opcode1. No effect if @insn->opcode.got
198 * is already 1.
199 */
200void insn_get_opcode(struct insn *insn)
201{
202 struct insn_field *opcode = &insn->opcode;
203 insn_byte_t op;
204 int pfx_id;
205 if (opcode->got)
206 return;
207 if (!insn->prefixes.got)
208 insn_get_prefixes(insn);
209
210 /* Get first opcode */
211 op = get_next(insn_byte_t, insn);
212 opcode->bytes[0] = op;
213 opcode->nbytes = 1;
214
215 /* Check if there is VEX prefix or not */
216 if (insn_is_avx(insn)) {
217 insn_byte_t m, p;
218 m = insn_vex_m_bits(insn);
219 p = insn_vex_p_bits(insn);
220 insn->attr = inat_get_avx_attribute(op, m, p);
221 if ((inat_must_evex(insn->attr) && !insn_is_evex(insn)) ||
222 (!inat_accept_vex(insn->attr) &&
223 !inat_is_group(insn->attr)))
224 insn->attr = 0; /* This instruction is bad */
225 goto end; /* VEX has only 1 byte for opcode */
226 }
227
228 insn->attr = inat_get_opcode_attribute(op);
229 while (inat_is_escape(insn->attr)) {
230 /* Get escaped opcode */
231 op = get_next(insn_byte_t, insn);
232 opcode->bytes[opcode->nbytes++] = op;
233 pfx_id = insn_last_prefix_id(insn);
234 insn->attr = inat_get_escape_attribute(op, pfx_id, insn->attr);
235 }
236 if (inat_must_vex(insn->attr))
237 insn->attr = 0; /* This instruction is bad */
238end:
239 opcode->got = 1;
240
241err_out:
242 return;
243}
244
245/**
246 * insn_get_modrm - collect ModRM byte, if any
247 * @insn: &struct insn containing instruction
248 *
249 * Populates @insn->modrm and updates @insn->next_byte to point past the
250 * ModRM byte, if any. If necessary, first collects the preceding bytes
251 * (prefixes and opcode(s)). No effect if @insn->modrm.got is already 1.
252 */
253void insn_get_modrm(struct insn *insn)
254{
255 struct insn_field *modrm = &insn->modrm;
256 insn_byte_t pfx_id, mod;
257 if (modrm->got)
258 return;
259 if (!insn->opcode.got)
260 insn_get_opcode(insn);
261
262 if (inat_has_modrm(insn->attr)) {
263 mod = get_next(insn_byte_t, insn);
264 modrm->value = mod;
265 modrm->nbytes = 1;
266 if (inat_is_group(insn->attr)) {
267 pfx_id = insn_last_prefix_id(insn);
268 insn->attr = inat_get_group_attribute(mod, pfx_id,
269 insn->attr);
270 if (insn_is_avx(insn) && !inat_accept_vex(insn->attr))
271 insn->attr = 0; /* This is bad */
272 }
273 }
274
275 if (insn->x86_64 && inat_is_force64(insn->attr))
276 insn->opnd_bytes = 8;
277 modrm->got = 1;
278
279err_out:
280 return;
281}
282
283
284/**
285 * insn_rip_relative() - Does instruction use RIP-relative addressing mode?
286 * @insn: &struct insn containing instruction
287 *
288 * If necessary, first collects the instruction up to and including the
289 * ModRM byte. No effect if @insn->x86_64 is 0.
290 */
291int insn_rip_relative(struct insn *insn)
292{
293 struct insn_field *modrm = &insn->modrm;
294
295 if (!insn->x86_64)
296 return 0;
297 if (!modrm->got)
298 insn_get_modrm(insn);
299 /*
300 * For rip-relative instructions, the mod field (top 2 bits)
301 * is zero and the r/m field (bottom 3 bits) is 0x5.
302 */
303 return (modrm->nbytes && (modrm->value & 0xc7) == 0x5);
304}
305
306/**
307 * insn_get_sib() - Get the SIB byte of instruction
308 * @insn: &struct insn containing instruction
309 *
310 * If necessary, first collects the instruction up to and including the
311 * ModRM byte.
312 */
313void insn_get_sib(struct insn *insn)
314{
315 insn_byte_t modrm;
316
317 if (insn->sib.got)
318 return;
319 if (!insn->modrm.got)
320 insn_get_modrm(insn);
321 if (insn->modrm.nbytes) {
322 modrm = (insn_byte_t)insn->modrm.value;
323 if (insn->addr_bytes != 2 &&
324 X86_MODRM_MOD(modrm) != 3 && X86_MODRM_RM(modrm) == 4) {
325 insn->sib.value = get_next(insn_byte_t, insn);
326 insn->sib.nbytes = 1;
327 }
328 }
329 insn->sib.got = 1;
330
331err_out:
332 return;
333}
334
335
336/**
337 * insn_get_displacement() - Get the displacement of instruction
338 * @insn: &struct insn containing instruction
339 *
340 * If necessary, first collects the instruction up to and including the
341 * SIB byte.
342 * Displacement value is sign-expanded.
343 */
344void insn_get_displacement(struct insn *insn)
345{
346 insn_byte_t mod, rm, base;
347
348 if (insn->displacement.got)
349 return;
350 if (!insn->sib.got)
351 insn_get_sib(insn);
352 if (insn->modrm.nbytes) {
353 /*
354 * Interpreting the modrm byte:
355 * mod = 00 - no displacement fields (exceptions below)
356 * mod = 01 - 1-byte displacement field
357 * mod = 10 - displacement field is 4 bytes, or 2 bytes if
358 * address size = 2 (0x67 prefix in 32-bit mode)
359 * mod = 11 - no memory operand
360 *
361 * If address size = 2...
362 * mod = 00, r/m = 110 - displacement field is 2 bytes
363 *
364 * If address size != 2...
365 * mod != 11, r/m = 100 - SIB byte exists
366 * mod = 00, SIB base = 101 - displacement field is 4 bytes
367 * mod = 00, r/m = 101 - rip-relative addressing, displacement
368 * field is 4 bytes
369 */
370 mod = X86_MODRM_MOD(insn->modrm.value);
371 rm = X86_MODRM_RM(insn->modrm.value);
372 base = X86_SIB_BASE(insn->sib.value);
373 if (mod == 3)
374 goto out;
375 if (mod == 1) {
376 insn->displacement.value = get_next(signed char, insn);
377 insn->displacement.nbytes = 1;
378 } else if (insn->addr_bytes == 2) {
379 if ((mod == 0 && rm == 6) || mod == 2) {
380 insn->displacement.value =
381 get_next(short, insn);
382 insn->displacement.nbytes = 2;
383 }
384 } else {
385 if ((mod == 0 && rm == 5) || mod == 2 ||
386 (mod == 0 && base == 5)) {
387 insn->displacement.value = get_next(int, insn);
388 insn->displacement.nbytes = 4;
389 }
390 }
391 }
392out:
393 insn->displacement.got = 1;
394
395err_out:
396 return;
397}
398
399/* Decode moffset16/32/64. Return 0 if failed */
400static int __get_moffset(struct insn *insn)
401{
402 switch (insn->addr_bytes) {
403 case 2:
404 insn->moffset1.value = get_next(short, insn);
405 insn->moffset1.nbytes = 2;
406 break;
407 case 4:
408 insn->moffset1.value = get_next(int, insn);
409 insn->moffset1.nbytes = 4;
410 break;
411 case 8:
412 insn->moffset1.value = get_next(int, insn);
413 insn->moffset1.nbytes = 4;
414 insn->moffset2.value = get_next(int, insn);
415 insn->moffset2.nbytes = 4;
416 break;
417 default: /* opnd_bytes must be modified manually */
418 goto err_out;
419 }
420 insn->moffset1.got = insn->moffset2.got = 1;
421
422 return 1;
423
424err_out:
425 return 0;
426}
427
428/* Decode imm v32(Iz). Return 0 if failed */
429static int __get_immv32(struct insn *insn)
430{
431 switch (insn->opnd_bytes) {
432 case 2:
433 insn->immediate.value = get_next(short, insn);
434 insn->immediate.nbytes = 2;
435 break;
436 case 4:
437 case 8:
438 insn->immediate.value = get_next(int, insn);
439 insn->immediate.nbytes = 4;
440 break;
441 default: /* opnd_bytes must be modified manually */
442 goto err_out;
443 }
444
445 return 1;
446
447err_out:
448 return 0;
449}
450
451/* Decode imm v64(Iv/Ov), Return 0 if failed */
452static int __get_immv(struct insn *insn)
453{
454 switch (insn->opnd_bytes) {
455 case 2:
456 insn->immediate1.value = get_next(short, insn);
457 insn->immediate1.nbytes = 2;
458 break;
459 case 4:
460 insn->immediate1.value = get_next(int, insn);
461 insn->immediate1.nbytes = 4;
462 break;
463 case 8:
464 insn->immediate1.value = get_next(int, insn);
465 insn->immediate1.nbytes = 4;
466 insn->immediate2.value = get_next(int, insn);
467 insn->immediate2.nbytes = 4;
468 break;
469 default: /* opnd_bytes must be modified manually */
470 goto err_out;
471 }
472 insn->immediate1.got = insn->immediate2.got = 1;
473
474 return 1;
475err_out:
476 return 0;
477}
478
479/* Decode ptr16:16/32(Ap) */
480static int __get_immptr(struct insn *insn)
481{
482 switch (insn->opnd_bytes) {
483 case 2:
484 insn->immediate1.value = get_next(short, insn);
485 insn->immediate1.nbytes = 2;
486 break;
487 case 4:
488 insn->immediate1.value = get_next(int, insn);
489 insn->immediate1.nbytes = 4;
490 break;
491 case 8:
492 /* ptr16:64 is not exist (no segment) */
493 return 0;
494 default: /* opnd_bytes must be modified manually */
495 goto err_out;
496 }
497 insn->immediate2.value = get_next(unsigned short, insn);
498 insn->immediate2.nbytes = 2;
499 insn->immediate1.got = insn->immediate2.got = 1;
500
501 return 1;
502err_out:
503 return 0;
504}
505
506/**
507 * insn_get_immediate() - Get the immediates of instruction
508 * @insn: &struct insn containing instruction
509 *
510 * If necessary, first collects the instruction up to and including the
511 * displacement bytes.
512 * Basically, most of immediates are sign-expanded. Unsigned-value can be
513 * get by bit masking with ((1 << (nbytes * 8)) - 1)
514 */
515void insn_get_immediate(struct insn *insn)
516{
517 if (insn->immediate.got)
518 return;
519 if (!insn->displacement.got)
520 insn_get_displacement(insn);
521
522 if (inat_has_moffset(insn->attr)) {
523 if (!__get_moffset(insn))
524 goto err_out;
525 goto done;
526 }
527
528 if (!inat_has_immediate(insn->attr))
529 /* no immediates */
530 goto done;
531
532 switch (inat_immediate_size(insn->attr)) {
533 case INAT_IMM_BYTE:
534 insn->immediate.value = get_next(signed char, insn);
535 insn->immediate.nbytes = 1;
536 break;
537 case INAT_IMM_WORD:
538 insn->immediate.value = get_next(short, insn);
539 insn->immediate.nbytes = 2;
540 break;
541 case INAT_IMM_DWORD:
542 insn->immediate.value = get_next(int, insn);
543 insn->immediate.nbytes = 4;
544 break;
545 case INAT_IMM_QWORD:
546 insn->immediate1.value = get_next(int, insn);
547 insn->immediate1.nbytes = 4;
548 insn->immediate2.value = get_next(int, insn);
549 insn->immediate2.nbytes = 4;
550 break;
551 case INAT_IMM_PTR:
552 if (!__get_immptr(insn))
553 goto err_out;
554 break;
555 case INAT_IMM_VWORD32:
556 if (!__get_immv32(insn))
557 goto err_out;
558 break;
559 case INAT_IMM_VWORD:
560 if (!__get_immv(insn))
561 goto err_out;
562 break;
563 default:
564 /* Here, insn must have an immediate, but failed */
565 goto err_out;
566 }
567 if (inat_has_second_immediate(insn->attr)) {
568 insn->immediate2.value = get_next(signed char, insn);
569 insn->immediate2.nbytes = 1;
570 }
571done:
572 insn->immediate.got = 1;
573
574err_out:
575 return;
576}
577
578/**
579 * insn_get_length() - Get the length of instruction
580 * @insn: &struct insn containing instruction
581 *
582 * If necessary, first collects the instruction up to and including the
583 * immediates bytes.
584 */
585void insn_get_length(struct insn *insn)
586{
587 if (insn->length)
588 return;
589 if (!insn->immediate.got)
590 insn_get_immediate(insn);
591 insn->length = (unsigned char)((unsigned long)insn->next_byte
592 - (unsigned long)insn->kaddr);
593}
diff --git a/tools/perf/util/intel-pt-decoder/insn.h b/tools/perf/util/intel-pt-decoder/insn.h
deleted file mode 100644
index 37a4c390750b..000000000000
--- a/tools/perf/util/intel-pt-decoder/insn.h
+++ /dev/null
@@ -1,216 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2#ifndef _ASM_X86_INSN_H
3#define _ASM_X86_INSN_H
4/*
5 * x86 instruction analysis
6 *
7 * Copyright (C) IBM Corporation, 2009
8 */
9
10/* insn_attr_t is defined in inat.h */
11#include "inat.h"
12
13struct insn_field {
14 union {
15 insn_value_t value;
16 insn_byte_t bytes[4];
17 };
18 /* !0 if we've run insn_get_xxx() for this field */
19 unsigned char got;
20 unsigned char nbytes;
21};
22
23struct insn {
24 struct insn_field prefixes; /*
25 * Prefixes
26 * prefixes.bytes[3]: last prefix
27 */
28 struct insn_field rex_prefix; /* REX prefix */
29 struct insn_field vex_prefix; /* VEX prefix */
30 struct insn_field opcode; /*
31 * opcode.bytes[0]: opcode1
32 * opcode.bytes[1]: opcode2
33 * opcode.bytes[2]: opcode3
34 */
35 struct insn_field modrm;
36 struct insn_field sib;
37 struct insn_field displacement;
38 union {
39 struct insn_field immediate;
40 struct insn_field moffset1; /* for 64bit MOV */
41 struct insn_field immediate1; /* for 64bit imm or off16/32 */
42 };
43 union {
44 struct insn_field moffset2; /* for 64bit MOV */
45 struct insn_field immediate2; /* for 64bit imm or seg16 */
46 };
47
48 insn_attr_t attr;
49 unsigned char opnd_bytes;
50 unsigned char addr_bytes;
51 unsigned char length;
52 unsigned char x86_64;
53
54 const insn_byte_t *kaddr; /* kernel address of insn to analyze */
55 const insn_byte_t *end_kaddr; /* kernel address of last insn in buffer */
56 const insn_byte_t *next_byte;
57};
58
59#define MAX_INSN_SIZE 15
60
61#define X86_MODRM_MOD(modrm) (((modrm) & 0xc0) >> 6)
62#define X86_MODRM_REG(modrm) (((modrm) & 0x38) >> 3)
63#define X86_MODRM_RM(modrm) ((modrm) & 0x07)
64
65#define X86_SIB_SCALE(sib) (((sib) & 0xc0) >> 6)
66#define X86_SIB_INDEX(sib) (((sib) & 0x38) >> 3)
67#define X86_SIB_BASE(sib) ((sib) & 0x07)
68
69#define X86_REX_W(rex) ((rex) & 8)
70#define X86_REX_R(rex) ((rex) & 4)
71#define X86_REX_X(rex) ((rex) & 2)
72#define X86_REX_B(rex) ((rex) & 1)
73
74/* VEX bit flags */
75#define X86_VEX_W(vex) ((vex) & 0x80) /* VEX3 Byte2 */
76#define X86_VEX_R(vex) ((vex) & 0x80) /* VEX2/3 Byte1 */
77#define X86_VEX_X(vex) ((vex) & 0x40) /* VEX3 Byte1 */
78#define X86_VEX_B(vex) ((vex) & 0x20) /* VEX3 Byte1 */
79#define X86_VEX_L(vex) ((vex) & 0x04) /* VEX3 Byte2, VEX2 Byte1 */
80/* VEX bit fields */
81#define X86_EVEX_M(vex) ((vex) & 0x03) /* EVEX Byte1 */
82#define X86_VEX3_M(vex) ((vex) & 0x1f) /* VEX3 Byte1 */
83#define X86_VEX2_M 1 /* VEX2.M always 1 */
84#define X86_VEX_V(vex) (((vex) & 0x78) >> 3) /* VEX3 Byte2, VEX2 Byte1 */
85#define X86_VEX_P(vex) ((vex) & 0x03) /* VEX3 Byte2, VEX2 Byte1 */
86#define X86_VEX_M_MAX 0x1f /* VEX3.M Maximum value */
87
88extern void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64);
89extern void insn_get_prefixes(struct insn *insn);
90extern void insn_get_opcode(struct insn *insn);
91extern void insn_get_modrm(struct insn *insn);
92extern void insn_get_sib(struct insn *insn);
93extern void insn_get_displacement(struct insn *insn);
94extern void insn_get_immediate(struct insn *insn);
95extern void insn_get_length(struct insn *insn);
96
97/* Attribute will be determined after getting ModRM (for opcode groups) */
98static inline void insn_get_attribute(struct insn *insn)
99{
100 insn_get_modrm(insn);
101}
102
103/* Instruction uses RIP-relative addressing */
104extern int insn_rip_relative(struct insn *insn);
105
106/* Init insn for kernel text */
107static inline void kernel_insn_init(struct insn *insn,
108 const void *kaddr, int buf_len)
109{
110#ifdef CONFIG_X86_64
111 insn_init(insn, kaddr, buf_len, 1);
112#else /* CONFIG_X86_32 */
113 insn_init(insn, kaddr, buf_len, 0);
114#endif
115}
116
117static inline int insn_is_avx(struct insn *insn)
118{
119 if (!insn->prefixes.got)
120 insn_get_prefixes(insn);
121 return (insn->vex_prefix.value != 0);
122}
123
124static inline int insn_is_evex(struct insn *insn)
125{
126 if (!insn->prefixes.got)
127 insn_get_prefixes(insn);
128 return (insn->vex_prefix.nbytes == 4);
129}
130
131/* Ensure this instruction is decoded completely */
132static inline int insn_complete(struct insn *insn)
133{
134 return insn->opcode.got && insn->modrm.got && insn->sib.got &&
135 insn->displacement.got && insn->immediate.got;
136}
137
138static inline insn_byte_t insn_vex_m_bits(struct insn *insn)
139{
140 if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */
141 return X86_VEX2_M;
142 else if (insn->vex_prefix.nbytes == 3) /* 3 bytes VEX */
143 return X86_VEX3_M(insn->vex_prefix.bytes[1]);
144 else /* EVEX */
145 return X86_EVEX_M(insn->vex_prefix.bytes[1]);
146}
147
148static inline insn_byte_t insn_vex_p_bits(struct insn *insn)
149{
150 if (insn->vex_prefix.nbytes == 2) /* 2 bytes VEX */
151 return X86_VEX_P(insn->vex_prefix.bytes[1]);
152 else
153 return X86_VEX_P(insn->vex_prefix.bytes[2]);
154}
155
156/* Get the last prefix id from last prefix or VEX prefix */
157static inline int insn_last_prefix_id(struct insn *insn)
158{
159 if (insn_is_avx(insn))
160 return insn_vex_p_bits(insn); /* VEX_p is a SIMD prefix id */
161
162 if (insn->prefixes.bytes[3])
163 return inat_get_last_prefix_id(insn->prefixes.bytes[3]);
164
165 return 0;
166}
167
168/* Offset of each field from kaddr */
169static inline int insn_offset_rex_prefix(struct insn *insn)
170{
171 return insn->prefixes.nbytes;
172}
173static inline int insn_offset_vex_prefix(struct insn *insn)
174{
175 return insn_offset_rex_prefix(insn) + insn->rex_prefix.nbytes;
176}
177static inline int insn_offset_opcode(struct insn *insn)
178{
179 return insn_offset_vex_prefix(insn) + insn->vex_prefix.nbytes;
180}
181static inline int insn_offset_modrm(struct insn *insn)
182{
183 return insn_offset_opcode(insn) + insn->opcode.nbytes;
184}
185static inline int insn_offset_sib(struct insn *insn)
186{
187 return insn_offset_modrm(insn) + insn->modrm.nbytes;
188}
189static inline int insn_offset_displacement(struct insn *insn)
190{
191 return insn_offset_sib(insn) + insn->sib.nbytes;
192}
193static inline int insn_offset_immediate(struct insn *insn)
194{
195 return insn_offset_displacement(insn) + insn->displacement.nbytes;
196}
197
198#define POP_SS_OPCODE 0x1f
199#define MOV_SREG_OPCODE 0x8e
200
201/*
202 * Intel SDM Vol.3A 6.8.3 states;
203 * "Any single-step trap that would be delivered following the MOV to SS
204 * instruction or POP to SS instruction (because EFLAGS.TF is 1) is
205 * suppressed."
206 * This function returns true if @insn is MOV SS or POP SS. On these
207 * instructions, single stepping is suppressed.
208 */
209static inline int insn_masking_exception(struct insn *insn)
210{
211 return insn->opcode.bytes[0] == POP_SS_OPCODE ||
212 (insn->opcode.bytes[0] == MOV_SREG_OPCODE &&
213 X86_MODRM_REG(insn->modrm.bytes[0]) == 2);
214}
215
216#endif /* _ASM_X86_INSN_H */
diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c
index 598f56be9f17..fb8a3558d3d5 100644
--- a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c
+++ b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c
@@ -4,17 +4,17 @@
4 * Copyright (c) 2013-2014, Intel Corporation. 4 * Copyright (c) 2013-2014, Intel Corporation.
5 */ 5 */
6 6
7#include <linux/kernel.h>
7#include <stdio.h> 8#include <stdio.h>
8#include <string.h> 9#include <string.h>
9#include <endian.h> 10#include <endian.h>
10#include <byteswap.h> 11#include <byteswap.h>
12#include "../../../arch/x86/include/asm/insn.h"
11 13
12#include "event.h" 14#include "../../../arch/x86/lib/inat.c"
13 15#include "../../../arch/x86/lib/insn.c"
14#include "insn.h"
15 16
16#include "inat.c" 17#include "event.h"
17#include "insn.c"
18 18
19#include "intel-pt-insn-decoder.h" 19#include "intel-pt-insn-decoder.h"
20#include "dump-insn.h" 20#include "dump-insn.h"
diff --git a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
deleted file mode 100644
index e0b85930dd77..000000000000
--- a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
+++ /dev/null
@@ -1,1072 +0,0 @@
1# x86 Opcode Maps
2#
3# This is (mostly) based on following documentations.
4# - Intel(R) 64 and IA-32 Architectures Software Developer's Manual Vol.2C
5# (#326018-047US, June 2013)
6#
7#<Opcode maps>
8# Table: table-name
9# Referrer: escaped-name
10# AVXcode: avx-code
11# opcode: mnemonic|GrpXXX [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
12# (or)
13# opcode: escape # escaped-name
14# EndTable
15#
16# mnemonics that begin with lowercase 'v' accept a VEX or EVEX prefix
17# mnemonics that begin with lowercase 'k' accept a VEX prefix
18#
19#<group maps>
20# GrpTable: GrpXXX
21# reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...]
22# EndTable
23#
24# AVX Superscripts
25# (ev): this opcode requires EVEX prefix.
26# (evo): this opcode is changed by EVEX prefix (EVEX opcode)
27# (v): this opcode requires VEX prefix.
28# (v1): this opcode only supports 128bit VEX.
29#
30# Last Prefix Superscripts
31# - (66): the last prefix is 0x66
32# - (F3): the last prefix is 0xF3
33# - (F2): the last prefix is 0xF2
34# - (!F3) : the last prefix is not 0xF3 (including non-last prefix case)
35# - (66&F2): Both 0x66 and 0xF2 prefixes are specified.
36
37Table: one byte opcode
38Referrer:
39AVXcode:
40# 0x00 - 0x0f
4100: ADD Eb,Gb
4201: ADD Ev,Gv
4302: ADD Gb,Eb
4403: ADD Gv,Ev
4504: ADD AL,Ib
4605: ADD rAX,Iz
4706: PUSH ES (i64)
4807: POP ES (i64)
4908: OR Eb,Gb
5009: OR Ev,Gv
510a: OR Gb,Eb
520b: OR Gv,Ev
530c: OR AL,Ib
540d: OR rAX,Iz
550e: PUSH CS (i64)
560f: escape # 2-byte escape
57# 0x10 - 0x1f
5810: ADC Eb,Gb
5911: ADC Ev,Gv
6012: ADC Gb,Eb
6113: ADC Gv,Ev
6214: ADC AL,Ib
6315: ADC rAX,Iz
6416: PUSH SS (i64)
6517: POP SS (i64)
6618: SBB Eb,Gb
6719: SBB Ev,Gv
681a: SBB Gb,Eb
691b: SBB Gv,Ev
701c: SBB AL,Ib
711d: SBB rAX,Iz
721e: PUSH DS (i64)
731f: POP DS (i64)
74# 0x20 - 0x2f
7520: AND Eb,Gb
7621: AND Ev,Gv
7722: AND Gb,Eb
7823: AND Gv,Ev
7924: AND AL,Ib
8025: AND rAx,Iz
8126: SEG=ES (Prefix)
8227: DAA (i64)
8328: SUB Eb,Gb
8429: SUB Ev,Gv
852a: SUB Gb,Eb
862b: SUB Gv,Ev
872c: SUB AL,Ib
882d: SUB rAX,Iz
892e: SEG=CS (Prefix)
902f: DAS (i64)
91# 0x30 - 0x3f
9230: XOR Eb,Gb
9331: XOR Ev,Gv
9432: XOR Gb,Eb
9533: XOR Gv,Ev
9634: XOR AL,Ib
9735: XOR rAX,Iz
9836: SEG=SS (Prefix)
9937: AAA (i64)
10038: CMP Eb,Gb
10139: CMP Ev,Gv
1023a: CMP Gb,Eb
1033b: CMP Gv,Ev
1043c: CMP AL,Ib
1053d: CMP rAX,Iz
1063e: SEG=DS (Prefix)
1073f: AAS (i64)
108# 0x40 - 0x4f
10940: INC eAX (i64) | REX (o64)
11041: INC eCX (i64) | REX.B (o64)
11142: INC eDX (i64) | REX.X (o64)
11243: INC eBX (i64) | REX.XB (o64)
11344: INC eSP (i64) | REX.R (o64)
11445: INC eBP (i64) | REX.RB (o64)
11546: INC eSI (i64) | REX.RX (o64)
11647: INC eDI (i64) | REX.RXB (o64)
11748: DEC eAX (i64) | REX.W (o64)
11849: DEC eCX (i64) | REX.WB (o64)
1194a: DEC eDX (i64) | REX.WX (o64)
1204b: DEC eBX (i64) | REX.WXB (o64)
1214c: DEC eSP (i64) | REX.WR (o64)
1224d: DEC eBP (i64) | REX.WRB (o64)
1234e: DEC eSI (i64) | REX.WRX (o64)
1244f: DEC eDI (i64) | REX.WRXB (o64)
125# 0x50 - 0x5f
12650: PUSH rAX/r8 (d64)
12751: PUSH rCX/r9 (d64)
12852: PUSH rDX/r10 (d64)
12953: PUSH rBX/r11 (d64)
13054: PUSH rSP/r12 (d64)
13155: PUSH rBP/r13 (d64)
13256: PUSH rSI/r14 (d64)
13357: PUSH rDI/r15 (d64)
13458: POP rAX/r8 (d64)
13559: POP rCX/r9 (d64)
1365a: POP rDX/r10 (d64)
1375b: POP rBX/r11 (d64)
1385c: POP rSP/r12 (d64)
1395d: POP rBP/r13 (d64)
1405e: POP rSI/r14 (d64)
1415f: POP rDI/r15 (d64)
142# 0x60 - 0x6f
14360: PUSHA/PUSHAD (i64)
14461: POPA/POPAD (i64)
14562: BOUND Gv,Ma (i64) | EVEX (Prefix)
14663: ARPL Ew,Gw (i64) | MOVSXD Gv,Ev (o64)
14764: SEG=FS (Prefix)
14865: SEG=GS (Prefix)
14966: Operand-Size (Prefix)
15067: Address-Size (Prefix)
15168: PUSH Iz (d64)
15269: IMUL Gv,Ev,Iz
1536a: PUSH Ib (d64)
1546b: IMUL Gv,Ev,Ib
1556c: INS/INSB Yb,DX
1566d: INS/INSW/INSD Yz,DX
1576e: OUTS/OUTSB DX,Xb
1586f: OUTS/OUTSW/OUTSD DX,Xz
159# 0x70 - 0x7f
16070: JO Jb
16171: JNO Jb
16272: JB/JNAE/JC Jb
16373: JNB/JAE/JNC Jb
16474: JZ/JE Jb
16575: JNZ/JNE Jb
16676: JBE/JNA Jb
16777: JNBE/JA Jb
16878: JS Jb
16979: JNS Jb
1707a: JP/JPE Jb
1717b: JNP/JPO Jb
1727c: JL/JNGE Jb
1737d: JNL/JGE Jb
1747e: JLE/JNG Jb
1757f: JNLE/JG Jb
176# 0x80 - 0x8f
17780: Grp1 Eb,Ib (1A)
17881: Grp1 Ev,Iz (1A)
17982: Grp1 Eb,Ib (1A),(i64)
18083: Grp1 Ev,Ib (1A)
18184: TEST Eb,Gb
18285: TEST Ev,Gv
18386: XCHG Eb,Gb
18487: XCHG Ev,Gv
18588: MOV Eb,Gb
18689: MOV Ev,Gv
1878a: MOV Gb,Eb
1888b: MOV Gv,Ev
1898c: MOV Ev,Sw
1908d: LEA Gv,M
1918e: MOV Sw,Ew
1928f: Grp1A (1A) | POP Ev (d64)
193# 0x90 - 0x9f
19490: NOP | PAUSE (F3) | XCHG r8,rAX
19591: XCHG rCX/r9,rAX
19692: XCHG rDX/r10,rAX
19793: XCHG rBX/r11,rAX
19894: XCHG rSP/r12,rAX
19995: XCHG rBP/r13,rAX
20096: XCHG rSI/r14,rAX
20197: XCHG rDI/r15,rAX
20298: CBW/CWDE/CDQE
20399: CWD/CDQ/CQO
2049a: CALLF Ap (i64)
2059b: FWAIT/WAIT
2069c: PUSHF/D/Q Fv (d64)
2079d: POPF/D/Q Fv (d64)
2089e: SAHF
2099f: LAHF
210# 0xa0 - 0xaf
211a0: MOV AL,Ob
212a1: MOV rAX,Ov
213a2: MOV Ob,AL
214a3: MOV Ov,rAX
215a4: MOVS/B Yb,Xb
216a5: MOVS/W/D/Q Yv,Xv
217a6: CMPS/B Xb,Yb
218a7: CMPS/W/D Xv,Yv
219a8: TEST AL,Ib
220a9: TEST rAX,Iz
221aa: STOS/B Yb,AL
222ab: STOS/W/D/Q Yv,rAX
223ac: LODS/B AL,Xb
224ad: LODS/W/D/Q rAX,Xv
225ae: SCAS/B AL,Yb
226# Note: The May 2011 Intel manual shows Xv for the second parameter of the
227# next instruction but Yv is correct
228af: SCAS/W/D/Q rAX,Yv
229# 0xb0 - 0xbf
230b0: MOV AL/R8L,Ib
231b1: MOV CL/R9L,Ib
232b2: MOV DL/R10L,Ib
233b3: MOV BL/R11L,Ib
234b4: MOV AH/R12L,Ib
235b5: MOV CH/R13L,Ib
236b6: MOV DH/R14L,Ib
237b7: MOV BH/R15L,Ib
238b8: MOV rAX/r8,Iv
239b9: MOV rCX/r9,Iv
240ba: MOV rDX/r10,Iv
241bb: MOV rBX/r11,Iv
242bc: MOV rSP/r12,Iv
243bd: MOV rBP/r13,Iv
244be: MOV rSI/r14,Iv
245bf: MOV rDI/r15,Iv
246# 0xc0 - 0xcf
247c0: Grp2 Eb,Ib (1A)
248c1: Grp2 Ev,Ib (1A)
249c2: RETN Iw (f64)
250c3: RETN
251c4: LES Gz,Mp (i64) | VEX+2byte (Prefix)
252c5: LDS Gz,Mp (i64) | VEX+1byte (Prefix)
253c6: Grp11A Eb,Ib (1A)
254c7: Grp11B Ev,Iz (1A)
255c8: ENTER Iw,Ib
256c9: LEAVE (d64)
257ca: RETF Iw
258cb: RETF
259cc: INT3
260cd: INT Ib
261ce: INTO (i64)
262cf: IRET/D/Q
263# 0xd0 - 0xdf
264d0: Grp2 Eb,1 (1A)
265d1: Grp2 Ev,1 (1A)
266d2: Grp2 Eb,CL (1A)
267d3: Grp2 Ev,CL (1A)
268d4: AAM Ib (i64)
269d5: AAD Ib (i64)
270d6:
271d7: XLAT/XLATB
272d8: ESC
273d9: ESC
274da: ESC
275db: ESC
276dc: ESC
277dd: ESC
278de: ESC
279df: ESC
280# 0xe0 - 0xef
281# Note: "forced64" is Intel CPU behavior: they ignore 0x66 prefix
282# in 64-bit mode. AMD CPUs accept 0x66 prefix, it causes RIP truncation
283# to 16 bits. In 32-bit mode, 0x66 is accepted by both Intel and AMD.
284e0: LOOPNE/LOOPNZ Jb (f64)
285e1: LOOPE/LOOPZ Jb (f64)
286e2: LOOP Jb (f64)
287e3: JrCXZ Jb (f64)
288e4: IN AL,Ib
289e5: IN eAX,Ib
290e6: OUT Ib,AL
291e7: OUT Ib,eAX
292# With 0x66 prefix in 64-bit mode, for AMD CPUs immediate offset
293# in "near" jumps and calls is 16-bit. For CALL,
294# push of return address is 16-bit wide, RSP is decremented by 2
295# but is not truncated to 16 bits, unlike RIP.
296e8: CALL Jz (f64)
297e9: JMP-near Jz (f64)
298ea: JMP-far Ap (i64)
299eb: JMP-short Jb (f64)
300ec: IN AL,DX
301ed: IN eAX,DX
302ee: OUT DX,AL
303ef: OUT DX,eAX
304# 0xf0 - 0xff
305f0: LOCK (Prefix)
306f1:
307f2: REPNE (Prefix) | XACQUIRE (Prefix)
308f3: REP/REPE (Prefix) | XRELEASE (Prefix)
309f4: HLT
310f5: CMC
311f6: Grp3_1 Eb (1A)
312f7: Grp3_2 Ev (1A)
313f8: CLC
314f9: STC
315fa: CLI
316fb: STI
317fc: CLD
318fd: STD
319fe: Grp4 (1A)
320ff: Grp5 (1A)
321EndTable
322
323Table: 2-byte opcode (0x0f)
324Referrer: 2-byte escape
325AVXcode: 1
326# 0x0f 0x00-0x0f
32700: Grp6 (1A)
32801: Grp7 (1A)
32902: LAR Gv,Ew
33003: LSL Gv,Ew
33104:
33205: SYSCALL (o64)
33306: CLTS
33407: SYSRET (o64)
33508: INVD
33609: WBINVD
3370a:
3380b: UD2 (1B)
3390c:
340# AMD's prefetch group. Intel supports prefetchw(/1) only.
3410d: GrpP
3420e: FEMMS
343# 3DNow! uses the last imm byte as opcode extension.
3440f: 3DNow! Pq,Qq,Ib
345# 0x0f 0x10-0x1f
346# NOTE: According to Intel SDM opcode map, vmovups and vmovupd has no operands
347# but it actually has operands. And also, vmovss and vmovsd only accept 128bit.
348# MOVSS/MOVSD has too many forms(3) on SDM. This map just shows a typical form.
349# Many AVX instructions lack v1 superscript, according to Intel AVX-Prgramming
350# Reference A.1
35110: vmovups Vps,Wps | vmovupd Vpd,Wpd (66) | vmovss Vx,Hx,Wss (F3),(v1) | vmovsd Vx,Hx,Wsd (F2),(v1)
35211: vmovups Wps,Vps | vmovupd Wpd,Vpd (66) | vmovss Wss,Hx,Vss (F3),(v1) | vmovsd Wsd,Hx,Vsd (F2),(v1)
35312: vmovlps Vq,Hq,Mq (v1) | vmovhlps Vq,Hq,Uq (v1) | vmovlpd Vq,Hq,Mq (66),(v1) | vmovsldup Vx,Wx (F3) | vmovddup Vx,Wx (F2)
35413: vmovlps Mq,Vq (v1) | vmovlpd Mq,Vq (66),(v1)
35514: vunpcklps Vx,Hx,Wx | vunpcklpd Vx,Hx,Wx (66)
35615: vunpckhps Vx,Hx,Wx | vunpckhpd Vx,Hx,Wx (66)
35716: vmovhps Vdq,Hq,Mq (v1) | vmovlhps Vdq,Hq,Uq (v1) | vmovhpd Vdq,Hq,Mq (66),(v1) | vmovshdup Vx,Wx (F3)
35817: vmovhps Mq,Vq (v1) | vmovhpd Mq,Vq (66),(v1)
35918: Grp16 (1A)
36019:
361# Intel SDM opcode map does not list MPX instructions. For now using Gv for
362# bnd registers and Ev for everything else is OK because the instruction
363# decoder does not use the information except as an indication that there is
364# a ModR/M byte.
3651a: BNDCL Gv,Ev (F3) | BNDCU Gv,Ev (F2) | BNDMOV Gv,Ev (66) | BNDLDX Gv,Ev
3661b: BNDCN Gv,Ev (F2) | BNDMOV Ev,Gv (66) | BNDMK Gv,Ev (F3) | BNDSTX Ev,Gv
3671c:
3681d:
3691e:
3701f: NOP Ev
371# 0x0f 0x20-0x2f
37220: MOV Rd,Cd
37321: MOV Rd,Dd
37422: MOV Cd,Rd
37523: MOV Dd,Rd
37624:
37725:
37826:
37927:
38028: vmovaps Vps,Wps | vmovapd Vpd,Wpd (66)
38129: vmovaps Wps,Vps | vmovapd Wpd,Vpd (66)
3822a: cvtpi2ps Vps,Qpi | cvtpi2pd Vpd,Qpi (66) | vcvtsi2ss Vss,Hss,Ey (F3),(v1) | vcvtsi2sd Vsd,Hsd,Ey (F2),(v1)
3832b: vmovntps Mps,Vps | vmovntpd Mpd,Vpd (66)
3842c: cvttps2pi Ppi,Wps | cvttpd2pi Ppi,Wpd (66) | vcvttss2si Gy,Wss (F3),(v1) | vcvttsd2si Gy,Wsd (F2),(v1)
3852d: cvtps2pi Ppi,Wps | cvtpd2pi Qpi,Wpd (66) | vcvtss2si Gy,Wss (F3),(v1) | vcvtsd2si Gy,Wsd (F2),(v1)
3862e: vucomiss Vss,Wss (v1) | vucomisd Vsd,Wsd (66),(v1)
3872f: vcomiss Vss,Wss (v1) | vcomisd Vsd,Wsd (66),(v1)
388# 0x0f 0x30-0x3f
38930: WRMSR
39031: RDTSC
39132: RDMSR
39233: RDPMC
39334: SYSENTER
39435: SYSEXIT
39536:
39637: GETSEC
39738: escape # 3-byte escape 1
39839:
3993a: escape # 3-byte escape 2
4003b:
4013c:
4023d:
4033e:
4043f:
405# 0x0f 0x40-0x4f
40640: CMOVO Gv,Ev
40741: CMOVNO Gv,Ev | kandw/q Vk,Hk,Uk | kandb/d Vk,Hk,Uk (66)
40842: CMOVB/C/NAE Gv,Ev | kandnw/q Vk,Hk,Uk | kandnb/d Vk,Hk,Uk (66)
40943: CMOVAE/NB/NC Gv,Ev
41044: CMOVE/Z Gv,Ev | knotw/q Vk,Uk | knotb/d Vk,Uk (66)
41145: CMOVNE/NZ Gv,Ev | korw/q Vk,Hk,Uk | korb/d Vk,Hk,Uk (66)
41246: CMOVBE/NA Gv,Ev | kxnorw/q Vk,Hk,Uk | kxnorb/d Vk,Hk,Uk (66)
41347: CMOVA/NBE Gv,Ev | kxorw/q Vk,Hk,Uk | kxorb/d Vk,Hk,Uk (66)
41448: CMOVS Gv,Ev
41549: CMOVNS Gv,Ev
4164a: CMOVP/PE Gv,Ev | kaddw/q Vk,Hk,Uk | kaddb/d Vk,Hk,Uk (66)
4174b: CMOVNP/PO Gv,Ev | kunpckbw Vk,Hk,Uk (66) | kunpckwd/dq Vk,Hk,Uk
4184c: CMOVL/NGE Gv,Ev
4194d: CMOVNL/GE Gv,Ev
4204e: CMOVLE/NG Gv,Ev
4214f: CMOVNLE/G Gv,Ev
422# 0x0f 0x50-0x5f
42350: vmovmskps Gy,Ups | vmovmskpd Gy,Upd (66)
42451: vsqrtps Vps,Wps | vsqrtpd Vpd,Wpd (66) | vsqrtss Vss,Hss,Wss (F3),(v1) | vsqrtsd Vsd,Hsd,Wsd (F2),(v1)
42552: vrsqrtps Vps,Wps | vrsqrtss Vss,Hss,Wss (F3),(v1)
42653: vrcpps Vps,Wps | vrcpss Vss,Hss,Wss (F3),(v1)
42754: vandps Vps,Hps,Wps | vandpd Vpd,Hpd,Wpd (66)
42855: vandnps Vps,Hps,Wps | vandnpd Vpd,Hpd,Wpd (66)
42956: vorps Vps,Hps,Wps | vorpd Vpd,Hpd,Wpd (66)
43057: vxorps Vps,Hps,Wps | vxorpd Vpd,Hpd,Wpd (66)
43158: vaddps Vps,Hps,Wps | vaddpd Vpd,Hpd,Wpd (66) | vaddss Vss,Hss,Wss (F3),(v1) | vaddsd Vsd,Hsd,Wsd (F2),(v1)
43259: vmulps Vps,Hps,Wps | vmulpd Vpd,Hpd,Wpd (66) | vmulss Vss,Hss,Wss (F3),(v1) | vmulsd Vsd,Hsd,Wsd (F2),(v1)
4335a: vcvtps2pd Vpd,Wps | vcvtpd2ps Vps,Wpd (66) | vcvtss2sd Vsd,Hx,Wss (F3),(v1) | vcvtsd2ss Vss,Hx,Wsd (F2),(v1)
4345b: vcvtdq2ps Vps,Wdq | vcvtqq2ps Vps,Wqq (evo) | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3)
4355c: vsubps Vps,Hps,Wps | vsubpd Vpd,Hpd,Wpd (66) | vsubss Vss,Hss,Wss (F3),(v1) | vsubsd Vsd,Hsd,Wsd (F2),(v1)
4365d: vminps Vps,Hps,Wps | vminpd Vpd,Hpd,Wpd (66) | vminss Vss,Hss,Wss (F3),(v1) | vminsd Vsd,Hsd,Wsd (F2),(v1)
4375e: vdivps Vps,Hps,Wps | vdivpd Vpd,Hpd,Wpd (66) | vdivss Vss,Hss,Wss (F3),(v1) | vdivsd Vsd,Hsd,Wsd (F2),(v1)
4385f: vmaxps Vps,Hps,Wps | vmaxpd Vpd,Hpd,Wpd (66) | vmaxss Vss,Hss,Wss (F3),(v1) | vmaxsd Vsd,Hsd,Wsd (F2),(v1)
439# 0x0f 0x60-0x6f
44060: punpcklbw Pq,Qd | vpunpcklbw Vx,Hx,Wx (66),(v1)
44161: punpcklwd Pq,Qd | vpunpcklwd Vx,Hx,Wx (66),(v1)
44262: punpckldq Pq,Qd | vpunpckldq Vx,Hx,Wx (66),(v1)
44363: packsswb Pq,Qq | vpacksswb Vx,Hx,Wx (66),(v1)
44464: pcmpgtb Pq,Qq | vpcmpgtb Vx,Hx,Wx (66),(v1)
44565: pcmpgtw Pq,Qq | vpcmpgtw Vx,Hx,Wx (66),(v1)
44666: pcmpgtd Pq,Qq | vpcmpgtd Vx,Hx,Wx (66),(v1)
44767: packuswb Pq,Qq | vpackuswb Vx,Hx,Wx (66),(v1)
44868: punpckhbw Pq,Qd | vpunpckhbw Vx,Hx,Wx (66),(v1)
44969: punpckhwd Pq,Qd | vpunpckhwd Vx,Hx,Wx (66),(v1)
4506a: punpckhdq Pq,Qd | vpunpckhdq Vx,Hx,Wx (66),(v1)
4516b: packssdw Pq,Qd | vpackssdw Vx,Hx,Wx (66),(v1)
4526c: vpunpcklqdq Vx,Hx,Wx (66),(v1)
4536d: vpunpckhqdq Vx,Hx,Wx (66),(v1)
4546e: movd/q Pd,Ey | vmovd/q Vy,Ey (66),(v1)
4556f: movq Pq,Qq | vmovdqa Vx,Wx (66) | vmovdqa32/64 Vx,Wx (66),(evo) | vmovdqu Vx,Wx (F3) | vmovdqu32/64 Vx,Wx (F3),(evo) | vmovdqu8/16 Vx,Wx (F2),(ev)
456# 0x0f 0x70-0x7f
45770: pshufw Pq,Qq,Ib | vpshufd Vx,Wx,Ib (66),(v1) | vpshufhw Vx,Wx,Ib (F3),(v1) | vpshuflw Vx,Wx,Ib (F2),(v1)
45871: Grp12 (1A)
45972: Grp13 (1A)
46073: Grp14 (1A)
46174: pcmpeqb Pq,Qq | vpcmpeqb Vx,Hx,Wx (66),(v1)
46275: pcmpeqw Pq,Qq | vpcmpeqw Vx,Hx,Wx (66),(v1)
46376: pcmpeqd Pq,Qq | vpcmpeqd Vx,Hx,Wx (66),(v1)
464# Note: Remove (v), because vzeroall and vzeroupper becomes emms without VEX.
46577: emms | vzeroupper | vzeroall
46678: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev)
46779: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev)
4687a: vcvtudq2pd/uqq2pd Vpd,Wx (F3),(ev) | vcvtudq2ps/uqq2ps Vpd,Wx (F2),(ev) | vcvttps2qq/pd2qq Vx,Wx (66),(ev)
4697b: vcvtusi2sd Vpd,Hpd,Ev (F2),(ev) | vcvtusi2ss Vps,Hps,Ev (F3),(ev) | vcvtps2qq/pd2qq Vx,Wx (66),(ev)
4707c: vhaddpd Vpd,Hpd,Wpd (66) | vhaddps Vps,Hps,Wps (F2)
4717d: vhsubpd Vpd,Hpd,Wpd (66) | vhsubps Vps,Hps,Wps (F2)
4727e: movd/q Ey,Pd | vmovd/q Ey,Vy (66),(v1) | vmovq Vq,Wq (F3),(v1)
4737f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqa32/64 Wx,Vx (66),(evo) | vmovdqu Wx,Vx (F3) | vmovdqu32/64 Wx,Vx (F3),(evo) | vmovdqu8/16 Wx,Vx (F2),(ev)
474# 0x0f 0x80-0x8f
475# Note: "forced64" is Intel CPU behavior (see comment about CALL insn).
47680: JO Jz (f64)
47781: JNO Jz (f64)
47882: JB/JC/JNAE Jz (f64)
47983: JAE/JNB/JNC Jz (f64)
48084: JE/JZ Jz (f64)
48185: JNE/JNZ Jz (f64)
48286: JBE/JNA Jz (f64)
48387: JA/JNBE Jz (f64)
48488: JS Jz (f64)
48589: JNS Jz (f64)
4868a: JP/JPE Jz (f64)
4878b: JNP/JPO Jz (f64)
4888c: JL/JNGE Jz (f64)
4898d: JNL/JGE Jz (f64)
4908e: JLE/JNG Jz (f64)
4918f: JNLE/JG Jz (f64)
492# 0x0f 0x90-0x9f
49390: SETO Eb | kmovw/q Vk,Wk | kmovb/d Vk,Wk (66)
49491: SETNO Eb | kmovw/q Mv,Vk | kmovb/d Mv,Vk (66)
49592: SETB/C/NAE Eb | kmovw Vk,Rv | kmovb Vk,Rv (66) | kmovq/d Vk,Rv (F2)
49693: SETAE/NB/NC Eb | kmovw Gv,Uk | kmovb Gv,Uk (66) | kmovq/d Gv,Uk (F2)
49794: SETE/Z Eb
49895: SETNE/NZ Eb
49996: SETBE/NA Eb
50097: SETA/NBE Eb
50198: SETS Eb | kortestw/q Vk,Uk | kortestb/d Vk,Uk (66)
50299: SETNS Eb | ktestw/q Vk,Uk | ktestb/d Vk,Uk (66)
5039a: SETP/PE Eb
5049b: SETNP/PO Eb
5059c: SETL/NGE Eb
5069d: SETNL/GE Eb
5079e: SETLE/NG Eb
5089f: SETNLE/G Eb
509# 0x0f 0xa0-0xaf
510a0: PUSH FS (d64)
511a1: POP FS (d64)
512a2: CPUID
513a3: BT Ev,Gv
514a4: SHLD Ev,Gv,Ib
515a5: SHLD Ev,Gv,CL
516a6: GrpPDLK
517a7: GrpRNG
518a8: PUSH GS (d64)
519a9: POP GS (d64)
520aa: RSM
521ab: BTS Ev,Gv
522ac: SHRD Ev,Gv,Ib
523ad: SHRD Ev,Gv,CL
524ae: Grp15 (1A),(1C)
525af: IMUL Gv,Ev
526# 0x0f 0xb0-0xbf
527b0: CMPXCHG Eb,Gb
528b1: CMPXCHG Ev,Gv
529b2: LSS Gv,Mp
530b3: BTR Ev,Gv
531b4: LFS Gv,Mp
532b5: LGS Gv,Mp
533b6: MOVZX Gv,Eb
534b7: MOVZX Gv,Ew
535b8: JMPE (!F3) | POPCNT Gv,Ev (F3)
536b9: Grp10 (1A)
537ba: Grp8 Ev,Ib (1A)
538bb: BTC Ev,Gv
539bc: BSF Gv,Ev (!F3) | TZCNT Gv,Ev (F3)
540bd: BSR Gv,Ev (!F3) | LZCNT Gv,Ev (F3)
541be: MOVSX Gv,Eb
542bf: MOVSX Gv,Ew
543# 0x0f 0xc0-0xcf
544c0: XADD Eb,Gb
545c1: XADD Ev,Gv
546c2: vcmpps Vps,Hps,Wps,Ib | vcmppd Vpd,Hpd,Wpd,Ib (66) | vcmpss Vss,Hss,Wss,Ib (F3),(v1) | vcmpsd Vsd,Hsd,Wsd,Ib (F2),(v1)
547c3: movnti My,Gy
548c4: pinsrw Pq,Ry/Mw,Ib | vpinsrw Vdq,Hdq,Ry/Mw,Ib (66),(v1)
549c5: pextrw Gd,Nq,Ib | vpextrw Gd,Udq,Ib (66),(v1)
550c6: vshufps Vps,Hps,Wps,Ib | vshufpd Vpd,Hpd,Wpd,Ib (66)
551c7: Grp9 (1A)
552c8: BSWAP RAX/EAX/R8/R8D
553c9: BSWAP RCX/ECX/R9/R9D
554ca: BSWAP RDX/EDX/R10/R10D
555cb: BSWAP RBX/EBX/R11/R11D
556cc: BSWAP RSP/ESP/R12/R12D
557cd: BSWAP RBP/EBP/R13/R13D
558ce: BSWAP RSI/ESI/R14/R14D
559cf: BSWAP RDI/EDI/R15/R15D
560# 0x0f 0xd0-0xdf
561d0: vaddsubpd Vpd,Hpd,Wpd (66) | vaddsubps Vps,Hps,Wps (F2)
562d1: psrlw Pq,Qq | vpsrlw Vx,Hx,Wx (66),(v1)
563d2: psrld Pq,Qq | vpsrld Vx,Hx,Wx (66),(v1)
564d3: psrlq Pq,Qq | vpsrlq Vx,Hx,Wx (66),(v1)
565d4: paddq Pq,Qq | vpaddq Vx,Hx,Wx (66),(v1)
566d5: pmullw Pq,Qq | vpmullw Vx,Hx,Wx (66),(v1)
567d6: vmovq Wq,Vq (66),(v1) | movq2dq Vdq,Nq (F3) | movdq2q Pq,Uq (F2)
568d7: pmovmskb Gd,Nq | vpmovmskb Gd,Ux (66),(v1)
569d8: psubusb Pq,Qq | vpsubusb Vx,Hx,Wx (66),(v1)
570d9: psubusw Pq,Qq | vpsubusw Vx,Hx,Wx (66),(v1)
571da: pminub Pq,Qq | vpminub Vx,Hx,Wx (66),(v1)
572db: pand Pq,Qq | vpand Vx,Hx,Wx (66),(v1) | vpandd/q Vx,Hx,Wx (66),(evo)
573dc: paddusb Pq,Qq | vpaddusb Vx,Hx,Wx (66),(v1)
574dd: paddusw Pq,Qq | vpaddusw Vx,Hx,Wx (66),(v1)
575de: pmaxub Pq,Qq | vpmaxub Vx,Hx,Wx (66),(v1)
576df: pandn Pq,Qq | vpandn Vx,Hx,Wx (66),(v1) | vpandnd/q Vx,Hx,Wx (66),(evo)
577# 0x0f 0xe0-0xef
578e0: pavgb Pq,Qq | vpavgb Vx,Hx,Wx (66),(v1)
579e1: psraw Pq,Qq | vpsraw Vx,Hx,Wx (66),(v1)
580e2: psrad Pq,Qq | vpsrad Vx,Hx,Wx (66),(v1)
581e3: pavgw Pq,Qq | vpavgw Vx,Hx,Wx (66),(v1)
582e4: pmulhuw Pq,Qq | vpmulhuw Vx,Hx,Wx (66),(v1)
583e5: pmulhw Pq,Qq | vpmulhw Vx,Hx,Wx (66),(v1)
584e6: vcvttpd2dq Vx,Wpd (66) | vcvtdq2pd Vx,Wdq (F3) | vcvtdq2pd/qq2pd Vx,Wdq (F3),(evo) | vcvtpd2dq Vx,Wpd (F2)
585e7: movntq Mq,Pq | vmovntdq Mx,Vx (66)
586e8: psubsb Pq,Qq | vpsubsb Vx,Hx,Wx (66),(v1)
587e9: psubsw Pq,Qq | vpsubsw Vx,Hx,Wx (66),(v1)
588ea: pminsw Pq,Qq | vpminsw Vx,Hx,Wx (66),(v1)
589eb: por Pq,Qq | vpor Vx,Hx,Wx (66),(v1) | vpord/q Vx,Hx,Wx (66),(evo)
590ec: paddsb Pq,Qq | vpaddsb Vx,Hx,Wx (66),(v1)
591ed: paddsw Pq,Qq | vpaddsw Vx,Hx,Wx (66),(v1)
592ee: pmaxsw Pq,Qq | vpmaxsw Vx,Hx,Wx (66),(v1)
593ef: pxor Pq,Qq | vpxor Vx,Hx,Wx (66),(v1) | vpxord/q Vx,Hx,Wx (66),(evo)
594# 0x0f 0xf0-0xff
595f0: vlddqu Vx,Mx (F2)
596f1: psllw Pq,Qq | vpsllw Vx,Hx,Wx (66),(v1)
597f2: pslld Pq,Qq | vpslld Vx,Hx,Wx (66),(v1)
598f3: psllq Pq,Qq | vpsllq Vx,Hx,Wx (66),(v1)
599f4: pmuludq Pq,Qq | vpmuludq Vx,Hx,Wx (66),(v1)
600f5: pmaddwd Pq,Qq | vpmaddwd Vx,Hx,Wx (66),(v1)
601f6: psadbw Pq,Qq | vpsadbw Vx,Hx,Wx (66),(v1)
602f7: maskmovq Pq,Nq | vmaskmovdqu Vx,Ux (66),(v1)
603f8: psubb Pq,Qq | vpsubb Vx,Hx,Wx (66),(v1)
604f9: psubw Pq,Qq | vpsubw Vx,Hx,Wx (66),(v1)
605fa: psubd Pq,Qq | vpsubd Vx,Hx,Wx (66),(v1)
606fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(v1)
607fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1)
608fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1)
609fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1)
610ff: UD0
611EndTable
612
613Table: 3-byte opcode 1 (0x0f 0x38)
614Referrer: 3-byte escape 1
615AVXcode: 2
616# 0x0f 0x38 0x00-0x0f
61700: pshufb Pq,Qq | vpshufb Vx,Hx,Wx (66),(v1)
61801: phaddw Pq,Qq | vphaddw Vx,Hx,Wx (66),(v1)
61902: phaddd Pq,Qq | vphaddd Vx,Hx,Wx (66),(v1)
62003: phaddsw Pq,Qq | vphaddsw Vx,Hx,Wx (66),(v1)
62104: pmaddubsw Pq,Qq | vpmaddubsw Vx,Hx,Wx (66),(v1)
62205: phsubw Pq,Qq | vphsubw Vx,Hx,Wx (66),(v1)
62306: phsubd Pq,Qq | vphsubd Vx,Hx,Wx (66),(v1)
62407: phsubsw Pq,Qq | vphsubsw Vx,Hx,Wx (66),(v1)
62508: psignb Pq,Qq | vpsignb Vx,Hx,Wx (66),(v1)
62609: psignw Pq,Qq | vpsignw Vx,Hx,Wx (66),(v1)
6270a: psignd Pq,Qq | vpsignd Vx,Hx,Wx (66),(v1)
6280b: pmulhrsw Pq,Qq | vpmulhrsw Vx,Hx,Wx (66),(v1)
6290c: vpermilps Vx,Hx,Wx (66),(v)
6300d: vpermilpd Vx,Hx,Wx (66),(v)
6310e: vtestps Vx,Wx (66),(v)
6320f: vtestpd Vx,Wx (66),(v)
633# 0x0f 0x38 0x10-0x1f
63410: pblendvb Vdq,Wdq (66) | vpsrlvw Vx,Hx,Wx (66),(evo) | vpmovuswb Wx,Vx (F3),(ev)
63511: vpmovusdb Wx,Vd (F3),(ev) | vpsravw Vx,Hx,Wx (66),(ev)
63612: vpmovusqb Wx,Vq (F3),(ev) | vpsllvw Vx,Hx,Wx (66),(ev)
63713: vcvtph2ps Vx,Wx (66),(v) | vpmovusdw Wx,Vd (F3),(ev)
63814: blendvps Vdq,Wdq (66) | vpmovusqw Wx,Vq (F3),(ev) | vprorvd/q Vx,Hx,Wx (66),(evo)
63915: blendvpd Vdq,Wdq (66) | vpmovusqd Wx,Vq (F3),(ev) | vprolvd/q Vx,Hx,Wx (66),(evo)
64016: vpermps Vqq,Hqq,Wqq (66),(v) | vpermps/d Vqq,Hqq,Wqq (66),(evo)
64117: vptest Vx,Wx (66)
64218: vbroadcastss Vx,Wd (66),(v)
64319: vbroadcastsd Vqq,Wq (66),(v) | vbroadcastf32x2 Vqq,Wq (66),(evo)
6441a: vbroadcastf128 Vqq,Mdq (66),(v) | vbroadcastf32x4/64x2 Vqq,Wq (66),(evo)
6451b: vbroadcastf32x8/64x4 Vqq,Mdq (66),(ev)
6461c: pabsb Pq,Qq | vpabsb Vx,Wx (66),(v1)
6471d: pabsw Pq,Qq | vpabsw Vx,Wx (66),(v1)
6481e: pabsd Pq,Qq | vpabsd Vx,Wx (66),(v1)
6491f: vpabsq Vx,Wx (66),(ev)
650# 0x0f 0x38 0x20-0x2f
65120: vpmovsxbw Vx,Ux/Mq (66),(v1) | vpmovswb Wx,Vx (F3),(ev)
65221: vpmovsxbd Vx,Ux/Md (66),(v1) | vpmovsdb Wx,Vd (F3),(ev)
65322: vpmovsxbq Vx,Ux/Mw (66),(v1) | vpmovsqb Wx,Vq (F3),(ev)
65423: vpmovsxwd Vx,Ux/Mq (66),(v1) | vpmovsdw Wx,Vd (F3),(ev)
65524: vpmovsxwq Vx,Ux/Md (66),(v1) | vpmovsqw Wx,Vq (F3),(ev)
65625: vpmovsxdq Vx,Ux/Mq (66),(v1) | vpmovsqd Wx,Vq (F3),(ev)
65726: vptestmb/w Vk,Hx,Wx (66),(ev) | vptestnmb/w Vk,Hx,Wx (F3),(ev)
65827: vptestmd/q Vk,Hx,Wx (66),(ev) | vptestnmd/q Vk,Hx,Wx (F3),(ev)
65928: vpmuldq Vx,Hx,Wx (66),(v1) | vpmovm2b/w Vx,Uk (F3),(ev)
66029: vpcmpeqq Vx,Hx,Wx (66),(v1) | vpmovb2m/w2m Vk,Ux (F3),(ev)
6612a: vmovntdqa Vx,Mx (66),(v1) | vpbroadcastmb2q Vx,Uk (F3),(ev)
6622b: vpackusdw Vx,Hx,Wx (66),(v1)
6632c: vmaskmovps Vx,Hx,Mx (66),(v) | vscalefps/d Vx,Hx,Wx (66),(evo)
6642d: vmaskmovpd Vx,Hx,Mx (66),(v) | vscalefss/d Vx,Hx,Wx (66),(evo)
6652e: vmaskmovps Mx,Hx,Vx (66),(v)
6662f: vmaskmovpd Mx,Hx,Vx (66),(v)
667# 0x0f 0x38 0x30-0x3f
66830: vpmovzxbw Vx,Ux/Mq (66),(v1) | vpmovwb Wx,Vx (F3),(ev)
66931: vpmovzxbd Vx,Ux/Md (66),(v1) | vpmovdb Wx,Vd (F3),(ev)
67032: vpmovzxbq Vx,Ux/Mw (66),(v1) | vpmovqb Wx,Vq (F3),(ev)
67133: vpmovzxwd Vx,Ux/Mq (66),(v1) | vpmovdw Wx,Vd (F3),(ev)
67234: vpmovzxwq Vx,Ux/Md (66),(v1) | vpmovqw Wx,Vq (F3),(ev)
67335: vpmovzxdq Vx,Ux/Mq (66),(v1) | vpmovqd Wx,Vq (F3),(ev)
67436: vpermd Vqq,Hqq,Wqq (66),(v) | vpermd/q Vqq,Hqq,Wqq (66),(evo)
67537: vpcmpgtq Vx,Hx,Wx (66),(v1)
67638: vpminsb Vx,Hx,Wx (66),(v1) | vpmovm2d/q Vx,Uk (F3),(ev)
67739: vpminsd Vx,Hx,Wx (66),(v1) | vpminsd/q Vx,Hx,Wx (66),(evo) | vpmovd2m/q2m Vk,Ux (F3),(ev)
6783a: vpminuw Vx,Hx,Wx (66),(v1) | vpbroadcastmw2d Vx,Uk (F3),(ev)
6793b: vpminud Vx,Hx,Wx (66),(v1) | vpminud/q Vx,Hx,Wx (66),(evo)
6803c: vpmaxsb Vx,Hx,Wx (66),(v1)
6813d: vpmaxsd Vx,Hx,Wx (66),(v1) | vpmaxsd/q Vx,Hx,Wx (66),(evo)
6823e: vpmaxuw Vx,Hx,Wx (66),(v1)
6833f: vpmaxud Vx,Hx,Wx (66),(v1) | vpmaxud/q Vx,Hx,Wx (66),(evo)
684# 0x0f 0x38 0x40-0x8f
68540: vpmulld Vx,Hx,Wx (66),(v1) | vpmulld/q Vx,Hx,Wx (66),(evo)
68641: vphminposuw Vdq,Wdq (66),(v1)
68742: vgetexpps/d Vx,Wx (66),(ev)
68843: vgetexpss/d Vx,Hx,Wx (66),(ev)
68944: vplzcntd/q Vx,Wx (66),(ev)
69045: vpsrlvd/q Vx,Hx,Wx (66),(v)
69146: vpsravd Vx,Hx,Wx (66),(v) | vpsravd/q Vx,Hx,Wx (66),(evo)
69247: vpsllvd/q Vx,Hx,Wx (66),(v)
693# Skip 0x48-0x4b
6944c: vrcp14ps/d Vpd,Wpd (66),(ev)
6954d: vrcp14ss/d Vsd,Hpd,Wsd (66),(ev)
6964e: vrsqrt14ps/d Vpd,Wpd (66),(ev)
6974f: vrsqrt14ss/d Vsd,Hsd,Wsd (66),(ev)
698# Skip 0x50-0x57
69958: vpbroadcastd Vx,Wx (66),(v)
70059: vpbroadcastq Vx,Wx (66),(v) | vbroadcasti32x2 Vx,Wx (66),(evo)
7015a: vbroadcasti128 Vqq,Mdq (66),(v) | vbroadcasti32x4/64x2 Vx,Wx (66),(evo)
7025b: vbroadcasti32x8/64x4 Vqq,Mdq (66),(ev)
703# Skip 0x5c-0x63
70464: vpblendmd/q Vx,Hx,Wx (66),(ev)
70565: vblendmps/d Vx,Hx,Wx (66),(ev)
70666: vpblendmb/w Vx,Hx,Wx (66),(ev)
707# Skip 0x67-0x74
70875: vpermi2b/w Vx,Hx,Wx (66),(ev)
70976: vpermi2d/q Vx,Hx,Wx (66),(ev)
71077: vpermi2ps/d Vx,Hx,Wx (66),(ev)
71178: vpbroadcastb Vx,Wx (66),(v)
71279: vpbroadcastw Vx,Wx (66),(v)
7137a: vpbroadcastb Vx,Rv (66),(ev)
7147b: vpbroadcastw Vx,Rv (66),(ev)
7157c: vpbroadcastd/q Vx,Rv (66),(ev)
7167d: vpermt2b/w Vx,Hx,Wx (66),(ev)
7177e: vpermt2d/q Vx,Hx,Wx (66),(ev)
7187f: vpermt2ps/d Vx,Hx,Wx (66),(ev)
71980: INVEPT Gy,Mdq (66)
72081: INVVPID Gy,Mdq (66)
72182: INVPCID Gy,Mdq (66)
72283: vpmultishiftqb Vx,Hx,Wx (66),(ev)
72388: vexpandps/d Vpd,Wpd (66),(ev)
72489: vpexpandd/q Vx,Wx (66),(ev)
7258a: vcompressps/d Wx,Vx (66),(ev)
7268b: vpcompressd/q Wx,Vx (66),(ev)
7278c: vpmaskmovd/q Vx,Hx,Mx (66),(v)
7288d: vpermb/w Vx,Hx,Wx (66),(ev)
7298e: vpmaskmovd/q Mx,Vx,Hx (66),(v)
730# 0x0f 0x38 0x90-0xbf (FMA)
73190: vgatherdd/q Vx,Hx,Wx (66),(v) | vpgatherdd/q Vx,Wx (66),(evo)
73291: vgatherqd/q Vx,Hx,Wx (66),(v) | vpgatherqd/q Vx,Wx (66),(evo)
73392: vgatherdps/d Vx,Hx,Wx (66),(v)
73493: vgatherqps/d Vx,Hx,Wx (66),(v)
73594:
73695:
73796: vfmaddsub132ps/d Vx,Hx,Wx (66),(v)
73897: vfmsubadd132ps/d Vx,Hx,Wx (66),(v)
73998: vfmadd132ps/d Vx,Hx,Wx (66),(v)
74099: vfmadd132ss/d Vx,Hx,Wx (66),(v),(v1)
7419a: vfmsub132ps/d Vx,Hx,Wx (66),(v)
7429b: vfmsub132ss/d Vx,Hx,Wx (66),(v),(v1)
7439c: vfnmadd132ps/d Vx,Hx,Wx (66),(v)
7449d: vfnmadd132ss/d Vx,Hx,Wx (66),(v),(v1)
7459e: vfnmsub132ps/d Vx,Hx,Wx (66),(v)
7469f: vfnmsub132ss/d Vx,Hx,Wx (66),(v),(v1)
747a0: vpscatterdd/q Wx,Vx (66),(ev)
748a1: vpscatterqd/q Wx,Vx (66),(ev)
749a2: vscatterdps/d Wx,Vx (66),(ev)
750a3: vscatterqps/d Wx,Vx (66),(ev)
751a6: vfmaddsub213ps/d Vx,Hx,Wx (66),(v)
752a7: vfmsubadd213ps/d Vx,Hx,Wx (66),(v)
753a8: vfmadd213ps/d Vx,Hx,Wx (66),(v)
754a9: vfmadd213ss/d Vx,Hx,Wx (66),(v),(v1)
755aa: vfmsub213ps/d Vx,Hx,Wx (66),(v)
756ab: vfmsub213ss/d Vx,Hx,Wx (66),(v),(v1)
757ac: vfnmadd213ps/d Vx,Hx,Wx (66),(v)
758ad: vfnmadd213ss/d Vx,Hx,Wx (66),(v),(v1)
759ae: vfnmsub213ps/d Vx,Hx,Wx (66),(v)
760af: vfnmsub213ss/d Vx,Hx,Wx (66),(v),(v1)
761b4: vpmadd52luq Vx,Hx,Wx (66),(ev)
762b5: vpmadd52huq Vx,Hx,Wx (66),(ev)
763b6: vfmaddsub231ps/d Vx,Hx,Wx (66),(v)
764b7: vfmsubadd231ps/d Vx,Hx,Wx (66),(v)
765b8: vfmadd231ps/d Vx,Hx,Wx (66),(v)
766b9: vfmadd231ss/d Vx,Hx,Wx (66),(v),(v1)
767ba: vfmsub231ps/d Vx,Hx,Wx (66),(v)
768bb: vfmsub231ss/d Vx,Hx,Wx (66),(v),(v1)
769bc: vfnmadd231ps/d Vx,Hx,Wx (66),(v)
770bd: vfnmadd231ss/d Vx,Hx,Wx (66),(v),(v1)
771be: vfnmsub231ps/d Vx,Hx,Wx (66),(v)
772bf: vfnmsub231ss/d Vx,Hx,Wx (66),(v),(v1)
773# 0x0f 0x38 0xc0-0xff
774c4: vpconflictd/q Vx,Wx (66),(ev)
775c6: Grp18 (1A)
776c7: Grp19 (1A)
777c8: sha1nexte Vdq,Wdq | vexp2ps/d Vx,Wx (66),(ev)
778c9: sha1msg1 Vdq,Wdq
779ca: sha1msg2 Vdq,Wdq | vrcp28ps/d Vx,Wx (66),(ev)
780cb: sha256rnds2 Vdq,Wdq | vrcp28ss/d Vx,Hx,Wx (66),(ev)
781cc: sha256msg1 Vdq,Wdq | vrsqrt28ps/d Vx,Wx (66),(ev)
782cd: sha256msg2 Vdq,Wdq | vrsqrt28ss/d Vx,Hx,Wx (66),(ev)
783db: VAESIMC Vdq,Wdq (66),(v1)
784dc: VAESENC Vdq,Hdq,Wdq (66),(v1)
785dd: VAESENCLAST Vdq,Hdq,Wdq (66),(v1)
786de: VAESDEC Vdq,Hdq,Wdq (66),(v1)
787df: VAESDECLAST Vdq,Hdq,Wdq (66),(v1)
788f0: MOVBE Gy,My | MOVBE Gw,Mw (66) | CRC32 Gd,Eb (F2) | CRC32 Gd,Eb (66&F2)
789f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2)
790f2: ANDN Gy,By,Ey (v)
791f3: Grp17 (1A)
792f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v)
793f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v)
794f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v)
795EndTable
796
797Table: 3-byte opcode 2 (0x0f 0x3a)
798Referrer: 3-byte escape 2
799AVXcode: 3
800# 0x0f 0x3a 0x00-0xff
80100: vpermq Vqq,Wqq,Ib (66),(v)
80201: vpermpd Vqq,Wqq,Ib (66),(v)
80302: vpblendd Vx,Hx,Wx,Ib (66),(v)
80403: valignd/q Vx,Hx,Wx,Ib (66),(ev)
80504: vpermilps Vx,Wx,Ib (66),(v)
80605: vpermilpd Vx,Wx,Ib (66),(v)
80706: vperm2f128 Vqq,Hqq,Wqq,Ib (66),(v)
80807:
80908: vroundps Vx,Wx,Ib (66) | vrndscaleps Vx,Wx,Ib (66),(evo)
81009: vroundpd Vx,Wx,Ib (66) | vrndscalepd Vx,Wx,Ib (66),(evo)
8110a: vroundss Vss,Wss,Ib (66),(v1) | vrndscaless Vx,Hx,Wx,Ib (66),(evo)
8120b: vroundsd Vsd,Wsd,Ib (66),(v1) | vrndscalesd Vx,Hx,Wx,Ib (66),(evo)
8130c: vblendps Vx,Hx,Wx,Ib (66)
8140d: vblendpd Vx,Hx,Wx,Ib (66)
8150e: vpblendw Vx,Hx,Wx,Ib (66),(v1)
8160f: palignr Pq,Qq,Ib | vpalignr Vx,Hx,Wx,Ib (66),(v1)
81714: vpextrb Rd/Mb,Vdq,Ib (66),(v1)
81815: vpextrw Rd/Mw,Vdq,Ib (66),(v1)
81916: vpextrd/q Ey,Vdq,Ib (66),(v1)
82017: vextractps Ed,Vdq,Ib (66),(v1)
82118: vinsertf128 Vqq,Hqq,Wqq,Ib (66),(v) | vinsertf32x4/64x2 Vqq,Hqq,Wqq,Ib (66),(evo)
82219: vextractf128 Wdq,Vqq,Ib (66),(v) | vextractf32x4/64x2 Wdq,Vqq,Ib (66),(evo)
8231a: vinsertf32x8/64x4 Vqq,Hqq,Wqq,Ib (66),(ev)
8241b: vextractf32x8/64x4 Wdq,Vqq,Ib (66),(ev)
8251d: vcvtps2ph Wx,Vx,Ib (66),(v)
8261e: vpcmpud/q Vk,Hd,Wd,Ib (66),(ev)
8271f: vpcmpd/q Vk,Hd,Wd,Ib (66),(ev)
82820: vpinsrb Vdq,Hdq,Ry/Mb,Ib (66),(v1)
82921: vinsertps Vdq,Hdq,Udq/Md,Ib (66),(v1)
83022: vpinsrd/q Vdq,Hdq,Ey,Ib (66),(v1)
83123: vshuff32x4/64x2 Vx,Hx,Wx,Ib (66),(ev)
83225: vpternlogd/q Vx,Hx,Wx,Ib (66),(ev)
83326: vgetmantps/d Vx,Wx,Ib (66),(ev)
83427: vgetmantss/d Vx,Hx,Wx,Ib (66),(ev)
83530: kshiftrb/w Vk,Uk,Ib (66),(v)
83631: kshiftrd/q Vk,Uk,Ib (66),(v)
83732: kshiftlb/w Vk,Uk,Ib (66),(v)
83833: kshiftld/q Vk,Uk,Ib (66),(v)
83938: vinserti128 Vqq,Hqq,Wqq,Ib (66),(v) | vinserti32x4/64x2 Vqq,Hqq,Wqq,Ib (66),(evo)
84039: vextracti128 Wdq,Vqq,Ib (66),(v) | vextracti32x4/64x2 Wdq,Vqq,Ib (66),(evo)
8413a: vinserti32x8/64x4 Vqq,Hqq,Wqq,Ib (66),(ev)
8423b: vextracti32x8/64x4 Wdq,Vqq,Ib (66),(ev)
8433e: vpcmpub/w Vk,Hk,Wx,Ib (66),(ev)
8443f: vpcmpb/w Vk,Hk,Wx,Ib (66),(ev)
84540: vdpps Vx,Hx,Wx,Ib (66)
84641: vdppd Vdq,Hdq,Wdq,Ib (66),(v1)
84742: vmpsadbw Vx,Hx,Wx,Ib (66),(v1) | vdbpsadbw Vx,Hx,Wx,Ib (66),(evo)
84843: vshufi32x4/64x2 Vx,Hx,Wx,Ib (66),(ev)
84944: vpclmulqdq Vdq,Hdq,Wdq,Ib (66),(v1)
85046: vperm2i128 Vqq,Hqq,Wqq,Ib (66),(v)
8514a: vblendvps Vx,Hx,Wx,Lx (66),(v)
8524b: vblendvpd Vx,Hx,Wx,Lx (66),(v)
8534c: vpblendvb Vx,Hx,Wx,Lx (66),(v1)
85450: vrangeps/d Vx,Hx,Wx,Ib (66),(ev)
85551: vrangess/d Vx,Hx,Wx,Ib (66),(ev)
85654: vfixupimmps/d Vx,Hx,Wx,Ib (66),(ev)
85755: vfixupimmss/d Vx,Hx,Wx,Ib (66),(ev)
85856: vreduceps/d Vx,Wx,Ib (66),(ev)
85957: vreducess/d Vx,Hx,Wx,Ib (66),(ev)
86060: vpcmpestrm Vdq,Wdq,Ib (66),(v1)
86161: vpcmpestri Vdq,Wdq,Ib (66),(v1)
86262: vpcmpistrm Vdq,Wdq,Ib (66),(v1)
86363: vpcmpistri Vdq,Wdq,Ib (66),(v1)
86466: vfpclassps/d Vk,Wx,Ib (66),(ev)
86567: vfpclassss/d Vk,Wx,Ib (66),(ev)
866cc: sha1rnds4 Vdq,Wdq,Ib
867df: VAESKEYGEN Vdq,Wdq,Ib (66),(v1)
868f0: RORX Gy,Ey,Ib (F2),(v)
869EndTable
870
871GrpTable: Grp1
8720: ADD
8731: OR
8742: ADC
8753: SBB
8764: AND
8775: SUB
8786: XOR
8797: CMP
880EndTable
881
882GrpTable: Grp1A
8830: POP
884EndTable
885
886GrpTable: Grp2
8870: ROL
8881: ROR
8892: RCL
8903: RCR
8914: SHL/SAL
8925: SHR
8936:
8947: SAR
895EndTable
896
897GrpTable: Grp3_1
8980: TEST Eb,Ib
8991: TEST Eb,Ib
9002: NOT Eb
9013: NEG Eb
9024: MUL AL,Eb
9035: IMUL AL,Eb
9046: DIV AL,Eb
9057: IDIV AL,Eb
906EndTable
907
908GrpTable: Grp3_2
9090: TEST Ev,Iz
9101:
9112: NOT Ev
9123: NEG Ev
9134: MUL rAX,Ev
9145: IMUL rAX,Ev
9156: DIV rAX,Ev
9167: IDIV rAX,Ev
917EndTable
918
919GrpTable: Grp4
9200: INC Eb
9211: DEC Eb
922EndTable
923
924GrpTable: Grp5
9250: INC Ev
9261: DEC Ev
927# Note: "forced64" is Intel CPU behavior (see comment about CALL insn).
9282: CALLN Ev (f64)
9293: CALLF Ep
9304: JMPN Ev (f64)
9315: JMPF Mp
9326: PUSH Ev (d64)
9337:
934EndTable
935
936GrpTable: Grp6
9370: SLDT Rv/Mw
9381: STR Rv/Mw
9392: LLDT Ew
9403: LTR Ew
9414: VERR Ew
9425: VERW Ew
943EndTable
944
945GrpTable: Grp7
9460: SGDT Ms | VMCALL (001),(11B) | VMLAUNCH (010),(11B) | VMRESUME (011),(11B) | VMXOFF (100),(11B)
9471: SIDT Ms | MONITOR (000),(11B) | MWAIT (001),(11B) | CLAC (010),(11B) | STAC (011),(11B)
9482: LGDT Ms | XGETBV (000),(11B) | XSETBV (001),(11B) | VMFUNC (100),(11B) | XEND (101)(11B) | XTEST (110)(11B)
9493: LIDT Ms
9504: SMSW Mw/Rv
9515: rdpkru (110),(11B) | wrpkru (111),(11B)
9526: LMSW Ew
9537: INVLPG Mb | SWAPGS (o64),(000),(11B) | RDTSCP (001),(11B)
954EndTable
955
956GrpTable: Grp8
9574: BT
9585: BTS
9596: BTR
9607: BTC
961EndTable
962
963GrpTable: Grp9
9641: CMPXCHG8B/16B Mq/Mdq
9653: xrstors
9664: xsavec
9675: xsaves
9686: VMPTRLD Mq | VMCLEAR Mq (66) | VMXON Mq (F3) | RDRAND Rv (11B)
9697: VMPTRST Mq | VMPTRST Mq (F3) | RDSEED Rv (11B)
970EndTable
971
972GrpTable: Grp10
973# all are UD1
9740: UD1
9751: UD1
9762: UD1
9773: UD1
9784: UD1
9795: UD1
9806: UD1
9817: UD1
982EndTable
983
984# Grp11A and Grp11B are expressed as Grp11 in Intel SDM
985GrpTable: Grp11A
9860: MOV Eb,Ib
9877: XABORT Ib (000),(11B)
988EndTable
989
990GrpTable: Grp11B
9910: MOV Eb,Iz
9927: XBEGIN Jz (000),(11B)
993EndTable
994
995GrpTable: Grp12
9962: psrlw Nq,Ib (11B) | vpsrlw Hx,Ux,Ib (66),(11B),(v1)
9974: psraw Nq,Ib (11B) | vpsraw Hx,Ux,Ib (66),(11B),(v1)
9986: psllw Nq,Ib (11B) | vpsllw Hx,Ux,Ib (66),(11B),(v1)
999EndTable
1000
1001GrpTable: Grp13
10020: vprord/q Hx,Wx,Ib (66),(ev)
10031: vprold/q Hx,Wx,Ib (66),(ev)
10042: psrld Nq,Ib (11B) | vpsrld Hx,Ux,Ib (66),(11B),(v1)
10054: psrad Nq,Ib (11B) | vpsrad Hx,Ux,Ib (66),(11B),(v1) | vpsrad/q Hx,Ux,Ib (66),(evo)
10066: pslld Nq,Ib (11B) | vpslld Hx,Ux,Ib (66),(11B),(v1)
1007EndTable
1008
1009GrpTable: Grp14
10102: psrlq Nq,Ib (11B) | vpsrlq Hx,Ux,Ib (66),(11B),(v1)
10113: vpsrldq Hx,Ux,Ib (66),(11B),(v1)
10126: psllq Nq,Ib (11B) | vpsllq Hx,Ux,Ib (66),(11B),(v1)
10137: vpslldq Hx,Ux,Ib (66),(11B),(v1)
1014EndTable
1015
1016GrpTable: Grp15
10170: fxsave | RDFSBASE Ry (F3),(11B)
10181: fxstor | RDGSBASE Ry (F3),(11B)
10192: vldmxcsr Md (v1) | WRFSBASE Ry (F3),(11B)
10203: vstmxcsr Md (v1) | WRGSBASE Ry (F3),(11B)
10214: XSAVE | ptwrite Ey (F3),(11B)
10225: XRSTOR | lfence (11B)
10236: XSAVEOPT | clwb (66) | mfence (11B)
10247: clflush | clflushopt (66) | sfence (11B)
1025EndTable
1026
1027GrpTable: Grp16
10280: prefetch NTA
10291: prefetch T0
10302: prefetch T1
10313: prefetch T2
1032EndTable
1033
1034GrpTable: Grp17
10351: BLSR By,Ey (v)
10362: BLSMSK By,Ey (v)
10373: BLSI By,Ey (v)
1038EndTable
1039
1040GrpTable: Grp18
10411: vgatherpf0dps/d Wx (66),(ev)
10422: vgatherpf1dps/d Wx (66),(ev)
10435: vscatterpf0dps/d Wx (66),(ev)
10446: vscatterpf1dps/d Wx (66),(ev)
1045EndTable
1046
1047GrpTable: Grp19
10481: vgatherpf0qps/d Wx (66),(ev)
10492: vgatherpf1qps/d Wx (66),(ev)
10505: vscatterpf0qps/d Wx (66),(ev)
10516: vscatterpf1qps/d Wx (66),(ev)
1052EndTable
1053
1054# AMD's Prefetch Group
1055GrpTable: GrpP
10560: PREFETCH
10571: PREFETCHW
1058EndTable
1059
1060GrpTable: GrpPDLK
10610: MONTMUL
10621: XSHA1
10632: XSHA2
1064EndTable
1065
1066GrpTable: GrpRNG
10670: xstore-rng
10681: xcrypt-ecb
10692: xcrypt-cbc
10704: xcrypt-cfb
10715: xcrypt-ofb
1072EndTable
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-16 20:18:41 -0400