Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf fixes from Ingo Molnar:
 "On the kernel side there's a bunch of ring-buffer ordering fixes for a
  reproducible bug, plus a PEBS constraints regression fix.

  Plus tooling fixes"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  tools headers UAPI: Sync kvm.h headers with the kernel sources
  perf record: Fix s390 missing module symbol and warning for non-root users
  perf machine: Read also the end of the kernel
  perf test vmlinux-kallsyms: Ignore aliases to _etext when searching on kallsyms
  perf session: Add missing swap ops for namespace events
  perf namespace: Protect reading thread's namespace
  tools headers UAPI: Sync drm/drm.h with the kernel
  tools headers UAPI: Sync drm/i915_drm.h with the kernel
  tools headers UAPI: Sync linux/fs.h with the kernel
  tools headers UAPI: Sync linux/sched.h with the kernel
  tools arch x86: Sync asm/cpufeatures.h with the with the kernel
  tools include UAPI: Update copy of files related to new fspick, fsmount, fsconfig, fsopen, move_mount and open_tree syscalls
  perf arm64: Fix mksyscalltbl when system kernel headers are ahead of the kernel
  perf data: Fix 'strncat may truncate' build failure with recent gcc
  perf/ring-buffer: Use regular variables for nesting
  perf/ring-buffer: Always use {READ,WRITE}_ONCE() for rb->user_page data
  perf/ring_buffer: Add ordering to rb->nest increment
  perf/ring_buffer: Fix exposing a temporarily decreased data_head
  perf/x86/intel/ds: Fix EVENT vs. UEVENT PEBS constraints

4 files changed, 95 insertions, 1 deletions

diff --git a/tools/arch/arm64/include/uapi/asm/kvm.h b/tools/arch/arm64/include/uapi/asm/kvm.h
index 97c3478ee6e7..7b7ac0f6cec9 100644
--- a/tools/arch/arm64/include/uapi/asm/kvm.h
+++ b/tools/arch/arm64/include/uapi/asm/kvm.h
@@ -35,6 +35,7 @@
 #include <linux/psci.h>
 #include <linux/types.h>
 #include <asm/ptrace.h>
+#include <asm/sve_context.h>
 
 #define __KVM_HAVE_GUEST_DEBUG
 #define __KVM_HAVE_IRQ_LINE
@@ -102,6 +103,9 @@ struct kvm_regs {
 #define KVM_ARM_VCPU_EL1_32BIT          1 /* CPU running a 32bit VM */
 #define KVM_ARM_VCPU_PSCI_0_2           2 /* CPU uses PSCI v0.2 */
 #define KVM_ARM_VCPU_PMU_V3             3 /* Support guest PMUv3 */
+#define KVM_ARM_VCPU_SVE                4 /* enable SVE for this CPU */
+#define KVM_ARM_VCPU_PTRAUTH_ADDRESS    5 /* VCPU uses address authentication */
+#define KVM_ARM_VCPU_PTRAUTH_GENERIC    6 /* VCPU uses generic authentication */
 
 struct kvm_vcpu_init {
         __u32 target;
@@ -226,6 +230,45 @@ struct kvm_vcpu_events {
                                          KVM_REG_ARM_FW | ((r) & 0xffff))
 #define KVM_REG_ARM_PSCI_VERSION        KVM_REG_ARM_FW_REG(0)
 
+/* SVE registers */
+#define KVM_REG_ARM64_SVE               (0x15 << KVM_REG_ARM_COPROC_SHIFT)
+
+/* Z- and P-regs occupy blocks at the following offsets within this range: */
+#define KVM_REG_ARM64_SVE_ZREG_BASE     0
+#define KVM_REG_ARM64_SVE_PREG_BASE     0x400
+#define KVM_REG_ARM64_SVE_FFR_BASE      0x600
+
+#define KVM_ARM64_SVE_NUM_ZREGS         __SVE_NUM_ZREGS
+#define KVM_ARM64_SVE_NUM_PREGS         __SVE_NUM_PREGS
+
+#define KVM_ARM64_SVE_MAX_SLICES        32
+
+#define KVM_REG_ARM64_SVE_ZREG(n, i)                                    \
+        (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \
+         KVM_REG_SIZE_U2048 |                                           \
+         (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) |                 \
+         ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
+
+#define KVM_REG_ARM64_SVE_PREG(n, i)                                    \
+        (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \
+         KVM_REG_SIZE_U256 |                                            \
+         (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) |                 \
+         ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
+
+#define KVM_REG_ARM64_SVE_FFR(i)                                        \
+        (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \
+         KVM_REG_SIZE_U256 |                                            \
+         ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
+
+#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
+#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
+
+/* Vector lengths pseudo-register: */
+#define KVM_REG_ARM64_SVE_VLS           (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \
+                                         KVM_REG_SIZE_U512 | 0xffff)
+#define KVM_ARM64_SVE_VLS_WORDS \
+        ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
+
 /* Device Control API: ARM VGIC */
 #define KVM_DEV_ARM_VGIC_GRP_ADDR       0
 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS  1
diff --git a/tools/arch/powerpc/include/uapi/asm/kvm.h b/tools/arch/powerpc/include/uapi/asm/kvm.h
index 26ca425f4c2c..b0f72dea8b11 100644
--- a/tools/arch/powerpc/include/uapi/asm/kvm.h
+++ b/tools/arch/powerpc/include/uapi/asm/kvm.h
@@ -482,6 +482,8 @@ struct kvm_ppc_cpu_char {
 #define  KVM_REG_PPC_ICP_PPRI_SHIFT     16      /* pending irq priority */
 #define  KVM_REG_PPC_ICP_PPRI_MASK      0xff
 
+#define KVM_REG_PPC_VP_STATE    (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x8d)
+
 /* Device control API: PPC-specific devices */
 #define KVM_DEV_MPIC_GRP_MISC           1
 #define   KVM_DEV_MPIC_BASE_ADDR        0       /* 64-bit */
@@ -677,4 +679,48 @@ struct kvm_ppc_cpu_char {
 #define  KVM_XICS_PRESENTED             (1ULL << 43)
 #define  KVM_XICS_QUEUED                (1ULL << 44)
 
+/* POWER9 XIVE Native Interrupt Controller */
+#define KVM_DEV_XIVE_GRP_CTRL           1
+#define   KVM_DEV_XIVE_RESET            1
+#define   KVM_DEV_XIVE_EQ_SYNC          2
+#define KVM_DEV_XIVE_GRP_SOURCE         2       /* 64-bit source identifier */
+#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG  3       /* 64-bit source identifier */
+#define KVM_DEV_XIVE_GRP_EQ_CONFIG      4       /* 64-bit EQ identifier */
+#define KVM_DEV_XIVE_GRP_SOURCE_SYNC    5       /* 64-bit source identifier */
+
+/* Layout of 64-bit XIVE source attribute values */
+#define KVM_XIVE_LEVEL_SENSITIVE        (1ULL << 0)
+#define KVM_XIVE_LEVEL_ASSERTED         (1ULL << 1)
+
+/* Layout of 64-bit XIVE source configuration attribute values */
+#define KVM_XIVE_SOURCE_PRIORITY_SHIFT  0
+#define KVM_XIVE_SOURCE_PRIORITY_MASK   0x7
+#define KVM_XIVE_SOURCE_SERVER_SHIFT    3
+#define KVM_XIVE_SOURCE_SERVER_MASK     0xfffffff8ULL
+#define KVM_XIVE_SOURCE_MASKED_SHIFT    32
+#define KVM_XIVE_SOURCE_MASKED_MASK     0x100000000ULL
+#define KVM_XIVE_SOURCE_EISN_SHIFT      33
+#define KVM_XIVE_SOURCE_EISN_MASK       0xfffffffe00000000ULL
+
+/* Layout of 64-bit EQ identifier */
+#define KVM_XIVE_EQ_PRIORITY_SHIFT      0
+#define KVM_XIVE_EQ_PRIORITY_MASK       0x7
+#define KVM_XIVE_EQ_SERVER_SHIFT        3
+#define KVM_XIVE_EQ_SERVER_MASK         0xfffffff8ULL
+
+/* Layout of EQ configuration values (64 bytes) */
+struct kvm_ppc_xive_eq {
+        __u32 flags;
+        __u32 qshift;
+        __u64 qaddr;
+        __u32 qtoggle;
+        __u32 qindex;
+        __u8  pad[40];
+};
+
+#define KVM_XIVE_EQ_ALWAYS_NOTIFY       0x00000001
+
+#define KVM_XIVE_TIMA_PAGE_OFFSET       0
+#define KVM_XIVE_ESB_PAGE_OFFSET        4
+
 #endif /* __LINUX_KVM_POWERPC_H */
diff --git a/tools/arch/s390/include/uapi/asm/kvm.h b/tools/arch/s390/include/uapi/asm/kvm.h
index 09652eabe769..47104e5b47fd 100644
--- a/tools/arch/s390/include/uapi/asm/kvm.h
+++ b/tools/arch/s390/include/uapi/asm/kvm.h
@@ -153,7 +153,9 @@ struct kvm_s390_vm_cpu_subfunc {
         __u8 ppno[16];          /* with MSA5 */
         __u8 kma[16];           /* with MSA8 */
         __u8 kdsa[16];          /* with MSA9 */
-        __u8 reserved[1792];
+        __u8 sortl[32];         /* with STFLE.150 */
+        __u8 dfltcc[32];        /* with STFLE.151 */
+        __u8 reserved[1728];
 };
 
 /* kvm attributes for crypto */
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 981ff9479648..75f27ee2c263 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -344,6 +344,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
 #define X86_FEATURE_AVX512_4VNNIW       (18*32+ 2) /* AVX-512 Neural Network Instructions */
 #define X86_FEATURE_AVX512_4FMAPS       (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
+#define X86_FEATURE_MD_CLEAR            (18*32+10) /* VERW clears CPU buffers */
 #define X86_FEATURE_TSX_FORCE_ABORT     (18*32+13) /* "" TSX_FORCE_ABORT */
 #define X86_FEATURE_PCONFIG             (18*32+18) /* Intel PCONFIG */
 #define X86_FEATURE_SPEC_CTRL           (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
@@ -382,5 +383,7 @@
 #define X86_BUG_SPECTRE_V2              X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
 #define X86_BUG_SPEC_STORE_BYPASS       X86_BUG(17) /* CPU is affected by speculative store bypass attack */
 #define X86_BUG_L1TF                    X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
+#define X86_BUG_MDS                     X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
+#define X86_BUG_MSBDS_ONLY              X86_BUG(20) /* CPU is only affected by the  MSDBS variant of BUG_MDS */
 
 #endif /* _ASM_X86_CPUFEATURES_H */