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authorTakashi Iwai <tiwai@suse.de>2017-02-03 02:50:06 -0500
committerTakashi Iwai <tiwai@suse.de>2017-02-05 02:47:25 -0500
commit83af57dd515cf06883f6e954dd0efa9b15b514a6 (patch)
tree8a3a51fa48599e700fdc580e78d66125bbec9f92 /sound/x86
parent412bbe7d5b8cdb103af82c3616149138c50d1efa (diff)
ALSA: x86: Don't check connection in lowlevel accessors
The lowlevel register read/write don't have to be careful about the connection state. It should be checked in the caller side instead. By dropping the check, we can simplify the code, and readability. This patch also refacors the functions slightly: namely, - drop the useless always-zero return values - fold the inline functions to the main accessor functions themselves - move the DP audio hack for AUD_CONFIG to the caller side - simplify snd_intelhad_eanble_audio() and drop the unused had_read_modify() Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'sound/x86')
-rw-r--r--sound/x86/intel_hdmi_audio.c91
1 files changed, 25 insertions, 66 deletions
diff --git a/sound/x86/intel_hdmi_audio.c b/sound/x86/intel_hdmi_audio.c
index fac30cf2794f..db437efbb87d 100644
--- a/sound/x86/intel_hdmi_audio.c
+++ b/sound/x86/intel_hdmi_audio.c
@@ -188,69 +188,20 @@ static void had_substream_put(struct snd_intelhad *intelhaddata)
188} 188}
189 189
190/* Register access functions */ 190/* Register access functions */
191static inline void 191static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
192mid_hdmi_audio_read(struct snd_intelhad *ctx, u32 reg, u32 *val)
193{ 192{
194 *val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg); 193 *val = ioread32(ctx->mmio_start + ctx->had_config_offset + reg);
195} 194}
196 195
197static inline void 196static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
198mid_hdmi_audio_write(struct snd_intelhad *ctx, u32 reg, u32 val)
199{ 197{
200 iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg); 198 iowrite32(val, ctx->mmio_start + ctx->had_config_offset + reg);
201} 199}
202 200
203static int had_read_register(struct snd_intelhad *intelhaddata,
204 u32 offset, u32 *data)
205{
206 if (!intelhaddata->connected)
207 return -ENODEV;
208
209 mid_hdmi_audio_read(intelhaddata, offset, data);
210 return 0;
211}
212
213static void fixup_dp_config(struct snd_intelhad *intelhaddata,
214 u32 offset, u32 *data)
215{
216 if (intelhaddata->dp_output) {
217 if (offset == AUD_CONFIG && (*data & AUD_CONFIG_VALID_BIT))
218 *data |= AUD_CONFIG_DP_MODE | AUD_CONFIG_BLOCK_BIT;
219 }
220}
221
222static int had_write_register(struct snd_intelhad *intelhaddata,
223 u32 offset, u32 data)
224{
225 if (!intelhaddata->connected)
226 return -ENODEV;
227
228 fixup_dp_config(intelhaddata, offset, &data);
229 mid_hdmi_audio_write(intelhaddata, offset, data);
230 return 0;
231}
232
233static int had_read_modify(struct snd_intelhad *intelhaddata, u32 offset,
234 u32 data, u32 mask)
235{
236 u32 val_tmp;
237
238 if (!intelhaddata->connected)
239 return -ENODEV;
240
241 mid_hdmi_audio_read(intelhaddata, offset, &val_tmp);
242 val_tmp &= ~mask;
243 val_tmp |= (data & mask);
244
245 fixup_dp_config(intelhaddata, offset, &val_tmp);
246 mid_hdmi_audio_write(intelhaddata, offset, val_tmp);
247 return 0;
248}
249
250/* 201/*
251 * enable / disable audio configuration 202 * enable / disable audio configuration
252 * 203 *
253 * The had_read_modify() function should not directly be used on VLV2 for 204 * The normal read/modify should not directly be used on VLV2 for
254 * updating AUD_CONFIG register. 205 * updating AUD_CONFIG register.
255 * This is because: 206 * This is because:
256 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2 207 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
@@ -267,24 +218,25 @@ static void snd_intelhad_enable_audio(struct snd_pcm_substream *substream,
267 bool enable) 218 bool enable)
268{ 219{
269 union aud_cfg cfg_val = {.regval = 0}; 220 union aud_cfg cfg_val = {.regval = 0};
270 u8 channels, data, mask; 221 u8 channels;
222 u32 mask, val;
271 223
272 /* 224 /*
273 * If substream is NULL, there is no active stream. 225 * If substream is NULL, there is no active stream.
274 * In this case just set channels to 2 226 * In this case just set channels to 2
275 */ 227 */
276 channels = substream ? substream->runtime->channels : 2; 228 channels = substream ? substream->runtime->channels : 2;
277 cfg_val.regx.num_ch = channels - 2; 229 dev_dbg(intelhaddata->dev, "enable %d, ch=%d\n", enable, channels);
278 230
279 data = cfg_val.regval; 231 cfg_val.regx.num_ch = channels - 2;
280 if (enable) 232 if (enable)
281 data |= 1; 233 cfg_val.regx.aud_en = 1;
282 mask = AUD_CONFIG_CH_MASK | 1; 234 mask = AUD_CONFIG_CH_MASK | 1;
283 235
284 dev_dbg(intelhaddata->dev, "%s : data = %x, mask =%x\n", 236 had_read_register(intelhaddata, AUD_CONFIG, &val);
285 __func__, data, mask); 237 val &= ~mask;
286 238 val |= cfg_val.regval;
287 had_read_modify(intelhaddata, AUD_CONFIG, data, mask); 239 had_write_register(intelhaddata, AUD_CONFIG, val);
288} 240}
289 241
290/* enable / disable the audio interface */ 242/* enable / disable the audio interface */
@@ -293,10 +245,10 @@ static void snd_intelhad_enable_audio_int(struct snd_intelhad *ctx, bool enable)
293 u32 status_reg; 245 u32 status_reg;
294 246
295 if (enable) { 247 if (enable) {
296 mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS, &status_reg); 248 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
297 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN; 249 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
298 mid_hdmi_audio_write(ctx, AUD_HDMI_STATUS, status_reg); 250 had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
299 mid_hdmi_audio_read(ctx, AUD_HDMI_STATUS, &status_reg); 251 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
300 } 252 }
301} 253}
302 254
@@ -401,6 +353,13 @@ static int snd_intelhad_audio_ctrl(struct snd_pcm_substream *substream,
401 cfg_val.regx.layout = LAYOUT1; 353 cfg_val.regx.layout = LAYOUT1;
402 354
403 cfg_val.regx.val_bit = 1; 355 cfg_val.regx.val_bit = 1;
356
357 /* fix up the DP bits */
358 if (intelhaddata->dp_output) {
359 cfg_val.regx.dp_modei = 1;
360 cfg_val.regx.set = 1;
361 }
362
404 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); 363 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
405 return 0; 364 return 0;
406} 365}
@@ -1684,15 +1643,15 @@ static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1684 u32 audio_stat, audio_reg; 1643 u32 audio_stat, audio_reg;
1685 1644
1686 audio_reg = AUD_HDMI_STATUS; 1645 audio_reg = AUD_HDMI_STATUS;
1687 mid_hdmi_audio_read(ctx, audio_reg, &audio_stat); 1646 had_read_register(ctx, audio_reg, &audio_stat);
1688 1647
1689 if (audio_stat & HDMI_AUDIO_UNDERRUN) { 1648 if (audio_stat & HDMI_AUDIO_UNDERRUN) {
1690 mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_UNDERRUN); 1649 had_write_register(ctx, audio_reg, HDMI_AUDIO_UNDERRUN);
1691 had_process_buffer_underrun(ctx); 1650 had_process_buffer_underrun(ctx);
1692 } 1651 }
1693 1652
1694 if (audio_stat & HDMI_AUDIO_BUFFER_DONE) { 1653 if (audio_stat & HDMI_AUDIO_BUFFER_DONE) {
1695 mid_hdmi_audio_write(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE); 1654 had_write_register(ctx, audio_reg, HDMI_AUDIO_BUFFER_DONE);
1696 had_process_buffer_done(ctx); 1655 had_process_buffer_done(ctx);
1697 } 1656 }
1698 1657