summaryrefslogtreecommitdiffstats
path: root/sound/soc/tegra
diff options
context:
space:
mode:
authorStephen Warren <swarren@nvidia.com>2012-04-10 18:32:00 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-04-13 06:29:23 -0400
commit4fb0384f3dc68da10cf3f134c45efc6ab14f71df (patch)
tree6da538a744d0977aa85b869780335566b6588642 /sound/soc/tegra
parentbe944d42ccc125f1b200e7a4185af5bb87865190 (diff)
ASoC: tegra: add tegra30-i2s driver
This provides an ASoC DAI interface for Tegra 30's I2S controller. Includes a squashed bugfix from Sumit Bhattacharya <sumitb@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/tegra')
-rw-r--r--sound/soc/tegra/tegra30_i2s.c536
-rw-r--r--sound/soc/tegra/tegra30_i2s.h242
2 files changed, 778 insertions, 0 deletions
diff --git a/sound/soc/tegra/tegra30_i2s.c b/sound/soc/tegra/tegra30_i2s.c
new file mode 100644
index 000000000000..8596032985dc
--- /dev/null
+++ b/sound/soc/tegra/tegra30_i2s.c
@@ -0,0 +1,536 @@
1/*
2 * tegra30_i2s.c - Tegra30 I2S driver
3 *
4 * Author: Stephen Warren <swarren@nvidia.com>
5 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
6 *
7 * Based on code copyright/by:
8 *
9 * Copyright (c) 2009-2010, NVIDIA Corporation.
10 * Scott Peterson <speterson@nvidia.com>
11 *
12 * Copyright (C) 2010 Google, Inc.
13 * Iliyan Malchev <malchev@google.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms and conditions of the GNU General Public License,
17 * version 2, as published by the Free Software Foundation.
18 *
19 * This program is distributed in the hope it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program. If not, see <http://www.gnu.org/licenses/>.
26 */
27
28#include <linux/clk.h>
29#include <linux/device.h>
30#include <linux/io.h>
31#include <linux/module.h>
32#include <linux/of.h>
33#include <linux/platform_device.h>
34#include <linux/pm_runtime.h>
35#include <linux/regmap.h>
36#include <linux/slab.h>
37#include <sound/core.h>
38#include <sound/pcm.h>
39#include <sound/pcm_params.h>
40#include <sound/soc.h>
41
42#include "tegra30_ahub.h"
43#include "tegra30_i2s.h"
44
45#define DRV_NAME "tegra30-i2s"
46
47static inline void tegra30_i2s_write(struct tegra30_i2s *i2s, u32 reg, u32 val)
48{
49 regmap_write(i2s->regmap, reg, val);
50}
51
52static inline u32 tegra30_i2s_read(struct tegra30_i2s *i2s, u32 reg)
53{
54 u32 val;
55 regmap_read(i2s->regmap, reg, &val);
56 return val;
57}
58
59static int tegra30_i2s_runtime_suspend(struct device *dev)
60{
61 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
62
63 regcache_cache_only(i2s->regmap, true);
64
65 clk_disable(i2s->clk_i2s);
66
67 return 0;
68}
69
70static int tegra30_i2s_runtime_resume(struct device *dev)
71{
72 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
73 int ret;
74
75 ret = clk_enable(i2s->clk_i2s);
76 if (ret) {
77 dev_err(dev, "clk_enable failed: %d\n", ret);
78 return ret;
79 }
80
81 regcache_cache_only(i2s->regmap, false);
82
83 return 0;
84}
85
86int tegra30_i2s_startup(struct snd_pcm_substream *substream,
87 struct snd_soc_dai *dai)
88{
89 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
90 int ret;
91
92 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
93 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
94 &i2s->playback_dma_data.addr,
95 &i2s->playback_dma_data.req_sel);
96 i2s->playback_dma_data.wrap = 4;
97 i2s->playback_dma_data.width = 32;
98 tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
99 i2s->playback_fifo_cif);
100 } else {
101 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
102 &i2s->capture_dma_data.addr,
103 &i2s->capture_dma_data.req_sel);
104 i2s->capture_dma_data.wrap = 4;
105 i2s->capture_dma_data.width = 32;
106 tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
107 i2s->capture_i2s_cif);
108 }
109
110 return ret;
111}
112
113void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
114 struct snd_soc_dai *dai)
115{
116 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
117
118 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
119 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
120 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
121 } else {
122 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
123 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
124 }
125}
126
127static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
128 unsigned int fmt)
129{
130 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
131
132 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
133 case SND_SOC_DAIFMT_NB_NF:
134 break;
135 default:
136 return -EINVAL;
137 }
138
139 i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_MASTER_ENABLE;
140 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
141 case SND_SOC_DAIFMT_CBS_CFS:
142 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
143 break;
144 case SND_SOC_DAIFMT_CBM_CFM:
145 break;
146 default:
147 return -EINVAL;
148 }
149
150 i2s->reg_ctrl &= ~(TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
151 TEGRA30_I2S_CTRL_LRCK_MASK);
152 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
153 case SND_SOC_DAIFMT_DSP_A:
154 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
155 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
156 break;
157 case SND_SOC_DAIFMT_DSP_B:
158 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
159 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
160 break;
161 case SND_SOC_DAIFMT_I2S:
162 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
163 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
164 break;
165 case SND_SOC_DAIFMT_RIGHT_J:
166 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
167 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
168 break;
169 case SND_SOC_DAIFMT_LEFT_J:
170 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
171 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
172 break;
173 default:
174 return -EINVAL;
175 }
176
177 return 0;
178}
179
180static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
181 struct snd_pcm_hw_params *params,
182 struct snd_soc_dai *dai)
183{
184 struct device *dev = substream->pcm->card->dev;
185 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
186 u32 val;
187 int ret, sample_size, srate, i2sclock, bitcnt;
188
189 if (params_channels(params) != 2)
190 return -EINVAL;
191
192 i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
193 switch (params_format(params)) {
194 case SNDRV_PCM_FORMAT_S16_LE:
195 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
196 sample_size = 16;
197 break;
198 default:
199 return -EINVAL;
200 }
201
202 srate = params_rate(params);
203
204 /* Final "* 2" required by Tegra hardware */
205 i2sclock = srate * params_channels(params) * sample_size * 2;
206
207 bitcnt = (i2sclock / (2 * srate)) - 1;
208 if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
209 return -EINVAL;
210
211 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
212 if (ret) {
213 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
214 return ret;
215 }
216
217 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
218
219 if (i2sclock % (2 * srate))
220 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
221
222 tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
223
224 val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
225 (1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
226 (1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
227 TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
228 TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
229
230 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
231 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
232 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
233 } else {
234 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
235 tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
236 }
237
238 val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
239 (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
240 tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
241
242 return 0;
243}
244
245static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
246{
247 tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
248 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
249 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
250}
251
252static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
253{
254 tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
255 i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
256 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
257}
258
259static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
260{
261 tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
262 i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
263 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
264}
265
266static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
267{
268 tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
269 i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
270 tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
271}
272
273static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
274 struct snd_soc_dai *dai)
275{
276 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
277
278 switch (cmd) {
279 case SNDRV_PCM_TRIGGER_START:
280 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
281 case SNDRV_PCM_TRIGGER_RESUME:
282 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
283 tegra30_i2s_start_playback(i2s);
284 else
285 tegra30_i2s_start_capture(i2s);
286 break;
287 case SNDRV_PCM_TRIGGER_STOP:
288 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
289 case SNDRV_PCM_TRIGGER_SUSPEND:
290 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
291 tegra30_i2s_stop_playback(i2s);
292 else
293 tegra30_i2s_stop_capture(i2s);
294 break;
295 default:
296 return -EINVAL;
297 }
298
299 return 0;
300}
301
302static int tegra30_i2s_probe(struct snd_soc_dai *dai)
303{
304 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
305
306 dai->capture_dma_data = &i2s->capture_dma_data;
307 dai->playback_dma_data = &i2s->playback_dma_data;
308
309 return 0;
310}
311
312static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
313 .startup = tegra30_i2s_startup,
314 .shutdown = tegra30_i2s_shutdown,
315 .set_fmt = tegra30_i2s_set_fmt,
316 .hw_params = tegra30_i2s_hw_params,
317 .trigger = tegra30_i2s_trigger,
318};
319
320static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
321 .probe = tegra30_i2s_probe,
322 .playback = {
323 .channels_min = 2,
324 .channels_max = 2,
325 .rates = SNDRV_PCM_RATE_8000_96000,
326 .formats = SNDRV_PCM_FMTBIT_S16_LE,
327 },
328 .capture = {
329 .channels_min = 2,
330 .channels_max = 2,
331 .rates = SNDRV_PCM_RATE_8000_96000,
332 .formats = SNDRV_PCM_FMTBIT_S16_LE,
333 },
334 .ops = &tegra30_i2s_dai_ops,
335 .symmetric_rates = 1,
336};
337
338static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
339{
340 switch (reg) {
341 case TEGRA30_I2S_CTRL:
342 case TEGRA30_I2S_TIMING:
343 case TEGRA30_I2S_OFFSET:
344 case TEGRA30_I2S_CH_CTRL:
345 case TEGRA30_I2S_SLOT_CTRL:
346 case TEGRA30_I2S_CIF_RX_CTRL:
347 case TEGRA30_I2S_CIF_TX_CTRL:
348 case TEGRA30_I2S_FLOWCTL:
349 case TEGRA30_I2S_TX_STEP:
350 case TEGRA30_I2S_FLOW_STATUS:
351 case TEGRA30_I2S_FLOW_TOTAL:
352 case TEGRA30_I2S_FLOW_OVER:
353 case TEGRA30_I2S_FLOW_UNDER:
354 case TEGRA30_I2S_LCOEF_1_4_0:
355 case TEGRA30_I2S_LCOEF_1_4_1:
356 case TEGRA30_I2S_LCOEF_1_4_2:
357 case TEGRA30_I2S_LCOEF_1_4_3:
358 case TEGRA30_I2S_LCOEF_1_4_4:
359 case TEGRA30_I2S_LCOEF_1_4_5:
360 case TEGRA30_I2S_LCOEF_2_4_0:
361 case TEGRA30_I2S_LCOEF_2_4_1:
362 case TEGRA30_I2S_LCOEF_2_4_2:
363 return true;
364 default:
365 return false;
366 };
367}
368
369static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
370{
371 switch (reg) {
372 case TEGRA30_I2S_FLOW_STATUS:
373 case TEGRA30_I2S_FLOW_TOTAL:
374 case TEGRA30_I2S_FLOW_OVER:
375 case TEGRA30_I2S_FLOW_UNDER:
376 return true;
377 default:
378 return false;
379 };
380}
381
382static const struct regmap_config tegra30_i2s_regmap_config = {
383 .reg_bits = 32,
384 .reg_stride = 4,
385 .val_bits = 32,
386 .max_register = TEGRA30_I2S_LCOEF_2_4_2,
387 .writeable_reg = tegra30_i2s_wr_rd_reg,
388 .readable_reg = tegra30_i2s_wr_rd_reg,
389 .volatile_reg = tegra30_i2s_volatile_reg,
390 .cache_type = REGCACHE_RBTREE,
391};
392
393static __devinit int tegra30_i2s_platform_probe(struct platform_device *pdev)
394{
395 struct tegra30_i2s *i2s;
396 u32 cif_ids[2];
397 struct resource *mem, *memregion;
398 void __iomem *regs;
399 int ret;
400
401 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
402 if (!i2s) {
403 dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n");
404 ret = -ENOMEM;
405 goto err;
406 }
407 dev_set_drvdata(&pdev->dev, i2s);
408
409 i2s->dai = tegra30_i2s_dai_template;
410 i2s->dai.name = dev_name(&pdev->dev);
411
412 ret = of_property_read_u32_array(pdev->dev.of_node,
413 "nvidia,ahub-cif-ids", cif_ids,
414 ARRAY_SIZE(cif_ids));
415 if (ret < 0)
416 goto err;
417
418 i2s->playback_i2s_cif = cif_ids[0];
419 i2s->capture_i2s_cif = cif_ids[1];
420
421 i2s->clk_i2s = clk_get(&pdev->dev, NULL);
422 if (IS_ERR(i2s->clk_i2s)) {
423 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
424 ret = PTR_ERR(i2s->clk_i2s);
425 goto err;
426 }
427
428 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
429 if (!mem) {
430 dev_err(&pdev->dev, "No memory resource\n");
431 ret = -ENODEV;
432 goto err_clk_put;
433 }
434
435 memregion = devm_request_mem_region(&pdev->dev, mem->start,
436 resource_size(mem), DRV_NAME);
437 if (!memregion) {
438 dev_err(&pdev->dev, "Memory region already claimed\n");
439 ret = -EBUSY;
440 goto err_clk_put;
441 }
442
443 regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
444 if (!regs) {
445 dev_err(&pdev->dev, "ioremap failed\n");
446 ret = -ENOMEM;
447 goto err_clk_put;
448 }
449
450 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
451 &tegra30_i2s_regmap_config);
452 if (IS_ERR(i2s->regmap)) {
453 dev_err(&pdev->dev, "regmap init failed\n");
454 ret = PTR_ERR(i2s->regmap);
455 goto err_clk_put;
456 }
457 regcache_cache_only(i2s->regmap, true);
458
459 pm_runtime_enable(&pdev->dev);
460 if (!pm_runtime_enabled(&pdev->dev)) {
461 ret = tegra30_i2s_runtime_resume(&pdev->dev);
462 if (ret)
463 goto err_pm_disable;
464 }
465
466 ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
467 if (ret) {
468 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
469 ret = -ENOMEM;
470 goto err_suspend;
471 }
472
473 ret = tegra_pcm_platform_register(&pdev->dev);
474 if (ret) {
475 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
476 goto err_unregister_dai;
477 }
478
479 return 0;
480
481err_unregister_dai:
482 snd_soc_unregister_dai(&pdev->dev);
483err_suspend:
484 if (!pm_runtime_status_suspended(&pdev->dev))
485 tegra30_i2s_runtime_suspend(&pdev->dev);
486err_pm_disable:
487 pm_runtime_disable(&pdev->dev);
488err_clk_put:
489 clk_put(i2s->clk_i2s);
490err:
491 return ret;
492}
493
494static int __devexit tegra30_i2s_platform_remove(struct platform_device *pdev)
495{
496 struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
497
498 pm_runtime_disable(&pdev->dev);
499 if (!pm_runtime_status_suspended(&pdev->dev))
500 tegra30_i2s_runtime_suspend(&pdev->dev);
501
502 tegra_pcm_platform_unregister(&pdev->dev);
503 snd_soc_unregister_dai(&pdev->dev);
504
505 clk_put(i2s->clk_i2s);
506
507 return 0;
508}
509
510static const struct of_device_id tegra30_i2s_of_match[] __devinitconst = {
511 { .compatible = "nvidia,tegra30-i2s", },
512 {},
513};
514
515static const struct dev_pm_ops tegra30_i2s_pm_ops __devinitconst = {
516 SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
517 tegra30_i2s_runtime_resume, NULL)
518};
519
520static struct platform_driver tegra30_i2s_driver = {
521 .driver = {
522 .name = DRV_NAME,
523 .owner = THIS_MODULE,
524 .of_match_table = tegra30_i2s_of_match,
525 .pm = &tegra30_i2s_pm_ops,
526 },
527 .probe = tegra30_i2s_platform_probe,
528 .remove = __devexit_p(tegra30_i2s_platform_remove),
529};
530module_platform_driver(tegra30_i2s_driver);
531
532MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
533MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
534MODULE_LICENSE("GPL");
535MODULE_ALIAS("platform:" DRV_NAME);
536MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);
diff --git a/sound/soc/tegra/tegra30_i2s.h b/sound/soc/tegra/tegra30_i2s.h
new file mode 100644
index 000000000000..91adf29c7a87
--- /dev/null
+++ b/sound/soc/tegra/tegra30_i2s.h
@@ -0,0 +1,242 @@
1/*
2 * tegra30_i2s.h - Definitions for Tegra30 I2S driver
3 *
4 * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef __TEGRA30_I2S_H__
20#define __TEGRA30_I2S_H__
21
22#include "tegra_pcm.h"
23
24/* Register offsets from TEGRA30_I2S*_BASE */
25
26#define TEGRA30_I2S_CTRL 0x0
27#define TEGRA30_I2S_TIMING 0x4
28#define TEGRA30_I2S_OFFSET 0x08
29#define TEGRA30_I2S_CH_CTRL 0x0c
30#define TEGRA30_I2S_SLOT_CTRL 0x10
31#define TEGRA30_I2S_CIF_RX_CTRL 0x14
32#define TEGRA30_I2S_CIF_TX_CTRL 0x18
33#define TEGRA30_I2S_FLOWCTL 0x1c
34#define TEGRA30_I2S_TX_STEP 0x20
35#define TEGRA30_I2S_FLOW_STATUS 0x24
36#define TEGRA30_I2S_FLOW_TOTAL 0x28
37#define TEGRA30_I2S_FLOW_OVER 0x2c
38#define TEGRA30_I2S_FLOW_UNDER 0x30
39#define TEGRA30_I2S_LCOEF_1_4_0 0x34
40#define TEGRA30_I2S_LCOEF_1_4_1 0x38
41#define TEGRA30_I2S_LCOEF_1_4_2 0x3c
42#define TEGRA30_I2S_LCOEF_1_4_3 0x40
43#define TEGRA30_I2S_LCOEF_1_4_4 0x44
44#define TEGRA30_I2S_LCOEF_1_4_5 0x48
45#define TEGRA30_I2S_LCOEF_2_4_0 0x4c
46#define TEGRA30_I2S_LCOEF_2_4_1 0x50
47#define TEGRA30_I2S_LCOEF_2_4_2 0x54
48
49/* Fields in TEGRA30_I2S_CTRL */
50
51#define TEGRA30_I2S_CTRL_XFER_EN_TX (1 << 31)
52#define TEGRA30_I2S_CTRL_XFER_EN_RX (1 << 30)
53#define TEGRA30_I2S_CTRL_CG_EN (1 << 29)
54#define TEGRA30_I2S_CTRL_SOFT_RESET (1 << 28)
55#define TEGRA30_I2S_CTRL_TX_FLOWCTL_EN (1 << 27)
56
57#define TEGRA30_I2S_CTRL_OBS_SEL_SHIFT 24
58#define TEGRA30_I2S_CTRL_OBS_SEL_MASK (7 << TEGRA30_I2S_CTRL_OBS_SEL_SHIFT)
59
60#define TEGRA30_I2S_FRAME_FORMAT_LRCK 0
61#define TEGRA30_I2S_FRAME_FORMAT_FSYNC 1
62
63#define TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT 12
64#define TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK (7 << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT)
65#define TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK (TEGRA30_I2S_FRAME_FORMAT_LRCK << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT)
66#define TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC (TEGRA30_I2S_FRAME_FORMAT_FSYNC << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT)
67
68#define TEGRA30_I2S_CTRL_MASTER_ENABLE (1 << 10)
69
70#define TEGRA30_I2S_LRCK_LEFT_LOW 0
71#define TEGRA30_I2S_LRCK_RIGHT_LOW 1
72
73#define TEGRA30_I2S_CTRL_LRCK_SHIFT 9
74#define TEGRA30_I2S_CTRL_LRCK_MASK (1 << TEGRA30_I2S_CTRL_LRCK_SHIFT)
75#define TEGRA30_I2S_CTRL_LRCK_L_LOW (TEGRA30_I2S_LRCK_LEFT_LOW << TEGRA30_I2S_CTRL_LRCK_SHIFT)
76#define TEGRA30_I2S_CTRL_LRCK_R_LOW (TEGRA30_I2S_LRCK_RIGHT_LOW << TEGRA30_I2S_CTRL_LRCK_SHIFT)
77
78#define TEGRA30_I2S_CTRL_LPBK_ENABLE (1 << 8)
79
80#define TEGRA30_I2S_BIT_CODE_LINEAR 0
81#define TEGRA30_I2S_BIT_CODE_ULAW 1
82#define TEGRA30_I2S_BIT_CODE_ALAW 2
83
84#define TEGRA30_I2S_CTRL_BIT_CODE_SHIFT 4
85#define TEGRA30_I2S_CTRL_BIT_CODE_MASK (3 << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
86#define TEGRA30_I2S_CTRL_BIT_CODE_LINEAR (TEGRA30_I2S_BIT_CODE_LINEAR << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
87#define TEGRA30_I2S_CTRL_BIT_CODE_ULAW (TEGRA30_I2S_BIT_CODE_ULAW << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
88#define TEGRA30_I2S_CTRL_BIT_CODE_ALAW (TEGRA30_I2S_BIT_CODE_ALAW << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
89
90#define TEGRA30_I2S_BITS_8 1
91#define TEGRA30_I2S_BITS_12 2
92#define TEGRA30_I2S_BITS_16 3
93#define TEGRA30_I2S_BITS_20 4
94#define TEGRA30_I2S_BITS_24 5
95#define TEGRA30_I2S_BITS_28 6
96#define TEGRA30_I2S_BITS_32 7
97
98/* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */
99#define TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT 0
100#define TEGRA30_I2S_CTRL_BIT_SIZE_MASK (7 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
101#define TEGRA30_I2S_CTRL_BIT_SIZE_8 (TEGRA30_I2S_BITS_8 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
102#define TEGRA30_I2S_CTRL_BIT_SIZE_12 (TEGRA30_I2S_BITS_12 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
103#define TEGRA30_I2S_CTRL_BIT_SIZE_16 (TEGRA30_I2S_BITS_16 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
104#define TEGRA30_I2S_CTRL_BIT_SIZE_20 (TEGRA30_I2S_BITS_20 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
105#define TEGRA30_I2S_CTRL_BIT_SIZE_24 (TEGRA30_I2S_BITS_24 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
106#define TEGRA30_I2S_CTRL_BIT_SIZE_28 (TEGRA30_I2S_BITS_28 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
107#define TEGRA30_I2S_CTRL_BIT_SIZE_32 (TEGRA30_I2S_BITS_32 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
108
109/* Fields in TEGRA30_I2S_TIMING */
110
111#define TEGRA30_I2S_TIMING_NON_SYM_ENABLE (1 << 12)
112#define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0
113#define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7fff
114#define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)
115
116/* Fields in TEGRA30_I2S_OFFSET */
117
118#define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT 16
119#define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US 0x7ff
120#define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK (TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT)
121#define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT 0
122#define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US 0x7ff
123#define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK (TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT)
124
125/* Fields in TEGRA30_I2S_CH_CTRL */
126
127/* (FSYNC width - 1) in bit clocks */
128#define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT 24
129#define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US 0xff
130#define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK (TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US << TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT)
131
132#define TEGRA30_I2S_HIGHZ_NO 0
133#define TEGRA30_I2S_HIGHZ_YES 1
134#define TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK 2
135
136#define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT 12
137#define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_MASK (3 << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
138#define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_NO (TEGRA30_I2S_HIGHZ_NO << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
139#define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_YES (TEGRA30_I2S_HIGHZ_YES << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
140#define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK (TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
141
142#define TEGRA30_I2S_MSB_FIRST 0
143#define TEGRA30_I2S_LSB_FIRST 1
144
145#define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT 10
146#define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MASK (1 << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT)
147#define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST (TEGRA30_I2S_MSB_FIRST << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT)
148#define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST (TEGRA30_I2S_LSB_FIRST << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT)
149#define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT 9
150#define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MASK (1 << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT)
151#define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST (TEGRA30_I2S_MSB_FIRST << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT)
152#define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST (TEGRA30_I2S_LSB_FIRST << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT)
153
154#define TEGRA30_I2S_POS_EDGE 0
155#define TEGRA30_I2S_NEG_EDGE 1
156
157#define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT 8
158#define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK (1 << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT)
159#define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE (TEGRA30_I2S_POS_EDGE << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT)
160#define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE (TEGRA30_I2S_NEG_EDGE << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT)
161
162/* Sample size is # bits from BIT_SIZE minus this field */
163#define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT 4
164#define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US 7
165#define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK (TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US << TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT)
166
167#define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT 0
168#define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US 7
169#define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK (TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US << TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT)
170
171/* Fields in TEGRA30_I2S_SLOT_CTRL */
172
173/* Number of slots in frame, minus 1 */
174#define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT 16
175#define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US 7
176#define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOT_MASK_US << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOT_SHIFT)
177
178/* TDM mode slot enable bitmask */
179#define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT 8
180#define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK (0xff << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT)
181
182#define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT 0
183#define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK (0xff << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT)
184
185/* Fields in TEGRA30_I2S_CIF_RX_CTRL */
186/* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */
187
188/* Fields in TEGRA30_I2S_CIF_TX_CTRL */
189/* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */
190
191/* Fields in TEGRA30_I2S_FLOWCTL */
192
193#define TEGRA30_I2S_FILTER_LINEAR 0
194#define TEGRA30_I2S_FILTER_QUAD 1
195
196#define TEGRA30_I2S_FLOWCTL_FILTER_SHIFT 31
197#define TEGRA30_I2S_FLOWCTL_FILTER_MASK (1 << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT)
198#define TEGRA30_I2S_FLOWCTL_FILTER_LINEAR (TEGRA30_I2S_FILTER_LINEAR << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT)
199#define TEGRA30_I2S_FLOWCTL_FILTER_QUAD (TEGRA30_I2S_FILTER_QUAD << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT)
200
201/* Fields in TEGRA30_I2S_TX_STEP */
202
203#define TEGRA30_I2S_TX_STEP_SHIFT 0
204#define TEGRA30_I2S_TX_STEP_MASK_US 0xffff
205#define TEGRA30_I2S_TX_STEP_MASK (TEGRA30_I2S_TX_STEP_MASK_US << TEGRA30_I2S_TX_STEP_SHIFT)
206
207/* Fields in TEGRA30_I2S_FLOW_STATUS */
208
209#define TEGRA30_I2S_FLOW_STATUS_UNDERFLOW (1 << 31)
210#define TEGRA30_I2S_FLOW_STATUS_OVERFLOW (1 << 30)
211#define TEGRA30_I2S_FLOW_STATUS_MONITOR_INT_EN (1 << 4)
212#define TEGRA30_I2S_FLOW_STATUS_COUNTER_CLR (1 << 3)
213#define TEGRA30_I2S_FLOW_STATUS_MONITOR_CLR (1 << 2)
214#define TEGRA30_I2S_FLOW_STATUS_COUNTER_EN (1 << 1)
215#define TEGRA30_I2S_FLOW_STATUS_MONITOR_EN (1 << 0)
216
217/*
218 * There are no fields in TEGRA30_I2S_FLOW_TOTAL, TEGRA30_I2S_FLOW_OVER,
219 * TEGRA30_I2S_FLOW_UNDER; they are counters taking the whole register.
220 */
221
222/* Fields in TEGRA30_I2S_LCOEF_* */
223
224#define TEGRA30_I2S_LCOEF_COEF_SHIFT 0
225#define TEGRA30_I2S_LCOEF_COEF_MASK_US 0xffff
226#define TEGRA30_I2S_LCOEF_COEF_MASK (TEGRA30_I2S_LCOEF_COEF_MASK_US << TEGRA30_I2S_LCOEF_COEF_SHIFT)
227
228struct tegra30_i2s {
229 struct snd_soc_dai_driver dai;
230 int cif_id;
231 struct clk *clk_i2s;
232 enum tegra30_ahub_txcif capture_i2s_cif;
233 enum tegra30_ahub_rxcif capture_fifo_cif;
234 struct tegra_pcm_dma_params capture_dma_data;
235 enum tegra30_ahub_rxcif playback_i2s_cif;
236 enum tegra30_ahub_txcif playback_fifo_cif;
237 struct tegra_pcm_dma_params playback_dma_data;
238 struct regmap *regmap;
239 u32 reg_ctrl;
240};
241
242#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-07 13:13:49 -0500