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authorPi-Hsun Shih <pihsun@chromium.org>2019-03-06 04:09:02 -0500
committerMark Brown <broonie@kernel.org>2019-03-19 08:51:13 -0400
commited1666f6867059e1ed4e2e565a1c87c5580f1b38 (patch)
treea01b5bb8ebb23c2aac1190888986a3b74e96b859 /sound/soc/mediatek
parent4e08d50d1fb6144df4b0b5c75a17edd344bf3d1b (diff)
ASoC: mediatek: Fix UBSAN warning.
In sound/soc/mediatek/common/mtk-afe-fe-dai.c, when xxx_reg is -1, it's a no-op to call mtk_regmap_update_bits, but since both xxx_reg and xxx_shift are set to -1, the (1 << xxx_shift) in the argument would trigger a UBSAN warning. Fix the warning by setting those xxx_shift to 0 instead. Note that since the code explicitly checks .mono_shift >= 0 and .fs_shift >= 0 before using them in '<<' operator, those two members are not set to 0. Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/mediatek')
-rw-r--r--sound/soc/mediatek/common/mtk-afe-fe-dai.c9
-rw-r--r--sound/soc/mediatek/mt2701/mt2701-afe-pcm.c13
-rw-r--r--sound/soc/mediatek/mt6797/mt6797-afe-pcm.c16
-rw-r--r--sound/soc/mediatek/mt8173/mt8173-afe-pcm.c16
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-afe-pcm.c20
5 files changed, 4 insertions, 70 deletions
diff --git a/sound/soc/mediatek/common/mtk-afe-fe-dai.c b/sound/soc/mediatek/common/mtk-afe-fe-dai.c
index cf4978be062f..3830e582e188 100644
--- a/sound/soc/mediatek/common/mtk-afe-fe-dai.c
+++ b/sound/soc/mediatek/common/mtk-afe-fe-dai.c
@@ -197,11 +197,10 @@ int mtk_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,
197 switch (cmd) { 197 switch (cmd) {
198 case SNDRV_PCM_TRIGGER_START: 198 case SNDRV_PCM_TRIGGER_START:
199 case SNDRV_PCM_TRIGGER_RESUME: 199 case SNDRV_PCM_TRIGGER_RESUME:
200 if (memif->data->enable_shift >= 0) 200 mtk_regmap_update_bits(afe->regmap,
201 mtk_regmap_update_bits(afe->regmap, 201 memif->data->enable_reg,
202 memif->data->enable_reg, 202 1 << memif->data->enable_shift,
203 1 << memif->data->enable_shift, 203 1 << memif->data->enable_shift);
204 1 << memif->data->enable_shift);
205 204
206 /* set irq counter */ 205 /* set irq counter */
207 mtk_regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg, 206 mtk_regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg,
diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
index 968fba4d7533..7064a9fd6f74 100644
--- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
+++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
@@ -994,7 +994,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
994 .agent_disable_reg = AUDIO_TOP_CON5, 994 .agent_disable_reg = AUDIO_TOP_CON5,
995 .agent_disable_shift = 6, 995 .agent_disable_shift = 6,
996 .msb_reg = -1, 996 .msb_reg = -1,
997 .msb_shift = -1,
998 }, 997 },
999 { 998 {
1000 .name = "DL2", 999 .name = "DL2",
@@ -1013,7 +1012,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1013 .agent_disable_reg = AUDIO_TOP_CON5, 1012 .agent_disable_reg = AUDIO_TOP_CON5,
1014 .agent_disable_shift = 7, 1013 .agent_disable_shift = 7,
1015 .msb_reg = -1, 1014 .msb_reg = -1,
1016 .msb_shift = -1,
1017 }, 1015 },
1018 { 1016 {
1019 .name = "DL3", 1017 .name = "DL3",
@@ -1032,7 +1030,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1032 .agent_disable_reg = AUDIO_TOP_CON5, 1030 .agent_disable_reg = AUDIO_TOP_CON5,
1033 .agent_disable_shift = 8, 1031 .agent_disable_shift = 8,
1034 .msb_reg = -1, 1032 .msb_reg = -1,
1035 .msb_shift = -1,
1036 }, 1033 },
1037 { 1034 {
1038 .name = "DL4", 1035 .name = "DL4",
@@ -1051,7 +1048,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1051 .agent_disable_reg = AUDIO_TOP_CON5, 1048 .agent_disable_reg = AUDIO_TOP_CON5,
1052 .agent_disable_shift = 9, 1049 .agent_disable_shift = 9,
1053 .msb_reg = -1, 1050 .msb_reg = -1,
1054 .msb_shift = -1,
1055 }, 1051 },
1056 { 1052 {
1057 .name = "DL5", 1053 .name = "DL5",
@@ -1070,7 +1066,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1070 .agent_disable_reg = AUDIO_TOP_CON5, 1066 .agent_disable_reg = AUDIO_TOP_CON5,
1071 .agent_disable_shift = 10, 1067 .agent_disable_shift = 10,
1072 .msb_reg = -1, 1068 .msb_reg = -1,
1073 .msb_shift = -1,
1074 }, 1069 },
1075 { 1070 {
1076 .name = "DLM", 1071 .name = "DLM",
@@ -1089,7 +1084,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1089 .agent_disable_reg = AUDIO_TOP_CON5, 1084 .agent_disable_reg = AUDIO_TOP_CON5,
1090 .agent_disable_shift = 12, 1085 .agent_disable_shift = 12,
1091 .msb_reg = -1, 1086 .msb_reg = -1,
1092 .msb_shift = -1,
1093 }, 1087 },
1094 { 1088 {
1095 .name = "UL1", 1089 .name = "UL1",
@@ -1108,7 +1102,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1108 .agent_disable_reg = AUDIO_TOP_CON5, 1102 .agent_disable_reg = AUDIO_TOP_CON5,
1109 .agent_disable_shift = 0, 1103 .agent_disable_shift = 0,
1110 .msb_reg = -1, 1104 .msb_reg = -1,
1111 .msb_shift = -1,
1112 }, 1105 },
1113 { 1106 {
1114 .name = "UL2", 1107 .name = "UL2",
@@ -1127,7 +1120,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1127 .agent_disable_reg = AUDIO_TOP_CON5, 1120 .agent_disable_reg = AUDIO_TOP_CON5,
1128 .agent_disable_shift = 1, 1121 .agent_disable_shift = 1,
1129 .msb_reg = -1, 1122 .msb_reg = -1,
1130 .msb_shift = -1,
1131 }, 1123 },
1132 { 1124 {
1133 .name = "UL3", 1125 .name = "UL3",
@@ -1146,7 +1138,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1146 .agent_disable_reg = AUDIO_TOP_CON5, 1138 .agent_disable_reg = AUDIO_TOP_CON5,
1147 .agent_disable_shift = 2, 1139 .agent_disable_shift = 2,
1148 .msb_reg = -1, 1140 .msb_reg = -1,
1149 .msb_shift = -1,
1150 }, 1141 },
1151 { 1142 {
1152 .name = "UL4", 1143 .name = "UL4",
@@ -1165,7 +1156,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1165 .agent_disable_reg = AUDIO_TOP_CON5, 1156 .agent_disable_reg = AUDIO_TOP_CON5,
1166 .agent_disable_shift = 3, 1157 .agent_disable_shift = 3,
1167 .msb_reg = -1, 1158 .msb_reg = -1,
1168 .msb_shift = -1,
1169 }, 1159 },
1170 { 1160 {
1171 .name = "UL5", 1161 .name = "UL5",
@@ -1184,7 +1174,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1184 .agent_disable_reg = AUDIO_TOP_CON5, 1174 .agent_disable_reg = AUDIO_TOP_CON5,
1185 .agent_disable_shift = 4, 1175 .agent_disable_shift = 4,
1186 .msb_reg = -1, 1176 .msb_reg = -1,
1187 .msb_shift = -1,
1188 }, 1177 },
1189 { 1178 {
1190 .name = "DLBT", 1179 .name = "DLBT",
@@ -1203,7 +1192,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1203 .agent_disable_reg = AUDIO_TOP_CON5, 1192 .agent_disable_reg = AUDIO_TOP_CON5,
1204 .agent_disable_shift = 13, 1193 .agent_disable_shift = 13,
1205 .msb_reg = -1, 1194 .msb_reg = -1,
1206 .msb_shift = -1,
1207 }, 1195 },
1208 { 1196 {
1209 .name = "ULBT", 1197 .name = "ULBT",
@@ -1222,7 +1210,6 @@ static const struct mtk_base_memif_data memif_data[MT2701_MEMIF_NUM] = {
1222 .agent_disable_reg = AUDIO_TOP_CON5, 1210 .agent_disable_reg = AUDIO_TOP_CON5,
1223 .agent_disable_shift = 16, 1211 .agent_disable_shift = 16,
1224 .msb_reg = -1, 1212 .msb_reg = -1,
1225 .msb_shift = -1,
1226 }, 1213 },
1227}; 1214};
1228 1215
diff --git a/sound/soc/mediatek/mt6797/mt6797-afe-pcm.c b/sound/soc/mediatek/mt6797/mt6797-afe-pcm.c
index bff7d71d0742..08a6532da322 100644
--- a/sound/soc/mediatek/mt6797/mt6797-afe-pcm.c
+++ b/sound/soc/mediatek/mt6797/mt6797-afe-pcm.c
@@ -401,9 +401,7 @@ static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = {
401 .hd_reg = AFE_MEMIF_HD_MODE, 401 .hd_reg = AFE_MEMIF_HD_MODE,
402 .hd_shift = DL1_HD_SFT, 402 .hd_shift = DL1_HD_SFT,
403 .agent_disable_reg = -1, 403 .agent_disable_reg = -1,
404 .agent_disable_shift = -1,
405 .msb_reg = -1, 404 .msb_reg = -1,
406 .msb_shift = -1,
407 }, 405 },
408 [MT6797_MEMIF_DL2] = { 406 [MT6797_MEMIF_DL2] = {
409 .name = "DL2", 407 .name = "DL2",
@@ -420,9 +418,7 @@ static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = {
420 .hd_reg = AFE_MEMIF_HD_MODE, 418 .hd_reg = AFE_MEMIF_HD_MODE,
421 .hd_shift = DL2_HD_SFT, 419 .hd_shift = DL2_HD_SFT,
422 .agent_disable_reg = -1, 420 .agent_disable_reg = -1,
423 .agent_disable_shift = -1,
424 .msb_reg = -1, 421 .msb_reg = -1,
425 .msb_shift = -1,
426 }, 422 },
427 [MT6797_MEMIF_DL3] = { 423 [MT6797_MEMIF_DL3] = {
428 .name = "DL3", 424 .name = "DL3",
@@ -439,9 +435,7 @@ static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = {
439 .hd_reg = AFE_MEMIF_HD_MODE, 435 .hd_reg = AFE_MEMIF_HD_MODE,
440 .hd_shift = DL3_HD_SFT, 436 .hd_shift = DL3_HD_SFT,
441 .agent_disable_reg = -1, 437 .agent_disable_reg = -1,
442 .agent_disable_shift = -1,
443 .msb_reg = -1, 438 .msb_reg = -1,
444 .msb_shift = -1,
445 }, 439 },
446 [MT6797_MEMIF_VUL] = { 440 [MT6797_MEMIF_VUL] = {
447 .name = "VUL", 441 .name = "VUL",
@@ -458,9 +452,7 @@ static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = {
458 .hd_reg = AFE_MEMIF_HD_MODE, 452 .hd_reg = AFE_MEMIF_HD_MODE,
459 .hd_shift = VUL_HD_SFT, 453 .hd_shift = VUL_HD_SFT,
460 .agent_disable_reg = -1, 454 .agent_disable_reg = -1,
461 .agent_disable_shift = -1,
462 .msb_reg = -1, 455 .msb_reg = -1,
463 .msb_shift = -1,
464 }, 456 },
465 [MT6797_MEMIF_AWB] = { 457 [MT6797_MEMIF_AWB] = {
466 .name = "AWB", 458 .name = "AWB",
@@ -477,9 +469,7 @@ static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = {
477 .hd_reg = AFE_MEMIF_HD_MODE, 469 .hd_reg = AFE_MEMIF_HD_MODE,
478 .hd_shift = AWB_HD_SFT, 470 .hd_shift = AWB_HD_SFT,
479 .agent_disable_reg = -1, 471 .agent_disable_reg = -1,
480 .agent_disable_shift = -1,
481 .msb_reg = -1, 472 .msb_reg = -1,
482 .msb_shift = -1,
483 }, 473 },
484 [MT6797_MEMIF_VUL12] = { 474 [MT6797_MEMIF_VUL12] = {
485 .name = "VUL12", 475 .name = "VUL12",
@@ -496,9 +486,7 @@ static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = {
496 .hd_reg = AFE_MEMIF_HD_MODE, 486 .hd_reg = AFE_MEMIF_HD_MODE,
497 .hd_shift = VUL_DATA2_HD_SFT, 487 .hd_shift = VUL_DATA2_HD_SFT,
498 .agent_disable_reg = -1, 488 .agent_disable_reg = -1,
499 .agent_disable_shift = -1,
500 .msb_reg = -1, 489 .msb_reg = -1,
501 .msb_shift = -1,
502 }, 490 },
503 [MT6797_MEMIF_DAI] = { 491 [MT6797_MEMIF_DAI] = {
504 .name = "DAI", 492 .name = "DAI",
@@ -515,9 +503,7 @@ static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = {
515 .hd_reg = AFE_MEMIF_HD_MODE, 503 .hd_reg = AFE_MEMIF_HD_MODE,
516 .hd_shift = DAI_HD_SFT, 504 .hd_shift = DAI_HD_SFT,
517 .agent_disable_reg = -1, 505 .agent_disable_reg = -1,
518 .agent_disable_shift = -1,
519 .msb_reg = -1, 506 .msb_reg = -1,
520 .msb_shift = -1,
521 }, 507 },
522 [MT6797_MEMIF_MOD_DAI] = { 508 [MT6797_MEMIF_MOD_DAI] = {
523 .name = "MOD_DAI", 509 .name = "MOD_DAI",
@@ -534,9 +520,7 @@ static const struct mtk_base_memif_data memif_data[MT6797_MEMIF_NUM] = {
534 .hd_reg = AFE_MEMIF_HD_MODE, 520 .hd_reg = AFE_MEMIF_HD_MODE,
535 .hd_shift = MOD_DAI_HD_SFT, 521 .hd_shift = MOD_DAI_HD_SFT,
536 .agent_disable_reg = -1, 522 .agent_disable_reg = -1,
537 .agent_disable_shift = -1,
538 .msb_reg = -1, 523 .msb_reg = -1,
539 .msb_shift = -1,
540 }, 524 },
541}; 525};
542 526
diff --git a/sound/soc/mediatek/mt8173/mt8173-afe-pcm.c b/sound/soc/mediatek/mt8173/mt8173-afe-pcm.c
index 166aed28330d..0382896c162e 100644
--- a/sound/soc/mediatek/mt8173/mt8173-afe-pcm.c
+++ b/sound/soc/mediatek/mt8173/mt8173-afe-pcm.c
@@ -714,13 +714,11 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
714 .mono_reg = AFE_DAC_CON1, 714 .mono_reg = AFE_DAC_CON1,
715 .mono_shift = 21, 715 .mono_shift = 21,
716 .hd_reg = -1, 716 .hd_reg = -1,
717 .hd_shift = -1,
718 .enable_reg = AFE_DAC_CON0, 717 .enable_reg = AFE_DAC_CON0,
719 .enable_shift = 1, 718 .enable_shift = 1,
720 .msb_reg = AFE_MEMIF_MSB, 719 .msb_reg = AFE_MEMIF_MSB,
721 .msb_shift = 0, 720 .msb_shift = 0,
722 .agent_disable_reg = -1, 721 .agent_disable_reg = -1,
723 .agent_disable_shift = -1,
724 }, { 722 }, {
725 .name = "DL2", 723 .name = "DL2",
726 .id = MT8173_AFE_MEMIF_DL2, 724 .id = MT8173_AFE_MEMIF_DL2,
@@ -732,13 +730,11 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
732 .mono_reg = AFE_DAC_CON1, 730 .mono_reg = AFE_DAC_CON1,
733 .mono_shift = 22, 731 .mono_shift = 22,
734 .hd_reg = -1, 732 .hd_reg = -1,
735 .hd_shift = -1,
736 .enable_reg = AFE_DAC_CON0, 733 .enable_reg = AFE_DAC_CON0,
737 .enable_shift = 2, 734 .enable_shift = 2,
738 .msb_reg = AFE_MEMIF_MSB, 735 .msb_reg = AFE_MEMIF_MSB,
739 .msb_shift = 1, 736 .msb_shift = 1,
740 .agent_disable_reg = -1, 737 .agent_disable_reg = -1,
741 .agent_disable_shift = -1,
742 }, { 738 }, {
743 .name = "VUL", 739 .name = "VUL",
744 .id = MT8173_AFE_MEMIF_VUL, 740 .id = MT8173_AFE_MEMIF_VUL,
@@ -750,13 +746,11 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
750 .mono_reg = AFE_DAC_CON1, 746 .mono_reg = AFE_DAC_CON1,
751 .mono_shift = 27, 747 .mono_shift = 27,
752 .hd_reg = -1, 748 .hd_reg = -1,
753 .hd_shift = -1,
754 .enable_reg = AFE_DAC_CON0, 749 .enable_reg = AFE_DAC_CON0,
755 .enable_shift = 3, 750 .enable_shift = 3,
756 .msb_reg = AFE_MEMIF_MSB, 751 .msb_reg = AFE_MEMIF_MSB,
757 .msb_shift = 6, 752 .msb_shift = 6,
758 .agent_disable_reg = -1, 753 .agent_disable_reg = -1,
759 .agent_disable_shift = -1,
760 }, { 754 }, {
761 .name = "DAI", 755 .name = "DAI",
762 .id = MT8173_AFE_MEMIF_DAI, 756 .id = MT8173_AFE_MEMIF_DAI,
@@ -768,13 +762,11 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
768 .mono_reg = -1, 762 .mono_reg = -1,
769 .mono_shift = -1, 763 .mono_shift = -1,
770 .hd_reg = -1, 764 .hd_reg = -1,
771 .hd_shift = -1,
772 .enable_reg = AFE_DAC_CON0, 765 .enable_reg = AFE_DAC_CON0,
773 .enable_shift = 4, 766 .enable_shift = 4,
774 .msb_reg = AFE_MEMIF_MSB, 767 .msb_reg = AFE_MEMIF_MSB,
775 .msb_shift = 5, 768 .msb_shift = 5,
776 .agent_disable_reg = -1, 769 .agent_disable_reg = -1,
777 .agent_disable_shift = -1,
778 }, { 770 }, {
779 .name = "AWB", 771 .name = "AWB",
780 .id = MT8173_AFE_MEMIF_AWB, 772 .id = MT8173_AFE_MEMIF_AWB,
@@ -786,13 +778,11 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
786 .mono_reg = AFE_DAC_CON1, 778 .mono_reg = AFE_DAC_CON1,
787 .mono_shift = 24, 779 .mono_shift = 24,
788 .hd_reg = -1, 780 .hd_reg = -1,
789 .hd_shift = -1,
790 .enable_reg = AFE_DAC_CON0, 781 .enable_reg = AFE_DAC_CON0,
791 .enable_shift = 6, 782 .enable_shift = 6,
792 .msb_reg = AFE_MEMIF_MSB, 783 .msb_reg = AFE_MEMIF_MSB,
793 .msb_shift = 3, 784 .msb_shift = 3,
794 .agent_disable_reg = -1, 785 .agent_disable_reg = -1,
795 .agent_disable_shift = -1,
796 }, { 786 }, {
797 .name = "MOD_DAI", 787 .name = "MOD_DAI",
798 .id = MT8173_AFE_MEMIF_MOD_DAI, 788 .id = MT8173_AFE_MEMIF_MOD_DAI,
@@ -804,13 +794,11 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
804 .mono_reg = AFE_DAC_CON1, 794 .mono_reg = AFE_DAC_CON1,
805 .mono_shift = 30, 795 .mono_shift = 30,
806 .hd_reg = -1, 796 .hd_reg = -1,
807 .hd_shift = -1,
808 .enable_reg = AFE_DAC_CON0, 797 .enable_reg = AFE_DAC_CON0,
809 .enable_shift = 7, 798 .enable_shift = 7,
810 .msb_reg = AFE_MEMIF_MSB, 799 .msb_reg = AFE_MEMIF_MSB,
811 .msb_shift = 4, 800 .msb_shift = 4,
812 .agent_disable_reg = -1, 801 .agent_disable_reg = -1,
813 .agent_disable_shift = -1,
814 }, { 802 }, {
815 .name = "HDMI", 803 .name = "HDMI",
816 .id = MT8173_AFE_MEMIF_HDMI, 804 .id = MT8173_AFE_MEMIF_HDMI,
@@ -822,13 +810,10 @@ static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = {
822 .mono_reg = -1, 810 .mono_reg = -1,
823 .mono_shift = -1, 811 .mono_shift = -1,
824 .hd_reg = -1, 812 .hd_reg = -1,
825 .hd_shift = -1,
826 .enable_reg = -1, 813 .enable_reg = -1,
827 .enable_shift = -1,
828 .msb_reg = AFE_MEMIF_MSB, 814 .msb_reg = AFE_MEMIF_MSB,
829 .msb_shift = 8, 815 .msb_shift = 8,
830 .agent_disable_reg = -1, 816 .agent_disable_reg = -1,
831 .agent_disable_shift = -1,
832 }, 817 },
833}; 818};
834 819
@@ -914,7 +899,6 @@ static const struct mtk_base_irq_data irq_data[MT8173_AFE_IRQ_NUM] = {
914 .irq_en_reg = AFE_IRQ_MCU_CON, 899 .irq_en_reg = AFE_IRQ_MCU_CON,
915 .irq_en_shift = 12, 900 .irq_en_shift = 12,
916 .irq_fs_reg = -1, 901 .irq_fs_reg = -1,
917 .irq_fs_shift = -1,
918 .irq_fs_maskbit = -1, 902 .irq_fs_maskbit = -1,
919 .irq_clr_reg = AFE_IRQ_CLR, 903 .irq_clr_reg = AFE_IRQ_CLR,
920 .irq_clr_shift = 4, 904 .irq_clr_shift = 4,
diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
index 4e045dd305a7..43be51bf0329 100644
--- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
+++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
@@ -421,9 +421,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
421 .hd_reg = AFE_MEMIF_HD_MODE, 421 .hd_reg = AFE_MEMIF_HD_MODE,
422 .hd_shift = DL1_HD_SFT, 422 .hd_shift = DL1_HD_SFT,
423 .agent_disable_reg = -1, 423 .agent_disable_reg = -1,
424 .agent_disable_shift = -1,
425 .msb_reg = -1, 424 .msb_reg = -1,
426 .msb_shift = -1,
427 }, 425 },
428 [MT8183_MEMIF_DL2] = { 426 [MT8183_MEMIF_DL2] = {
429 .name = "DL2", 427 .name = "DL2",
@@ -440,9 +438,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
440 .hd_reg = AFE_MEMIF_HD_MODE, 438 .hd_reg = AFE_MEMIF_HD_MODE,
441 .hd_shift = DL2_HD_SFT, 439 .hd_shift = DL2_HD_SFT,
442 .agent_disable_reg = -1, 440 .agent_disable_reg = -1,
443 .agent_disable_shift = -1,
444 .msb_reg = -1, 441 .msb_reg = -1,
445 .msb_shift = -1,
446 }, 442 },
447 [MT8183_MEMIF_DL3] = { 443 [MT8183_MEMIF_DL3] = {
448 .name = "DL3", 444 .name = "DL3",
@@ -459,9 +455,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
459 .hd_reg = AFE_MEMIF_HD_MODE, 455 .hd_reg = AFE_MEMIF_HD_MODE,
460 .hd_shift = DL3_HD_SFT, 456 .hd_shift = DL3_HD_SFT,
461 .agent_disable_reg = -1, 457 .agent_disable_reg = -1,
462 .agent_disable_shift = -1,
463 .msb_reg = -1, 458 .msb_reg = -1,
464 .msb_shift = -1,
465 }, 459 },
466 [MT8183_MEMIF_VUL2] = { 460 [MT8183_MEMIF_VUL2] = {
467 .name = "VUL2", 461 .name = "VUL2",
@@ -478,9 +472,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
478 .hd_reg = AFE_MEMIF_HD_MODE, 472 .hd_reg = AFE_MEMIF_HD_MODE,
479 .hd_shift = VUL2_HD_SFT, 473 .hd_shift = VUL2_HD_SFT,
480 .agent_disable_reg = -1, 474 .agent_disable_reg = -1,
481 .agent_disable_shift = -1,
482 .msb_reg = -1, 475 .msb_reg = -1,
483 .msb_shift = -1,
484 }, 476 },
485 [MT8183_MEMIF_AWB] = { 477 [MT8183_MEMIF_AWB] = {
486 .name = "AWB", 478 .name = "AWB",
@@ -497,9 +489,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
497 .hd_reg = AFE_MEMIF_HD_MODE, 489 .hd_reg = AFE_MEMIF_HD_MODE,
498 .hd_shift = AWB_HD_SFT, 490 .hd_shift = AWB_HD_SFT,
499 .agent_disable_reg = -1, 491 .agent_disable_reg = -1,
500 .agent_disable_shift = -1,
501 .msb_reg = -1, 492 .msb_reg = -1,
502 .msb_shift = -1,
503 }, 493 },
504 [MT8183_MEMIF_AWB2] = { 494 [MT8183_MEMIF_AWB2] = {
505 .name = "AWB2", 495 .name = "AWB2",
@@ -516,9 +506,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
516 .hd_reg = AFE_MEMIF_HD_MODE, 506 .hd_reg = AFE_MEMIF_HD_MODE,
517 .hd_shift = AWB2_HD_SFT, 507 .hd_shift = AWB2_HD_SFT,
518 .agent_disable_reg = -1, 508 .agent_disable_reg = -1,
519 .agent_disable_shift = -1,
520 .msb_reg = -1, 509 .msb_reg = -1,
521 .msb_shift = -1,
522 }, 510 },
523 [MT8183_MEMIF_VUL12] = { 511 [MT8183_MEMIF_VUL12] = {
524 .name = "VUL12", 512 .name = "VUL12",
@@ -535,9 +523,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
535 .hd_reg = AFE_MEMIF_HD_MODE, 523 .hd_reg = AFE_MEMIF_HD_MODE,
536 .hd_shift = VUL12_HD_SFT, 524 .hd_shift = VUL12_HD_SFT,
537 .agent_disable_reg = -1, 525 .agent_disable_reg = -1,
538 .agent_disable_shift = -1,
539 .msb_reg = -1, 526 .msb_reg = -1,
540 .msb_shift = -1,
541 }, 527 },
542 [MT8183_MEMIF_MOD_DAI] = { 528 [MT8183_MEMIF_MOD_DAI] = {
543 .name = "MOD_DAI", 529 .name = "MOD_DAI",
@@ -554,9 +540,7 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
554 .hd_reg = AFE_MEMIF_HD_MODE, 540 .hd_reg = AFE_MEMIF_HD_MODE,
555 .hd_shift = MOD_DAI_HD_SFT, 541 .hd_shift = MOD_DAI_HD_SFT,
556 .agent_disable_reg = -1, 542 .agent_disable_reg = -1,
557 .agent_disable_shift = -1,
558 .msb_reg = -1, 543 .msb_reg = -1,
559 .msb_shift = -1,
560 }, 544 },
561 [MT8183_MEMIF_HDMI] = { 545 [MT8183_MEMIF_HDMI] = {
562 .name = "HDMI", 546 .name = "HDMI",
@@ -569,13 +553,10 @@ static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
569 .mono_reg = -1, 553 .mono_reg = -1,
570 .mono_shift = -1, 554 .mono_shift = -1,
571 .enable_reg = -1, /* control in tdm for sync start */ 555 .enable_reg = -1, /* control in tdm for sync start */
572 .enable_shift = -1,
573 .hd_reg = AFE_MEMIF_HD_MODE, 556 .hd_reg = AFE_MEMIF_HD_MODE,
574 .hd_shift = HDMI_HD_SFT, 557 .hd_shift = HDMI_HD_SFT,
575 .agent_disable_reg = -1, 558 .agent_disable_reg = -1,
576 .agent_disable_shift = -1,
577 .msb_reg = -1, 559 .msb_reg = -1,
578 .msb_shift = -1,
579 }, 560 },
580}; 561};
581 562
@@ -690,7 +671,6 @@ static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
690 .irq_cnt_shift = 0, 671 .irq_cnt_shift = 0,
691 .irq_cnt_maskbit = 0x3ffff, 672 .irq_cnt_maskbit = 0x3ffff,
692 .irq_fs_reg = -1, 673 .irq_fs_reg = -1,
693 .irq_fs_shift = -1,
694 .irq_fs_maskbit = -1, 674 .irq_fs_maskbit = -1,
695 .irq_en_reg = AFE_IRQ_MCU_CON0, 675 .irq_en_reg = AFE_IRQ_MCU_CON0,
696 .irq_en_shift = IRQ8_MCU_ON_SFT, 676 .irq_en_shift = IRQ8_MCU_ON_SFT,
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 21:18:45 -0500