Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq core updates from Thomas Gleixner:
 "A rather large update for the interrupt core code and the irq chip drivers:

   - Add a new bitmap matrix allocator and supporting changes, which is
     used to replace the x86 vector allocator which comes with separate
     pull request. This allows to replace the convoluted nested loop
     allocation function in x86 with a facility which supports the
     recently added property of managed interrupts proper and allows to
     switch to a best effort vector reservation scheme, which addresses
     problems with vector exhaustion.

   - A large update to the ARM GIC-V3-ITS driver adding support for
     range selectors.

   - New interrupt controllers:
       - Meson and Meson8 GPIO
       - BCM7271 L2
       - Socionext EXIU

     If you expected that this will stop at some point, I have to
     disappoint you. There are new ones posted already. Sigh!

   - STM32 interrupt controller support for new platforms.

   - A pile of fixes, cleanups and updates to the MIPS GIC driver

   - The usual small fixes, cleanups and updates all over the place.
     Most visible one is to move the irq chip drivers Kconfig switches
     into a separate Kconfig menu"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (70 commits)
  genirq: Fix type of shifting literal 1 in __setup_irq()
  irqdomain: Drop pointless NULL check in virq_debug_show_one
  genirq/proc: Return proper error code when irq_set_affinity() fails
  irq/work: Use llist_for_each_entry_safe
  irqchip: mips-gic: Print warning if inherited GIC base is used
  irqchip/mips-gic: Add pr_fmt and reword pr_* messages
  irqchip/stm32: Move the wakeup on interrupt mask
  irqchip/stm32: Fix initial values
  irqchip/stm32: Add stm32h7 support
  dt-bindings/interrupt-controllers: Add compatible string for stm32h7
  irqchip/stm32: Add multi-bank management
  irqchip/stm32: Select GENERIC_IRQ_CHIP
  irqchip/exiu: Add support for Socionext Synquacer EXIU controller
  dt-bindings: Add description of Socionext EXIU interrupt controller
  irqchip/gic-v3-its: Fix VPE activate callback return value
  irqchip: mips-gic: Make IPI bitmaps static
  irqchip: mips-gic: Share register writes in gic_set_type()
  irqchip: mips-gic: Remove gic_vpes variable
  irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs
  irqchip: mips-gic: Configure EIC when CPUs come online
  ...

1 files changed, 19 insertions, 4 deletions

diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c
index 4bff6a10ae8e..2ff1c0c82fc9 100644
--- a/kernel/irq/manage.c
+++ b/kernel/irq/manage.c
@@ -398,7 +398,8 @@ int irq_select_affinity_usr(unsigned int irq)
 /**
  *      irq_set_vcpu_affinity - Set vcpu affinity for the interrupt
  *      @irq: interrupt number to set affinity
- *      @vcpu_info: vCPU specific data
+ *      @vcpu_info: vCPU specific data or pointer to a percpu array of vCPU
+ *                  specific data for percpu_devid interrupts
  *
  *      This function uses the vCPU specific data to set the vCPU
  *      affinity for an irq. The vCPU specific data is passed from
@@ -536,7 +537,7 @@ void __enable_irq(struct irq_desc *desc)
                  * time. If it was already started up, then irq_startup()
                  * will invoke irq_enable() under the hood.
                  */
-                irq_startup(desc, IRQ_RESEND, IRQ_START_COND);
+                irq_startup(desc, IRQ_RESEND, IRQ_START_FORCE);
                 break;
         }
         default:
@@ -1305,7 +1306,7 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new)
                  * thread_mask assigned. See the loop above which or's
                  * all existing action->thread_mask bits.
                  */
-                new->thread_mask = 1 << ffz(thread_mask);
+                new->thread_mask = 1UL << ffz(thread_mask);
 
         } else if (new->handler == irq_default_primary_handler &&
                    !(desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)) {
@@ -1342,6 +1343,21 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new)
                                 goto out_unlock;
                 }
 
+                /*
+                 * Activate the interrupt. That activation must happen
+                 * independently of IRQ_NOAUTOEN. request_irq() can fail
+                 * and the callers are supposed to handle
+                 * that. enable_irq() of an interrupt requested with
+                 * IRQ_NOAUTOEN is not supposed to fail. The activation
+                 * keeps it in shutdown mode, it merily associates
+                 * resources if necessary and if that's not possible it
+                 * fails. Interrupts which are in managed shutdown mode
+                 * will simply ignore that activation request.
+                 */
+                ret = irq_activate(desc);
+                if (ret)
+                        goto out_unlock;
+
                 desc->istate &= ~(IRQS_AUTODETECT | IRQS_SPURIOUS_DISABLED | \
                                   IRQS_ONESHOT | IRQS_WAITING);
                 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
@@ -1417,7 +1433,6 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new)
                 wake_up_process(new->secondary->thread);
 
         register_irq_proc(irq, desc);
-        irq_add_debugfs_entry(irq, desc);
         new->dir = NULL;
         register_handler_proc(irq, new);
         return 0;