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authorMaciej S. Szmigiero <mail@maciej.szmigiero.name>2019-04-29 12:16:55 -0400
committerMauro Carvalho Chehab <mchehab+samsung@kernel.org>2019-05-28 15:55:28 -0400
commite81a9076b4d60351bd574bc1c353793301427635 (patch)
tree0bb31a7a17882200c6b7accebb02027072f0fa5a /include/media
parent763549a3cf121d59d5e9ad078ae71d94be9be748 (diff)
media: cx25840: add pin to pad mapping and output format configuration
This commit adds pin to pad mapping and output format configuration support in CX2584x-series chips to cx25840 driver. This functionality is then used to allow disabling ivtv-specific hacks and configuration values (called a "generic mode"), so cx25840 driver can be used for other devices not needing them without risking compatibility problems. Signed-off-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'include/media')
-rw-r--r--include/media/drv-intf/cx25840.h77
1 files changed, 76 insertions, 1 deletions
diff --git a/include/media/drv-intf/cx25840.h b/include/media/drv-intf/cx25840.h
index 4eae27c163ba..ed8ee1c77a6c 100644
--- a/include/media/drv-intf/cx25840.h
+++ b/include/media/drv-intf/cx25840.h
@@ -82,6 +82,81 @@ enum cx25840_video_input {
82 CX25840_DIF_ON = 0x80000400, 82 CX25840_DIF_ON = 0x80000400,
83}; 83};
84 84
85/*
86 * The defines below are used to set the chip video output settings
87 * in the generic mode that can be enabled by calling the subdevice
88 * init core op.
89 *
90 * The requested settings can be passed to the init core op as
91 * @val parameter and to the s_routing video op as @config parameter.
92 *
93 * For details please refer to the section 3.7 Video Output Formatting and
94 * to Video Out Control 1 to 4 registers in the section 5.6 Video Decoder Core
95 * of the chip datasheet.
96 */
97#define CX25840_VCONFIG_FMT_SHIFT 0
98#define CX25840_VCONFIG_FMT_MASK GENMASK(2, 0)
99#define CX25840_VCONFIG_FMT_BT601 BIT(0)
100#define CX25840_VCONFIG_FMT_BT656 BIT(1)
101#define CX25840_VCONFIG_FMT_VIP11 GENMASK(1, 0)
102#define CX25840_VCONFIG_FMT_VIP2 BIT(2)
103
104#define CX25840_VCONFIG_RES_SHIFT 3
105#define CX25840_VCONFIG_RES_MASK GENMASK(4, 3)
106#define CX25840_VCONFIG_RES_8BIT BIT(3)
107#define CX25840_VCONFIG_RES_10BIT BIT(4)
108
109#define CX25840_VCONFIG_VBIRAW_SHIFT 5
110#define CX25840_VCONFIG_VBIRAW_MASK GENMASK(6, 5)
111#define CX25840_VCONFIG_VBIRAW_DISABLED BIT(5)
112#define CX25840_VCONFIG_VBIRAW_ENABLED BIT(6)
113
114#define CX25840_VCONFIG_ANCDATA_SHIFT 7
115#define CX25840_VCONFIG_ANCDATA_MASK GENMASK(8, 7)
116#define CX25840_VCONFIG_ANCDATA_DISABLED BIT(7)
117#define CX25840_VCONFIG_ANCDATA_ENABLED BIT(8)
118
119#define CX25840_VCONFIG_TASKBIT_SHIFT 9
120#define CX25840_VCONFIG_TASKBIT_MASK GENMASK(10, 9)
121#define CX25840_VCONFIG_TASKBIT_ZERO BIT(9)
122#define CX25840_VCONFIG_TASKBIT_ONE BIT(10)
123
124#define CX25840_VCONFIG_ACTIVE_SHIFT 11
125#define CX25840_VCONFIG_ACTIVE_MASK GENMASK(12, 11)
126#define CX25840_VCONFIG_ACTIVE_COMPOSITE BIT(11)
127#define CX25840_VCONFIG_ACTIVE_HORIZONTAL BIT(12)
128
129#define CX25840_VCONFIG_VALID_SHIFT 13
130#define CX25840_VCONFIG_VALID_MASK GENMASK(14, 13)
131#define CX25840_VCONFIG_VALID_NORMAL BIT(13)
132#define CX25840_VCONFIG_VALID_ANDACTIVE BIT(14)
133
134#define CX25840_VCONFIG_HRESETW_SHIFT 15
135#define CX25840_VCONFIG_HRESETW_MASK GENMASK(16, 15)
136#define CX25840_VCONFIG_HRESETW_NORMAL BIT(15)
137#define CX25840_VCONFIG_HRESETW_PIXCLK BIT(16)
138
139#define CX25840_VCONFIG_CLKGATE_SHIFT 17
140#define CX25840_VCONFIG_CLKGATE_MASK GENMASK(18, 17)
141#define CX25840_VCONFIG_CLKGATE_NONE BIT(17)
142#define CX25840_VCONFIG_CLKGATE_VALID BIT(18)
143#define CX25840_VCONFIG_CLKGATE_VALIDACTIVE GENMASK(18, 17)
144
145#define CX25840_VCONFIG_DCMODE_SHIFT 19
146#define CX25840_VCONFIG_DCMODE_MASK GENMASK(20, 19)
147#define CX25840_VCONFIG_DCMODE_DWORDS BIT(19)
148#define CX25840_VCONFIG_DCMODE_BYTES BIT(20)
149
150#define CX25840_VCONFIG_IDID0S_SHIFT 21
151#define CX25840_VCONFIG_IDID0S_MASK GENMASK(22, 21)
152#define CX25840_VCONFIG_IDID0S_NORMAL BIT(21)
153#define CX25840_VCONFIG_IDID0S_LINECNT BIT(22)
154
155#define CX25840_VCONFIG_VIPCLAMP_SHIFT 23
156#define CX25840_VCONFIG_VIPCLAMP_MASK GENMASK(24, 23)
157#define CX25840_VCONFIG_VIPCLAMP_ENABLED BIT(23)
158#define CX25840_VCONFIG_VIPCLAMP_DISABLED BIT(24)
159
85enum cx25840_audio_input { 160enum cx25840_audio_input {
86 /* Audio inputs: serial or In4-In8 */ 161 /* Audio inputs: serial or In4-In8 */
87 CX25840_AUDIO_SERIAL, 162 CX25840_AUDIO_SERIAL,
@@ -109,7 +184,7 @@ enum cx25840_io_pin {
109}; 184};
110 185
111enum cx25840_io_pad { 186enum cx25840_io_pad {
112 /* Output pads */ 187 /* Output pads, these must match the actual chip register values */
113 CX25840_PAD_DEFAULT = 0, 188 CX25840_PAD_DEFAULT = 0,
114 CX25840_PAD_ACTIVE, 189 CX25840_PAD_ACTIVE,
115 CX25840_PAD_VACTIVE, 190 CX25840_PAD_VACTIVE,