memory: ti-emif-sram: Add ti_emif_run_hw_leveling for DDR3 hardware leveling

In certain situations, such as when returning from low power modes, the
EMIF must re-run hardware leveling to properly restore DDR3 access.

This is accomplished by introducing a new ti-emif-sram-pm call,
ti_emif_run_hw_leveling, to check if DDR3 is in use and if so, trigger
the full write and read leveling processes.

Suggested-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/include/linux/ti-emif-sram.h b/include/linux/ti-emif-sram.h
index 53604b087f2c..2fc854155c27 100644
--- a/include/linux/ti-emif-sram.h
+++ b/include/linux/ti-emif-sram.h
@@ -55,6 +55,7 @@ struct ti_emif_pm_data {
 struct ti_emif_pm_functions {
         u32 save_context;
         u32 restore_context;
+        u32 run_hw_leveling;
         u32 enter_sr;
         u32 exit_sr;
         u32 abort_sr;
@@ -126,6 +127,8 @@ static inline void ti_emif_asm_offsets(void)
                offsetof(struct ti_emif_pm_functions, save_context));
         DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
                offsetof(struct ti_emif_pm_functions, restore_context));
+        DEFINE(EMIF_PM_RUN_HW_LEVELING,
+               offsetof(struct ti_emif_pm_functions, run_hw_leveling));
         DEFINE(EMIF_PM_ENTER_SR_OFFSET,
                offsetof(struct ti_emif_pm_functions, enter_sr));
         DEFINE(EMIF_PM_EXIT_SR_OFFSET,