node: Add memory-side caching attributes

System memory may have caches to help improve access speed to frequently
requested address ranges. While the system provided cache is transparent
to the software accessing these memory ranges, applications can optimize
their own access based on cache attributes.

Provide a new API for the kernel to register these memory-side caches
under the memory node that provides it.

The new sysfs representation is modeled from the existing cpu cacheinfo
attributes, as seen from /sys/devices/system/cpu/<cpu>/cache/.  Unlike CPU
cacheinfo though, the node cache level is reported from the view of the
memory. A higher level number is nearer to the CPU, while lower levels
are closer to the last level memory.

The exported attributes are the cache size, the line size, associativity
indexing, and write back policy, and add the attributes for the system
memory caches to sysfs stable documentation.

Signed-off-by: Keith Busch <keith.busch@intel.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Brice Goglin <Brice.Goglin@inria.fr>
Tested-by: Brice Goglin <Brice.Goglin@inria.fr>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

1 files changed, 39 insertions, 0 deletions

diff --git a/include/linux/node.h b/include/linux/node.h
index 4139d728f8b3..1a557c589ecb 100644
--- a/include/linux/node.h
+++ b/include/linux/node.h
@@ -35,10 +35,45 @@ struct node_hmem_attrs {
         unsigned int write_latency;
 };
 
+enum cache_indexing {
+        NODE_CACHE_DIRECT_MAP,
+        NODE_CACHE_INDEXED,
+        NODE_CACHE_OTHER,
+};
+
+enum cache_write_policy {
+        NODE_CACHE_WRITE_BACK,
+        NODE_CACHE_WRITE_THROUGH,
+        NODE_CACHE_WRITE_OTHER,
+};
+
+/**
+ * struct node_cache_attrs - system memory caching attributes
+ *
+ * @indexing:           The ways memory blocks may be placed in cache
+ * @write_policy:       Write back or write through policy
+ * @size:               Total size of cache in bytes
+ * @line_size:          Number of bytes fetched on a cache miss
+ * @level:              The cache hierarchy level
+ */
+struct node_cache_attrs {
+        enum cache_indexing indexing;
+        enum cache_write_policy write_policy;
+        u64 size;
+        u16 line_size;
+        u8 level;
+};
+
 #ifdef CONFIG_HMEM_REPORTING
+void node_add_cache(unsigned int nid, struct node_cache_attrs *cache_attrs);
 void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs,
                          unsigned access);
 #else
+static inline void node_add_cache(unsigned int nid,
+                                  struct node_cache_attrs *cache_attrs)
+{
+}
+
 static inline void node_set_perf_attrs(unsigned int nid,
                                        struct node_hmem_attrs *hmem_attrs,
                                        unsigned access)
@@ -53,6 +88,10 @@ struct node {
 #if defined(CONFIG_MEMORY_HOTPLUG_SPARSE) && defined(CONFIG_HUGETLBFS)
         struct work_struct      node_work;
 #endif
+#ifdef CONFIG_HMEM_REPORTING
+        struct list_head cache_attrs;
+        struct device *cache_dev;
+#endif
 };
 
 struct memory_block;