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authorLinus Torvalds <torvalds@linux-foundation.org>2019-07-15 23:18:40 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2019-07-15 23:18:40 -0400
commit8de262531f5fbb7458463224a7587429800c24bf (patch)
treec95d1d2bdeaff95cea17982f1c0e1e552591e40f /include/linux/mfd
parentbe8454afc50f43016ca8b6130d9673bdd0bd56ec (diff)
parent7efd105c27fd2323789b41b64763a0e33ed79c08 (diff)
Merge tag 'mfd-next-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones: "Core Frameworks: - Set 'struct device' fwnode when registering a new device New Drivers: - Add support for ROHM BD70528 PMIC New Device Support: - Add support for LP87561 4-Phase Regulator to TI LP87565 PMIC - Add support for RK809 and RK817 to Rockchip RK808 - Add support for Lid Angle to ChromeOS core - Add support for CS47L15 CODEC to Madera core - Add support for CS47L92 CODEC to Madera core - Add support for ChromeOS (legacy) Accelerometers in ChromeOS core - Add support for Add Intel Elkhart Lake PCH to Intel LPSS New Functionality: - Provide regulator supply information when registering; madera-core - Additional Device Tree support; lp87565, madera, cros-ec, rohm,bd71837-pmic - Allow over-riding power button press via Device Tree; rohm-bd718x7 - Differentiate between running processors; cros_ec_dev Fix-ups: - Big header file update; cros_ec_commands.h - Split header per-subsystem; rohm-bd718x7 - Remove superfluous code; menelaus, cs5535-mfd, cs47lXX-tables - Trivial; sorting, coding style; intel-lpss-pci - Only remove Power Off functionality if set locally; rk808 - Make use for Power Off Prepare(); rk808 - Fix spelling mistake in header guards; stmfx - Properly free IDA resources - SPDX fixups; cs47lXX-tables, madera - Error path fixups; hi655x-pmic Bug Fixes: - Add missing break in case() statement - Repair undefined behaviour when not initialising variables; arizona-core, madera-core - Fix reference to Device Tree documentation; madera" * tag 'mfd-next-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (45 commits) mfd: hi655x-pmic: Fix missing return value check for devm_regmap_init_mmio_clk mfd: madera: Fixup SPDX headers mfd: madera: Remove some unused registers and fix some defaults mfd: intel-lpss: Release IDA resources mfd: intel-lpss: Add Intel Elkhart Lake PCH PCI IDs mfd: cs5535-mfd: Remove ifdef OLPC noise mfd: stmfx: Fix macro definition spelling dt-bindings: mfd: Add link to ROHM BD71847 Datasheet MAINAINERS: Swap words in INTEL PMIC MULTIFUNCTION DEVICE DRIVERS mfd: cros_ec_dev: Register cros_ec_accel_legacy driver as a subdevice mfd: rk808: Prepare rk805 for poweroff mfd: rk808: Check pm_power_off pointer mfd: cros_ec: differentiate SCP from EC by feature bit dt-bindings: Add binding for cros-ec-rpmsg mfd: madera: Add Madera core support for CS47L92 mfd: madera: Add Madera core support for CS47L15 mfd: madera: Update DT bindings to add additional CODECs mfd: madera: Add supply mapping for MICVDD mfd: madera: Fix potential uninitialised use of variable mfd: madera: Fix bad reference to pinctrl.txt file ...
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/cros_ec.h1
-rw-r--r--include/linux/mfd/lp87565.h2
-rw-r--r--include/linux/mfd/madera/core.h12
-rw-r--r--include/linux/mfd/madera/pdata.h9
-rw-r--r--include/linux/mfd/madera/registers.h286
-rw-r--r--include/linux/mfd/rk808.h177
-rw-r--r--include/linux/mfd/rohm-bd70528.h408
-rw-r--r--include/linux/mfd/rohm-bd718x7.h22
-rw-r--r--include/linux/mfd/rohm-generic.h20
-rw-r--r--include/linux/mfd/stmfx.h2
10 files changed, 828 insertions, 111 deletions
diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h
index 45aba26db964..77805c3f2de7 100644
--- a/include/linux/mfd/cros_ec.h
+++ b/include/linux/mfd/cros_ec.h
@@ -19,6 +19,7 @@
19#define CROS_EC_DEV_PD_NAME "cros_pd" 19#define CROS_EC_DEV_PD_NAME "cros_pd"
20#define CROS_EC_DEV_TP_NAME "cros_tp" 20#define CROS_EC_DEV_TP_NAME "cros_tp"
21#define CROS_EC_DEV_ISH_NAME "cros_ish" 21#define CROS_EC_DEV_ISH_NAME "cros_ish"
22#define CROS_EC_DEV_SCP_NAME "cros_scp"
22 23
23/* 24/*
24 * The EC is unresponsive for a time after a reboot command. Add a 25 * The EC is unresponsive for a time after a reboot command. Add a
diff --git a/include/linux/mfd/lp87565.h b/include/linux/mfd/lp87565.h
index e619def115b4..ce965354bbad 100644
--- a/include/linux/mfd/lp87565.h
+++ b/include/linux/mfd/lp87565.h
@@ -14,6 +14,7 @@
14 14
15enum lp87565_device_type { 15enum lp87565_device_type {
16 LP87565_DEVICE_TYPE_UNKNOWN = 0, 16 LP87565_DEVICE_TYPE_UNKNOWN = 0,
17 LP87565_DEVICE_TYPE_LP87561_Q1,
17 LP87565_DEVICE_TYPE_LP87565_Q1, 18 LP87565_DEVICE_TYPE_LP87565_Q1,
18}; 19};
19 20
@@ -246,6 +247,7 @@ enum LP87565_regulator_id {
246 LP87565_BUCK_3, 247 LP87565_BUCK_3,
247 LP87565_BUCK_10, 248 LP87565_BUCK_10,
248 LP87565_BUCK_23, 249 LP87565_BUCK_23,
250 LP87565_BUCK_3210,
249}; 251};
250 252
251/** 253/**
diff --git a/include/linux/mfd/madera/core.h b/include/linux/mfd/madera/core.h
index 4d5d51a9c8a6..7ffa696cce7c 100644
--- a/include/linux/mfd/madera/core.h
+++ b/include/linux/mfd/madera/core.h
@@ -1,12 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0 1/* SPDX-License-Identifier: GPL-2.0-only */
2/* 2/*
3 * MFD internals for Cirrus Logic Madera codecs 3 * MFD internals for Cirrus Logic Madera codecs
4 * 4 *
5 * Copyright (C) 2015-2018 Cirrus Logic 5 * Copyright (C) 2015-2018 Cirrus Logic
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; version 2.
10 */ 6 */
11 7
12#ifndef MADERA_CORE_H 8#ifndef MADERA_CORE_H
@@ -26,15 +22,21 @@ enum madera_type {
26 CS47L85 = 2, 22 CS47L85 = 2,
27 CS47L90 = 3, 23 CS47L90 = 3,
28 CS47L91 = 4, 24 CS47L91 = 4,
25 CS47L92 = 5,
26 CS47L93 = 6,
29 WM1840 = 7, 27 WM1840 = 7,
28 CS47L15 = 8,
29 CS42L92 = 9,
30}; 30};
31 31
32#define MADERA_MAX_CORE_SUPPLIES 2 32#define MADERA_MAX_CORE_SUPPLIES 2
33#define MADERA_MAX_GPIOS 40 33#define MADERA_MAX_GPIOS 40
34 34
35#define CS47L15_NUM_GPIOS 15
35#define CS47L35_NUM_GPIOS 16 36#define CS47L35_NUM_GPIOS 16
36#define CS47L85_NUM_GPIOS 40 37#define CS47L85_NUM_GPIOS 40
37#define CS47L90_NUM_GPIOS 38 38#define CS47L90_NUM_GPIOS 38
39#define CS47L92_NUM_GPIOS 16
38 40
39#define MADERA_MAX_MICBIAS 4 41#define MADERA_MAX_MICBIAS 4
40 42
diff --git a/include/linux/mfd/madera/pdata.h b/include/linux/mfd/madera/pdata.h
index 60cd8ec98563..fa9595dd42ba 100644
--- a/include/linux/mfd/madera/pdata.h
+++ b/include/linux/mfd/madera/pdata.h
@@ -1,12 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0 1/* SPDX-License-Identifier: GPL-2.0-only */
2/* 2/*
3 * Platform data for Cirrus Logic Madera codecs 3 * Platform data for Cirrus Logic Madera codecs
4 * 4 *
5 * Copyright (C) 2015-2018 Cirrus Logic 5 * Copyright (C) 2015-2018 Cirrus Logic
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; version 2.
10 */ 6 */
11 7
12#ifndef MADERA_PDATA_H 8#ifndef MADERA_PDATA_H
@@ -35,7 +31,8 @@ struct madera_codec_pdata;
35 * @micvdd: Substruct of pdata for the MICVDD regulator 31 * @micvdd: Substruct of pdata for the MICVDD regulator
36 * @irq_flags: Mode for primary IRQ (defaults to active low) 32 * @irq_flags: Mode for primary IRQ (defaults to active low)
37 * @gpio_base: Base GPIO number 33 * @gpio_base: Base GPIO number
38 * @gpio_configs: Array of GPIO configurations (See Documentation/pinctrl.txt) 34 * @gpio_configs: Array of GPIO configurations (See
35 * Documentation/driver-api/pinctl.rst)
39 * @n_gpio_configs: Number of entries in gpio_configs 36 * @n_gpio_configs: Number of entries in gpio_configs
40 * @gpsw: General purpose switch mode setting. Depends on the external 37 * @gpsw: General purpose switch mode setting. Depends on the external
41 * hardware connected to the switch. (See the SW1_MODE field 38 * hardware connected to the switch. (See the SW1_MODE field
diff --git a/include/linux/mfd/madera/registers.h b/include/linux/mfd/madera/registers.h
index 977e06101711..fe909d177762 100644
--- a/include/linux/mfd/madera/registers.h
+++ b/include/linux/mfd/madera/registers.h
@@ -1,12 +1,8 @@
1// SPDX-License-Identifier: GPL-2.0 1/* SPDX-License-Identifier: GPL-2.0-only */
2/* 2/*
3 * Madera register definitions 3 * Madera register definitions
4 * 4 *
5 * Copyright (C) 2015-2018 Cirrus Logic 5 * Copyright (C) 2015-2018 Cirrus Logic
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; version 2.
10 */ 6 */
11 7
12#ifndef MADERA_REGISTERS_H 8#ifndef MADERA_REGISTERS_H
@@ -76,10 +72,14 @@
76#define MADERA_FLL1_CONTROL_4 0x174 72#define MADERA_FLL1_CONTROL_4 0x174
77#define MADERA_FLL1_CONTROL_5 0x175 73#define MADERA_FLL1_CONTROL_5 0x175
78#define MADERA_FLL1_CONTROL_6 0x176 74#define MADERA_FLL1_CONTROL_6 0x176
79#define MADERA_FLL1_LOOP_FILTER_TEST_1 0x177 75#define CS47L92_FLL1_CONTROL_7 0x177
80#define MADERA_FLL1_NCO_TEST_0 0x178 76#define CS47L92_FLL1_CONTROL_8 0x178
81#define MADERA_FLL1_CONTROL_7 0x179 77#define MADERA_FLL1_CONTROL_7 0x179
78#define CS47L92_FLL1_CONTROL_9 0x179
82#define MADERA_FLL1_EFS_2 0x17A 79#define MADERA_FLL1_EFS_2 0x17A
80#define CS47L92_FLL1_CONTROL_10 0x17A
81#define MADERA_FLL1_CONTROL_11 0x17B
82#define MADERA_FLL1_DIGITAL_TEST_1 0x17D
83#define CS47L35_FLL1_SYNCHRONISER_1 0x17F 83#define CS47L35_FLL1_SYNCHRONISER_1 0x17F
84#define CS47L35_FLL1_SYNCHRONISER_2 0x180 84#define CS47L35_FLL1_SYNCHRONISER_2 0x180
85#define CS47L35_FLL1_SYNCHRONISER_3 0x181 85#define CS47L35_FLL1_SYNCHRONISER_3 0x181
@@ -98,16 +98,21 @@
98#define MADERA_FLL1_SYNCHRONISER_7 0x187 98#define MADERA_FLL1_SYNCHRONISER_7 0x187
99#define MADERA_FLL1_SPREAD_SPECTRUM 0x189 99#define MADERA_FLL1_SPREAD_SPECTRUM 0x189
100#define MADERA_FLL1_GPIO_CLOCK 0x18A 100#define MADERA_FLL1_GPIO_CLOCK 0x18A
101#define CS47L92_FLL1_GPIO_CLOCK 0x18E
101#define MADERA_FLL2_CONTROL_1 0x191 102#define MADERA_FLL2_CONTROL_1 0x191
102#define MADERA_FLL2_CONTROL_2 0x192 103#define MADERA_FLL2_CONTROL_2 0x192
103#define MADERA_FLL2_CONTROL_3 0x193 104#define MADERA_FLL2_CONTROL_3 0x193
104#define MADERA_FLL2_CONTROL_4 0x194 105#define MADERA_FLL2_CONTROL_4 0x194
105#define MADERA_FLL2_CONTROL_5 0x195 106#define MADERA_FLL2_CONTROL_5 0x195
106#define MADERA_FLL2_CONTROL_6 0x196 107#define MADERA_FLL2_CONTROL_6 0x196
107#define MADERA_FLL2_LOOP_FILTER_TEST_1 0x197 108#define CS47L92_FLL2_CONTROL_7 0x197
108#define MADERA_FLL2_NCO_TEST_0 0x198 109#define CS47L92_FLL2_CONTROL_8 0x198
109#define MADERA_FLL2_CONTROL_7 0x199 110#define MADERA_FLL2_CONTROL_7 0x199
111#define CS47L92_FLL2_CONTROL_9 0x199
110#define MADERA_FLL2_EFS_2 0x19A 112#define MADERA_FLL2_EFS_2 0x19A
113#define CS47L92_FLL2_CONTROL_10 0x19A
114#define MADERA_FLL2_CONTROL_11 0x19B
115#define MADERA_FLL2_DIGITAL_TEST_1 0x19D
111#define MADERA_FLL2_SYNCHRONISER_1 0x1A1 116#define MADERA_FLL2_SYNCHRONISER_1 0x1A1
112#define MADERA_FLL2_SYNCHRONISER_2 0x1A2 117#define MADERA_FLL2_SYNCHRONISER_2 0x1A2
113#define MADERA_FLL2_SYNCHRONISER_3 0x1A3 118#define MADERA_FLL2_SYNCHRONISER_3 0x1A3
@@ -117,14 +122,13 @@
117#define MADERA_FLL2_SYNCHRONISER_7 0x1A7 122#define MADERA_FLL2_SYNCHRONISER_7 0x1A7
118#define MADERA_FLL2_SPREAD_SPECTRUM 0x1A9 123#define MADERA_FLL2_SPREAD_SPECTRUM 0x1A9
119#define MADERA_FLL2_GPIO_CLOCK 0x1AA 124#define MADERA_FLL2_GPIO_CLOCK 0x1AA
125#define CS47L92_FLL2_GPIO_CLOCK 0x1AE
120#define MADERA_FLL3_CONTROL_1 0x1B1 126#define MADERA_FLL3_CONTROL_1 0x1B1
121#define MADERA_FLL3_CONTROL_2 0x1B2 127#define MADERA_FLL3_CONTROL_2 0x1B2
122#define MADERA_FLL3_CONTROL_3 0x1B3 128#define MADERA_FLL3_CONTROL_3 0x1B3
123#define MADERA_FLL3_CONTROL_4 0x1B4 129#define MADERA_FLL3_CONTROL_4 0x1B4
124#define MADERA_FLL3_CONTROL_5 0x1B5 130#define MADERA_FLL3_CONTROL_5 0x1B5
125#define MADERA_FLL3_CONTROL_6 0x1B6 131#define MADERA_FLL3_CONTROL_6 0x1B6
126#define MADERA_FLL3_LOOP_FILTER_TEST_1 0x1B7
127#define MADERA_FLL3_NCO_TEST_0 0x1B8
128#define MADERA_FLL3_CONTROL_7 0x1B9 132#define MADERA_FLL3_CONTROL_7 0x1B9
129#define MADERA_FLL3_SYNCHRONISER_1 0x1C1 133#define MADERA_FLL3_SYNCHRONISER_1 0x1C1
130#define MADERA_FLL3_SYNCHRONISER_2 0x1C2 134#define MADERA_FLL3_SYNCHRONISER_2 0x1C2
@@ -244,6 +248,8 @@
244#define MADERA_IN6R_CONTROL 0x33C 248#define MADERA_IN6R_CONTROL 0x33C
245#define MADERA_ADC_DIGITAL_VOLUME_6R 0x33D 249#define MADERA_ADC_DIGITAL_VOLUME_6R 0x33D
246#define MADERA_DMIC6R_CONTROL 0x33E 250#define MADERA_DMIC6R_CONTROL 0x33E
251#define CS47L15_ADC_INT_BIAS 0x3A8
252#define CS47L15_PGA_BIAS_SEL 0x3C4
247#define MADERA_OUTPUT_ENABLES_1 0x400 253#define MADERA_OUTPUT_ENABLES_1 0x400
248#define MADERA_OUTPUT_STATUS_1 0x401 254#define MADERA_OUTPUT_STATUS_1 0x401
249#define MADERA_RAW_OUTPUT_STATUS_1 0x406 255#define MADERA_RAW_OUTPUT_STATUS_1 0x406
@@ -265,6 +271,7 @@
265#define MADERA_NOISE_GATE_SELECT_2R 0x41F 271#define MADERA_NOISE_GATE_SELECT_2R 0x41F
266#define MADERA_OUTPUT_PATH_CONFIG_3L 0x420 272#define MADERA_OUTPUT_PATH_CONFIG_3L 0x420
267#define MADERA_DAC_DIGITAL_VOLUME_3L 0x421 273#define MADERA_DAC_DIGITAL_VOLUME_3L 0x421
274#define MADERA_OUTPUT_PATH_CONFIG_3 0x422
268#define MADERA_NOISE_GATE_SELECT_3L 0x423 275#define MADERA_NOISE_GATE_SELECT_3L 0x423
269#define MADERA_OUTPUT_PATH_CONFIG_3R 0x424 276#define MADERA_OUTPUT_PATH_CONFIG_3R 0x424
270#define MADERA_DAC_DIGITAL_VOLUME_3R 0x425 277#define MADERA_DAC_DIGITAL_VOLUME_3R 0x425
@@ -287,9 +294,6 @@
287#define MADERA_OUTPUT_PATH_CONFIG_6R 0x43C 294#define MADERA_OUTPUT_PATH_CONFIG_6R 0x43C
288#define MADERA_DAC_DIGITAL_VOLUME_6R 0x43D 295#define MADERA_DAC_DIGITAL_VOLUME_6R 0x43D
289#define MADERA_NOISE_GATE_SELECT_6R 0x43F 296#define MADERA_NOISE_GATE_SELECT_6R 0x43F
290#define MADERA_DRE_ENABLE 0x440
291#define MADERA_EDRE_ENABLE 0x448
292#define MADERA_EDRE_MANUAL 0x44A
293#define MADERA_DAC_AEC_CONTROL_1 0x450 297#define MADERA_DAC_AEC_CONTROL_1 0x450
294#define MADERA_DAC_AEC_CONTROL_2 0x451 298#define MADERA_DAC_AEC_CONTROL_2 0x451
295#define MADERA_NOISE_GATE_CONTROL 0x458 299#define MADERA_NOISE_GATE_CONTROL 0x458
@@ -367,8 +371,20 @@
367#define MADERA_AIF3_FRAME_CTRL_2 0x588 371#define MADERA_AIF3_FRAME_CTRL_2 0x588
368#define MADERA_AIF3_FRAME_CTRL_3 0x589 372#define MADERA_AIF3_FRAME_CTRL_3 0x589
369#define MADERA_AIF3_FRAME_CTRL_4 0x58A 373#define MADERA_AIF3_FRAME_CTRL_4 0x58A
374#define MADERA_AIF3_FRAME_CTRL_5 0x58B
375#define MADERA_AIF3_FRAME_CTRL_6 0x58C
376#define MADERA_AIF3_FRAME_CTRL_7 0x58D
377#define MADERA_AIF3_FRAME_CTRL_8 0x58E
378#define MADERA_AIF3_FRAME_CTRL_9 0x58F
379#define MADERA_AIF3_FRAME_CTRL_10 0x590
370#define MADERA_AIF3_FRAME_CTRL_11 0x591 380#define MADERA_AIF3_FRAME_CTRL_11 0x591
371#define MADERA_AIF3_FRAME_CTRL_12 0x592 381#define MADERA_AIF3_FRAME_CTRL_12 0x592
382#define MADERA_AIF3_FRAME_CTRL_13 0x593
383#define MADERA_AIF3_FRAME_CTRL_14 0x594
384#define MADERA_AIF3_FRAME_CTRL_15 0x595
385#define MADERA_AIF3_FRAME_CTRL_16 0x596
386#define MADERA_AIF3_FRAME_CTRL_17 0x597
387#define MADERA_AIF3_FRAME_CTRL_18 0x598
372#define MADERA_AIF3_TX_ENABLES 0x599 388#define MADERA_AIF3_TX_ENABLES 0x599
373#define MADERA_AIF3_RX_ENABLES 0x59A 389#define MADERA_AIF3_RX_ENABLES 0x59A
374#define MADERA_AIF3_FORCE_WRITE 0x59B 390#define MADERA_AIF3_FORCE_WRITE 0x59B
@@ -660,6 +676,54 @@
660#define MADERA_AIF3TX2MIX_INPUT_3_VOLUME 0x78D 676#define MADERA_AIF3TX2MIX_INPUT_3_VOLUME 0x78D
661#define MADERA_AIF3TX2MIX_INPUT_4_SOURCE 0x78E 677#define MADERA_AIF3TX2MIX_INPUT_4_SOURCE 0x78E
662#define MADERA_AIF3TX2MIX_INPUT_4_VOLUME 0x78F 678#define MADERA_AIF3TX2MIX_INPUT_4_VOLUME 0x78F
679#define MADERA_AIF3TX3MIX_INPUT_1_SOURCE 0x790
680#define MADERA_AIF3TX3MIX_INPUT_1_VOLUME 0x791
681#define MADERA_AIF3TX3MIX_INPUT_2_SOURCE 0x792
682#define MADERA_AIF3TX3MIX_INPUT_2_VOLUME 0x793
683#define MADERA_AIF3TX3MIX_INPUT_3_SOURCE 0x794
684#define MADERA_AIF3TX3MIX_INPUT_3_VOLUME 0x795
685#define MADERA_AIF3TX3MIX_INPUT_4_SOURCE 0x796
686#define MADERA_AIF3TX3MIX_INPUT_4_VOLUME 0x797
687#define MADERA_AIF3TX4MIX_INPUT_1_SOURCE 0x798
688#define MADERA_AIF3TX4MIX_INPUT_1_VOLUME 0x799
689#define MADERA_AIF3TX4MIX_INPUT_2_SOURCE 0x79A
690#define MADERA_AIF3TX4MIX_INPUT_2_VOLUME 0x79B
691#define MADERA_AIF3TX4MIX_INPUT_3_SOURCE 0x79C
692#define MADERA_AIF3TX4MIX_INPUT_3_VOLUME 0x79D
693#define MADERA_AIF3TX4MIX_INPUT_4_SOURCE 0x79E
694#define MADERA_AIF3TX4MIX_INPUT_4_VOLUME 0x79F
695#define CS47L92_AIF3TX5MIX_INPUT_1_SOURCE 0x7A0
696#define CS47L92_AIF3TX5MIX_INPUT_1_VOLUME 0x7A1
697#define CS47L92_AIF3TX5MIX_INPUT_2_SOURCE 0x7A2
698#define CS47L92_AIF3TX5MIX_INPUT_2_VOLUME 0x7A3
699#define CS47L92_AIF3TX5MIX_INPUT_3_SOURCE 0x7A4
700#define CS47L92_AIF3TX5MIX_INPUT_3_VOLUME 0x7A5
701#define CS47L92_AIF3TX5MIX_INPUT_4_SOURCE 0x7A6
702#define CS47L92_AIF3TX5MIX_INPUT_4_VOLUME 0x7A7
703#define CS47L92_AIF3TX6MIX_INPUT_1_SOURCE 0x7A8
704#define CS47L92_AIF3TX6MIX_INPUT_1_VOLUME 0x7A9
705#define CS47L92_AIF3TX6MIX_INPUT_2_SOURCE 0x7AA
706#define CS47L92_AIF3TX6MIX_INPUT_2_VOLUME 0x7AB
707#define CS47L92_AIF3TX6MIX_INPUT_3_SOURCE 0x7AC
708#define CS47L92_AIF3TX6MIX_INPUT_3_VOLUME 0x7AD
709#define CS47L92_AIF3TX6MIX_INPUT_4_SOURCE 0x7AE
710#define CS47L92_AIF3TX6MIX_INPUT_4_VOLUME 0x7AF
711#define CS47L92_AIF3TX7MIX_INPUT_1_SOURCE 0x7B0
712#define CS47L92_AIF3TX7MIX_INPUT_1_VOLUME 0x7B1
713#define CS47L92_AIF3TX7MIX_INPUT_2_SOURCE 0x7B2
714#define CS47L92_AIF3TX7MIX_INPUT_2_VOLUME 0x7B3
715#define CS47L92_AIF3TX7MIX_INPUT_3_SOURCE 0x7B4
716#define CS47L92_AIF3TX7MIX_INPUT_3_VOLUME 0x7B5
717#define CS47L92_AIF3TX7MIX_INPUT_4_SOURCE 0x7B6
718#define CS47L92_AIF3TX7MIX_INPUT_4_VOLUME 0x7B7
719#define CS47L92_AIF3TX8MIX_INPUT_1_SOURCE 0x7B8
720#define CS47L92_AIF3TX8MIX_INPUT_1_VOLUME 0x7B9
721#define CS47L92_AIF3TX8MIX_INPUT_2_SOURCE 0x7BA
722#define CS47L92_AIF3TX8MIX_INPUT_2_VOLUME 0x7BB
723#define CS47L92_AIF3TX8MIX_INPUT_3_SOURCE 0x7BC
724#define CS47L92_AIF3TX8MIX_INPUT_3_VOLUME 0x7BD
725#define CS47L92_AIF3TX8MIX_INPUT_4_SOURCE 0x7BE
726#define CS47L92_AIF3TX8MIX_INPUT_4_VOLUME 0x7BF
663#define MADERA_AIF4TX1MIX_INPUT_1_SOURCE 0x7A0 727#define MADERA_AIF4TX1MIX_INPUT_1_SOURCE 0x7A0
664#define MADERA_AIF4TX1MIX_INPUT_1_VOLUME 0x7A1 728#define MADERA_AIF4TX1MIX_INPUT_1_VOLUME 0x7A1
665#define MADERA_AIF4TX1MIX_INPUT_2_SOURCE 0x7A2 729#define MADERA_AIF4TX1MIX_INPUT_2_SOURCE 0x7A2
@@ -1103,68 +1167,8 @@
1103#define MADERA_FCR_ADC_REFORMATTER_CONTROL 0xF73 1167#define MADERA_FCR_ADC_REFORMATTER_CONTROL 0xF73
1104#define MADERA_FCR_COEFF_START 0xF74 1168#define MADERA_FCR_COEFF_START 0xF74
1105#define MADERA_FCR_COEFF_END 0xFC5 1169#define MADERA_FCR_COEFF_END 0xFC5
1106#define MADERA_DAC_COMP_1 0x1300 1170#define MADERA_AUXPDM1_CTRL_0 0x10C0
1107#define MADERA_DAC_COMP_2 0x1302 1171#define MADERA_AUXPDM1_CTRL_1 0x10C1
1108#define MADERA_FRF_COEFFICIENT_1L_1 0x1380
1109#define MADERA_FRF_COEFFICIENT_1L_2 0x1381
1110#define MADERA_FRF_COEFFICIENT_1L_3 0x1382
1111#define MADERA_FRF_COEFFICIENT_1L_4 0x1383
1112#define MADERA_FRF_COEFFICIENT_1R_1 0x1390
1113#define MADERA_FRF_COEFFICIENT_1R_2 0x1391
1114#define MADERA_FRF_COEFFICIENT_1R_3 0x1392
1115#define MADERA_FRF_COEFFICIENT_1R_4 0x1393
1116#define MADERA_FRF_COEFFICIENT_2L_1 0x13A0
1117#define MADERA_FRF_COEFFICIENT_2L_2 0x13A1
1118#define MADERA_FRF_COEFFICIENT_2L_3 0x13A2
1119#define MADERA_FRF_COEFFICIENT_2L_4 0x13A3
1120#define MADERA_FRF_COEFFICIENT_2R_1 0x13B0
1121#define MADERA_FRF_COEFFICIENT_2R_2 0x13B1
1122#define MADERA_FRF_COEFFICIENT_2R_3 0x13B2
1123#define MADERA_FRF_COEFFICIENT_2R_4 0x13B3
1124#define MADERA_FRF_COEFFICIENT_3L_1 0x13C0
1125#define MADERA_FRF_COEFFICIENT_3L_2 0x13C1
1126#define MADERA_FRF_COEFFICIENT_3L_3 0x13C2
1127#define MADERA_FRF_COEFFICIENT_3L_4 0x13C3
1128#define MADERA_FRF_COEFFICIENT_3R_1 0x13D0
1129#define MADERA_FRF_COEFFICIENT_3R_2 0x13D1
1130#define MADERA_FRF_COEFFICIENT_3R_3 0x13D2
1131#define MADERA_FRF_COEFFICIENT_3R_4 0x13D3
1132#define MADERA_FRF_COEFFICIENT_4L_1 0x13E0
1133#define MADERA_FRF_COEFFICIENT_4L_2 0x13E1
1134#define MADERA_FRF_COEFFICIENT_4L_3 0x13E2
1135#define MADERA_FRF_COEFFICIENT_4L_4 0x13E3
1136#define MADERA_FRF_COEFFICIENT_4R_1 0x13F0
1137#define MADERA_FRF_COEFFICIENT_4R_2 0x13F1
1138#define MADERA_FRF_COEFFICIENT_4R_3 0x13F2
1139#define MADERA_FRF_COEFFICIENT_4R_4 0x13F3
1140#define CS47L35_FRF_COEFFICIENT_4L_1 0x13A0
1141#define CS47L35_FRF_COEFFICIENT_4L_2 0x13A1
1142#define CS47L35_FRF_COEFFICIENT_4L_3 0x13A2
1143#define CS47L35_FRF_COEFFICIENT_4L_4 0x13A3
1144#define CS47L35_FRF_COEFFICIENT_5L_1 0x13B0
1145#define CS47L35_FRF_COEFFICIENT_5L_2 0x13B1
1146#define CS47L35_FRF_COEFFICIENT_5L_3 0x13B2
1147#define CS47L35_FRF_COEFFICIENT_5L_4 0x13B3
1148#define CS47L35_FRF_COEFFICIENT_5R_1 0x13C0
1149#define CS47L35_FRF_COEFFICIENT_5R_2 0x13C1
1150#define CS47L35_FRF_COEFFICIENT_5R_3 0x13C2
1151#define CS47L35_FRF_COEFFICIENT_5R_4 0x13C3
1152#define MADERA_FRF_COEFFICIENT_5L_1 0x1400
1153#define MADERA_FRF_COEFFICIENT_5L_2 0x1401
1154#define MADERA_FRF_COEFFICIENT_5L_3 0x1402
1155#define MADERA_FRF_COEFFICIENT_5L_4 0x1403
1156#define MADERA_FRF_COEFFICIENT_5R_1 0x1410
1157#define MADERA_FRF_COEFFICIENT_5R_2 0x1411
1158#define MADERA_FRF_COEFFICIENT_5R_3 0x1412
1159#define MADERA_FRF_COEFFICIENT_5R_4 0x1413
1160#define MADERA_FRF_COEFFICIENT_6L_1 0x1420
1161#define MADERA_FRF_COEFFICIENT_6L_2 0x1421
1162#define MADERA_FRF_COEFFICIENT_6L_3 0x1422
1163#define MADERA_FRF_COEFFICIENT_6L_4 0x1423
1164#define MADERA_FRF_COEFFICIENT_6R_1 0x1430
1165#define MADERA_FRF_COEFFICIENT_6R_2 0x1431
1166#define MADERA_FRF_COEFFICIENT_6R_3 0x1432
1167#define MADERA_FRF_COEFFICIENT_6R_4 0x1433
1168#define MADERA_DFC1_CTRL 0x1480 1172#define MADERA_DFC1_CTRL 0x1480
1169#define MADERA_DFC1_RX 0x1482 1173#define MADERA_DFC1_RX 0x1482
1170#define MADERA_DFC1_TX 0x1484 1174#define MADERA_DFC1_TX 0x1484
@@ -1202,6 +1206,8 @@
1202#define MADERA_GPIO1_CTRL_2 0x1701 1206#define MADERA_GPIO1_CTRL_2 0x1701
1203#define MADERA_GPIO2_CTRL_1 0x1702 1207#define MADERA_GPIO2_CTRL_1 0x1702
1204#define MADERA_GPIO2_CTRL_2 0x1703 1208#define MADERA_GPIO2_CTRL_2 0x1703
1209#define MADERA_GPIO15_CTRL_1 0x171C
1210#define MADERA_GPIO15_CTRL_2 0x171D
1205#define MADERA_GPIO16_CTRL_1 0x171E 1211#define MADERA_GPIO16_CTRL_1 0x171E
1206#define MADERA_GPIO16_CTRL_2 0x171F 1212#define MADERA_GPIO16_CTRL_2 0x171F
1207#define MADERA_GPIO38_CTRL_1 0x174A 1213#define MADERA_GPIO38_CTRL_1 0x174A
@@ -1232,6 +1238,7 @@
1232#define MADERA_IRQ2_CTRL 0x1A82 1238#define MADERA_IRQ2_CTRL 0x1A82
1233#define MADERA_INTERRUPT_RAW_STATUS_1 0x1AA0 1239#define MADERA_INTERRUPT_RAW_STATUS_1 0x1AA0
1234#define MADERA_WSEQ_SEQUENCE_1 0x3000 1240#define MADERA_WSEQ_SEQUENCE_1 0x3000
1241#define MADERA_WSEQ_SEQUENCE_225 0x31C0
1235#define MADERA_WSEQ_SEQUENCE_252 0x31F6 1242#define MADERA_WSEQ_SEQUENCE_252 0x31F6
1236#define CS47L35_OTP_HPDET_CAL_1 0x31F8 1243#define CS47L35_OTP_HPDET_CAL_1 0x31F8
1237#define CS47L35_OTP_HPDET_CAL_2 0x31FA 1244#define CS47L35_OTP_HPDET_CAL_2 0x31FA
@@ -1441,6 +1448,12 @@
1441#define MADERA_OPCLK_ASYNC_SEL_WIDTH 3 1448#define MADERA_OPCLK_ASYNC_SEL_WIDTH 3
1442 1449
1443/* (0x0171) FLL1_Control_1 */ 1450/* (0x0171) FLL1_Control_1 */
1451#define CS47L92_FLL1_REFCLK_SRC_MASK 0xF000
1452#define CS47L92_FLL1_REFCLK_SRC_SHIFT 12
1453#define CS47L92_FLL1_REFCLK_SRC_WIDTH 4
1454#define MADERA_FLL1_HOLD_MASK 0x0004
1455#define MADERA_FLL1_HOLD_SHIFT 2
1456#define MADERA_FLL1_HOLD_WIDTH 1
1444#define MADERA_FLL1_FREERUN 0x0002 1457#define MADERA_FLL1_FREERUN 0x0002
1445#define MADERA_FLL1_FREERUN_MASK 0x0002 1458#define MADERA_FLL1_FREERUN_MASK 0x0002
1446#define MADERA_FLL1_FREERUN_SHIFT 1 1459#define MADERA_FLL1_FREERUN_SHIFT 1
@@ -1473,6 +1486,9 @@
1473#define MADERA_FLL1_FRATIO_MASK 0x0F00 1486#define MADERA_FLL1_FRATIO_MASK 0x0F00
1474#define MADERA_FLL1_FRATIO_SHIFT 8 1487#define MADERA_FLL1_FRATIO_SHIFT 8
1475#define MADERA_FLL1_FRATIO_WIDTH 4 1488#define MADERA_FLL1_FRATIO_WIDTH 4
1489#define MADERA_FLL1_FB_DIV_MASK 0x03FF
1490#define MADERA_FLL1_FB_DIV_SHIFT 0
1491#define MADERA_FLL1_FB_DIV_WIDTH 10
1476 1492
1477/* (0x0176) FLL1_Control_6 */ 1493/* (0x0176) FLL1_Control_6 */
1478#define MADERA_FLL1_REFCLK_DIV_MASK 0x00C0 1494#define MADERA_FLL1_REFCLK_DIV_MASK 0x00C0
@@ -1482,15 +1498,6 @@
1482#define MADERA_FLL1_REFCLK_SRC_SHIFT 0 1498#define MADERA_FLL1_REFCLK_SRC_SHIFT 0
1483#define MADERA_FLL1_REFCLK_SRC_WIDTH 4 1499#define MADERA_FLL1_REFCLK_SRC_WIDTH 4
1484 1500
1485/* (0x0177) FLL1_Loop_Filter_Test_1 */
1486#define MADERA_FLL1_FRC_INTEG_UPD 0x8000
1487#define MADERA_FLL1_FRC_INTEG_UPD_MASK 0x8000
1488#define MADERA_FLL1_FRC_INTEG_UPD_SHIFT 15
1489#define MADERA_FLL1_FRC_INTEG_UPD_WIDTH 1
1490#define MADERA_FLL1_FRC_INTEG_VAL_MASK 0x0FFF
1491#define MADERA_FLL1_FRC_INTEG_VAL_SHIFT 0
1492#define MADERA_FLL1_FRC_INTEG_VAL_WIDTH 12
1493
1494/* (0x0179) FLL1_Control_7 */ 1501/* (0x0179) FLL1_Control_7 */
1495#define MADERA_FLL1_GAIN_MASK 0x003c 1502#define MADERA_FLL1_GAIN_MASK 0x003c
1496#define MADERA_FLL1_GAIN_SHIFT 2 1503#define MADERA_FLL1_GAIN_SHIFT 2
@@ -1504,6 +1511,30 @@
1504#define MADERA_FLL1_PHASE_ENA_SHIFT 11 1511#define MADERA_FLL1_PHASE_ENA_SHIFT 11
1505#define MADERA_FLL1_PHASE_ENA_WIDTH 1 1512#define MADERA_FLL1_PHASE_ENA_WIDTH 1
1506 1513
1514/* (0x017A) FLL1_Control_10 */
1515#define MADERA_FLL1_HP_MASK 0xC000
1516#define MADERA_FLL1_HP_SHIFT 14
1517#define MADERA_FLL1_HP_WIDTH 2
1518#define MADERA_FLL1_PHASEDET_ENA_MASK 0x1000
1519#define MADERA_FLL1_PHASEDET_ENA_SHIFT 12
1520#define MADERA_FLL1_PHASEDET_ENA_WIDTH 1
1521
1522/* (0x017B) FLL1_Control_11 */
1523#define MADERA_FLL1_LOCKDET_THR_MASK 0x001E
1524#define MADERA_FLL1_LOCKDET_THR_SHIFT 1
1525#define MADERA_FLL1_LOCKDET_THR_WIDTH 4
1526#define MADERA_FLL1_LOCKDET_MASK 0x0001
1527#define MADERA_FLL1_LOCKDET_SHIFT 0
1528#define MADERA_FLL1_LOCKDET_WIDTH 1
1529
1530/* (0x017D) FLL1_Digital_Test_1 */
1531#define MADERA_FLL1_SYNC_EFS_ENA_MASK 0x0100
1532#define MADERA_FLL1_SYNC_EFS_ENA_SHIFT 8
1533#define MADERA_FLL1_SYNC_EFS_ENA_WIDTH 1
1534#define MADERA_FLL1_CLK_VCO_FAST_SRC_MASK 0x0003
1535#define MADERA_FLL1_CLK_VCO_FAST_SRC_SHIFT 0
1536#define MADERA_FLL1_CLK_VCO_FAST_SRC_WIDTH 2
1537
1507/* (0x0181) FLL1_Synchroniser_1 */ 1538/* (0x0181) FLL1_Synchroniser_1 */
1508#define MADERA_FLL1_SYNC_ENA 0x0001 1539#define MADERA_FLL1_SYNC_ENA 0x0001
1509#define MADERA_FLL1_SYNC_ENA_MASK 0x0001 1540#define MADERA_FLL1_SYNC_ENA_MASK 0x0001
@@ -1625,6 +1656,13 @@
1625#define MADERA_LDO2_ENA_WIDTH 1 1656#define MADERA_LDO2_ENA_WIDTH 1
1626 1657
1627/* (0x0218) Mic_Bias_Ctrl_1 */ 1658/* (0x0218) Mic_Bias_Ctrl_1 */
1659#define MADERA_MICB1_EXT_CAP 0x8000
1660#define MADERA_MICB1_EXT_CAP_MASK 0x8000
1661#define MADERA_MICB1_EXT_CAP_SHIFT 15
1662#define MADERA_MICB1_EXT_CAP_WIDTH 1
1663#define MADERA_MICB1_LVL_MASK 0x01E0
1664#define MADERA_MICB1_LVL_SHIFT 5
1665#define MADERA_MICB1_LVL_WIDTH 4
1628#define MADERA_MICB1_ENA 0x0001 1666#define MADERA_MICB1_ENA 0x0001
1629#define MADERA_MICB1_ENA_MASK 0x0001 1667#define MADERA_MICB1_ENA_MASK 0x0001
1630#define MADERA_MICB1_ENA_SHIFT 0 1668#define MADERA_MICB1_ENA_SHIFT 0
@@ -2308,6 +2346,17 @@
2308#define MADERA_OUT1R_ENA_SHIFT 0 2346#define MADERA_OUT1R_ENA_SHIFT 0
2309#define MADERA_OUT1R_ENA_WIDTH 1 2347#define MADERA_OUT1R_ENA_WIDTH 1
2310 2348
2349/* (0x0408) Output_Rate_1 */
2350#define MADERA_CP_DAC_MODE_MASK 0x0040
2351#define MADERA_CP_DAC_MODE_SHIFT 6
2352#define MADERA_CP_DAC_MODE_WIDTH 1
2353#define MADERA_OUT_EXT_CLK_DIV_MASK 0x0030
2354#define MADERA_OUT_EXT_CLK_DIV_SHIFT 4
2355#define MADERA_OUT_EXT_CLK_DIV_WIDTH 2
2356#define MADERA_OUT_CLK_SRC_MASK 0x0007
2357#define MADERA_OUT_CLK_SRC_SHIFT 0
2358#define MADERA_OUT_CLK_SRC_WIDTH 3
2359
2311/* (0x0409) Output_Volume_Ramp */ 2360/* (0x0409) Output_Volume_Ramp */
2312#define MADERA_OUT_VD_RAMP_MASK 0x0070 2361#define MADERA_OUT_VD_RAMP_MASK 0x0070
2313#define MADERA_OUT_VD_RAMP_SHIFT 4 2362#define MADERA_OUT_VD_RAMP_SHIFT 4
@@ -2829,6 +2878,30 @@
2829#define MADERA_AIF2RX1_ENA_WIDTH 1 2878#define MADERA_AIF2RX1_ENA_WIDTH 1
2830 2879
2831/* (0x0599) AIF3_Tx_Enables */ 2880/* (0x0599) AIF3_Tx_Enables */
2881#define MADERA_AIF3TX8_ENA 0x0080
2882#define MADERA_AIF3TX8_ENA_MASK 0x0080
2883#define MADERA_AIF3TX8_ENA_SHIFT 7
2884#define MADERA_AIF3TX8_ENA_WIDTH 1
2885#define MADERA_AIF3TX7_ENA 0x0040
2886#define MADERA_AIF3TX7_ENA_MASK 0x0040
2887#define MADERA_AIF3TX7_ENA_SHIFT 6
2888#define MADERA_AIF3TX7_ENA_WIDTH 1
2889#define MADERA_AIF3TX6_ENA 0x0020
2890#define MADERA_AIF3TX6_ENA_MASK 0x0020
2891#define MADERA_AIF3TX6_ENA_SHIFT 5
2892#define MADERA_AIF3TX6_ENA_WIDTH 1
2893#define MADERA_AIF3TX5_ENA 0x0010
2894#define MADERA_AIF3TX5_ENA_MASK 0x0010
2895#define MADERA_AIF3TX5_ENA_SHIFT 4
2896#define MADERA_AIF3TX5_ENA_WIDTH 1
2897#define MADERA_AIF3TX4_ENA 0x0008
2898#define MADERA_AIF3TX4_ENA_MASK 0x0008
2899#define MADERA_AIF3TX4_ENA_SHIFT 3
2900#define MADERA_AIF3TX4_ENA_WIDTH 1
2901#define MADERA_AIF3TX3_ENA 0x0004
2902#define MADERA_AIF3TX3_ENA_MASK 0x0004
2903#define MADERA_AIF3TX3_ENA_SHIFT 2
2904#define MADERA_AIF3TX3_ENA_WIDTH 1
2832#define MADERA_AIF3TX2_ENA 0x0002 2905#define MADERA_AIF3TX2_ENA 0x0002
2833#define MADERA_AIF3TX2_ENA_MASK 0x0002 2906#define MADERA_AIF3TX2_ENA_MASK 0x0002
2834#define MADERA_AIF3TX2_ENA_SHIFT 1 2907#define MADERA_AIF3TX2_ENA_SHIFT 1
@@ -2839,6 +2912,30 @@
2839#define MADERA_AIF3TX1_ENA_WIDTH 1 2912#define MADERA_AIF3TX1_ENA_WIDTH 1
2840 2913
2841/* (0x059A) AIF3_Rx_Enables */ 2914/* (0x059A) AIF3_Rx_Enables */
2915#define MADERA_AIF3RX8_ENA 0x0080
2916#define MADERA_AIF3RX8_ENA_MASK 0x0080
2917#define MADERA_AIF3RX8_ENA_SHIFT 7
2918#define MADERA_AIF3RX8_ENA_WIDTH 1
2919#define MADERA_AIF3RX7_ENA 0x0040
2920#define MADERA_AIF3RX7_ENA_MASK 0x0040
2921#define MADERA_AIF3RX7_ENA_SHIFT 6
2922#define MADERA_AIF3RX7_ENA_WIDTH 1
2923#define MADERA_AIF3RX6_ENA 0x0020
2924#define MADERA_AIF3RX6_ENA_MASK 0x0020
2925#define MADERA_AIF3RX6_ENA_SHIFT 5
2926#define MADERA_AIF3RX6_ENA_WIDTH 1
2927#define MADERA_AIF3RX5_ENA 0x0010
2928#define MADERA_AIF3RX5_ENA_MASK 0x0010
2929#define MADERA_AIF3RX5_ENA_SHIFT 4
2930#define MADERA_AIF3RX5_ENA_WIDTH 1
2931#define MADERA_AIF3RX4_ENA 0x0008
2932#define MADERA_AIF3RX4_ENA_MASK 0x0008
2933#define MADERA_AIF3RX4_ENA_SHIFT 3
2934#define MADERA_AIF3RX4_ENA_WIDTH 1
2935#define MADERA_AIF3RX3_ENA 0x0004
2936#define MADERA_AIF3RX3_ENA_MASK 0x0004
2937#define MADERA_AIF3RX3_ENA_SHIFT 2
2938#define MADERA_AIF3RX3_ENA_WIDTH 1
2842#define MADERA_AIF3RX2_ENA 0x0002 2939#define MADERA_AIF3RX2_ENA 0x0002
2843#define MADERA_AIF3RX2_ENA_MASK 0x0002 2940#define MADERA_AIF3RX2_ENA_MASK 0x0002
2844#define MADERA_AIF3RX2_ENA_SHIFT 1 2941#define MADERA_AIF3RX2_ENA_SHIFT 1
@@ -3453,6 +3550,25 @@
3453#define MADERA_FCR_MIC_MODE_SEL_SHIFT 2 3550#define MADERA_FCR_MIC_MODE_SEL_SHIFT 2
3454#define MADERA_FCR_MIC_MODE_SEL_WIDTH 2 3551#define MADERA_FCR_MIC_MODE_SEL_WIDTH 2
3455 3552
3553/* (0x10C0) AUXPDM1_CTRL_0 */
3554#define MADERA_AUXPDM1_SRC_MASK 0x0F00
3555#define MADERA_AUXPDM1_SRC_SHIFT 8
3556#define MADERA_AUXPDM1_SRC_WIDTH 4
3557#define MADERA_AUXPDM1_TXEDGE_MASK 0x0010
3558#define MADERA_AUXPDM1_TXEDGE_SHIFT 4
3559#define MADERA_AUXPDM1_TXEDGE_WIDTH 1
3560#define MADERA_AUXPDM1_MSTR_MASK 0x0008
3561#define MADERA_AUXPDM1_MSTR_SHIFT 3
3562#define MADERA_AUXPDM1_MSTR_WIDTH 1
3563#define MADERA_AUXPDM1_ENABLE_MASK 0x0001
3564#define MADERA_AUXPDM1_ENABLE_SHIFT 0
3565#define MADERA_AUXPDM1_ENABLE_WIDTH 1
3566
3567/* (0x10C1) AUXPDM1_CTRL_1 */
3568#define MADERA_AUXPDM1_CLK_FREQ_MASK 0xC000
3569#define MADERA_AUXPDM1_CLK_FREQ_SHIFT 14
3570#define MADERA_AUXPDM1_CLK_FREQ_WIDTH 2
3571
3456/* (0x1480) DFC1_CTRL_W0 */ 3572/* (0x1480) DFC1_CTRL_W0 */
3457#define MADERA_DFC1_RATE_MASK 0x007C 3573#define MADERA_DFC1_RATE_MASK 0x007C
3458#define MADERA_DFC1_RATE_SHIFT 2 3574#define MADERA_DFC1_RATE_SHIFT 2
diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h
index 1d831c7222b9..7cfd2b0504df 100644
--- a/include/linux/mfd/rk808.h
+++ b/include/linux/mfd/rk808.h
@@ -374,6 +374,7 @@ enum rk805_reg {
374#define SWITCH1_EN BIT(5) 374#define SWITCH1_EN BIT(5)
375#define DEV_OFF_RST BIT(3) 375#define DEV_OFF_RST BIT(3)
376#define DEV_OFF BIT(0) 376#define DEV_OFF BIT(0)
377#define RTC_STOP BIT(0)
377 378
378#define VB_LO_ACT BIT(4) 379#define VB_LO_ACT BIT(4)
379#define VB_LO_SEL_3500MV (7 << 0) 380#define VB_LO_SEL_3500MV (7 << 0)
@@ -387,7 +388,179 @@ enum rk805_reg {
387#define SHUTDOWN_FUN (0x2 << 2) 388#define SHUTDOWN_FUN (0x2 << 2)
388#define SLEEP_FUN (0x1 << 2) 389#define SLEEP_FUN (0x1 << 2)
389#define RK8XX_ID_MSK 0xfff0 390#define RK8XX_ID_MSK 0xfff0
391#define PWM_MODE_MSK BIT(7)
390#define FPWM_MODE BIT(7) 392#define FPWM_MODE BIT(7)
393#define AUTO_PWM_MODE 0
394
395enum rk817_reg_id {
396 RK817_ID_DCDC1 = 0,
397 RK817_ID_DCDC2,
398 RK817_ID_DCDC3,
399 RK817_ID_DCDC4,
400 RK817_ID_LDO1,
401 RK817_ID_LDO2,
402 RK817_ID_LDO3,
403 RK817_ID_LDO4,
404 RK817_ID_LDO5,
405 RK817_ID_LDO6,
406 RK817_ID_LDO7,
407 RK817_ID_LDO8,
408 RK817_ID_LDO9,
409 RK817_ID_BOOST,
410 RK817_ID_BOOST_OTG_SW,
411 RK817_NUM_REGULATORS
412};
413
414enum rk809_reg_id {
415 RK809_ID_DCDC5 = RK817_ID_BOOST,
416 RK809_ID_SW1,
417 RK809_ID_SW2,
418 RK809_NUM_REGULATORS
419};
420
421#define RK817_SECONDS_REG 0x00
422#define RK817_MINUTES_REG 0x01
423#define RK817_HOURS_REG 0x02
424#define RK817_DAYS_REG 0x03
425#define RK817_MONTHS_REG 0x04
426#define RK817_YEARS_REG 0x05
427#define RK817_WEEKS_REG 0x06
428#define RK817_ALARM_SECONDS_REG 0x07
429#define RK817_ALARM_MINUTES_REG 0x08
430#define RK817_ALARM_HOURS_REG 0x09
431#define RK817_ALARM_DAYS_REG 0x0a
432#define RK817_ALARM_MONTHS_REG 0x0b
433#define RK817_ALARM_YEARS_REG 0x0c
434#define RK817_RTC_CTRL_REG 0xd
435#define RK817_RTC_STATUS_REG 0xe
436#define RK817_RTC_INT_REG 0xf
437#define RK817_RTC_COMP_LSB_REG 0x10
438#define RK817_RTC_COMP_MSB_REG 0x11
439
440#define RK817_POWER_EN_REG(i) (0xb1 + (i))
441#define RK817_POWER_SLP_EN_REG(i) (0xb5 + (i))
442
443#define RK817_POWER_CONFIG (0xb9)
444
445#define RK817_BUCK_CONFIG_REG(i) (0xba + (i) * 3)
446
447#define RK817_BUCK1_ON_VSEL_REG 0xBB
448#define RK817_BUCK1_SLP_VSEL_REG 0xBC
449
450#define RK817_BUCK2_CONFIG_REG 0xBD
451#define RK817_BUCK2_ON_VSEL_REG 0xBE
452#define RK817_BUCK2_SLP_VSEL_REG 0xBF
453
454#define RK817_BUCK3_CONFIG_REG 0xC0
455#define RK817_BUCK3_ON_VSEL_REG 0xC1
456#define RK817_BUCK3_SLP_VSEL_REG 0xC2
457
458#define RK817_BUCK4_CONFIG_REG 0xC3
459#define RK817_BUCK4_ON_VSEL_REG 0xC4
460#define RK817_BUCK4_SLP_VSEL_REG 0xC5
461
462#define RK817_LDO_ON_VSEL_REG(idx) (0xcc + (idx) * 2)
463#define RK817_BOOST_OTG_CFG (0xde)
464
465#define RK817_ID_MSB 0xed
466#define RK817_ID_LSB 0xee
467
468#define RK817_SYS_STS 0xf0
469#define RK817_SYS_CFG(i) (0xf1 + (i))
470
471#define RK817_ON_SOURCE_REG 0xf5
472#define RK817_OFF_SOURCE_REG 0xf6
473
474/* INTERRUPT REGISTER */
475#define RK817_INT_STS_REG0 0xf8
476#define RK817_INT_STS_MSK_REG0 0xf9
477#define RK817_INT_STS_REG1 0xfa
478#define RK817_INT_STS_MSK_REG1 0xfb
479#define RK817_INT_STS_REG2 0xfc
480#define RK817_INT_STS_MSK_REG2 0xfd
481#define RK817_GPIO_INT_CFG 0xfe
482
483/* IRQ Definitions */
484#define RK817_IRQ_PWRON_FALL 0
485#define RK817_IRQ_PWRON_RISE 1
486#define RK817_IRQ_PWRON 2
487#define RK817_IRQ_PWMON_LP 3
488#define RK817_IRQ_HOTDIE 4
489#define RK817_IRQ_RTC_ALARM 5
490#define RK817_IRQ_RTC_PERIOD 6
491#define RK817_IRQ_VB_LO 7
492#define RK817_IRQ_PLUG_IN 8
493#define RK817_IRQ_PLUG_OUT 9
494#define RK817_IRQ_CHRG_TERM 10
495#define RK817_IRQ_CHRG_TIME 11
496#define RK817_IRQ_CHRG_TS 12
497#define RK817_IRQ_USB_OV 13
498#define RK817_IRQ_CHRG_IN_CLMP 14
499#define RK817_IRQ_BAT_DIS_ILIM 15
500#define RK817_IRQ_GATE_GPIO 16
501#define RK817_IRQ_TS_GPIO 17
502#define RK817_IRQ_CODEC_PD 18
503#define RK817_IRQ_CODEC_PO 19
504#define RK817_IRQ_CLASSD_MUTE_DONE 20
505#define RK817_IRQ_CLASSD_OCP 21
506#define RK817_IRQ_BAT_OVP 22
507#define RK817_IRQ_CHRG_BAT_HI 23
508#define RK817_IRQ_END (RK817_IRQ_CHRG_BAT_HI + 1)
509
510/*
511 * rtc_ctrl 0xd
512 * same as 808, except bit4
513 */
514#define RK817_RTC_CTRL_RSV4 BIT(4)
515
516/* power config 0xb9 */
517#define RK817_BUCK3_FB_RES_MSK BIT(6)
518#define RK817_BUCK3_FB_RES_INTER BIT(6)
519#define RK817_BUCK3_FB_RES_EXT 0
520
521/* buck config 0xba */
522#define RK817_RAMP_RATE_OFFSET 6
523#define RK817_RAMP_RATE_MASK (0x3 << RK817_RAMP_RATE_OFFSET)
524#define RK817_RAMP_RATE_3MV_PER_US (0x0 << RK817_RAMP_RATE_OFFSET)
525#define RK817_RAMP_RATE_6_3MV_PER_US (0x1 << RK817_RAMP_RATE_OFFSET)
526#define RK817_RAMP_RATE_12_5MV_PER_US (0x2 << RK817_RAMP_RATE_OFFSET)
527#define RK817_RAMP_RATE_25MV_PER_US (0x3 << RK817_RAMP_RATE_OFFSET)
528
529/* sys_cfg1 0xf2 */
530#define RK817_HOTDIE_TEMP_MSK (0x3 << 4)
531#define RK817_HOTDIE_85 (0x0 << 4)
532#define RK817_HOTDIE_95 (0x1 << 4)
533#define RK817_HOTDIE_105 (0x2 << 4)
534#define RK817_HOTDIE_115 (0x3 << 4)
535
536#define RK817_TSD_TEMP_MSK BIT(6)
537#define RK817_TSD_140 0
538#define RK817_TSD_160 BIT(6)
539
540#define RK817_CLK32KOUT2_EN BIT(7)
541
542/* sys_cfg3 0xf4 */
543#define RK817_SLPPIN_FUNC_MSK (0x3 << 3)
544#define SLPPIN_NULL_FUN (0x0 << 3)
545#define SLPPIN_SLP_FUN (0x1 << 3)
546#define SLPPIN_DN_FUN (0x2 << 3)
547#define SLPPIN_RST_FUN (0x3 << 3)
548
549#define RK817_RST_FUNC_MSK (0x3 << 6)
550#define RK817_RST_FUNC_SFT (6)
551#define RK817_RST_FUNC_CNT (3)
552#define RK817_RST_FUNC_DEV (0) /* reset the dev */
553#define RK817_RST_FUNC_REG (0x1 << 6) /* reset the reg only */
554
555#define RK817_SLPPOL_MSK BIT(5)
556#define RK817_SLPPOL_H BIT(5)
557#define RK817_SLPPOL_L (0)
558
559/* gpio&int 0xfe */
560#define RK817_INT_POL_MSK BIT(1)
561#define RK817_INT_POL_H BIT(1)
562#define RK817_INT_POL_L 0
563#define RK809_BUCK5_CONFIG(i) (RK817_BOOST_OTG_CFG + (i) * 1)
391 564
392enum { 565enum {
393 BUCK_ILMIN_50MA, 566 BUCK_ILMIN_50MA,
@@ -435,6 +608,8 @@ enum {
435enum { 608enum {
436 RK805_ID = 0x8050, 609 RK805_ID = 0x8050,
437 RK808_ID = 0x0000, 610 RK808_ID = 0x0000,
611 RK809_ID = 0x8090,
612 RK817_ID = 0x8170,
438 RK818_ID = 0x8181, 613 RK818_ID = 0x8181,
439}; 614};
440 615
@@ -445,5 +620,7 @@ struct rk808 {
445 long variant; 620 long variant;
446 const struct regmap_config *regmap_cfg; 621 const struct regmap_config *regmap_cfg;
447 const struct regmap_irq_chip *regmap_irq_chip; 622 const struct regmap_irq_chip *regmap_irq_chip;
623 void (*pm_pwroff_fn)(void);
624 void (*pm_pwroff_prep_fn)(void);
448}; 625};
449#endif /* __LINUX_REGULATOR_RK808_H */ 626#endif /* __LINUX_REGULATOR_RK808_H */
diff --git a/include/linux/mfd/rohm-bd70528.h b/include/linux/mfd/rohm-bd70528.h
new file mode 100644
index 000000000000..1013e60c5b25
--- /dev/null
+++ b/include/linux/mfd/rohm-bd70528.h
@@ -0,0 +1,408 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* Copyright (C) 2018 ROHM Semiconductors */
3
4#ifndef __LINUX_MFD_BD70528_H__
5#define __LINUX_MFD_BD70528_H__
6
7#include <linux/bits.h>
8#include <linux/device.h>
9#include <linux/mfd/rohm-generic.h>
10#include <linux/regmap.h>
11
12enum {
13 BD70528_BUCK1,
14 BD70528_BUCK2,
15 BD70528_BUCK3,
16 BD70528_LDO1,
17 BD70528_LDO2,
18 BD70528_LDO3,
19 BD70528_LED1,
20 BD70528_LED2,
21};
22
23struct bd70528_data {
24 struct rohm_regmap_dev chip;
25 struct mutex rtc_timer_lock;
26};
27
28#define BD70528_BUCK_VOLTS 17
29#define BD70528_BUCK_VOLTS 17
30#define BD70528_BUCK_VOLTS 17
31#define BD70528_LDO_VOLTS 0x20
32
33#define BD70528_REG_BUCK1_EN 0x0F
34#define BD70528_REG_BUCK1_VOLT 0x15
35#define BD70528_REG_BUCK2_EN 0x10
36#define BD70528_REG_BUCK2_VOLT 0x16
37#define BD70528_REG_BUCK3_EN 0x11
38#define BD70528_REG_BUCK3_VOLT 0x17
39#define BD70528_REG_LDO1_EN 0x1b
40#define BD70528_REG_LDO1_VOLT 0x1e
41#define BD70528_REG_LDO2_EN 0x1c
42#define BD70528_REG_LDO2_VOLT 0x1f
43#define BD70528_REG_LDO3_EN 0x1d
44#define BD70528_REG_LDO3_VOLT 0x20
45#define BD70528_REG_LED_CTRL 0x2b
46#define BD70528_REG_LED_VOLT 0x29
47#define BD70528_REG_LED_EN 0x2a
48
49/* main irq registers */
50#define BD70528_REG_INT_MAIN 0x7E
51#define BD70528_REG_INT_MAIN_MASK 0x74
52
53/* 'sub irq' registers */
54#define BD70528_REG_INT_SHDN 0x7F
55#define BD70528_REG_INT_PWR_FLT 0x80
56#define BD70528_REG_INT_VR_FLT 0x81
57#define BD70528_REG_INT_MISC 0x82
58#define BD70528_REG_INT_BAT1 0x83
59#define BD70528_REG_INT_BAT2 0x84
60#define BD70528_REG_INT_RTC 0x85
61#define BD70528_REG_INT_GPIO 0x86
62#define BD70528_REG_INT_OP_FAIL 0x87
63
64#define BD70528_REG_INT_SHDN_MASK 0x75
65#define BD70528_REG_INT_PWR_FLT_MASK 0x76
66#define BD70528_REG_INT_VR_FLT_MASK 0x77
67#define BD70528_REG_INT_MISC_MASK 0x78
68#define BD70528_REG_INT_BAT1_MASK 0x79
69#define BD70528_REG_INT_BAT2_MASK 0x7a
70#define BD70528_REG_INT_RTC_MASK 0x7b
71#define BD70528_REG_INT_GPIO_MASK 0x7c
72#define BD70528_REG_INT_OP_FAIL_MASK 0x7d
73
74/* Reset related 'magic' registers */
75#define BD70528_REG_SHIPMODE 0x03
76#define BD70528_REG_HWRESET 0x04
77#define BD70528_REG_WARMRESET 0x05
78#define BD70528_REG_STANDBY 0x06
79
80/* GPIO registers */
81#define BD70528_REG_GPIO_STATE 0x8F
82
83#define BD70528_REG_GPIO1_IN 0x4d
84#define BD70528_REG_GPIO2_IN 0x4f
85#define BD70528_REG_GPIO3_IN 0x51
86#define BD70528_REG_GPIO4_IN 0x53
87#define BD70528_REG_GPIO1_OUT 0x4e
88#define BD70528_REG_GPIO2_OUT 0x50
89#define BD70528_REG_GPIO3_OUT 0x52
90#define BD70528_REG_GPIO4_OUT 0x54
91
92/* clk control */
93
94#define BD70528_REG_CLK_OUT 0x2c
95
96/* RTC */
97
98#define BD70528_REG_RTC_COUNT_H 0x2d
99#define BD70528_REG_RTC_COUNT_L 0x2e
100#define BD70528_REG_RTC_SEC 0x2f
101#define BD70528_REG_RTC_MINUTE 0x30
102#define BD70528_REG_RTC_HOUR 0x31
103#define BD70528_REG_RTC_WEEK 0x32
104#define BD70528_REG_RTC_DAY 0x33
105#define BD70528_REG_RTC_MONTH 0x34
106#define BD70528_REG_RTC_YEAR 0x35
107
108#define BD70528_REG_RTC_ALM_SEC 0x36
109#define BD70528_REG_RTC_ALM_START BD70528_REG_RTC_ALM_SEC
110#define BD70528_REG_RTC_ALM_MINUTE 0x37
111#define BD70528_REG_RTC_ALM_HOUR 0x38
112#define BD70528_REG_RTC_ALM_WEEK 0x39
113#define BD70528_REG_RTC_ALM_DAY 0x3a
114#define BD70528_REG_RTC_ALM_MONTH 0x3b
115#define BD70528_REG_RTC_ALM_YEAR 0x3c
116#define BD70528_REG_RTC_ALM_MASK 0x3d
117#define BD70528_REG_RTC_ALM_REPEAT 0x3e
118#define BD70528_REG_RTC_START BD70528_REG_RTC_SEC
119
120#define BD70528_REG_RTC_WAKE_SEC 0x43
121#define BD70528_REG_RTC_WAKE_START BD70528_REG_RTC_WAKE_SEC
122#define BD70528_REG_RTC_WAKE_MIN 0x44
123#define BD70528_REG_RTC_WAKE_HOUR 0x45
124#define BD70528_REG_RTC_WAKE_CTRL 0x46
125
126#define BD70528_REG_ELAPSED_TIMER_EN 0x42
127#define BD70528_REG_WAKE_EN 0x46
128
129/* WDT registers */
130#define BD70528_REG_WDT_CTRL 0x4A
131#define BD70528_REG_WDT_HOUR 0x49
132#define BD70528_REG_WDT_MINUTE 0x48
133#define BD70528_REG_WDT_SEC 0x47
134
135/* Charger / Battery */
136#define BD70528_REG_CHG_CURR_STAT 0x59
137#define BD70528_REG_CHG_BAT_STAT 0x57
138#define BD70528_REG_CHG_BAT_TEMP 0x58
139#define BD70528_REG_CHG_IN_STAT 0x56
140#define BD70528_REG_CHG_DCIN_ILIM 0x5d
141#define BD70528_REG_CHG_CHG_CURR_WARM 0x61
142#define BD70528_REG_CHG_CHG_CURR_COLD 0x62
143
144/* Masks for main IRQ register bits */
145enum {
146 BD70528_INT_SHDN,
147#define BD70528_INT_SHDN_MASK BIT(BD70528_INT_SHDN)
148 BD70528_INT_PWR_FLT,
149#define BD70528_INT_PWR_FLT_MASK BIT(BD70528_INT_PWR_FLT)
150 BD70528_INT_VR_FLT,
151#define BD70528_INT_VR_FLT_MASK BIT(BD70528_INT_VR_FLT)
152 BD70528_INT_MISC,
153#define BD70528_INT_MISC_MASK BIT(BD70528_INT_MISC)
154 BD70528_INT_BAT1,
155#define BD70528_INT_BAT1_MASK BIT(BD70528_INT_BAT1)
156 BD70528_INT_RTC,
157#define BD70528_INT_RTC_MASK BIT(BD70528_INT_RTC)
158 BD70528_INT_GPIO,
159#define BD70528_INT_GPIO_MASK BIT(BD70528_INT_GPIO)
160 BD70528_INT_OP_FAIL,
161#define BD70528_INT_OP_FAIL_MASK BIT(BD70528_INT_OP_FAIL)
162};
163
164/* IRQs */
165enum {
166 /* Shutdown register IRQs */
167 BD70528_INT_LONGPUSH,
168 BD70528_INT_WDT,
169 BD70528_INT_HWRESET,
170 BD70528_INT_RSTB_FAULT,
171 BD70528_INT_VBAT_UVLO,
172 BD70528_INT_TSD,
173 BD70528_INT_RSTIN,
174 /* Power failure register IRQs */
175 BD70528_INT_BUCK1_FAULT,
176 BD70528_INT_BUCK2_FAULT,
177 BD70528_INT_BUCK3_FAULT,
178 BD70528_INT_LDO1_FAULT,
179 BD70528_INT_LDO2_FAULT,
180 BD70528_INT_LDO3_FAULT,
181 BD70528_INT_LED1_FAULT,
182 BD70528_INT_LED2_FAULT,
183 /* VR FAULT register IRQs */
184 BD70528_INT_BUCK1_OCP,
185 BD70528_INT_BUCK2_OCP,
186 BD70528_INT_BUCK3_OCP,
187 BD70528_INT_LED1_OCP,
188 BD70528_INT_LED2_OCP,
189 BD70528_INT_BUCK1_FULLON,
190 BD70528_INT_BUCK2_FULLON,
191 /* PMU register interrupts */
192 BD70528_INT_SHORTPUSH,
193 BD70528_INT_AUTO_WAKEUP,
194 BD70528_INT_STATE_CHANGE,
195 /* Charger 1 register IRQs */
196 BD70528_INT_BAT_OV_RES,
197 BD70528_INT_BAT_OV_DET,
198 BD70528_INT_DBAT_DET,
199 BD70528_INT_BATTSD_COLD_RES,
200 BD70528_INT_BATTSD_COLD_DET,
201 BD70528_INT_BATTSD_HOT_RES,
202 BD70528_INT_BATTSD_HOT_DET,
203 BD70528_INT_CHG_TSD,
204 /* Charger 2 register IRQs */
205 BD70528_INT_BAT_RMV,
206 BD70528_INT_BAT_DET,
207 BD70528_INT_DCIN2_OV_RES,
208 BD70528_INT_DCIN2_OV_DET,
209 BD70528_INT_DCIN2_RMV,
210 BD70528_INT_DCIN2_DET,
211 BD70528_INT_DCIN1_RMV,
212 BD70528_INT_DCIN1_DET,
213 /* RTC register IRQs */
214 BD70528_INT_RTC_ALARM,
215 BD70528_INT_ELPS_TIM,
216 /* GPIO register IRQs */
217 BD70528_INT_GPIO0,
218 BD70528_INT_GPIO1,
219 BD70528_INT_GPIO2,
220 BD70528_INT_GPIO3,
221 /* Invalid operation register IRQs */
222 BD70528_INT_BUCK1_DVS_OPFAIL,
223 BD70528_INT_BUCK2_DVS_OPFAIL,
224 BD70528_INT_BUCK3_DVS_OPFAIL,
225 BD70528_INT_LED1_VOLT_OPFAIL,
226 BD70528_INT_LED2_VOLT_OPFAIL,
227};
228
229/* Masks */
230#define BD70528_INT_LONGPUSH_MASK 0x1
231#define BD70528_INT_WDT_MASK 0x2
232#define BD70528_INT_HWRESET_MASK 0x4
233#define BD70528_INT_RSTB_FAULT_MASK 0x8
234#define BD70528_INT_VBAT_UVLO_MASK 0x10
235#define BD70528_INT_TSD_MASK 0x20
236#define BD70528_INT_RSTIN_MASK 0x40
237
238#define BD70528_INT_BUCK1_FAULT_MASK 0x1
239#define BD70528_INT_BUCK2_FAULT_MASK 0x2
240#define BD70528_INT_BUCK3_FAULT_MASK 0x4
241#define BD70528_INT_LDO1_FAULT_MASK 0x8
242#define BD70528_INT_LDO2_FAULT_MASK 0x10
243#define BD70528_INT_LDO3_FAULT_MASK 0x20
244#define BD70528_INT_LED1_FAULT_MASK 0x40
245#define BD70528_INT_LED2_FAULT_MASK 0x80
246
247#define BD70528_INT_BUCK1_OCP_MASK 0x1
248#define BD70528_INT_BUCK2_OCP_MASK 0x2
249#define BD70528_INT_BUCK3_OCP_MASK 0x4
250#define BD70528_INT_LED1_OCP_MASK 0x8
251#define BD70528_INT_LED2_OCP_MASK 0x10
252#define BD70528_INT_BUCK1_FULLON_MASK 0x20
253#define BD70528_INT_BUCK2_FULLON_MASK 0x40
254
255#define BD70528_INT_SHORTPUSH_MASK 0x1
256#define BD70528_INT_AUTO_WAKEUP_MASK 0x2
257#define BD70528_INT_STATE_CHANGE_MASK 0x10
258
259#define BD70528_INT_BAT_OV_RES_MASK 0x1
260#define BD70528_INT_BAT_OV_DET_MASK 0x2
261#define BD70528_INT_DBAT_DET_MASK 0x4
262#define BD70528_INT_BATTSD_COLD_RES_MASK 0x8
263#define BD70528_INT_BATTSD_COLD_DET_MASK 0x10
264#define BD70528_INT_BATTSD_HOT_RES_MASK 0x20
265#define BD70528_INT_BATTSD_HOT_DET_MASK 0x40
266#define BD70528_INT_CHG_TSD_MASK 0x80
267
268#define BD70528_INT_BAT_RMV_MASK 0x1
269#define BD70528_INT_BAT_DET_MASK 0x2
270#define BD70528_INT_DCIN2_OV_RES_MASK 0x4
271#define BD70528_INT_DCIN2_OV_DET_MASK 0x8
272#define BD70528_INT_DCIN2_RMV_MASK 0x10
273#define BD70528_INT_DCIN2_DET_MASK 0x20
274#define BD70528_INT_DCIN1_RMV_MASK 0x40
275#define BD70528_INT_DCIN1_DET_MASK 0x80
276
277#define BD70528_INT_RTC_ALARM_MASK 0x1
278#define BD70528_INT_ELPS_TIM_MASK 0x2
279
280#define BD70528_INT_GPIO0_MASK 0x1
281#define BD70528_INT_GPIO1_MASK 0x2
282#define BD70528_INT_GPIO2_MASK 0x4
283#define BD70528_INT_GPIO3_MASK 0x8
284
285#define BD70528_INT_BUCK1_DVS_OPFAIL_MASK 0x1
286#define BD70528_INT_BUCK2_DVS_OPFAIL_MASK 0x2
287#define BD70528_INT_BUCK3_DVS_OPFAIL_MASK 0x4
288#define BD70528_INT_LED1_VOLT_OPFAIL_MASK 0x10
289#define BD70528_INT_LED2_VOLT_OPFAIL_MASK 0x20
290
291#define BD70528_DEBOUNCE_MASK 0x3
292
293#define BD70528_DEBOUNCE_DISABLE 0
294#define BD70528_DEBOUNCE_15MS 1
295#define BD70528_DEBOUNCE_30MS 2
296#define BD70528_DEBOUNCE_50MS 3
297
298#define BD70528_GPIO_DRIVE_MASK 0x2
299#define BD70528_GPIO_PUSH_PULL 0x0
300#define BD70528_GPIO_OPEN_DRAIN 0x2
301
302#define BD70528_GPIO_OUT_EN_MASK 0x80
303#define BD70528_GPIO_OUT_ENABLE 0x80
304#define BD70528_GPIO_OUT_DISABLE 0x0
305
306#define BD70528_GPIO_OUT_HI 0x1
307#define BD70528_GPIO_OUT_LO 0x0
308#define BD70528_GPIO_OUT_MASK 0x1
309
310#define BD70528_GPIO_IN_STATE_BASE 1
311
312#define BD70528_CLK_OUT_EN_MASK 0x1
313
314/* RTC masks to mask out reserved bits */
315
316#define BD70528_MASK_RTC_SEC 0x7f
317#define BD70528_MASK_RTC_MINUTE 0x7f
318#define BD70528_MASK_RTC_HOUR_24H 0x80
319#define BD70528_MASK_RTC_HOUR_PM 0x20
320#define BD70528_MASK_RTC_HOUR 0x1f
321#define BD70528_MASK_RTC_DAY 0x3f
322#define BD70528_MASK_RTC_WEEK 0x07
323#define BD70528_MASK_RTC_MONTH 0x1f
324#define BD70528_MASK_RTC_YEAR 0xff
325#define BD70528_MASK_RTC_COUNT_L 0x7f
326
327#define BD70528_MASK_ELAPSED_TIMER_EN 0x1
328/* Mask second, min and hour fields
329 * HW would support ALM irq for over 24h
330 * (by setting day, month and year too)
331 * but as we wish to keep this same as for
332 * wake-up we limit ALM to 24H and only
333 * unmask sec, min and hour
334 */
335#define BD70528_MASK_ALM_EN 0x7
336#define BD70528_MASK_WAKE_EN 0x1
337
338/* WDT masks */
339#define BD70528_MASK_WDT_EN 0x1
340#define BD70528_MASK_WDT_HOUR 0x1
341#define BD70528_MASK_WDT_MINUTE 0x7f
342#define BD70528_MASK_WDT_SEC 0x7f
343
344#define BD70528_WDT_STATE_BIT 0x1
345#define BD70528_ELAPSED_STATE_BIT 0x2
346#define BD70528_WAKE_STATE_BIT 0x4
347
348/* Charger masks */
349#define BD70528_MASK_CHG_STAT 0x7f
350#define BD70528_MASK_CHG_BAT_TIMER 0x20
351#define BD70528_MASK_CHG_BAT_OVERVOLT 0x10
352#define BD70528_MASK_CHG_BAT_DETECT 0x1
353#define BD70528_MASK_CHG_DCIN1_UVLO 0x1
354#define BD70528_MASK_CHG_DCIN_ILIM 0x3f
355#define BD70528_MASK_CHG_CHG_CURR 0x1f
356#define BD70528_MASK_CHG_TRICKLE_CURR 0x10
357
358/*
359 * Note, external battery register is the lonely rider at
360 * address 0xc5. See how to stuff that in the regmap
361 */
362#define BD70528_MAX_REGISTER 0x94
363
364/* Buck control masks */
365#define BD70528_MASK_RUN_EN 0x4
366#define BD70528_MASK_STBY_EN 0x2
367#define BD70528_MASK_IDLE_EN 0x1
368#define BD70528_MASK_LED1_EN 0x1
369#define BD70528_MASK_LED2_EN 0x10
370
371#define BD70528_MASK_BUCK_VOLT 0xf
372#define BD70528_MASK_LDO_VOLT 0x1f
373#define BD70528_MASK_LED1_VOLT 0x1
374#define BD70528_MASK_LED2_VOLT 0x10
375
376/* Misc irq masks */
377#define BD70528_INT_MASK_SHORT_PUSH 1
378#define BD70528_INT_MASK_AUTO_WAKE 2
379#define BD70528_INT_MASK_POWER_STATE 4
380
381#define BD70528_MASK_BUCK_RAMP 0x10
382#define BD70528_SIFT_BUCK_RAMP 4
383
384#if IS_ENABLED(CONFIG_BD70528_WATCHDOG)
385
386int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, int *old_state);
387void bd70528_wdt_lock(struct rohm_regmap_dev *data);
388void bd70528_wdt_unlock(struct rohm_regmap_dev *data);
389
390#else /* CONFIG_BD70528_WATCHDOG */
391
392static inline int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable,
393 int *old_state)
394{
395 return 0;
396}
397
398static inline void bd70528_wdt_lock(struct rohm_regmap_dev *data)
399{
400}
401
402static inline void bd70528_wdt_unlock(struct rohm_regmap_dev *data)
403{
404}
405
406#endif /* CONFIG_BD70528_WATCHDOG */
407
408#endif /* __LINUX_MFD_BD70528_H__ */
diff --git a/include/linux/mfd/rohm-bd718x7.h b/include/linux/mfd/rohm-bd718x7.h
index fd194bfc836f..7f2dbde402a1 100644
--- a/include/linux/mfd/rohm-bd718x7.h
+++ b/include/linux/mfd/rohm-bd718x7.h
@@ -4,15 +4,10 @@
4#ifndef __LINUX_MFD_BD718XX_H__ 4#ifndef __LINUX_MFD_BD718XX_H__
5#define __LINUX_MFD_BD718XX_H__ 5#define __LINUX_MFD_BD718XX_H__
6 6
7#include <linux/mfd/rohm-generic.h>
7#include <linux/regmap.h> 8#include <linux/regmap.h>
8 9
9enum { 10enum {
10 BD718XX_TYPE_BD71837 = 0,
11 BD718XX_TYPE_BD71847,
12 BD718XX_TYPE_AMOUNT
13};
14
15enum {
16 BD718XX_BUCK1 = 0, 11 BD718XX_BUCK1 = 0,
17 BD718XX_BUCK2, 12 BD718XX_BUCK2,
18 BD718XX_BUCK3, 13 BD718XX_BUCK3,
@@ -321,18 +316,17 @@ enum {
321 BD718XX_PWRBTN_LONG_PRESS_15S 316 BD718XX_PWRBTN_LONG_PRESS_15S
322}; 317};
323 318
324struct bd718xx_clk;
325
326struct bd718xx { 319struct bd718xx {
327 unsigned int chip_type; 320 /*
328 struct device *dev; 321 * Please keep this as the first member here as some
329 struct regmap *regmap; 322 * drivers (clk) supporting more than one chip may only know this
330 unsigned long int id; 323 * generic struct 'struct rohm_regmap_dev' and assume it is
324 * the first chunk of parent device's private data.
325 */
326 struct rohm_regmap_dev chip;
331 327
332 int chip_irq; 328 int chip_irq;
333 struct regmap_irq_chip_data *irq_data; 329 struct regmap_irq_chip_data *irq_data;
334
335 struct bd718xx_clk *clk;
336}; 330};
337 331
338#endif /* __LINUX_MFD_BD718XX_H__ */ 332#endif /* __LINUX_MFD_BD718XX_H__ */
diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h
new file mode 100644
index 000000000000..bff15ac26f2c
--- /dev/null
+++ b/include/linux/mfd/rohm-generic.h
@@ -0,0 +1,20 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* Copyright (C) 2018 ROHM Semiconductors */
3
4#ifndef __LINUX_MFD_ROHM_H__
5#define __LINUX_MFD_ROHM_H__
6
7enum {
8 ROHM_CHIP_TYPE_BD71837 = 0,
9 ROHM_CHIP_TYPE_BD71847,
10 ROHM_CHIP_TYPE_BD70528,
11 ROHM_CHIP_TYPE_AMOUNT
12};
13
14struct rohm_regmap_dev {
15 unsigned int chip_type;
16 struct device *dev;
17 struct regmap *regmap;
18};
19
20#endif
diff --git a/include/linux/mfd/stmfx.h b/include/linux/mfd/stmfx.h
index d890595b89b6..3c67983678ec 100644
--- a/include/linux/mfd/stmfx.h
+++ b/include/linux/mfd/stmfx.h
@@ -5,7 +5,7 @@
5 */ 5 */
6 6
7#ifndef MFD_STMFX_H 7#ifndef MFD_STMFX_H
8#define MFX_STMFX_H 8#define MFD_STMFX_H
9 9
10#include <linux/regmap.h> 10#include <linux/regmap.h>
11 11
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-15 18:14:07 -0400