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authoryangbo lu <yangbo.lu@nxp.com>2016-11-08 22:14:08 -0500
committerUlf Hansson <ulf.hansson@linaro.org>2016-11-29 03:17:20 -0500
commita6fc3b698130230a2342baacd7821eea0405154c (patch)
tree37edafb8747b0d0e22cdd68d02705ff43eecb7b1 /include/linux/fsl
parenta8c759c78f709a8c0642a67debf88ec597d74757 (diff)
soc: fsl: add GUTS driver for QorIQ platforms
The global utilities block controls power management, I/O device enabling, power-onreset(POR) configuration monitoring, alternate function selection for multiplexed signals,and clock control. This patch adds a driver to manage and access global utilities block. Initially only reading SVR and registering soc device are supported. Other guts accesses, such as reading RCW, should eventually be moved into this driver as well. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'include/linux/fsl')
-rw-r--r--include/linux/fsl/guts.h125
1 files changed, 77 insertions, 48 deletions
diff --git a/include/linux/fsl/guts.h b/include/linux/fsl/guts.h
index 649e9171a9b3..3efa3b861d44 100644
--- a/include/linux/fsl/guts.h
+++ b/include/linux/fsl/guts.h
@@ -29,83 +29,112 @@
29 * #ifdefs. 29 * #ifdefs.
30 */ 30 */
31struct ccsr_guts { 31struct ccsr_guts {
32 __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ 32 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
33 __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ 33 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
34 __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ 34 u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
35 __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ 35 * Control Register
36 __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ 36 */
37 __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */ 37 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
38 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
39 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
38 u8 res018[0x20 - 0x18]; 40 u8 res018[0x20 - 0x18];
39 __be32 porcir; /* 0x.0020 - POR Configuration Information Register */ 41 u32 porcir; /* 0x.0020 - POR Configuration Information
42 * Register
43 */
40 u8 res024[0x30 - 0x24]; 44 u8 res024[0x30 - 0x24];
41 __be32 gpiocr; /* 0x.0030 - GPIO Control Register */ 45 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
42 u8 res034[0x40 - 0x34]; 46 u8 res034[0x40 - 0x34];
43 __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ 47 u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
48 * Register
49 */
44 u8 res044[0x50 - 0x44]; 50 u8 res044[0x50 - 0x44];
45 __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */ 51 u32 gpindr; /* 0x.0050 - General-Purpose Input Data
52 * Register
53 */
46 u8 res054[0x60 - 0x54]; 54 u8 res054[0x60 - 0x54];
47 __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ 55 u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
48 __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */ 56 * Multiplex Control
49 __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */ 57 */
58 u32 pmuxcr2; /* 0x.0064 - Alternate function signal
59 * multiplex control 2
60 */
61 u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
50 u8 res06c[0x70 - 0x6c]; 62 u8 res06c[0x70 - 0x6c];
51 __be32 devdisr; /* 0x.0070 - Device Disable Control */ 63 u32 devdisr; /* 0x.0070 - Device Disable Control */
52#define CCSR_GUTS_DEVDISR_TB1 0x00001000 64#define CCSR_GUTS_DEVDISR_TB1 0x00001000
53#define CCSR_GUTS_DEVDISR_TB0 0x00004000 65#define CCSR_GUTS_DEVDISR_TB0 0x00004000
54 __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ 66 u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
55 u8 res078[0x7c - 0x78]; 67 u8 res078[0x7c - 0x78];
56 __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */ 68 u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
57 __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ 69 * Register
58 __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */ 70 */
59 __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */ 71 u32 powmgtcsr; /* 0x.0080 - Power Management Status and
60 __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */ 72 * Control Register
61 __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ 73 */
62 __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ 74 u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
63 __be32 ectrstcr; /* 0x.0098 - Exception reset control register */ 75 * Configuration Register
64 __be32 autorstsr; /* 0x.009c - Automatic reset status register */ 76 */
65 __be32 pvr; /* 0x.00a0 - Processor Version Register */ 77 u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
66 __be32 svr; /* 0x.00a4 - System Version Register */ 78 * Configuration Register
79 */
80 u32 pmcdr; /* 0x.008c - 4Power management clock disable
81 * register
82 */
83 u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
84 u32 rstrscr; /* 0x.0094 - Reset Request Status and
85 * Control Register
86 */
87 u32 ectrstcr; /* 0x.0098 - Exception reset control register */
88 u32 autorstsr; /* 0x.009c - Automatic reset status register */
89 u32 pvr; /* 0x.00a0 - Processor Version Register */
90 u32 svr; /* 0x.00a4 - System Version Register */
67 u8 res0a8[0xb0 - 0xa8]; 91 u8 res0a8[0xb0 - 0xa8];
68 __be32 rstcr; /* 0x.00b0 - Reset Control Register */ 92 u32 rstcr; /* 0x.00b0 - Reset Control Register */
69 u8 res0b4[0xc0 - 0xb4]; 93 u8 res0b4[0xc0 - 0xb4];
70 __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register 94 u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
71 Called 'elbcvselcr' on 86xx SOCs */ 95 Called 'elbcvselcr' on 86xx SOCs */
72 u8 res0c4[0x100 - 0xc4]; 96 u8 res0c4[0x100 - 0xc4];
73 __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers 97 u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
74 There are 16 registers */ 98 There are 16 registers */
75 u8 res140[0x224 - 0x140]; 99 u8 res140[0x224 - 0x140];
76 __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */ 100 u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
77 __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */ 101 u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
78 u8 res22c[0x604 - 0x22c]; 102 u8 res22c[0x604 - 0x22c];
79 __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */ 103 u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
80 u8 res608[0x800 - 0x608]; 104 u8 res608[0x800 - 0x608];
81 __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */ 105 u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
82 u8 res804[0x900 - 0x804]; 106 u8 res804[0x900 - 0x804];
83 __be32 ircr; /* 0x.0900 - Infrared Control Register */ 107 u32 ircr; /* 0x.0900 - Infrared Control Register */
84 u8 res904[0x908 - 0x904]; 108 u8 res904[0x908 - 0x904];
85 __be32 dmacr; /* 0x.0908 - DMA Control Register */ 109 u32 dmacr; /* 0x.0908 - DMA Control Register */
86 u8 res90c[0x914 - 0x90c]; 110 u8 res90c[0x914 - 0x90c];
87 __be32 elbccr; /* 0x.0914 - eLBC Control Register */ 111 u32 elbccr; /* 0x.0914 - eLBC Control Register */
88 u8 res918[0xb20 - 0x918]; 112 u8 res918[0xb20 - 0x918];
89 __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ 113 u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
90 __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ 114 u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
91 __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ 115 u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
92 u8 resb2c[0xe00 - 0xb2c]; 116 u8 resb2c[0xe00 - 0xb2c];
93 __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */ 117 u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
94 u8 rese04[0xe10 - 0xe04]; 118 u8 rese04[0xe10 - 0xe04];
95 __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ 119 u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
96 u8 rese14[0xe20 - 0xe14]; 120 u8 rese14[0xe20 - 0xe14];
97 __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ 121 u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
98 __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */ 122 u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
123 * register
124 */
99 u8 rese28[0xf04 - 0xe28]; 125 u8 rese28[0xf04 - 0xe28];
100 __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ 126 u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
101 __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ 127 u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
102 u8 resf0c[0xf2c - 0xf0c]; 128 u8 resf0c[0xf2c - 0xf0c];
103 __be32 itcr; /* 0x.0f2c - Internal transaction control register */ 129 u32 itcr; /* 0x.0f2c - Internal transaction control
130 * register
131 */
104 u8 resf30[0xf40 - 0xf30]; 132 u8 resf30[0xf40 - 0xf30];
105 __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */ 133 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
106 __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */ 134 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
107} __attribute__ ((packed)); 135} __attribute__ ((packed));
108 136
137u32 fsl_guts_get_svr(void);
109 138
110/* Alternate function signal multiplex control */ 139/* Alternate function signal multiplex control */
111#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x)) 140#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 16:43:38 -0500