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authorMaxime Ripard <maxime.ripard@free-electrons.com>2015-07-20 04:41:32 -0400
committerVinod Koul <vinod.koul@intel.com>2015-08-05 01:23:52 -0400
commit77a68e56aae141d3e9c740a0ac43362af75d4890 (patch)
tree331c81fe450bb885ec34ccedc4fd57fdc1bc68e5 /include/linux/dmaengine.h
parent056f6c87028544de934f27caf95aa1545d585767 (diff)
dmaengine: Add an enum for the dmaengine alignment constraints
Most drivers need to set constraints on the buffer alignment for async tx operations. However, even though it is documented, some drivers either use a defined constant that is not matching what the alignment variable expects (like DMA_BUSWIDTH_* constants) or fill the alignment in bytes instead of power of two. Add a new enum for these alignments that matches what the framework expects, and convert the drivers to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'include/linux/dmaengine.h')
-rw-r--r--include/linux/dmaengine.h25
1 files changed, 20 insertions, 5 deletions
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index e2f5eb419976..03ed832adbc2 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -585,6 +585,20 @@ struct dma_tx_state {
585}; 585};
586 586
587/** 587/**
588 * enum dmaengine_alignment - defines alignment of the DMA async tx
589 * buffers
590 */
591enum dmaengine_alignment {
592 DMAENGINE_ALIGN_1_BYTE = 0,
593 DMAENGINE_ALIGN_2_BYTES = 1,
594 DMAENGINE_ALIGN_4_BYTES = 2,
595 DMAENGINE_ALIGN_8_BYTES = 3,
596 DMAENGINE_ALIGN_16_BYTES = 4,
597 DMAENGINE_ALIGN_32_BYTES = 5,
598 DMAENGINE_ALIGN_64_BYTES = 6,
599};
600
601/**
588 * struct dma_device - info on the entity supplying DMA services 602 * struct dma_device - info on the entity supplying DMA services
589 * @chancnt: how many DMA channels are supported 603 * @chancnt: how many DMA channels are supported
590 * @privatecnt: how many DMA channels are requested by dma_request_channel 604 * @privatecnt: how many DMA channels are requested by dma_request_channel
@@ -645,10 +659,10 @@ struct dma_device {
645 dma_cap_mask_t cap_mask; 659 dma_cap_mask_t cap_mask;
646 unsigned short max_xor; 660 unsigned short max_xor;
647 unsigned short max_pq; 661 unsigned short max_pq;
648 u8 copy_align; 662 enum dmaengine_alignment copy_align;
649 u8 xor_align; 663 enum dmaengine_alignment xor_align;
650 u8 pq_align; 664 enum dmaengine_alignment pq_align;
651 u8 fill_align; 665 enum dmaengine_alignment fill_align;
652 #define DMA_HAS_PQ_CONTINUE (1 << 15) 666 #define DMA_HAS_PQ_CONTINUE (1 << 15)
653 667
654 int dev_id; 668 int dev_id;
@@ -833,7 +847,8 @@ static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc
833 return desc->tx_submit(desc); 847 return desc->tx_submit(desc);
834} 848}
835 849
836static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len) 850static inline bool dmaengine_check_align(enum dmaengine_alignment align,
851 size_t off1, size_t off2, size_t len)
837{ 852{
838 size_t mask; 853 size_t mask;
839 854