diff options
author | Florian Fainelli <f.fainelli@gmail.com> | 2014-02-13 19:08:45 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2014-02-14 00:27:58 -0500 |
commit | b560a58c45c66f68936127040e86b7f02e4c5332 (patch) | |
tree | c26590a91c655f38e7857446f22669f73dc58d1e /include/linux/brcmphy.h | |
parent | 439d39a9ac8fbbba9c04581361188f33f21ced50 (diff) |
net: phy: add Broadcom BCM7xxx internal PHY driver
This patch adds support for the Broadcom BCM7xxx Set Top Box SoCs
internal PHYs. This driver supports the following generation of SoCs:
- BCM7366, BCM7439, BCM7445 (28nm process)
- all 40nm and 65nm (older MIPS-based SoCs)
The PHYs on these SoCs require a bunch of workarounds to operate
correctly, both during configuration time and at suspend/resume time,
the driver handles that for us.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/brcmphy.h')
-rw-r--r-- | include/linux/brcmphy.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h index 104e3efe46af..6f76277baf39 100644 --- a/include/linux/brcmphy.h +++ b/include/linux/brcmphy.h | |||
@@ -13,10 +13,17 @@ | |||
13 | #define PHY_ID_BCM5461 0x002060c0 | 13 | #define PHY_ID_BCM5461 0x002060c0 |
14 | #define PHY_ID_BCM57780 0x03625d90 | 14 | #define PHY_ID_BCM57780 0x03625d90 |
15 | 15 | ||
16 | #define PHY_ID_BCM7366 0x600d8490 | ||
17 | #define PHY_ID_BCM7439 0x600d8480 | ||
18 | #define PHY_ID_BCM7445 0x600d8510 | ||
19 | #define PHY_ID_BCM7XXX_28 0x600d8400 | ||
20 | |||
16 | #define PHY_BCM_OUI_MASK 0xfffffc00 | 21 | #define PHY_BCM_OUI_MASK 0xfffffc00 |
17 | #define PHY_BCM_OUI_1 0x00206000 | 22 | #define PHY_BCM_OUI_1 0x00206000 |
18 | #define PHY_BCM_OUI_2 0x0143bc00 | 23 | #define PHY_BCM_OUI_2 0x0143bc00 |
19 | #define PHY_BCM_OUI_3 0x03625c00 | 24 | #define PHY_BCM_OUI_3 0x03625c00 |
25 | #define PHY_BCM_OUI_4 0x600d0000 | ||
26 | #define PHY_BCM_OUI_5 0x03625e00 | ||
20 | 27 | ||
21 | 28 | ||
22 | #define PHY_BCM_FLAGS_MODE_COPPER 0x00000001 | 29 | #define PHY_BCM_FLAGS_MODE_COPPER 0x00000001 |
@@ -31,6 +38,8 @@ | |||
31 | #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000 | 38 | #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000 |
32 | #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000 | 39 | #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000 |
33 | #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000 | 40 | #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000 |
41 | /* Broadcom BCM7xxx specific workarounds */ | ||
42 | #define PHY_BRCM_100MBPS_WAR 0x00010000 | ||
34 | #define PHY_BCM_FLAGS_VALID 0x80000000 | 43 | #define PHY_BCM_FLAGS_VALID 0x80000000 |
35 | 44 | ||
36 | /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */ | 45 | /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */ |