Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM Device-tree updates from Olof Johansson:
 "Besides new bindings and additional descriptions of hardware blocks
  for various SoCs and boards, the main new contents here is:

  SoCs:
   - Intel Agilex (SoCFPGA)
   - NXP i.MX8MM (Quad Cortex-A53 with media/graphics focus)

  New boards:
   - Allwinner:
      + RerVision H3-DVK (H3)
      + Oceanic 5205 5inMFD (H6)
      + Beelink GS2 (H6)
      + Orange Pi 3 (H6)
   - Rockchip:
      + Orange Pi RK3399
      + Nanopi NEO4
      + Veyron-Mighty Chromebook variant
   - Amlogic:
      + SEI Robotics SEI510
   - ST Micro:
      + stm32mp157a discovery1
      + stm32mp157c discovery2
   - NXP:
      + Eckelmann ci4x10 (i.MX6DL)
      + i.MX8MM EVK (i.MX8MM)
      + ZII i.MX7 RPU2 (i.MX7)
      + ZII SPB4 (VF610)
      + Zii Ultra (i.MX8M)
      + TQ TQMa7S (i.MX7Solo)
      + TQ TQMa7D (i.MX7Dual)
      + Kobo Aura (i.MX50)
      + Menlosystems M53 (i.MX53)j
   - Nvidia:
      + Jetson Nano (Tegra T210)"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (593 commits)
  arm64: dts: bitmain: Add UART pinctrl support for Sophon Edge
  arm64: dts: bitmain: Add pinctrl support for BM1880 SoC
  arm64: dts: bitmain: Add GPIO Line names for Sophon Edge board
  arm64: dts: bitmain: Add GPIO support for BM1880 SoC
  ARM: dts: gemini: Indent DIR-685 partition table
  dt-bindings: hwmon (pwm-fan) Remove dead "cooling-*-state" properties
  ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY
  arm64: dts: msm8998: thermal: Restrict thermal zone name length to under 20
  arm64: dts: msm8998: thermal: Fix number of supported sensors
  arm64: dts: msm8998-mtp: thermal: Remove skin and battery thermal zones
  arm64: dts: exynos: Move fixed-clocks out of soc
  arm64: dts: exynos: Move pmu and timer nodes out of soc
  ARM: dts: s5pv210: Fix camera clock provider on Goni board
  ARM: dts: exynos: Properly override node to use MDMA0 on Universal C210
  ARM: dts: exynos: Move fixed-clocks out of soc on Exynos3250
  ARM: dts: exynos: Remove unneeded address/size cells from fixed-clock on Exynos3250
  ARM: dts: exynos: Move pmu and timer nodes out of soc
  arm64: dts: rockchip: fix IO domain voltage setting of APIO5 on rockpro64
  arm64: dts: db820c: Add sound card support
  arm64: dts: apq8096-db820c: Add HDMI display support
  ...

5 files changed, 156 insertions, 27 deletions

diff --git a/include/dt-bindings/clock/xlnx,zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h
index 4aebe6e2049e..cdc4c0b9a374 100644
--- a/include/dt-bindings/clock/xlnx,zynqmp-clk.h
+++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h
@@ -54,14 +54,14 @@
 #define IOU_SWITCH              42
 #define GEM_TSU_REF             43
 #define GEM_TSU                 44
-#define GEM0_REF                45
-#define GEM1_REF                46
-#define GEM2_REF                47
-#define GEM3_REF                48
-#define GEM0_TX                 49
-#define GEM1_TX                 50
-#define GEM2_TX                 51
-#define GEM3_TX                 52
+#define GEM0_TX                 45
+#define GEM1_TX                 46
+#define GEM2_TX                 47
+#define GEM3_TX                 48
+#define GEM0_RX                 49
+#define GEM1_RX                 50
+#define GEM2_RX                 51
+#define GEM3_RX                 52
 #define QSPI_REF                53
 #define SDIO0_REF               54
 #define SDIO1_REF               55
@@ -112,5 +112,15 @@
 #define VPLL_POST_SRC           100
 #define CAN0_MIO                101
 #define CAN1_MIO                102
+#define ACPU_FULL               103
+#define GEM0_REF                104
+#define GEM1_REF                105
+#define GEM2_REF                106
+#define GEM3_REF                107
+#define GEM0_REF_UNG            108
+#define GEM1_REF_UNG            109
+#define GEM2_REF_UNG            110
+#define GEM3_REF_UNG            111
+#define LPD_WDT                 112
 
 #endif
diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h
index 4481f2d60d65..4e61f6485097 100644
--- a/include/dt-bindings/firmware/imx/rsrc.h
+++ b/include/dt-bindings/firmware/imx/rsrc.h
@@ -36,15 +36,11 @@
 #define IMX_SC_R_DC_0_BLIT1             20
 #define IMX_SC_R_DC_0_BLIT2             21
 #define IMX_SC_R_DC_0_BLIT_OUT          22
-#define IMX_SC_R_DC_0_CAPTURE0          23
-#define IMX_SC_R_DC_0_CAPTURE1          24
+#define IMX_SC_R_PERF                   23
 #define IMX_SC_R_DC_0_WARP              25
-#define IMX_SC_R_DC_0_INTEGRAL0         26
-#define IMX_SC_R_DC_0_INTEGRAL1         27
 #define IMX_SC_R_DC_0_VIDEO0            28
 #define IMX_SC_R_DC_0_VIDEO1            29
 #define IMX_SC_R_DC_0_FRAC0             30
-#define IMX_SC_R_DC_0_FRAC1             31
 #define IMX_SC_R_DC_0                   32
 #define IMX_SC_R_GPU_2_PID0             33
 #define IMX_SC_R_DC_0_PLL_0             34
@@ -53,17 +49,11 @@
 #define IMX_SC_R_DC_1_BLIT1             37
 #define IMX_SC_R_DC_1_BLIT2             38
 #define IMX_SC_R_DC_1_BLIT_OUT          39
-#define IMX_SC_R_DC_1_CAPTURE0          40
-#define IMX_SC_R_DC_1_CAPTURE1          41
 #define IMX_SC_R_DC_1_WARP              42
-#define IMX_SC_R_DC_1_INTEGRAL0         43
-#define IMX_SC_R_DC_1_INTEGRAL1         44
 #define IMX_SC_R_DC_1_VIDEO0            45
 #define IMX_SC_R_DC_1_VIDEO1            46
 #define IMX_SC_R_DC_1_FRAC0             47
-#define IMX_SC_R_DC_1_FRAC1             48
 #define IMX_SC_R_DC_1                   49
-#define IMX_SC_R_GPU_3_PID0             50
 #define IMX_SC_R_DC_1_PLL_0             51
 #define IMX_SC_R_DC_1_PLL_1             52
 #define IMX_SC_R_SPI_0                  53
@@ -303,8 +293,6 @@
 #define IMX_SC_R_M4_0_UART              287
 #define IMX_SC_R_M4_0_I2C               288
 #define IMX_SC_R_M4_0_INTMUX            289
-#define IMX_SC_R_M4_0_SIM               290
-#define IMX_SC_R_M4_0_WDOG              291
 #define IMX_SC_R_M4_0_MU_0B             292
 #define IMX_SC_R_M4_0_MU_0A0            293
 #define IMX_SC_R_M4_0_MU_0A1            294
@@ -323,8 +311,6 @@
 #define IMX_SC_R_M4_1_UART              307
 #define IMX_SC_R_M4_1_I2C               308
 #define IMX_SC_R_M4_1_INTMUX            309
-#define IMX_SC_R_M4_1_SIM               310
-#define IMX_SC_R_M4_1_WDOG              311
 #define IMX_SC_R_M4_1_MU_0B             312
 #define IMX_SC_R_M4_1_MU_0A0            313
 #define IMX_SC_R_M4_1_MU_0A1            314
@@ -337,7 +323,7 @@
 #define IMX_SC_R_IRQSTR_SCU2            321
 #define IMX_SC_R_IRQSTR_DSP             322
 #define IMX_SC_R_ELCDIF_PLL             323
-#define IMX_SC_R_UNUSED6                324
+#define IMX_SC_R_OCRAM                  324
 #define IMX_SC_R_AUDIO_PLL_0            325
 #define IMX_SC_R_PI_0                   326
 #define IMX_SC_R_PI_0_PWM_0             327
@@ -554,6 +540,11 @@
 #define IMX_SC_R_VPU_MU_3               538
 #define IMX_SC_R_VPU_ENC_1              539
 #define IMX_SC_R_VPU                    540
-#define IMX_SC_R_LAST                   541
+#define IMX_SC_R_DMA_5_CH0              541
+#define IMX_SC_R_DMA_5_CH1              542
+#define IMX_SC_R_DMA_5_CH2              543
+#define IMX_SC_R_DMA_5_CH3              544
+#define IMX_SC_R_ATTESTATION            545
+#define IMX_SC_R_LAST                   546
 
 #endif /* __DT_BINDINGS_RSCRC_IMX_H */
diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h
index 7d947a597220..17877e85980b 100644
--- a/include/dt-bindings/pinctrl/am33xx.h
+++ b/include/dt-bindings/pinctrl/am33xx.h
@@ -40,5 +40,133 @@
 #undef PIN_OFF_INPUT_PULLDOWN
 #undef PIN_OFF_WAKEUPENABLE
 
-#endif
+#define AM335X_PIN_OFFSET_MIN                   0x0800U
+
+#define AM335X_PIN_GPMC_AD0                     0x800
+#define AM335X_PIN_GPMC_AD1                     0x804
+#define AM335X_PIN_GPMC_AD2                     0x808
+#define AM335X_PIN_GPMC_AD3                     0x80c
+#define AM335X_PIN_GPMC_AD4                     0x810
+#define AM335X_PIN_GPMC_AD5                     0x814
+#define AM335X_PIN_GPMC_AD6                     0x818
+#define AM335X_PIN_GPMC_AD7                     0x81c
+#define AM335X_PIN_GPMC_AD8                     0x820
+#define AM335X_PIN_GPMC_AD9                     0x824
+#define AM335X_PIN_GPMC_AD10                    0x828
+#define AM335X_PIN_GPMC_AD11                    0x82c
+#define AM335X_PIN_GPMC_AD12                    0x830
+#define AM335X_PIN_GPMC_AD13                    0x834
+#define AM335X_PIN_GPMC_AD14                    0x838
+#define AM335X_PIN_GPMC_AD15                    0x83c
+#define AM335X_PIN_GPMC_A0                      0x840
+#define AM335X_PIN_GPMC_A1                      0x844
+#define AM335X_PIN_GPMC_A2                      0x848
+#define AM335X_PIN_GPMC_A3                      0x84c
+#define AM335X_PIN_GPMC_A4                      0x850
+#define AM335X_PIN_GPMC_A5                      0x854
+#define AM335X_PIN_GPMC_A6                      0x858
+#define AM335X_PIN_GPMC_A7                      0x85c
+#define AM335X_PIN_GPMC_A8                      0x860
+#define AM335X_PIN_GPMC_A9                      0x864
+#define AM335X_PIN_GPMC_A10                     0x868
+#define AM335X_PIN_GPMC_A11                     0x86c
+#define AM335X_PIN_GPMC_WAIT0                   0x870
+#define AM335X_PIN_GPMC_WPN                     0x874
+#define AM335X_PIN_GPMC_BEN1                    0x878
+#define AM335X_PIN_GPMC_CSN0                    0x87c
+#define AM335X_PIN_GPMC_CSN1                    0x880
+#define AM335X_PIN_GPMC_CSN2                    0x884
+#define AM335X_PIN_GPMC_CSN3                    0x888
+#define AM335X_PIN_GPMC_CLK                     0x88c
+#define AM335X_PIN_GPMC_ADVN_ALE                0x890
+#define AM335X_PIN_GPMC_OEN_REN                 0x894
+#define AM335X_PIN_GPMC_WEN                     0x898
+#define AM335X_PIN_GPMC_BEN0_CLE                0x89c
+#define AM335X_PIN_LCD_DATA0                    0x8a0
+#define AM335X_PIN_LCD_DATA1                    0x8a4
+#define AM335X_PIN_LCD_DATA2                    0x8a8
+#define AM335X_PIN_LCD_DATA3                    0x8ac
+#define AM335X_PIN_LCD_DATA4                    0x8b0
+#define AM335X_PIN_LCD_DATA5                    0x8b4
+#define AM335X_PIN_LCD_DATA6                    0x8b8
+#define AM335X_PIN_LCD_DATA7                    0x8bc
+#define AM335X_PIN_LCD_DATA8                    0x8c0
+#define AM335X_PIN_LCD_DATA9                    0x8c4
+#define AM335X_PIN_LCD_DATA10                   0x8c8
+#define AM335X_PIN_LCD_DATA11                   0x8cc
+#define AM335X_PIN_LCD_DATA12                   0x8d0
+#define AM335X_PIN_LCD_DATA13                   0x8d4
+#define AM335X_PIN_LCD_DATA14                   0x8d8
+#define AM335X_PIN_LCD_DATA15                   0x8dc
+#define AM335X_PIN_LCD_VSYNC                    0x8e0
+#define AM335X_PIN_LCD_HSYNC                    0x8e4
+#define AM335X_PIN_LCD_PCLK                     0x8e8
+#define AM335X_PIN_LCD_AC_BIAS_EN               0x8ec
+#define AM335X_PIN_MMC0_DAT3                    0x8f0
+#define AM335X_PIN_MMC0_DAT2                    0x8f4
+#define AM335X_PIN_MMC0_DAT1                    0x8f8
+#define AM335X_PIN_MMC0_DAT0                    0x8fc
+#define AM335X_PIN_MMC0_CLK                     0x900
+#define AM335X_PIN_MMC0_CMD                     0x904
+#define AM335X_PIN_MII1_COL                     0x908
+#define AM335X_PIN_MII1_CRS                     0x90c
+#define AM335X_PIN_MII1_RX_ER                   0x910
+#define AM335X_PIN_MII1_TX_EN                   0x914
+#define AM335X_PIN_MII1_RX_DV                   0x918
+#define AM335X_PIN_MII1_TXD3                    0x91c
+#define AM335X_PIN_MII1_TXD2                    0x920
+#define AM335X_PIN_MII1_TXD1                    0x924
+#define AM335X_PIN_MII1_TXD0                    0x928
+#define AM335X_PIN_MII1_TX_CLK                  0x92c
+#define AM335X_PIN_MII1_RX_CLK                  0x930
+#define AM335X_PIN_MII1_RXD3                    0x934
+#define AM335X_PIN_MII1_RXD2                    0x938
+#define AM335X_PIN_MII1_RXD1                    0x93c
+#define AM335X_PIN_MII1_RXD0                    0x940
+#define AM335X_PIN_RMII1_REF_CLK                0x944
+#define AM335X_PIN_MDIO                         0x948
+#define AM335X_PIN_MDC                          0x94c
+#define AM335X_PIN_SPI0_SCLK                    0x950
+#define AM335X_PIN_SPI0_D0                      0x954
+#define AM335X_PIN_SPI0_D1                      0x958
+#define AM335X_PIN_SPI0_CS0                     0x95c
+#define AM335X_PIN_SPI0_CS1                     0x960
+#define AM335X_PIN_ECAP0_IN_PWM0_OUT            0x964
+#define AM335X_PIN_UART0_CTSN                   0x968
+#define AM335X_PIN_UART0_RTSN                   0x96c
+#define AM335X_PIN_UART0_RXD                    0x970
+#define AM335X_PIN_UART0_TXD                    0x974
+#define AM335X_PIN_UART1_CTSN                   0x978
+#define AM335X_PIN_UART1_RTSN                   0x97c
+#define AM335X_PIN_UART1_RXD                    0x980
+#define AM335X_PIN_UART1_TXD                    0x984
+#define AM335X_PIN_I2C0_SDA                     0x988
+#define AM335X_PIN_I2C0_SCL                     0x98c
+#define AM335X_PIN_MCASP0_ACLKX                 0x990
+#define AM335X_PIN_MCASP0_FSX                   0x994
+#define AM335X_PIN_MCASP0_AXR0                  0x998
+#define AM335X_PIN_MCASP0_AHCLKR                0x99c
+#define AM335X_PIN_MCASP0_ACLKR                 0x9a0
+#define AM335X_PIN_MCASP0_FSR                   0x9a4
+#define AM335X_PIN_MCASP0_AXR1                  0x9a8
+#define AM335X_PIN_MCASP0_AHCLKX                0x9ac
+#define AM335X_PIN_XDMA_EVENT_INTR0             0x9b0
+#define AM335X_PIN_XDMA_EVENT_INTR1             0x9b4
+#define AM335X_PIN_WARMRSTN                     0x9b8
+#define AM335X_PIN_NNMI                         0x9c0
+#define AM335X_PIN_TMS                          0x9d0
+#define AM335X_PIN_TDI                          0x9d4
+#define AM335X_PIN_TDO                          0x9d8
+#define AM335X_PIN_TCK                          0x9dc
+#define AM335X_PIN_TRSTN                        0x9e0
+#define AM335X_PIN_EMU0                         0x9e4
+#define AM335X_PIN_EMU1                         0x9e8
+#define AM335X_PIN_RTC_PWRONRSTN                0x9f8
+#define AM335X_PIN_PMIC_POWER_EN                0x9fc
+#define AM335X_PIN_EXT_WAKEUP                   0xa00
+#define AM335X_PIN_USB0_DRVVBUS                 0xa1c
+#define AM335X_PIN_USB1_DRVVBUS                 0xa34
 
+#define AM335X_PIN_OFFSET_MAX                   0x0a34U
+
+#endif
diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
index 49b5dea2b388..625718042413 100644
--- a/include/dt-bindings/pinctrl/omap.h
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -65,6 +65,7 @@
 #define DM814X_IOPAD(pa, val)           OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
 #define DM816X_IOPAD(pa, val)           OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
 #define AM33XX_IOPAD(pa, val)           OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define AM33XX_PADCONF(pa, dir, mux)    OMAP_IOPAD_OFFSET((pa), 0x0800) ((dir) | (mux))
 
 /*
  * Macros to allow using the offset from the padconf physical address
diff --git a/include/dt-bindings/power/r8a77965-sysc.h b/include/dt-bindings/power/r8a77965-sysc.h
index 05a4b5917314..de82d8a15ea1 100644
--- a/include/dt-bindings/power/r8a77965-sysc.h
+++ b/include/dt-bindings/power/r8a77965-sysc.h
@@ -21,7 +21,6 @@
 #define R8A77965_PD_A3VC                14
 #define R8A77965_PD_3DG_A               17
 #define R8A77965_PD_3DG_B               18
-#define R8A77965_PD_A3IR                24
 #define R8A77965_PD_A2VC1               26
 
 /* Always-on power area */