Merge tag 'pinctrl-v4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for v4.18.

  No core changes this time! Just a calm all-over-the-place drivers,
  updates and fixes cycle as it seems.

  New drivers/subdrivers:

   - Actions Semiconductor S900 driver with more Actions variants for
     S700, S500 in the pipe. Also generic GPIO support on top of the
     same driver and IRQ support is in the pipe.

   - Renesas r8a77470 PFC support.

   - Renesas r8a77990 PFC support.

   - Allwinner Sunxi H6 R_PIO support.

   - Rockchip PX30 support.

   - Meson Meson8m2 support.

   - Remove support for the ill-fated Samsung Exynos 5440 SoC.

  Improvements:

   - Context save/restore support in pinctrl-single.

   - External interrupt support for the Mediatek MT7622.

   - Qualcomm ACPI HID QCOM8002 supported.

  Fixes:

   - Fix up suspend/resume support for Exynos 5433.

   - Fix Strago DMI fixes on the Intel Cherryview"

* tag 'pinctrl-v4.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
  pinctrl: cherryview: limit Strago DMI workarounds to version 1.0
  pinctrl: at91-pio4: add missing of_node_put
  pinctrl: armada-37xx: Fix spurious irq management
  gpiolib: discourage gpiochip_add_pin[group]_range for DT pinctrls
  pinctrl: msm: fix gpio-hog related boot issues
  MAINTAINERS: update entry for Mediatek pin controller
  pinctrl: mediatek: remove unused fields in struct mtk_eint_hw
  pinctrl: mediatek: use generic EINT register maps for each SoC
  pinctrl: mediatek: add EINT support to MT7622 SoC
  pinctrl: mediatek: refactor EINT related code for all MediaTek pinctrl can fit
  dt-bindings: pinctrl: add external interrupt support to MT7622 pinctrl
  pinctrl: freescale: Switch to SPDX identifier
  pinctrl: samsung: Fix suspend/resume for Exynos5433 GPF1..5 banks
  pinctrl: sh-pfc: rcar-gen3: Fix grammar in static pin comments
  pinctrl: sh-pfc: r8a77965: Add I2C pin support
  pinctrl: sh-pfc: r8a77990: Add EthernetAVB pins, groups and functions
  pinctrl: sh-pfc: r8a77990: Add I2C{1,2,4,5,6,7} pins, groups and functions
  pinctrl: sh-pfc: r8a77990: Add SCIF pins, groups and functions
  pinctrl: sh-pfc: r8a77990: Add bias pinconf support
  pinctrl: sh-pfc: Initial R8A77990 PFC support
  ...

92 files changed, 11689 insertions, 2130 deletions

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 55d596f3035e..5dfd3c17fffc 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -2078,6 +2078,11 @@ EXPORT_SYMBOL_GPL(gpiochip_generic_config);
  * @pctldev: the pin controller to map to
  * @gpio_offset: the start offset in the current gpio_chip number space
  * @pin_group: name of the pin group inside the pin controller
+ *
+ * Calling this function directly from a DeviceTree-supported
+ * pinctrl driver is DEPRECATED. Please see Section 2.1 of
+ * Documentation/devicetree/bindings/gpio/gpio.txt on how to
+ * bind pinctrl and gpio drivers via the "gpio-ranges" property.
  */
 int gpiochip_add_pingroup_range(struct gpio_chip *chip,
                         struct pinctrl_dev *pctldev,
@@ -2131,6 +2136,11 @@ EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range);
  *
  * Returns:
  * 0 on success, or a negative error-code on failure.
+ *
+ * Calling this function directly from a DeviceTree-supported
+ * pinctrl driver is DEPRECATED. Please see Section 2.1 of
+ * Documentation/devicetree/bindings/gpio/gpio.txt on how to
+ * bind pinctrl and gpio drivers via the "gpio-ranges" property.
  */
 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
                            unsigned int gpio_offset, unsigned int pin_offset,
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 01fe8e0455a0..dd50371225bc 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -337,6 +337,7 @@ config PINCTRL_OCELOT
         select GENERIC_PINMUX_FUNCTIONS
         select REGMAP_MMIO
 
+source "drivers/pinctrl/actions/Kconfig"
 source "drivers/pinctrl/aspeed/Kconfig"
 source "drivers/pinctrl/bcm/Kconfig"
 source "drivers/pinctrl/berlin/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 657332b121fb..de40863e7297 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_PINCTRL_INGENIC)	+= pinctrl-ingenic.o
 obj-$(CONFIG_PINCTRL_RK805)     += pinctrl-rk805.o
 obj-$(CONFIG_PINCTRL_OCELOT)    += pinctrl-ocelot.o
 
+obj-y                           += actions/
 obj-$(CONFIG_ARCH_ASPEED)       += aspeed/
 obj-y                           += bcm/
 obj-$(CONFIG_PINCTRL_BERLIN)    += berlin/
diff --git a/drivers/pinctrl/actions/Kconfig b/drivers/pinctrl/actions/Kconfig
new file mode 100644
index 000000000000..490927b4ea76
--- /dev/null
+++ b/drivers/pinctrl/actions/Kconfig
@@ -0,0 +1,15 @@
+config PINCTRL_OWL
+        bool "Actions Semi OWL pinctrl driver"
+        depends on (ARCH_ACTIONS || COMPILE_TEST) && OF
+        select PINMUX
+        select PINCONF
+        select GENERIC_PINCONF
+        select GPIOLIB
+        help
+          Say Y here to enable Actions Semi OWL pinctrl driver
+
+config PINCTRL_S900
+        bool "Actions Semi S900 pinctrl driver"
+        depends on PINCTRL_OWL
+        help
+          Say Y here to enable Actions Semi S900 pinctrl driver
diff --git a/drivers/pinctrl/actions/Makefile b/drivers/pinctrl/actions/Makefile
new file mode 100644
index 000000000000..bd232d28400f
--- /dev/null
+++ b/drivers/pinctrl/actions/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_PINCTRL_OWL)       += pinctrl-owl.o
+obj-$(CONFIG_PINCTRL_S900)      += pinctrl-s900.o
diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c
new file mode 100644
index 000000000000..76243caa08c6
--- /dev/null
+++ b/drivers/pinctrl/actions/pinctrl-owl.c
@@ -0,0 +1,785 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OWL SoC's Pinctrl driver
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <liuwei@actions-semi.com>
+ *
+ * Copyright (c) 2018 Linaro Ltd.
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-owl.h"
+
+/**
+ * struct owl_pinctrl - pinctrl state of the device
+ * @dev: device handle
+ * @pctrldev: pinctrl handle
+ * @chip: gpio chip
+ * @lock: spinlock to protect registers
+ * @soc: reference to soc_data
+ * @base: pinctrl register base address
+ */
+struct owl_pinctrl {
+        struct device *dev;
+        struct pinctrl_dev *pctrldev;
+        struct gpio_chip chip;
+        raw_spinlock_t lock;
+        struct clk *clk;
+        const struct owl_pinctrl_soc_data *soc;
+        void __iomem *base;
+};
+
+static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
+{
+        u32 reg_val;
+
+        reg_val = readl_relaxed(base);
+
+        reg_val = (reg_val & ~mask) | (val & mask);
+
+        writel_relaxed(reg_val, base);
+}
+
+static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
+                                u32 bit, u32 width)
+{
+        u32 tmp, mask;
+
+        tmp = readl_relaxed(pctrl->base + reg);
+        mask = (1 << width) - 1;
+
+        return (tmp >> bit) & mask;
+}
+
+static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
+                                u32 bit, u32 width)
+{
+        u32 mask;
+
+        mask = (1 << width) - 1;
+        mask = mask << bit;
+
+        owl_update_bits(pctrl->base + reg, mask, (arg << bit));
+}
+
+static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
+{
+        struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
+
+        return pctrl->soc->ngroups;
+}
+
+static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
+                                unsigned int group)
+{
+        struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
+
+        return pctrl->soc->groups[group].name;
+}
+
+static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
+                                unsigned int group,
+                                const unsigned int **pins,
+                                unsigned int *num_pins)
+{
+        struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
+
+        *pins = pctrl->soc->groups[group].pads;
+        *num_pins = pctrl->soc->groups[group].npads;
+
+        return 0;
+}
+
+static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
+                                struct seq_file *s,
+                                unsigned int offset)
+{
+        struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
+
+        seq_printf(s, "%s", dev_name(pctrl->dev));
+}
+
+static struct pinctrl_ops owl_pinctrl_ops = {
+        .get_groups_count = owl_get_groups_count,
+        .get_group_name = owl_get_group_name,
+        .get_group_pins = owl_get_group_pins,
+        .pin_dbg_show = owl_pin_dbg_show,
+        .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
+        .dt_free_map = pinctrl_utils_free_map,
+};
+
+static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
+{
+        struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
+
+        return pctrl->soc->nfunctions;
+}
+
+static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
+                                unsigned int function)
+{
+        struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
+
+        return pctrl->soc->functions[function].name;
+}
+
+static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
+                                unsigned int function,
+                                const char * const **groups,
+                                unsigned int * const num_groups)
+{
+        struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
+
+        *groups = pctrl->soc->functions[function].groups;
+        *num_groups = pctrl->soc->functions[function].ngroups;
+
+        return 0;
+}
+
+static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
+                                int function,
+                                u32 *mask,
+                                u32 *val)
+{
+        int id;
+        u32 option_num;
+        u32 option_mask;
+
+        for (id = 0; id < g->nfuncs; id++) {
+                if (g->funcs[id] == function)
+                        break;
+        }
+        if (WARN_ON(id == g->nfuncs))
+                return -EINVAL;
+
+        option_num = (1 << g->mfpctl_width);
+        if (id > option_num)
+                id -= option_num;
+
+        option_mask = option_num - 1;
+        *mask = (option_mask  << g->mfpctl_shift);
+        *val = (id << g->mfpctl_shift);
+
+        return 0;
+}
+
+static int owl_set_mux(struct pinctrl_dev *pctrldev,
+                                unsigned int function,
+                                unsigned int group)
+{
+        struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
+        const struct owl_pingroup *g;
+        unsigned long flags;
+        u32 val, mask;
+
+        g = &pctrl->soc->groups[group];
+
+        if (get_group_mfp_mask_val(g, function, &mask, &val))
+                return -EINVAL;
+
+        raw_spin_lock_irqsave(&pctrl->lock, flags);
+
+        owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
+
+        raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+
+        return 0;
+}
+
+static struct pinmux_ops owl_pinmux_ops = {
+        .get_functions_count = owl_get_funcs_count,
+        .get_function_name = owl_get_func_name,
+        .get_function_groups = owl_get_func_groups,
+        .set_mux = owl_set_mux,
+};
+
+static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
+                                unsigned int param,
+                                u32 *reg,
+                                u32 *bit,
+                                u32 *width)
+{
+        switch (param) {
+        case PIN_CONFIG_BIAS_BUS_HOLD:
+        case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+        case PIN_CONFIG_BIAS_PULL_UP:
+                if (!info->pullctl)
+                        return -EINVAL;
+                *reg = info->pullctl->reg;
+                *bit = info->pullctl->shift;
+                *width = info->pullctl->width;
+                break;
+        case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+                if (!info->st)
+                        return -EINVAL;
+                *reg = info->st->reg;
+                *bit = info->st->shift;
+                *width = info->st->width;
+                break;
+        default:
+                return -ENOTSUPP;
+        }
+
+        return 0;
+}
+
+static int owl_pad_pinconf_arg2val(const struct owl_padinfo *info,
+                                unsigned int param,
+                                u32 *arg)
+{
+        switch (param) {
+        case PIN_CONFIG_BIAS_BUS_HOLD:
+                *arg = OWL_PINCONF_PULL_HOLD;
+                break;
+        case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+                *arg = OWL_PINCONF_PULL_HIZ;
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                *arg = OWL_PINCONF_PULL_DOWN;
+                break;
+        case PIN_CONFIG_BIAS_PULL_UP:
+                *arg = OWL_PINCONF_PULL_UP;
+                break;
+        case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+                *arg = (*arg >= 1 ? 1 : 0);
+                break;
+        default:
+                return -ENOTSUPP;
+        }
+
+        return 0;
+}
+
+static int owl_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
+                                unsigned int param,
+                                u32 *arg)
+{
+        switch (param) {
+        case PIN_CONFIG_BIAS_BUS_HOLD:
+                *arg = *arg == OWL_PINCONF_PULL_HOLD;
+                break;
+        case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
+                *arg = *arg == OWL_PINCONF_PULL_HIZ;
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                *arg = *arg == OWL_PINCONF_PULL_DOWN;
+                break;
+        case PIN_CONFIG_BIAS_PULL_UP:
+                *arg = *arg == OWL_PINCONF_PULL_UP;
+                break;
+        case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+                *arg = *arg == 1;
+                break;
+        default:
+                return -ENOTSUPP;
+        }
+
+        return 0;
+}
+
+static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
+                                unsigned int pin,
+                                unsigned long *config)
+{
+        int ret = 0;
+        struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
+        const struct owl_padinfo *info;
+        unsigned int param = pinconf_to_config_param(*config);
+        u32 reg, bit, width, arg;
+
+        info = &pctrl->soc->padinfo[pin];
+
+        ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);
+        if (ret)
+                return ret;
+
+        arg = owl_read_field(pctrl, reg, bit, width);
+
+        ret = owl_pad_pinconf_val2arg(info, param, &arg);
+        if (ret)
+                return ret;
+
+        *config = pinconf_to_config_packed(param, arg);
+
+        return ret;
+}
+
+static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
+                                unsigned int pin,
+                                unsigned long *configs,
+                                unsigned int num_configs)
+{
+        struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
+        const struct owl_padinfo *info;
+        unsigned long flags;
+        unsigned int param;
+        u32 reg, bit, width, arg;
+        int ret, i;
+
+        info = &pctrl->soc->padinfo[pin];
+
+        for (i = 0; i < num_configs; i++) {
+                param = pinconf_to_config_param(configs[i]);
+                arg = pinconf_to_config_argument(configs[i]);
+
+                ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);
+                if (ret)
+                        return ret;
+
+                ret = owl_pad_pinconf_arg2val(info, param, &arg);
+                if (ret)
+                        return ret;
+
+                raw_spin_lock_irqsave(&pctrl->lock, flags);
+
+                owl_write_field(pctrl, reg, arg, bit, width);
+
+                raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+        }
+
+        return ret;
+}
+
+static int owl_group_pinconf_reg(const struct owl_pingroup *g,
+                                unsigned int param,
+                                u32 *reg,
+                                u32 *bit,
+                                u32 *width)
+{
+        switch (param) {
+        case PIN_CONFIG_DRIVE_STRENGTH:
+                if (g->drv_reg < 0)
+                        return -EINVAL;
+                *reg = g->drv_reg;
+                *bit = g->drv_shift;
+                *width = g->drv_width;
+                break;
+        case PIN_CONFIG_SLEW_RATE:
+                if (g->sr_reg < 0)
+                        return -EINVAL;
+                *reg = g->sr_reg;
+                *bit = g->sr_shift;
+                *width = g->sr_width;
+                break;
+        default:
+                return -ENOTSUPP;
+        }
+
+        return 0;
+}
+
+static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
+                                unsigned int param,
+                                u32 *arg)
+{
+        switch (param) {
+        case PIN_CONFIG_DRIVE_STRENGTH:
+                switch (*arg) {
+                case 2:
+                        *arg = OWL_PINCONF_DRV_2MA;
+                        break;
+                case 4:
+                        *arg = OWL_PINCONF_DRV_4MA;
+                        break;
+                case 8:
+                        *arg = OWL_PINCONF_DRV_8MA;
+                        break;
+                case 12:
+                        *arg = OWL_PINCONF_DRV_12MA;
+                        break;
+                default:
+                        return -EINVAL;
+                }
+                break;
+        case PIN_CONFIG_SLEW_RATE:
+                if (*arg)
+                        *arg = OWL_PINCONF_SLEW_FAST;
+                else
+                        *arg = OWL_PINCONF_SLEW_SLOW;
+                break;
+        default:
+                return -ENOTSUPP;
+        }
+
+        return 0;
+}
+
+static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
+                                unsigned int param,
+                                u32 *arg)
+{
+        switch (param) {
+        case PIN_CONFIG_DRIVE_STRENGTH:
+                switch (*arg) {
+                case OWL_PINCONF_DRV_2MA:
+                        *arg = 2;
+                        break;
+                case OWL_PINCONF_DRV_4MA:
+                        *arg = 4;
+                        break;
+                case OWL_PINCONF_DRV_8MA:
+                        *arg = 8;
+                        break;
+                case OWL_PINCONF_DRV_12MA:
+                        *arg = 12;
+                        break;
+                default:
+                        return -EINVAL;
+                }
+                break;
+        case PIN_CONFIG_SLEW_RATE:
+                if (*arg)
+                        *arg = 1;
+                else
+                        *arg = 0;
+                break;
+        default:
+                return -ENOTSUPP;
+        }
+
+        return 0;
+}
+
+static int owl_group_config_get(struct pinctrl_dev *pctrldev,
+                                unsigned int group,
+                                unsigned long *config)
+{
+        const struct owl_pingroup *g;
+        struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
+        unsigned int param = pinconf_to_config_param(*config);
+        u32 reg, bit, width, arg;
+        int ret;
+
+        g = &pctrl->soc->groups[group];
+
+        ret = owl_group_pinconf_reg(g, param, &reg, &bit, &width);
+        if (ret)
+                return ret;
+
+        arg = owl_read_field(pctrl, reg, bit, width);
+
+        ret = owl_group_pinconf_val2arg(g, param, &arg);
+        if (ret)
+                return ret;
+
+        *config = pinconf_to_config_packed(param, arg);
+
+        return ret;
+
+}
+
+static int owl_group_config_set(struct pinctrl_dev *pctrldev,
+                                unsigned int group,
+                                unsigned long *configs,
+                                unsigned int num_configs)
+{
+        const struct owl_pingroup *g;
+        struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
+        unsigned long flags;
+        unsigned int param;
+        u32 reg, bit, width, arg;
+        int ret, i;
+
+        g = &pctrl->soc->groups[group];
+
+        for (i = 0; i < num_configs; i++) {
+                param = pinconf_to_config_param(configs[i]);
+                arg = pinconf_to_config_argument(configs[i]);
+
+                ret = owl_group_pinconf_reg(g, param, &reg, &bit, &width);
+                if (ret)
+                        return ret;
+
+                ret = owl_group_pinconf_arg2val(g, param, &arg);
+                if (ret)
+                        return ret;
+
+                /* Update register */
+                raw_spin_lock_irqsave(&pctrl->lock, flags);
+
+                owl_write_field(pctrl, reg, arg, bit, width);
+
+                raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+        }
+
+        return 0;
+}
+
+static const struct pinconf_ops owl_pinconf_ops = {
+        .is_generic = true,
+        .pin_config_get = owl_pin_config_get,
+        .pin_config_set = owl_pin_config_set,
+        .pin_config_group_get = owl_group_config_get,
+        .pin_config_group_set = owl_group_config_set,
+};
+
+static struct pinctrl_desc owl_pinctrl_desc = {
+        .pctlops = &owl_pinctrl_ops,
+        .pmxops = &owl_pinmux_ops,
+        .confops = &owl_pinconf_ops,
+        .owner = THIS_MODULE,
+};
+
+static const struct owl_gpio_port *
+owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
+{
+        unsigned int start = 0, i;
+
+        for (i = 0; i < pctrl->soc->nports; i++) {
+                const struct owl_gpio_port *port = &pctrl->soc->ports[i];
+
+                if (*pin >= start && *pin < start + port->pins) {
+                        *pin -= start;
+                        return port;
+                }
+
+                start += port->pins;
+        }
+
+        return NULL;
+}
+
+static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
+{
+        u32 val;
+
+        val = readl_relaxed(base);
+
+        if (flag)
+                val |= BIT(pin);
+        else
+                val &= ~BIT(pin);
+
+        writel_relaxed(val, base);
+}
+
+static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
+{
+        struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
+        const struct owl_gpio_port *port;
+        void __iomem *gpio_base;
+        unsigned long flags;
+
+        port = owl_gpio_get_port(pctrl, &offset);
+        if (WARN_ON(port == NULL))
+                return -ENODEV;
+
+        gpio_base = pctrl->base + port->offset;
+
+        /*
+         * GPIOs have higher priority over other modules, so either setting
+         * them as OUT or IN is sufficient
+         */
+        raw_spin_lock_irqsave(&pctrl->lock, flags);
+        owl_gpio_update_reg(gpio_base + port->outen, offset, true);
+        raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+
+        return 0;
+}
+
+static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
+{
+        struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
+        const struct owl_gpio_port *port;
+        void __iomem *gpio_base;
+        unsigned long flags;
+
+        port = owl_gpio_get_port(pctrl, &offset);
+        if (WARN_ON(port == NULL))
+                return;
+
+        gpio_base = pctrl->base + port->offset;
+
+        raw_spin_lock_irqsave(&pctrl->lock, flags);
+        /* disable gpio output */
+        owl_gpio_update_reg(gpio_base + port->outen, offset, false);
+
+        /* disable gpio input */
+        owl_gpio_update_reg(gpio_base + port->inen, offset, false);
+        raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+}
+
+static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+        struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
+        const struct owl_gpio_port *port;
+        void __iomem *gpio_base;
+        unsigned long flags;
+        u32 val;
+
+        port = owl_gpio_get_port(pctrl, &offset);
+        if (WARN_ON(port == NULL))
+                return -ENODEV;
+
+        gpio_base = pctrl->base + port->offset;
+
+        raw_spin_lock_irqsave(&pctrl->lock, flags);
+        val = readl_relaxed(gpio_base + port->dat);
+        raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+
+        return !!(val & BIT(offset));
+}
+
+static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
+{
+        struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
+        const struct owl_gpio_port *port;
+        void __iomem *gpio_base;
+        unsigned long flags;
+
+        port = owl_gpio_get_port(pctrl, &offset);
+        if (WARN_ON(port == NULL))
+                return;
+
+        gpio_base = pctrl->base + port->offset;
+
+        raw_spin_lock_irqsave(&pctrl->lock, flags);
+        owl_gpio_update_reg(gpio_base + port->dat, offset, value);
+        raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+}
+
+static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
+{
+        struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
+        const struct owl_gpio_port *port;
+        void __iomem *gpio_base;
+        unsigned long flags;
+
+        port = owl_gpio_get_port(pctrl, &offset);
+        if (WARN_ON(port == NULL))
+                return -ENODEV;
+
+        gpio_base = pctrl->base + port->offset;
+
+        raw_spin_lock_irqsave(&pctrl->lock, flags);
+        owl_gpio_update_reg(gpio_base + port->outen, offset, false);
+        owl_gpio_update_reg(gpio_base + port->inen, offset, true);
+        raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+
+        return 0;
+}
+
+static int owl_gpio_direction_output(struct gpio_chip *chip,
+                                unsigned int offset, int value)
+{
+        struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
+        const struct owl_gpio_port *port;
+        void __iomem *gpio_base;
+        unsigned long flags;
+
+        port = owl_gpio_get_port(pctrl, &offset);
+        if (WARN_ON(port == NULL))
+                return -ENODEV;
+
+        gpio_base = pctrl->base + port->offset;
+
+        raw_spin_lock_irqsave(&pctrl->lock, flags);
+        owl_gpio_update_reg(gpio_base + port->inen, offset, false);
+        owl_gpio_update_reg(gpio_base + port->outen, offset, true);
+        owl_gpio_update_reg(gpio_base + port->dat, offset, value);
+        raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+
+        return 0;
+}
+
+static int owl_gpio_init(struct owl_pinctrl *pctrl)
+{
+        struct gpio_chip *chip;
+        int ret;
+
+        chip = &pctrl->chip;
+        chip->base = -1;
+        chip->ngpio = pctrl->soc->ngpios;
+        chip->label = dev_name(pctrl->dev);
+        chip->parent = pctrl->dev;
+        chip->owner = THIS_MODULE;
+        chip->of_node = pctrl->dev->of_node;
+
+        ret = gpiochip_add_data(&pctrl->chip, pctrl);
+        if (ret) {
+                dev_err(pctrl->dev, "failed to register gpiochip\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+int owl_pinctrl_probe(struct platform_device *pdev,
+                                struct owl_pinctrl_soc_data *soc_data)
+{
+        struct resource *res;
+        struct owl_pinctrl *pctrl;
+        int ret;
+
+        pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
+        if (!pctrl)
+                return -ENOMEM;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        pctrl->base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(pctrl->base))
+                return PTR_ERR(pctrl->base);
+
+        /* enable GPIO/MFP clock */
+        pctrl->clk = devm_clk_get(&pdev->dev, NULL);
+        if (IS_ERR(pctrl->clk)) {
+                dev_err(&pdev->dev, "no clock defined\n");
+                return PTR_ERR(pctrl->clk);
+        }
+
+        ret = clk_prepare_enable(pctrl->clk);
+        if (ret) {
+                dev_err(&pdev->dev, "clk enable failed\n");
+                return ret;
+        }
+
+        raw_spin_lock_init(&pctrl->lock);
+
+        owl_pinctrl_desc.name = dev_name(&pdev->dev);
+        owl_pinctrl_desc.pins = soc_data->pins;
+        owl_pinctrl_desc.npins = soc_data->npins;
+
+        pctrl->chip.direction_input  = owl_gpio_direction_input;
+        pctrl->chip.direction_output = owl_gpio_direction_output;
+        pctrl->chip.get = owl_gpio_get;
+        pctrl->chip.set = owl_gpio_set;
+        pctrl->chip.request = owl_gpio_request;
+        pctrl->chip.free = owl_gpio_free;
+
+        pctrl->soc = soc_data;
+        pctrl->dev = &pdev->dev;
+
+        pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
+                                        &owl_pinctrl_desc, pctrl);
+        if (IS_ERR(pctrl->pctrldev)) {
+                dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
+                return PTR_ERR(pctrl->pctrldev);
+        }
+
+        ret = owl_gpio_init(pctrl);
+        if (ret)
+                return ret;
+
+        platform_set_drvdata(pdev, pctrl);
+
+        return 0;
+}
diff --git a/drivers/pinctrl/actions/pinctrl-owl.h b/drivers/pinctrl/actions/pinctrl-owl.h
new file mode 100644
index 000000000000..74342378937c
--- /dev/null
+++ b/drivers/pinctrl/actions/pinctrl-owl.h
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OWL SoC's Pinctrl definitions
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <liuwei@actions-semi.com>
+ *
+ * Copyright (c) 2018 Linaro Ltd.
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#ifndef __PINCTRL_OWL_H__
+#define __PINCTRL_OWL_H__
+
+#define OWL_PINCONF_SLEW_SLOW 0
+#define OWL_PINCONF_SLEW_FAST 1
+
+enum owl_pinconf_pull {
+        OWL_PINCONF_PULL_HIZ,
+        OWL_PINCONF_PULL_DOWN,
+        OWL_PINCONF_PULL_UP,
+        OWL_PINCONF_PULL_HOLD,
+};
+
+enum owl_pinconf_drv {
+        OWL_PINCONF_DRV_2MA,
+        OWL_PINCONF_DRV_4MA,
+        OWL_PINCONF_DRV_8MA,
+        OWL_PINCONF_DRV_12MA,
+};
+
+/**
+ * struct owl_pullctl - Actions pad pull control register
+ * @reg: offset to the pull control register
+ * @shift: shift value of the register
+ * @width: width of the register
+ */
+struct owl_pullctl {
+        int reg;
+        unsigned int shift;
+        unsigned int width;
+};
+
+/**
+ * struct owl_st - Actions pad schmitt trigger enable register
+ * @reg: offset to the schmitt trigger enable register
+ * @shift: shift value of the register
+ * @width: width of the register
+ */
+struct owl_st {
+        int reg;
+        unsigned int shift;
+        unsigned int width;
+};
+
+/**
+ * struct owl_pingroup - Actions pingroup definition
+ * @name: name of the  pin group
+ * @pads: list of pins assigned to this pingroup
+ * @npads: size of @pads array
+ * @funcs: list of pinmux functions for this pingroup
+ * @nfuncs: size of @funcs array
+ * @mfpctl_reg: multiplexing control register offset
+ * @mfpctl_shift: multiplexing control register bit mask
+ * @mfpctl_width: multiplexing control register width
+ * @drv_reg: drive control register offset
+ * @drv_shift: drive control register bit mask
+ * @drv_width: driver control register width
+ * @sr_reg: slew rate control register offset
+ * @sr_shift: slew rate control register bit mask
+ * @sr_width: slew rate control register width
+ */
+struct owl_pingroup {
+        const char *name;
+        unsigned int *pads;
+        unsigned int npads;
+        unsigned int *funcs;
+        unsigned int nfuncs;
+
+        int mfpctl_reg;
+        unsigned int mfpctl_shift;
+        unsigned int mfpctl_width;
+
+        int drv_reg;
+        unsigned int drv_shift;
+        unsigned int drv_width;
+
+        int sr_reg;
+        unsigned int sr_shift;
+        unsigned int sr_width;
+};
+
+/**
+ * struct owl_padinfo - Actions pinctrl pad info
+ * @pad: pad name of the SoC
+ * @pullctl: pull control register info
+ * @st: schmitt trigger register info
+ */
+struct owl_padinfo {
+        int pad;
+        struct owl_pullctl *pullctl;
+        struct owl_st *st;
+};
+
+/**
+ * struct owl_pinmux_func - Actions pinctrl mux functions
+ * @name: name of the pinmux function.
+ * @groups: array of pin groups that may select this function.
+ * @ngroups: number of entries in @groups.
+ */
+struct owl_pinmux_func {
+        const char *name;
+        const char * const *groups;
+        unsigned int ngroups;
+};
+
+/**
+ * struct owl_gpio_port - Actions GPIO port info
+ * @offset: offset of the GPIO port.
+ * @pins: number of pins belongs to the GPIO port.
+ * @outen: offset of the output enable register.
+ * @inen: offset of the input enable register.
+ * @dat: offset of the data register.
+ */
+struct owl_gpio_port {
+        unsigned int offset;
+        unsigned int pins;
+        unsigned int outen;
+        unsigned int inen;
+        unsigned int dat;
+};
+
+/**
+ * struct owl_pinctrl_soc_data - Actions pin controller driver configuration
+ * @pins: array describing all pins of the pin controller.
+ * @npins: number of entries in @pins.
+ * @functions: array describing all mux functions of this SoC.
+ * @nfunction: number of entries in @functions.
+ * @groups: array describing all pin groups of this SoC.
+ * @ngroups: number of entries in @groups.
+ * @padinfo: array describing the pad info of this SoC.
+ * @ngpios: number of pingroups the driver should expose as GPIOs.
+ * @port: array describing all GPIO ports of this SoC.
+ * @nports: number of GPIO ports in this SoC.
+ */
+struct owl_pinctrl_soc_data {
+        const struct pinctrl_pin_desc *pins;
+        unsigned int npins;
+        const struct owl_pinmux_func *functions;
+        unsigned int nfunctions;
+        const struct owl_pingroup *groups;
+        unsigned int ngroups;
+        const struct owl_padinfo *padinfo;
+        unsigned int ngpios;
+        const struct owl_gpio_port *ports;
+        unsigned int nports;
+};
+
+int owl_pinctrl_probe(struct platform_device *pdev,
+                struct owl_pinctrl_soc_data *soc_data);
+
+#endif /* __PINCTRL_OWL_H__ */
diff --git a/drivers/pinctrl/actions/pinctrl-s900.c b/drivers/pinctrl/actions/pinctrl-s900.c
new file mode 100644
index 000000000000..5503c7945764
--- /dev/null
+++ b/drivers/pinctrl/actions/pinctrl-s900.c
@@ -0,0 +1,1888 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OWL S900 Pinctrl driver
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <liuwei@actions-semi.com>
+ *
+ * Copyright (c) 2018 Linaro Ltd.
+ * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include "pinctrl-owl.h"
+
+/* Pinctrl registers offset */
+#define MFCTL0                  (0x0040)
+#define MFCTL1                  (0x0044)
+#define MFCTL2                  (0x0048)
+#define MFCTL3                  (0x004C)
+#define PAD_PULLCTL0            (0x0060)
+#define PAD_PULLCTL1            (0x0064)
+#define PAD_PULLCTL2            (0x0068)
+#define PAD_ST0                 (0x006C)
+#define PAD_ST1                 (0x0070)
+#define PAD_CTL                 (0x0074)
+#define PAD_DRV0                (0x0080)
+#define PAD_DRV1                (0x0084)
+#define PAD_DRV2                (0x0088)
+#define PAD_SR0                 (0x0270)
+#define PAD_SR1                 (0x0274)
+#define PAD_SR2                 (0x0278)
+
+#define OWL_GPIO_PORT_A         0
+#define OWL_GPIO_PORT_B         1
+#define OWL_GPIO_PORT_C         2
+#define OWL_GPIO_PORT_D         3
+#define OWL_GPIO_PORT_E         4
+#define OWL_GPIO_PORT_F         5
+
+#define _GPIOA(offset)          (offset)
+#define _GPIOB(offset)          (32 + (offset))
+#define _GPIOC(offset)          (64 + (offset))
+#define _GPIOD(offset)          (76 + (offset))
+#define _GPIOE(offset)          (106 + (offset))
+#define _GPIOF(offset)          (138 + (offset))
+
+#define NUM_GPIOS               (_GPIOF(7) + 1)
+#define _PIN(offset)            (NUM_GPIOS + (offset))
+
+#define ETH_TXD0                _GPIOA(0)
+#define ETH_TXD1                _GPIOA(1)
+#define ETH_TXEN                _GPIOA(2)
+#define ETH_RXER                _GPIOA(3)
+#define ETH_CRS_DV              _GPIOA(4)
+#define ETH_RXD1                _GPIOA(5)
+#define ETH_RXD0                _GPIOA(6)
+#define ETH_REF_CLK             _GPIOA(7)
+#define ETH_MDC                 _GPIOA(8)
+#define ETH_MDIO                _GPIOA(9)
+#define SIRQ0                   _GPIOA(10)
+#define SIRQ1                   _GPIOA(11)
+#define SIRQ2                   _GPIOA(12)
+#define I2S_D0                  _GPIOA(13)
+#define I2S_BCLK0               _GPIOA(14)
+#define I2S_LRCLK0              _GPIOA(15)
+#define I2S_MCLK0               _GPIOA(16)
+#define I2S_D1                  _GPIOA(17)
+#define I2S_BCLK1               _GPIOA(18)
+#define I2S_LRCLK1              _GPIOA(19)
+#define I2S_MCLK1               _GPIOA(20)
+#define ERAM_A5                 _GPIOA(21)
+#define ERAM_A6                 _GPIOA(22)
+#define ERAM_A7                 _GPIOA(23)
+#define ERAM_A8                 _GPIOA(24)
+#define ERAM_A9                 _GPIOA(25)
+#define ERAM_A10                _GPIOA(26)
+#define ERAM_A11                _GPIOA(27)
+#define SD0_D0                  _GPIOA(28)
+#define SD0_D1                  _GPIOA(29)
+#define SD0_D2                  _GPIOA(30)
+#define SD0_D3                  _GPIOA(31)
+
+#define SD1_D0                  _GPIOB(0)
+#define SD1_D1                  _GPIOB(1)
+#define SD1_D2                  _GPIOB(2)
+#define SD1_D3                  _GPIOB(3)
+#define SD0_CMD                 _GPIOB(4)
+#define SD0_CLK                 _GPIOB(5)
+#define SD1_CMD                 _GPIOB(6)
+#define SD1_CLK                 _GPIOB(7)
+#define SPI0_SCLK               _GPIOB(8)
+#define SPI0_SS                 _GPIOB(9)
+#define SPI0_MISO               _GPIOB(10)
+#define SPI0_MOSI               _GPIOB(11)
+#define UART0_RX                _GPIOB(12)
+#define UART0_TX                _GPIOB(13)
+#define UART2_RX                _GPIOB(14)
+#define UART2_TX                _GPIOB(15)
+#define UART2_RTSB              _GPIOB(16)
+#define UART2_CTSB              _GPIOB(17)
+#define UART4_RX                _GPIOB(18)
+#define UART4_TX                _GPIOB(19)
+#define I2C0_SCLK               _GPIOB(20)
+#define I2C0_SDATA              _GPIOB(21)
+#define I2C1_SCLK               _GPIOB(22)
+#define I2C1_SDATA              _GPIOB(23)
+#define I2C2_SCLK               _GPIOB(24)
+#define I2C2_SDATA              _GPIOB(25)
+#define CSI0_DN0                _GPIOB(26)
+#define CSI0_DP0                _GPIOB(27)
+#define CSI0_DN1                _GPIOB(28)
+#define CSI0_DP1                _GPIOB(29)
+#define CSI0_CN                 _GPIOB(30)
+#define CSI0_CP                 _GPIOB(31)
+
+#define CSI0_DN2                _GPIOC(0)
+#define CSI0_DP2                _GPIOC(1)
+#define CSI0_DN3                _GPIOC(2)
+#define CSI0_DP3                _GPIOC(3)
+#define SENSOR0_PCLK            _GPIOC(4)
+#define CSI1_DN0                _GPIOC(5)
+#define CSI1_DP0                _GPIOC(6)
+#define CSI1_DN1                _GPIOC(7)
+#define CSI1_DP1                _GPIOC(8)
+#define CSI1_CN                 _GPIOC(9)
+#define CSI1_CP                 _GPIOC(10)
+#define SENSOR0_CKOUT           _GPIOC(11)
+
+#define LVDS_OEP                _GPIOD(0)
+#define LVDS_OEN                _GPIOD(1)
+#define LVDS_ODP                _GPIOD(2)
+#define LVDS_ODN                _GPIOD(3)
+#define LVDS_OCP                _GPIOD(4)
+#define LVDS_OCN                _GPIOD(5)
+#define LVDS_OBP                _GPIOD(6)
+#define LVDS_OBN                _GPIOD(7)
+#define LVDS_OAP                _GPIOD(8)
+#define LVDS_OAN                _GPIOD(9)
+#define LVDS_EEP                _GPIOD(10)
+#define LVDS_EEN                _GPIOD(11)
+#define LVDS_EDP                _GPIOD(12)
+#define LVDS_EDN                _GPIOD(13)
+#define LVDS_ECP                _GPIOD(14)
+#define LVDS_ECN                _GPIOD(15)
+#define LVDS_EBP                _GPIOD(16)
+#define LVDS_EBN                _GPIOD(17)
+#define LVDS_EAP                _GPIOD(18)
+#define LVDS_EAN                _GPIOD(19)
+#define DSI_DP3                 _GPIOD(20)
+#define DSI_DN3                 _GPIOD(21)
+#define DSI_DP1                 _GPIOD(22)
+#define DSI_DN1                 _GPIOD(23)
+#define DSI_CP                  _GPIOD(24)
+#define DSI_CN                  _GPIOD(25)
+#define DSI_DP0                 _GPIOD(26)
+#define DSI_DN0                 _GPIOD(27)
+#define DSI_DP2                 _GPIOD(28)
+#define DSI_DN2                 _GPIOD(29)
+
+#define NAND0_D0                _GPIOE(0)
+#define NAND0_D1                _GPIOE(1)
+#define NAND0_D2                _GPIOE(2)
+#define NAND0_D3                _GPIOE(3)
+#define NAND0_D4                _GPIOE(4)
+#define NAND0_D5                _GPIOE(5)
+#define NAND0_D6                _GPIOE(6)
+#define NAND0_D7                _GPIOE(7)
+#define NAND0_DQS               _GPIOE(8)
+#define NAND0_DQSN              _GPIOE(9)
+#define NAND0_ALE               _GPIOE(10)
+#define NAND0_CLE               _GPIOE(11)
+#define NAND0_CEB0              _GPIOE(12)
+#define NAND0_CEB1              _GPIOE(13)
+#define NAND0_CEB2              _GPIOE(14)
+#define NAND0_CEB3              _GPIOE(15)
+#define NAND1_D0                _GPIOE(16)
+#define NAND1_D1                _GPIOE(17)
+#define NAND1_D2                _GPIOE(18)
+#define NAND1_D3                _GPIOE(19)
+#define NAND1_D4                _GPIOE(20)
+#define NAND1_D5                _GPIOE(21)
+#define NAND1_D6                _GPIOE(22)
+#define NAND1_D7                _GPIOE(23)
+#define NAND1_DQS               _GPIOE(24)
+#define NAND1_DQSN              _GPIOE(25)
+#define NAND1_ALE               _GPIOE(26)
+#define NAND1_CLE               _GPIOE(27)
+#define NAND1_CEB0              _GPIOE(28)
+#define NAND1_CEB1              _GPIOE(29)
+#define NAND1_CEB2              _GPIOE(30)
+#define NAND1_CEB3              _GPIOE(31)
+
+#define PCM1_IN                 _GPIOF(0)
+#define PCM1_CLK                _GPIOF(1)
+#define PCM1_SYNC               _GPIOF(2)
+#define PCM1_OUT                _GPIOF(3)
+#define UART3_RX                _GPIOF(4)
+#define UART3_TX                _GPIOF(5)
+#define UART3_RTSB              _GPIOF(6)
+#define UART3_CTSB              _GPIOF(7)
+
+/* System */
+#define SGPIO0                  _PIN(0)
+#define SGPIO1                  _PIN(1)
+#define SGPIO2                  _PIN(2)
+#define SGPIO3                  _PIN(3)
+
+#define NUM_PADS                (_PIN(3) + 1)
+
+/* Pad names as specified in datasheet */
+static const struct pinctrl_pin_desc s900_pads[] = {
+        PINCTRL_PIN(ETH_TXD0, "eth_txd0"),
+        PINCTRL_PIN(ETH_TXD1, "eth_txd1"),
+        PINCTRL_PIN(ETH_TXEN, "eth_txen"),
+        PINCTRL_PIN(ETH_RXER, "eth_rxer"),
+        PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"),
+        PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),
+        PINCTRL_PIN(ETH_RXD0, "eth_rxd0"),
+        PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"),
+        PINCTRL_PIN(ETH_MDC, "eth_mdc"),
+        PINCTRL_PIN(ETH_MDIO, "eth_mdio"),
+        PINCTRL_PIN(SIRQ0, "sirq0"),
+        PINCTRL_PIN(SIRQ1, "sirq1"),
+        PINCTRL_PIN(SIRQ2, "sirq2"),
+        PINCTRL_PIN(I2S_D0, "i2s_d0"),
+        PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"),
+        PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"),
+        PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"),
+        PINCTRL_PIN(I2S_D1, "i2s_d1"),
+        PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"),
+        PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"),
+        PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"),
+        PINCTRL_PIN(PCM1_IN, "pcm1_in"),
+        PINCTRL_PIN(PCM1_CLK, "pcm1_clk"),
+        PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"),
+        PINCTRL_PIN(PCM1_OUT, "pcm1_out"),
+        PINCTRL_PIN(ERAM_A5, "eram_a5"),
+        PINCTRL_PIN(ERAM_A6, "eram_a6"),
+        PINCTRL_PIN(ERAM_A7, "eram_a7"),
+        PINCTRL_PIN(ERAM_A8, "eram_a8"),
+        PINCTRL_PIN(ERAM_A9, "eram_a9"),
+        PINCTRL_PIN(ERAM_A10, "eram_a10"),
+        PINCTRL_PIN(ERAM_A11, "eram_a11"),
+        PINCTRL_PIN(LVDS_OEP, "lvds_oep"),
+        PINCTRL_PIN(LVDS_OEN, "lvds_oen"),
+        PINCTRL_PIN(LVDS_ODP, "lvds_odp"),
+        PINCTRL_PIN(LVDS_ODN, "lvds_odn"),
+        PINCTRL_PIN(LVDS_OCP, "lvds_ocp"),
+        PINCTRL_PIN(LVDS_OCN, "lvds_ocn"),
+        PINCTRL_PIN(LVDS_OBP, "lvds_obp"),
+        PINCTRL_PIN(LVDS_OBN, "lvds_obn"),
+        PINCTRL_PIN(LVDS_OAP, "lvds_oap"),
+        PINCTRL_PIN(LVDS_OAN, "lvds_oan"),
+        PINCTRL_PIN(LVDS_EEP, "lvds_eep"),
+        PINCTRL_PIN(LVDS_EEN, "lvds_een"),
+        PINCTRL_PIN(LVDS_EDP, "lvds_edp"),
+        PINCTRL_PIN(LVDS_EDN, "lvds_edn"),
+        PINCTRL_PIN(LVDS_ECP, "lvds_ecp"),
+        PINCTRL_PIN(LVDS_ECN, "lvds_ecn"),
+        PINCTRL_PIN(LVDS_EBP, "lvds_ebp"),
+        PINCTRL_PIN(LVDS_EBN, "lvds_ebn"),
+        PINCTRL_PIN(LVDS_EAP, "lvds_eap"),
+        PINCTRL_PIN(LVDS_EAN, "lvds_ean"),
+        PINCTRL_PIN(SD0_D0, "sd0_d0"),
+        PINCTRL_PIN(SD0_D1, "sd0_d1"),
+        PINCTRL_PIN(SD0_D2, "sd0_d2"),
+        PINCTRL_PIN(SD0_D3, "sd0_d3"),
+        PINCTRL_PIN(SD1_D0, "sd1_d0"),
+        PINCTRL_PIN(SD1_D1, "sd1_d1"),
+        PINCTRL_PIN(SD1_D2, "sd1_d2"),
+        PINCTRL_PIN(SD1_D3, "sd1_d3"),
+        PINCTRL_PIN(SD0_CMD, "sd0_cmd"),
+        PINCTRL_PIN(SD0_CLK, "sd0_clk"),
+        PINCTRL_PIN(SD1_CMD, "sd1_cmd"),
+        PINCTRL_PIN(SD1_CLK, "sd1_clk"),
+        PINCTRL_PIN(SPI0_SCLK, "spi0_sclk"),
+        PINCTRL_PIN(SPI0_SS, "spi0_ss"),
+        PINCTRL_PIN(SPI0_MISO, "spi0_miso"),
+        PINCTRL_PIN(SPI0_MOSI, "spi0_mosi"),
+        PINCTRL_PIN(UART0_RX, "uart0_rx"),
+        PINCTRL_PIN(UART0_TX, "uart0_tx"),
+        PINCTRL_PIN(UART2_RX, "uart2_rx"),
+        PINCTRL_PIN(UART2_TX, "uart2_tx"),
+        PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"),
+        PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"),
+        PINCTRL_PIN(UART3_RX, "uart3_rx"),
+        PINCTRL_PIN(UART3_TX, "uart3_tx"),
+        PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"),
+        PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"),
+        PINCTRL_PIN(UART4_RX, "uart4_rx"),
+        PINCTRL_PIN(UART4_TX, "uart4_tx"),
+        PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"),
+        PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"),
+        PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"),
+        PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"),
+        PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"),
+        PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"),
+        PINCTRL_PIN(CSI0_DN0, "csi0_dn0"),
+        PINCTRL_PIN(CSI0_DP0, "csi0_dp0"),
+        PINCTRL_PIN(CSI0_DN1, "csi0_dn1"),
+        PINCTRL_PIN(CSI0_DP1, "csi0_dp1"),
+        PINCTRL_PIN(CSI0_CN, "csi0_cn"),
+        PINCTRL_PIN(CSI0_CP, "csi0_cp"),
+        PINCTRL_PIN(CSI0_DN2, "csi0_dn2"),
+        PINCTRL_PIN(CSI0_DP2, "csi0_dp2"),
+        PINCTRL_PIN(CSI0_DN3, "csi0_dn3"),
+        PINCTRL_PIN(CSI0_DP3, "csi0_dp3"),
+        PINCTRL_PIN(DSI_DP3, "dsi_dp3"),
+        PINCTRL_PIN(DSI_DN3, "dsi_dn3"),
+        PINCTRL_PIN(DSI_DP1, "dsi_dp1"),
+        PINCTRL_PIN(DSI_DN1, "dsi_dn1"),
+        PINCTRL_PIN(DSI_CP, "dsi_cp"),
+        PINCTRL_PIN(DSI_CN, "dsi_cn"),
+        PINCTRL_PIN(DSI_DP0, "dsi_dp0"),
+        PINCTRL_PIN(DSI_DN0, "dsi_dn0"),
+        PINCTRL_PIN(DSI_DP2, "dsi_dp2"),
+        PINCTRL_PIN(DSI_DN2, "dsi_dn2"),
+        PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"),
+        PINCTRL_PIN(CSI1_DN0, "csi1_dn0"),
+        PINCTRL_PIN(CSI1_DP0, "csi1_dp0"),
+        PINCTRL_PIN(CSI1_DN1, "csi1_dn1"),
+        PINCTRL_PIN(CSI1_DP1, "csi1_dp1"),
+        PINCTRL_PIN(CSI1_CN, "csi1_cn"),
+        PINCTRL_PIN(CSI1_CP, "csi1_cp"),
+        PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"),
+        PINCTRL_PIN(NAND0_D0, "nand0_d0"),
+        PINCTRL_PIN(NAND0_D1, "nand0_d1"),
+        PINCTRL_PIN(NAND0_D2, "nand0_d2"),
+        PINCTRL_PIN(NAND0_D3, "nand0_d3"),
+        PINCTRL_PIN(NAND0_D4, "nand0_d4"),
+        PINCTRL_PIN(NAND0_D5, "nand0_d5"),
+        PINCTRL_PIN(NAND0_D6, "nand0_d6"),
+        PINCTRL_PIN(NAND0_D7, "nand0_d7"),
+        PINCTRL_PIN(NAND0_DQS, "nand0_dqs"),
+        PINCTRL_PIN(NAND0_DQSN, "nand0_dqsn"),
+        PINCTRL_PIN(NAND0_ALE, "nand0_ale"),
+        PINCTRL_PIN(NAND0_CLE, "nand0_cle"),
+        PINCTRL_PIN(NAND0_CEB0, "nand0_ceb0"),
+        PINCTRL_PIN(NAND0_CEB1, "nand0_ceb1"),
+        PINCTRL_PIN(NAND0_CEB2, "nand0_ceb2"),
+        PINCTRL_PIN(NAND0_CEB3, "nand0_ceb3"),
+        PINCTRL_PIN(NAND1_D0, "nand1_d0"),
+        PINCTRL_PIN(NAND1_D1, "nand1_d1"),
+        PINCTRL_PIN(NAND1_D2, "nand1_d2"),
+        PINCTRL_PIN(NAND1_D3, "nand1_d3"),
+        PINCTRL_PIN(NAND1_D4, "nand1_d4"),
+        PINCTRL_PIN(NAND1_D5, "nand1_d5"),
+        PINCTRL_PIN(NAND1_D6, "nand1_d6"),
+        PINCTRL_PIN(NAND1_D7, "nand1_d7"),
+        PINCTRL_PIN(NAND1_DQS, "nand1_dqs"),
+        PINCTRL_PIN(NAND1_DQSN, "nand1_dqsn"),
+        PINCTRL_PIN(NAND1_ALE, "nand1_ale"),
+        PINCTRL_PIN(NAND1_CLE, "nand1_cle"),
+        PINCTRL_PIN(NAND1_CEB0, "nand1_ceb0"),
+        PINCTRL_PIN(NAND1_CEB1, "nand1_ceb1"),
+        PINCTRL_PIN(NAND1_CEB2, "nand1_ceb2"),
+        PINCTRL_PIN(NAND1_CEB3, "nand1_ceb3"),
+        PINCTRL_PIN(SGPIO0, "sgpio0"),
+        PINCTRL_PIN(SGPIO1, "sgpio1"),
+        PINCTRL_PIN(SGPIO2, "sgpio2"),
+        PINCTRL_PIN(SGPIO3, "sgpio3")
+};
+
+enum s900_pinmux_functions {
+        S900_MUX_ERAM,
+        S900_MUX_ETH_RMII,
+        S900_MUX_ETH_SMII,
+        S900_MUX_SPI0,
+        S900_MUX_SPI1,
+        S900_MUX_SPI2,
+        S900_MUX_SPI3,
+        S900_MUX_SENS0,
+        S900_MUX_UART0,
+        S900_MUX_UART1,
+        S900_MUX_UART2,
+        S900_MUX_UART3,
+        S900_MUX_UART4,
+        S900_MUX_UART5,
+        S900_MUX_UART6,
+        S900_MUX_I2S0,
+        S900_MUX_I2S1,
+        S900_MUX_PCM0,
+        S900_MUX_PCM1,
+        S900_MUX_JTAG,
+        S900_MUX_PWM0,
+        S900_MUX_PWM1,
+        S900_MUX_PWM2,
+        S900_MUX_PWM3,
+        S900_MUX_PWM4,
+        S900_MUX_PWM5,
+        S900_MUX_SD0,
+        S900_MUX_SD1,
+        S900_MUX_SD2,
+        S900_MUX_SD3,
+        S900_MUX_I2C0,
+        S900_MUX_I2C1,
+        S900_MUX_I2C2,
+        S900_MUX_I2C3,
+        S900_MUX_I2C4,
+        S900_MUX_I2C5,
+        S900_MUX_LVDS,
+        S900_MUX_USB20,
+        S900_MUX_USB30,
+        S900_MUX_GPU,
+        S900_MUX_MIPI_CSI0,
+        S900_MUX_MIPI_CSI1,
+        S900_MUX_MIPI_DSI,
+        S900_MUX_NAND0,
+        S900_MUX_NAND1,
+        S900_MUX_SPDIF,
+        S900_MUX_SIRQ0,
+        S900_MUX_SIRQ1,
+        S900_MUX_SIRQ2,
+        S900_MUX_AUX_START,
+        S900_MUX_MAX,
+        S900_MUX_RESERVED
+};
+
+/* mfp0_22 */
+static unsigned int lvds_oxx_uart4_mfp_pads[]   = { LVDS_OAP, LVDS_OAN };
+static unsigned int lvds_oxx_uart4_mfp_funcs[]  = { S900_MUX_ERAM,
+                                                    S900_MUX_UART4 };
+/* mfp0_21_20 */
+static unsigned int rmii_mdc_mfp_pads[]         = { ETH_MDC };
+static unsigned int rmii_mdc_mfp_funcs[]        = { S900_MUX_ETH_RMII,
+                                                    S900_MUX_PWM2,
+                                                    S900_MUX_UART2,
+                                                    S900_MUX_RESERVED };
+static unsigned int rmii_mdio_mfp_pads[]        = { ETH_MDIO };
+static unsigned int rmii_mdio_mfp_funcs[]       = { S900_MUX_ETH_RMII,
+                                                    S900_MUX_PWM3,
+                                                    S900_MUX_UART2,
+                                                    S900_MUX_RESERVED };
+/* mfp0_19 */
+static unsigned int sirq0_mfp_pads[]            = { SIRQ0 };
+static unsigned int sirq0_mfp_funcs[]           = { S900_MUX_SIRQ0,
+                                                    S900_MUX_PWM0 };
+static unsigned int sirq1_mfp_pads[]            = { SIRQ1 };
+static unsigned int sirq1_mfp_funcs[]           = { S900_MUX_SIRQ1,
+                                                    S900_MUX_PWM1 };
+/* mfp0_18_16 */
+static unsigned int rmii_txd0_mfp_pads[]        = { ETH_TXD0 };
+static unsigned int rmii_txd0_mfp_funcs[]       = { S900_MUX_ETH_RMII,
+                                                    S900_MUX_ETH_SMII,
+                                                    S900_MUX_SPI2,
+                                                    S900_MUX_UART6,
+                                                    S900_MUX_SENS0,
+                                                    S900_MUX_PWM0 };
+static unsigned int rmii_txd1_mfp_pads[]        = { ETH_TXD1 };
+static unsigned int rmii_txd1_mfp_funcs[]       = { S900_MUX_ETH_RMII,
+                                                    S900_MUX_ETH_SMII,
+                                                    S900_MUX_SPI2,
+                                                    S900_MUX_UART6,
+                                                    S900_MUX_SENS0,
+                                                    S900_MUX_PWM1 };
+/* mfp0_15_13 */
+static unsigned int rmii_txen_mfp_pads[]        = { ETH_TXEN };
+static unsigned int rmii_txen_mfp_funcs[]       = { S900_MUX_ETH_RMII,
+                                                    S900_MUX_UART2,
+                                                    S900_MUX_SPI3,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_PWM2,
+                                                    S900_MUX_SENS0 };
+
+static unsigned int rmii_rxer_mfp_pads[]        = { ETH_RXER };
+static unsigned int rmii_rxer_mfp_funcs[]       = { S900_MUX_ETH_RMII,
+                                                    S900_MUX_UART2,
+                                                    S900_MUX_SPI3,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_PWM3,
+                                                    S900_MUX_SENS0 };
+/* mfp0_12_11 */
+static unsigned int rmii_crs_dv_mfp_pads[]      = { ETH_CRS_DV };
+static unsigned int rmii_crs_dv_mfp_funcs[]     = { S900_MUX_ETH_RMII,
+                                                    S900_MUX_ETH_SMII,
+                                                    S900_MUX_SPI2,
+                                                    S900_MUX_UART4 };
+/* mfp0_10_8 */
+static unsigned int rmii_rxd1_mfp_pads[]        = { ETH_RXD1 };
+static unsigned int rmii_rxd1_mfp_funcs[]       = { S900_MUX_ETH_RMII,
+                                                    S900_MUX_UART2,
+                                                    S900_MUX_SPI3,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_UART5,
+                                                    S900_MUX_PWM0,
+                                                    S900_MUX_SENS0 };
+static unsigned int rmii_rxd0_mfp_pads[]        = { ETH_RXD0 };
+static unsigned int rmii_rxd0_mfp_funcs[]       = { S900_MUX_ETH_RMII,
+                                                    S900_MUX_UART2,
+                                                    S900_MUX_SPI3,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_UART5,
+                                                    S900_MUX_PWM1,
+                                                    S900_MUX_SENS0 };
+/* mfp0_7_6 */
+static unsigned int rmii_ref_clk_mfp_pads[]     = { ETH_REF_CLK };
+static unsigned int rmii_ref_clk_mfp_funcs[]    = { S900_MUX_ETH_RMII,
+                                                    S900_MUX_UART4,
+                                                    S900_MUX_SPI2,
+                                                    S900_MUX_RESERVED };
+/* mfp0_5 */
+static unsigned int i2s_d0_mfp_pads[]           = { I2S_D0 };
+static unsigned int i2s_d0_mfp_funcs[]          = { S900_MUX_I2S0,
+                                                    S900_MUX_PCM0 };
+static unsigned int i2s_d1_mfp_pads[]           = { I2S_D1 };
+static unsigned int i2s_d1_mfp_funcs[]          = { S900_MUX_I2S1,
+                                                    S900_MUX_PCM0 };
+
+/* mfp0_4_3 */
+static unsigned int i2s_lr_m_clk0_mfp_pads[]    = { I2S_LRCLK0,
+                                                    I2S_MCLK0 };
+static unsigned int i2s_lr_m_clk0_mfp_funcs[]   = { S900_MUX_I2S0,
+                                                    S900_MUX_PCM0,
+                                                    S900_MUX_PCM1,
+                                                    S900_MUX_RESERVED };
+/* mfp0_2 */
+static unsigned int i2s_bclk0_mfp_pads[]        = { I2S_BCLK0 };
+static unsigned int i2s_bclk0_mfp_funcs[]       = { S900_MUX_I2S0,
+                                                    S900_MUX_PCM0 };
+static unsigned int i2s_bclk1_mclk1_mfp_pads[]  = { I2S_BCLK1,
+                                                    I2S_LRCLK1,
+                                                    I2S_MCLK1 };
+static unsigned int i2s_bclk1_mclk1_mfp_funcs[] = { S900_MUX_I2S1,
+                                                    S900_MUX_PCM0 };
+/* mfp0_1_0 */
+static unsigned int pcm1_in_out_mfp_pads[]      = { PCM1_IN,
+                                                    PCM1_OUT };
+static unsigned int pcm1_in_out_mfp_funcs[]     = { S900_MUX_PCM1,
+                                                    S900_MUX_SPI1,
+                                                    S900_MUX_I2C3,
+                                                    S900_MUX_UART4 };
+static unsigned int pcm1_clk_mfp_pads[]         = { PCM1_CLK };
+static unsigned int pcm1_clk_mfp_funcs[]        = { S900_MUX_PCM1,
+                                                    S900_MUX_SPI1,
+                                                    S900_MUX_PWM4,
+                                                    S900_MUX_UART4 };
+static unsigned int pcm1_sync_mfp_pads[]        = { PCM1_SYNC };
+static unsigned int pcm1_sync_mfp_funcs[]       = { S900_MUX_PCM1,
+                                                    S900_MUX_SPI1,
+                                                    S900_MUX_PWM5,
+                                                    S900_MUX_UART4 };
+/* mfp1_31_29 */
+static unsigned int eram_a5_mfp_pads[]          = { ERAM_A5 };
+static unsigned int eram_a5_mfp_funcs[]         = { S900_MUX_UART4,
+                                                    S900_MUX_JTAG,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_PWM0,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_SENS0 };
+static unsigned int eram_a6_mfp_pads[]          = { ERAM_A6 };
+static unsigned int eram_a6_mfp_funcs[]         = { S900_MUX_UART4,
+                                                    S900_MUX_JTAG,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_PWM1,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_SENS0,
+};
+static unsigned int eram_a7_mfp_pads[]          = { ERAM_A7 };
+static unsigned int eram_a7_mfp_funcs[]         = { S900_MUX_RESERVED,
+                                                    S900_MUX_JTAG,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_SENS0 };
+/* mfp1_28_26 */
+static unsigned int eram_a8_mfp_pads[]          = { ERAM_A8 };
+static unsigned int eram_a8_mfp_funcs[]         = { S900_MUX_RESERVED,
+                                                    S900_MUX_JTAG,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_PWM1,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_SENS0 };
+static unsigned int eram_a9_mfp_pads[]          = { ERAM_A9 };
+static unsigned int eram_a9_mfp_funcs[]         = { S900_MUX_USB20,
+                                                    S900_MUX_UART5,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_PWM2,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_SENS0 };
+static unsigned int eram_a10_mfp_pads[]         = { ERAM_A10 };
+static unsigned int eram_a10_mfp_funcs[]        = { S900_MUX_USB30,
+                                                    S900_MUX_JTAG,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_PWM3,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_SENS0,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_RESERVED };
+/* mfp1_25_23 */
+static unsigned int eram_a11_mfp_pads[]         = { ERAM_A11 };
+static unsigned int eram_a11_mfp_funcs[]        = { S900_MUX_RESERVED,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_PWM2,
+                                                    S900_MUX_UART5,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_SENS0,
+                                                    S900_MUX_RESERVED };
+/* mfp1_22 */
+static unsigned int lvds_oep_odn_mfp_pads[]     = { LVDS_OEP,
+                                                    LVDS_OEN,
+                                                    LVDS_ODP,
+                                                    LVDS_ODN };
+static unsigned int lvds_oep_odn_mfp_funcs[]    = { S900_MUX_LVDS,
+                                                    S900_MUX_UART2 };
+static unsigned int lvds_ocp_obn_mfp_pads[]     = { LVDS_OCP,
+                                                    LVDS_OCN,
+                                                    LVDS_OBP,
+                                                    LVDS_OBN };
+static unsigned int lvds_ocp_obn_mfp_funcs[]    = { S900_MUX_LVDS,
+                                                    S900_MUX_PCM1 };
+static unsigned int lvds_oap_oan_mfp_pads[]     = { LVDS_OAP,
+                                                    LVDS_OAN };
+static unsigned int lvds_oap_oan_mfp_funcs[]    = { S900_MUX_LVDS,
+                                                    S900_MUX_ERAM };
+/* mfp1_21 */
+static unsigned int lvds_e_mfp_pads[]           = { LVDS_EEP,
+                                                    LVDS_EEN,
+                                                    LVDS_EDP,
+                                                    LVDS_EDN,
+                                                    LVDS_ECP,
+                                                    LVDS_ECN,
+                                                    LVDS_EBP,
+                                                    LVDS_EBN,
+                                                    LVDS_EAP,
+                                                    LVDS_EAN };
+static unsigned int lvds_e_mfp_funcs[]          = { S900_MUX_LVDS,
+                                                    S900_MUX_ERAM };
+/* mfp1_5_4 */
+static unsigned int spi0_sclk_mosi_mfp_pads[]   = { SPI0_SCLK,
+                                                    SPI0_MOSI };
+static unsigned int spi0_sclk_mosi_mfp_funcs[]  = { S900_MUX_SPI0,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_I2C3,
+                                                    S900_MUX_PCM0 };
+/* mfp1_3_1 */
+static unsigned int spi0_ss_mfp_pads[]          = { SPI0_SS };
+static unsigned int spi0_ss_mfp_funcs[]         = { S900_MUX_SPI0,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_I2S1,
+                                                    S900_MUX_PCM1,
+                                                    S900_MUX_PCM0,
+                                                    S900_MUX_PWM4 };
+static unsigned int spi0_miso_mfp_pads[]        = { SPI0_MISO };
+static unsigned int spi0_miso_mfp_funcs[]       = { S900_MUX_SPI0,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_I2S1,
+                                                    S900_MUX_PCM1,
+                                                    S900_MUX_PCM0,
+                                                    S900_MUX_PWM5 };
+/* mfp2_23 */
+static unsigned int uart2_rtsb_mfp_pads[]       = { UART2_RTSB };
+static unsigned int uart2_rtsb_mfp_funcs[]      = { S900_MUX_UART2,
+                                                    S900_MUX_UART0 };
+/* mfp2_22 */
+static unsigned int uart2_ctsb_mfp_pads[]       = { UART2_CTSB };
+static unsigned int uart2_ctsb_mfp_funcs[]      = { S900_MUX_UART2,
+                                                    S900_MUX_UART0 };
+/* mfp2_21 */
+static unsigned int uart3_rtsb_mfp_pads[]       = { UART3_RTSB };
+static unsigned int uart3_rtsb_mfp_funcs[]      = { S900_MUX_UART3,
+                                                    S900_MUX_UART5 };
+/* mfp2_20 */
+static unsigned int uart3_ctsb_mfp_pads[]       = { UART3_CTSB };
+static unsigned int uart3_ctsb_mfp_funcs[]      = { S900_MUX_UART3,
+                                                    S900_MUX_UART5 };
+/* mfp2_19_17 */
+static unsigned int sd0_d0_mfp_pads[]           = { SD0_D0 };
+static unsigned int sd0_d0_mfp_funcs[]          = { S900_MUX_SD0,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_JTAG,
+                                                    S900_MUX_UART2,
+                                                    S900_MUX_UART5,
+                                                    S900_MUX_GPU };
+/* mfp2_16_14 */
+static unsigned int sd0_d1_mfp_pads[]           = { SD0_D1 };
+static unsigned int sd0_d1_mfp_funcs[]          = { S900_MUX_SD0,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_GPU,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_UART2,
+                                                    S900_MUX_UART5 };
+/* mfp_13_11 */
+static unsigned int sd0_d2_d3_mfp_pads[]        = { SD0_D2,
+                                                    SD0_D3 };
+static unsigned int sd0_d2_d3_mfp_funcs[]       = { S900_MUX_SD0,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_RESERVED,
+                                                    S900_MUX_JTAG,
+                                                    S900_MUX_UART2,
+                                                    S900_MUX_UART1,
+                                                    S900_MUX_GPU };
+/* mfp2_10_9 */
+static unsigned int sd1_d0_d3_mfp_pads[]        = { SD1_D0, SD1_D1,
+                                                    SD1_D2, SD1_D3 };
+static unsigned int sd1_d0_d3_mfp_funcs[]       = { S900_MUX_SD1,
+                                                    S900_MUX_ERAM };
+/* mfp2_8_7 */
+static unsigned int sd0_cmd_mfp_pads[]          = { SD0_CMD };
+static unsigned int sd0_cmd_mfp_funcs[]         = { S900_MUX_SD0,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_GPU,
+                                                    S900_MUX_JTAG };
+/* mfp2_6_5 */
+static unsigned int sd0_clk_mfp_pads[]          = { SD0_CLK };
+static unsigned int sd0_clk_mfp_funcs[]         = { S900_MUX_SD0,
+                                                    S900_MUX_ERAM,
+                                                    S900_MUX_JTAG,
+                                                    S900_MUX_GPU };
+/* mfp2_4_3 */
+static unsigned int sd1_cmd_clk_mfp_pads[]      = { SD1_CMD, SD1_CLK };
+static unsigned int sd1_cmd_clk_mfp_funcs[]     = { S900_MUX_SD1,
+                                                    S900_MUX_ERAM };
+/* mfp2_2_0 */
+static unsigned int uart0_rx_mfp_pads[]         = { UART0_RX };
+static unsigned int uart0_rx_mfp_funcs[]        = { S900_MUX_UART0,
+                                                    S900_MUX_UART2,
+                                                    S900_MUX_SPI1,
+                                                    S900_MUX_I2C5,
+                                                    S900_MUX_PCM1,
+                                                    S900_MUX_I2S1 };
+/* mfp3_27 */
+static unsigned int nand0_d0_ceb3_mfp_pads[]    = { NAND0_D0, NAND0_D1,
+                                                    NAND0_D2, NAND0_D3,
+                                                    NAND0_D4, NAND0_D5,
+                                                    NAND0_D6, NAND0_D7,
+                                                    NAND0_DQSN, NAND0_CEB3 };
+static unsigned int nand0_d0_ceb3_mfp_funcs[]   = { S900_MUX_NAND0,
+                                                    S900_MUX_SD2 };
+/* mfp3_21_19 */
+static unsigned int uart0_tx_mfp_pads[]         = { UART0_TX };
+static unsigned int uart0_tx_mfp_funcs[]        = { S900_MUX_UART0,
+                                                    S900_MUX_UART2,
+                                                    S900_MUX_SPI1,
+                                                    S900_MUX_I2C5,
+                                                    S900_MUX_SPDIF,
+                                                    S900_MUX_PCM1,
+                                                    S900_MUX_I2S1 };
+/* mfp3_18_16 */
+static unsigned int i2c0_mfp_pads[]             = { I2C0_SCLK, I2C0_SDATA };
+static unsigned int i2c0_mfp_funcs[]            = { S900_MUX_I2C0,
+                                                    S900_MUX_UART2,
+                                                    S900_MUX_I2C1,
+                                                    S900_MUX_UART1,
+                                                    S900_MUX_SPI1 };
+/* mfp3_15 */
+static unsigned int csi0_cn_cp_mfp_pads[]       = { CSI0_CN, CSI0_CP };
+static unsigned int csi0_cn_cp_mfp_funcs[]      = { S900_MUX_SENS0,
+                                                    S900_MUX_SENS0 };
+/* mfp3_14 */
+static unsigned int csi0_dn0_dp3_mfp_pads[]     = { CSI0_DN0, CSI0_DP0,
+                                                    CSI0_DN1, CSI0_DP1,
+                                                    CSI0_CN, CSI0_CP,
+                                                    CSI0_DP2, CSI0_DN2,
+                                                    CSI0_DN3, CSI0_DP3 };
+static unsigned int csi0_dn0_dp3_mfp_funcs[]    = { S900_MUX_MIPI_CSI0,
+                                                    S900_MUX_SENS0 };
+/* mfp3_13 */
+static unsigned int csi1_dn0_cp_mfp_pads[]      = { CSI1_DN0, CSI1_DP0,
+                                                    CSI1_DN1, CSI1_DP1,
+                                                    CSI1_CN, CSI1_CP };
+static unsigned int csi1_dn0_cp_mfp_funcs[]     = { S900_MUX_MIPI_CSI1,
+                                                    S900_MUX_SENS0 };
+/* mfp3_12_dsi */
+static unsigned int dsi_dp3_dn1_mfp_pads[]      = { DSI_DP3, DSI_DN2,
+                                                    DSI_DP1, DSI_DN1 };
+static unsigned int dsi_dp3_dn1_mfp_funcs[]     = { S900_MUX_MIPI_DSI,
+                                                    S900_MUX_UART2 };
+static unsigned int dsi_cp_dn0_mfp_pads[]       = { DSI_CP, DSI_CN,
+                                                    DSI_DP0, DSI_DN0 };
+static unsigned int dsi_cp_dn0_mfp_funcs[]      = { S900_MUX_MIPI_DSI,
+                                                    S900_MUX_PCM1 };
+static unsigned int dsi_dp2_dn2_mfp_pads[]      = { DSI_DP2, DSI_DN2 };
+static unsigned int dsi_dp2_dn2_mfp_funcs[]     = { S900_MUX_MIPI_DSI,
+                                                    S900_MUX_UART4 };
+/* mfp3_11 */
+static unsigned int nand1_d0_ceb1_mfp_pads[]    = { NAND1_D0, NAND1_D1,
+                                                    NAND1_D2, NAND1_D3,
+                                                    NAND1_D4, NAND1_D5,
+                                                    NAND1_D6, NAND1_D7,
+                                                    NAND1_DQSN, NAND1_CEB1 };
+static unsigned int nand1_d0_ceb1_mfp_funcs[]   = { S900_MUX_NAND1,
+                                                    S900_MUX_SD3 };
+/* mfp3_10 */
+static unsigned int nand1_ceb3_mfp_pads[]       = { NAND1_CEB3 };
+static unsigned int nand1_ceb3_mfp_funcs[]      = { S900_MUX_NAND1,
+                                                    S900_MUX_PWM0 };
+static unsigned int nand1_ceb0_mfp_pads[]       = { NAND1_CEB0 };
+static unsigned int nand1_ceb0_mfp_funcs[]      = { S900_MUX_NAND1,
+                                                    S900_MUX_PWM1 };
+/* mfp3_9 */
+static unsigned int csi1_dn0_dp0_mfp_pads[]     = { CSI1_DN0, CSI1_DP0 };
+static unsigned int csi1_dn0_dp0_mfp_funcs[]    = { S900_MUX_SENS0,
+                                                    S900_MUX_SENS0 };
+/* mfp3_8 */
+static unsigned int uart4_rx_tx_mfp_pads[]      = { UART4_RX, UART4_TX };
+static unsigned int uart4_rx_tx_mfp_funcs[]     = { S900_MUX_UART4,
+                                                    S900_MUX_I2C4 };
+/* PADDRV group data */
+/* drv0 */
+static unsigned int sgpio3_drv_pads[]           = { SGPIO3 };
+static unsigned int sgpio2_drv_pads[]           = { SGPIO2 };
+static unsigned int sgpio1_drv_pads[]           = { SGPIO1 };
+static unsigned int sgpio0_drv_pads[]           = { SGPIO0 };
+static unsigned int rmii_tx_d0_d1_drv_pads[]    = { ETH_TXD0, ETH_TXD1 };
+static unsigned int rmii_txen_rxer_drv_pads[]   = { ETH_TXEN, ETH_RXER };
+static unsigned int rmii_crs_dv_drv_pads[]      = { ETH_CRS_DV };
+static unsigned int rmii_rx_d1_d0_drv_pads[]    = { ETH_RXD1, ETH_RXD0 };
+static unsigned int rmii_ref_clk_drv_pads[]     = { ETH_REF_CLK };
+static unsigned int rmii_mdc_mdio_drv_pads[]    = { ETH_MDC, ETH_MDIO };
+static unsigned int sirq_0_1_drv_pads[]         = { SIRQ0, SIRQ1 };
+static unsigned int sirq2_drv_pads[]            = { SIRQ2 };
+static unsigned int i2s_d0_d1_drv_pads[]        = { I2S_D0, I2S_D1 };
+static unsigned int i2s_lr_m_clk0_drv_pads[]    = { I2S_LRCLK0, I2S_MCLK0 };
+static unsigned int i2s_blk1_mclk1_drv_pads[]   = { I2S_BCLK0, I2S_BCLK1,
+                                                    I2S_LRCLK1, I2S_MCLK1 };
+static unsigned int pcm1_in_out_drv_pads[]      = { PCM1_IN, PCM1_CLK,
+                                                    PCM1_SYNC, PCM1_OUT };
+/* drv1 */
+static unsigned int lvds_oap_oan_drv_pads[]     = { LVDS_OAP, LVDS_OAN };
+static unsigned int lvds_oep_odn_drv_pads[]     = { LVDS_OEP, LVDS_OEN,
+                                                    LVDS_ODP, LVDS_ODN };
+static unsigned int lvds_ocp_obn_drv_pads[]     = { LVDS_OCP, LVDS_OCN,
+                                                    LVDS_OBP, LVDS_OBN };
+static unsigned int lvds_e_drv_pads[]           = { LVDS_EEP, LVDS_EEN,
+                                                    LVDS_EDP, LVDS_EDN,
+                                                    LVDS_ECP, LVDS_ECN,
+                                                    LVDS_EBP, LVDS_EBN };
+static unsigned int sd0_d3_d0_drv_pads[]        = { SD0_D3, SD0_D2,
+                                                    SD0_D1, SD0_D0 };
+static unsigned int sd1_d3_d0_drv_pads[]        = { SD1_D3, SD1_D2,
+                                                    SD1_D1, SD1_D0 };
+static unsigned int sd0_sd1_cmd_clk_drv_pads[]  = { SD0_CLK, SD0_CMD,
+                                                    SD1_CLK, SD1_CMD };
+static unsigned int spi0_sclk_mosi_drv_pads[]   = { SPI0_SCLK, SPI0_MOSI };
+static unsigned int spi0_ss_miso_drv_pads[]     = { SPI0_SS, SPI0_MISO };
+static unsigned int uart0_rx_tx_drv_pads[]      = { UART0_RX, UART0_TX };
+static unsigned int uart4_rx_tx_drv_pads[]      = { UART4_RX, UART4_TX };
+static unsigned int uart2_drv_pads[]            = { UART2_RX, UART2_TX,
+                                                    UART2_RTSB, UART2_CTSB };
+static unsigned int uart3_drv_pads[]            = { UART3_RX, UART3_TX,
+                                                    UART3_RTSB, UART3_CTSB };
+/* drv2 */
+static unsigned int i2c0_drv_pads[]             = { I2C0_SCLK, I2C0_SDATA };
+static unsigned int i2c1_drv_pads[]             = { I2C1_SCLK, I2C1_SDATA };
+static unsigned int i2c2_drv_pads[]             = { I2C2_SCLK, I2C2_SDATA };
+static unsigned int sensor0_drv_pads[]          = { SENSOR0_PCLK,
+                                                    SENSOR0_CKOUT };
+/* SR group data */
+/* sr0 */
+static unsigned int sgpio3_sr_pads[]            = { SGPIO3 };
+static unsigned int sgpio2_sr_pads[]            = { SGPIO2 };
+static unsigned int sgpio1_sr_pads[]            = { SGPIO1 };
+static unsigned int sgpio0_sr_pads[]            = { SGPIO0 };
+static unsigned int rmii_tx_d0_d1_sr_pads[]     = { ETH_TXD0, ETH_TXD1 };
+static unsigned int rmii_txen_rxer_sr_pads[]    = { ETH_TXEN, ETH_RXER };
+static unsigned int rmii_crs_dv_sr_pads[]       = { ETH_CRS_DV };
+static unsigned int rmii_rx_d1_d0_sr_pads[]     = { ETH_RXD1, ETH_RXD0 };
+static unsigned int rmii_ref_clk_sr_pads[]      = { ETH_REF_CLK };
+static unsigned int rmii_mdc_mdio_sr_pads[]     = { ETH_MDC, ETH_MDIO };
+static unsigned int sirq_0_1_sr_pads[]          = { SIRQ0, SIRQ1 };
+static unsigned int sirq2_sr_pads[]             = { SIRQ2 };
+static unsigned int i2s_do_d1_sr_pads[]         = { I2S_D0, I2S_D1 };
+static unsigned int i2s_lr_m_clk0_sr_pads[]     = { I2S_LRCLK0, I2S_MCLK0 };
+static unsigned int i2s_bclk0_mclk1_sr_pads[]   = { I2S_BCLK0, I2S_BCLK1,
+                                                    I2S_LRCLK1, I2S_MCLK1 };
+static unsigned int pcm1_in_out_sr_pads[]       = { PCM1_IN, PCM1_CLK,
+                                                    PCM1_SYNC, PCM1_OUT };
+/* sr1 */
+static unsigned int sd1_d3_d0_sr_pads[]         = { SD1_D3, SD1_D2,
+                                                    SD1_D1, SD1_D0 };
+static unsigned int sd0_sd1_clk_cmd_sr_pads[]   = { SD0_CLK, SD0_CMD,
+                                                    SD1_CLK, SD1_CMD };
+static unsigned int spi0_sclk_mosi_sr_pads[]    = { SPI0_SCLK, SPI0_MOSI };
+static unsigned int spi0_ss_miso_sr_pads[]      = { SPI0_SS, SPI0_MISO };
+static unsigned int uart0_rx_tx_sr_pads[]       = { UART0_RX, UART0_TX };
+static unsigned int uart4_rx_tx_sr_pads[]       = { UART4_RX, UART4_TX };
+static unsigned int uart2_sr_pads[]             = { UART2_RX, UART2_TX,
+                                                    UART2_RTSB, UART2_CTSB };
+static unsigned int uart3_sr_pads[]             = { UART3_RX, UART3_TX,
+                                                    UART3_RTSB, UART3_CTSB };
+/* sr2 */
+static unsigned int i2c0_sr_pads[]              = { I2C0_SCLK, I2C0_SDATA };
+static unsigned int i2c1_sr_pads[]              = { I2C1_SCLK, I2C1_SDATA };
+static unsigned int i2c2_sr_pads[]              = { I2C2_SCLK, I2C2_SDATA };
+static unsigned int sensor0_sr_pads[]           = { SENSOR0_PCLK,
+                                                    SENSOR0_CKOUT };
+
+#define MUX_PG(group_name, reg, shift, width)                           \
+        {                                                               \
+                .name = #group_name,                                    \
+                .pads = group_name##_pads,                              \
+                .npads = ARRAY_SIZE(group_name##_pads),                 \
+                .funcs = group_name##_funcs,                            \
+                .nfuncs = ARRAY_SIZE(group_name##_funcs),               \
+                .mfpctl_reg  = MFCTL##reg,                              \
+                .mfpctl_shift = shift,                                  \
+                .mfpctl_width = width,                                  \
+                .drv_reg = -1,                                          \
+                .drv_shift = -1,                                        \
+                .drv_width = -1,                                        \
+                .sr_reg = -1,                                           \
+                .sr_shift = -1,                                         \
+                .sr_width = -1,                                         \
+        }
+
+#define DRV_PG(group_name, reg, shift, width)                           \
+        {                                                               \
+                .name = #group_name,                                    \
+                .pads = group_name##_pads,                              \
+                .npads = ARRAY_SIZE(group_name##_pads),                 \
+                .mfpctl_reg  = -1,                                      \
+                .mfpctl_shift = -1,                                     \
+                .mfpctl_width = -1,                                     \
+                .drv_reg = PAD_DRV##reg,                                \
+                .drv_shift = shift,                                     \
+                .drv_width = width,                                     \
+                .sr_reg = -1,                                           \
+                .sr_shift = -1,                                         \
+                .sr_width = -1,                                         \
+        }
+
+#define SR_PG(group_name, reg, shift, width)                            \
+        {                                                               \
+                .name = #group_name,                                    \
+                .pads = group_name##_pads,                              \
+                .npads = ARRAY_SIZE(group_name##_pads),                 \
+                .mfpctl_reg  = -1,                                      \
+                .mfpctl_shift = -1,                                     \
+                .mfpctl_width = -1,                                     \
+                .drv_reg = -1,                                          \
+                .drv_shift = -1,                                        \
+                .drv_width = -1,                                        \
+                .sr_reg = PAD_SR##reg,                                  \
+                .sr_shift = shift,                                      \
+                .sr_width = width,                                      \
+        }
+
+/* Pinctrl groups */
+static const struct owl_pingroup s900_groups[] = {
+        MUX_PG(lvds_oxx_uart4_mfp, 0, 22, 1),
+        MUX_PG(rmii_mdc_mfp, 0, 20, 2),
+        MUX_PG(rmii_mdio_mfp, 0, 20, 2),
+        MUX_PG(sirq0_mfp, 0, 19, 1),
+        MUX_PG(sirq1_mfp, 0, 19, 1),
+        MUX_PG(rmii_txd0_mfp, 0, 16, 3),
+        MUX_PG(rmii_txd1_mfp, 0, 16, 3),
+        MUX_PG(rmii_txen_mfp, 0, 13, 3),
+        MUX_PG(rmii_rxer_mfp, 0, 13, 3),
+        MUX_PG(rmii_crs_dv_mfp, 0, 11, 2),
+        MUX_PG(rmii_rxd1_mfp, 0, 8, 3),
+        MUX_PG(rmii_rxd0_mfp, 0, 8, 3),
+        MUX_PG(rmii_ref_clk_mfp, 0, 6, 2),
+        MUX_PG(i2s_d0_mfp, 0, 5, 1),
+        MUX_PG(i2s_d1_mfp, 0, 5, 1),
+        MUX_PG(i2s_lr_m_clk0_mfp, 0, 3, 2),
+        MUX_PG(i2s_bclk0_mfp, 0, 2, 1),
+        MUX_PG(i2s_bclk1_mclk1_mfp, 0, 2, 1),
+        MUX_PG(pcm1_in_out_mfp, 0, 0, 2),
+        MUX_PG(pcm1_clk_mfp, 0, 0, 2),
+        MUX_PG(pcm1_sync_mfp, 0, 0, 2),
+        MUX_PG(eram_a5_mfp, 1, 29, 3),
+        MUX_PG(eram_a6_mfp, 1, 29, 3),
+        MUX_PG(eram_a7_mfp, 1, 29, 3),
+        MUX_PG(eram_a8_mfp, 1, 26, 3),
+        MUX_PG(eram_a9_mfp, 1, 26, 3),
+        MUX_PG(eram_a10_mfp, 1, 26, 3),
+        MUX_PG(eram_a11_mfp, 1, 23, 3),
+        MUX_PG(lvds_oep_odn_mfp, 1, 22, 1),
+        MUX_PG(lvds_ocp_obn_mfp, 1, 22, 1),
+        MUX_PG(lvds_oap_oan_mfp, 1, 22, 1),
+        MUX_PG(lvds_e_mfp, 1, 21, 1),
+        MUX_PG(spi0_sclk_mosi_mfp, 1, 4, 2),
+        MUX_PG(spi0_ss_mfp, 1, 1, 3),
+        MUX_PG(spi0_miso_mfp, 1, 1, 3),
+        MUX_PG(uart2_rtsb_mfp, 2, 23, 1),
+        MUX_PG(uart2_ctsb_mfp, 2, 22, 1),
+        MUX_PG(uart3_rtsb_mfp, 2, 21, 1),
+        MUX_PG(uart3_ctsb_mfp, 2, 20, 1),
+        MUX_PG(sd0_d0_mfp, 2, 17, 3),
+        MUX_PG(sd0_d1_mfp, 2, 14, 3),
+        MUX_PG(sd0_d2_d3_mfp, 2, 11, 3),
+        MUX_PG(sd1_d0_d3_mfp, 2, 9, 2),
+        MUX_PG(sd0_cmd_mfp, 2, 7, 2),
+        MUX_PG(sd0_clk_mfp, 2, 5, 2),
+        MUX_PG(sd1_cmd_clk_mfp, 2, 3, 2),
+        MUX_PG(uart0_rx_mfp, 2, 0, 3),
+        MUX_PG(nand0_d0_ceb3_mfp, 3, 27, 1),
+        MUX_PG(uart0_tx_mfp, 3, 19, 3),
+        MUX_PG(i2c0_mfp, 3, 16, 3),
+        MUX_PG(csi0_cn_cp_mfp, 3, 15, 1),
+        MUX_PG(csi0_dn0_dp3_mfp, 3, 14, 1),
+        MUX_PG(csi1_dn0_cp_mfp, 3, 13, 1),
+        MUX_PG(dsi_dp3_dn1_mfp, 3, 12, 1),
+        MUX_PG(dsi_cp_dn0_mfp, 3, 12, 1),
+        MUX_PG(dsi_dp2_dn2_mfp, 3, 12, 1),
+        MUX_PG(nand1_d0_ceb1_mfp, 3, 11, 1),
+        MUX_PG(nand1_ceb3_mfp, 3, 10, 1),
+        MUX_PG(nand1_ceb0_mfp, 3, 10, 1),
+        MUX_PG(csi1_dn0_dp0_mfp, 3, 9, 1),
+        MUX_PG(uart4_rx_tx_mfp, 3, 8, 1),
+
+        DRV_PG(sgpio3_drv, 0, 30, 2),
+        DRV_PG(sgpio2_drv, 0, 28, 2),
+        DRV_PG(sgpio1_drv, 0, 26, 2),
+        DRV_PG(sgpio0_drv, 0, 24, 2),
+        DRV_PG(rmii_tx_d0_d1_drv, 0, 22, 2),
+        DRV_PG(rmii_txen_rxer_drv, 0, 20, 2),
+        DRV_PG(rmii_crs_dv_drv, 0, 18, 2),
+        DRV_PG(rmii_rx_d1_d0_drv, 0, 16, 2),
+        DRV_PG(rmii_ref_clk_drv, 0, 14, 2),
+        DRV_PG(rmii_mdc_mdio_drv, 0, 12, 2),
+        DRV_PG(sirq_0_1_drv, 0, 10, 2),
+        DRV_PG(sirq2_drv, 0, 8, 2),
+        DRV_PG(i2s_d0_d1_drv, 0, 6, 2),
+        DRV_PG(i2s_lr_m_clk0_drv, 0, 4, 2),
+        DRV_PG(i2s_blk1_mclk1_drv, 0, 2, 2),
+        DRV_PG(pcm1_in_out_drv, 0, 0, 2),
+        DRV_PG(lvds_oap_oan_drv, 1, 28, 2),
+        DRV_PG(lvds_oep_odn_drv, 1, 26, 2),
+        DRV_PG(lvds_ocp_obn_drv, 1, 24, 2),
+        DRV_PG(lvds_e_drv, 1, 22, 2),
+        DRV_PG(sd0_d3_d0_drv, 1, 20, 2),
+        DRV_PG(sd1_d3_d0_drv, 1, 18, 2),
+        DRV_PG(sd0_sd1_cmd_clk_drv, 1, 16, 2),
+        DRV_PG(spi0_sclk_mosi_drv, 1, 14, 2),
+        DRV_PG(spi0_ss_miso_drv, 1, 12, 2),
+        DRV_PG(uart0_rx_tx_drv, 1, 10, 2),
+        DRV_PG(uart4_rx_tx_drv, 1, 8, 2),
+        DRV_PG(uart2_drv, 1, 6, 2),
+        DRV_PG(uart3_drv, 1, 4, 2),
+        DRV_PG(i2c0_drv, 2, 30, 2),
+        DRV_PG(i2c1_drv, 2, 28, 2),
+        DRV_PG(i2c2_drv, 2, 26, 2),
+        DRV_PG(sensor0_drv, 2, 20, 2),
+
+        SR_PG(sgpio3_sr, 0, 15, 1),
+        SR_PG(sgpio2_sr, 0, 14, 1),
+        SR_PG(sgpio1_sr, 0, 13, 1),
+        SR_PG(sgpio0_sr, 0, 12, 1),
+        SR_PG(rmii_tx_d0_d1_sr, 0, 11, 1),
+        SR_PG(rmii_txen_rxer_sr, 0, 10, 1),
+        SR_PG(rmii_crs_dv_sr, 0, 9, 1),
+        SR_PG(rmii_rx_d1_d0_sr, 0, 8, 1),
+        SR_PG(rmii_ref_clk_sr, 0, 7, 1),
+        SR_PG(rmii_mdc_mdio_sr, 0, 6, 1),
+        SR_PG(sirq_0_1_sr, 0, 5, 1),
+        SR_PG(sirq2_sr, 0, 4, 1),
+        SR_PG(i2s_do_d1_sr, 0, 3, 1),
+        SR_PG(i2s_lr_m_clk0_sr, 0, 2, 1),
+        SR_PG(i2s_bclk0_mclk1_sr, 0, 1, 1),
+        SR_PG(pcm1_in_out_sr, 0, 0, 1),
+        SR_PG(sd1_d3_d0_sr, 1, 25, 1),
+        SR_PG(sd0_sd1_clk_cmd_sr, 1, 24, 1),
+        SR_PG(spi0_sclk_mosi_sr, 1, 23, 1),
+        SR_PG(spi0_ss_miso_sr, 1, 22, 1),
+        SR_PG(uart0_rx_tx_sr, 1, 21, 1),
+        SR_PG(uart4_rx_tx_sr, 1, 20, 1),
+        SR_PG(uart2_sr, 1, 19, 1),
+        SR_PG(uart3_sr, 1, 18, 1),
+        SR_PG(i2c0_sr, 2, 31, 1),
+        SR_PG(i2c1_sr, 2, 30, 1),
+        SR_PG(i2c2_sr, 2, 29, 1),
+        SR_PG(sensor0_sr, 2, 25, 1)
+};
+
+static const char * const eram_groups[] = {
+        "lvds_oxx_uart4_mfp",
+        "eram_a5_mfp",
+        "eram_a6_mfp",
+        "eram_a7_mfp",
+        "eram_a8_mfp",
+        "eram_a9_mfp",
+        "eram_a10_mfp",
+        "eram_a11_mfp",
+        "lvds_oap_oan_mfp",
+        "lvds_e_mfp",
+        "spi0_sclk_mosi_mfp",
+        "spi0_ss_mfp",
+        "spi0_miso_mfp",
+        "sd0_d0_mfp",
+        "sd0_d1_mfp",
+        "sd0_d2_d3_mfp",
+        "sd1_d0_d3_mfp",
+        "sd0_cmd_mfp",
+        "sd0_clk_mfp",
+        "sd1_cmd_clk_mfp",
+};
+
+static const char * const eth_rmii_groups[] = {
+        "rmii_mdc_mfp",
+        "rmii_mdio_mfp",
+        "rmii_txd0_mfp",
+        "rmii_txd1_mfp",
+        "rmii_txen_mfp",
+        "rmii_rxer_mfp",
+        "rmii_crs_dv_mfp",
+        "rmii_rxd1_mfp",
+        "rmii_rxd0_mfp",
+        "rmii_ref_clk_mfp",
+        "eth_smi_dummy",
+};
+
+static const char * const eth_smii_groups[] = {
+        "rmii_txd0_mfp",
+        "rmii_txd1_mfp",
+        "rmii_crs_dv_mfp",
+        "eth_smi_dummy",
+};
+
+static const char * const spi0_groups[] = {
+        "spi0_sclk_mosi_mfp",
+        "spi0_ss_mfp",
+        "spi0_miso_mfp",
+        "spi0_sclk_mosi_mfp",
+        "spi0_ss_mfp",
+        "spi0_miso_mfp",
+};
+
+static const char * const spi1_groups[] = {
+        "pcm1_in_out_mfp",
+        "pcm1_clk_mfp",
+        "pcm1_sync_mfp",
+        "uart0_rx_mfp",
+        "uart0_tx_mfp",
+        "i2c0_mfp",
+};
+
+static const char * const spi2_groups[] = {
+        "rmii_txd0_mfp",
+        "rmii_txd1_mfp",
+        "rmii_crs_dv_mfp",
+        "rmii_ref_clk_mfp",
+};
+
+static const char * const spi3_groups[] = {
+        "rmii_txen_mfp",
+        "rmii_rxer_mfp",
+};
+
+static const char * const sens0_groups[] = {
+        "rmii_txd0_mfp",
+        "rmii_txd1_mfp",
+        "rmii_txen_mfp",
+        "rmii_rxer_mfp",
+        "rmii_rxd1_mfp",
+        "rmii_rxd0_mfp",
+        "eram_a5_mfp",
+        "eram_a6_mfp",
+        "eram_a7_mfp",
+        "eram_a8_mfp",
+        "eram_a9_mfp",
+        "csi0_cn_cp_mfp",
+        "csi0_dn0_dp3_mfp",
+        "csi1_dn0_cp_mfp",
+        "csi1_dn0_dp0_mfp",
+};
+
+static const char * const uart0_groups[] = {
+        "uart2_rtsb_mfp",
+        "uart2_ctsb_mfp",
+        "uart0_rx_mfp",
+        "uart0_tx_mfp",
+};
+
+static const char * const uart1_groups[] = {
+        "sd0_d2_d3_mfp",
+        "i2c0_mfp",
+};
+
+static const char * const uart2_groups[] = {
+        "rmii_mdc_mfp",
+        "rmii_mdio_mfp",
+        "rmii_txen_mfp",
+        "rmii_rxer_mfp",
+        "rmii_rxd1_mfp",
+        "rmii_rxd0_mfp",
+        "lvds_oep_odn_mfp",
+        "uart2_rtsb_mfp",
+        "uart2_ctsb_mfp",
+        "sd0_d0_mfp",
+        "sd0_d1_mfp",
+        "sd0_d2_d3_mfp",
+        "uart0_rx_mfp",
+        "uart0_tx_mfp_pads",
+        "i2c0_mfp_pads",
+        "dsi_dp3_dn1_mfp",
+        "uart2_dummy"
+};
+
+static const char * const uart3_groups[] = {
+        "uart3_rtsb_mfp",
+        "uart3_ctsb_mfp",
+        "uart3_dummy"
+};
+
+static const char * const uart4_groups[] = {
+        "lvds_oxx_uart4_mfp",
+        "rmii_crs_dv_mfp",
+        "rmii_ref_clk_mfp",
+        "pcm1_in_out_mfp",
+        "pcm1_clk_mfp",
+        "pcm1_sync_mfp",
+        "eram_a5_mfp",
+        "eram_a6_mfp",
+        "dsi_dp2_dn2_mfp",
+        "uart4_rx_tx_mfp_pads",
+        "uart4_dummy"
+};
+
+static const char * const uart5_groups[] = {
+        "rmii_rxd1_mfp",
+        "rmii_rxd0_mfp",
+        "eram_a9_mfp",
+        "eram_a11_mfp",
+        "uart3_rtsb_mfp",
+        "uart3_ctsb_mfp",
+        "sd0_d0_mfp",
+        "sd0_d1_mfp",
+};
+
+static const char * const uart6_groups[] = {
+        "rmii_txd0_mfp",
+        "rmii_txd1_mfp",
+};
+
+static const char * const i2s0_groups[] = {
+        "i2s_d0_mfp",
+        "i2s_lr_m_clk0_mfp",
+        "i2s_bclk0_mfp",
+        "i2s0_dummy",
+};
+
+static const char * const i2s1_groups[] = {
+        "i2s_d1_mfp",
+        "i2s_bclk1_mclk1_mfp",
+        "spi0_ss_mfp",
+        "spi0_miso_mfp",
+        "uart0_rx_mfp",
+        "uart0_tx_mfp",
+        "i2s1_dummy",
+};
+
+static const char * const pcm0_groups[] = {
+        "i2s_d0_mfp",
+        "i2s_d1_mfp",
+        "i2s_lr_m_clk0_mfp",
+        "i2s_bclk0_mfp",
+        "i2s_bclk1_mclk1_mfp",
+        "spi0_sclk_mosi_mfp",
+        "spi0_ss_mfp",
+        "spi0_miso_mfp",
+};
+
+static const char * const pcm1_groups[] = {
+        "i2s_lr_m_clk0_mfp",
+        "pcm1_in_out_mfp",
+        "pcm1_clk_mfp",
+        "pcm1_sync_mfp",
+        "lvds_oep_odn_mfp",
+        "spi0_ss_mfp",
+        "spi0_miso_mfp",
+        "uart0_rx_mfp",
+        "uart0_tx_mfp",
+        "dsi_cp_dn0_mfp",
+        "pcm1_dummy",
+};
+
+static const char * const jtag_groups[] = {
+        "eram_a5_mfp",
+        "eram_a6_mfp",
+        "eram_a7_mfp",
+        "eram_a8_mfp",
+        "eram_a10_mfp",
+        "eram_a10_mfp",
+        "sd0_d2_d3_mfp",
+        "sd0_cmd_mfp",
+        "sd0_clk_mfp",
+};
+
+static const char * const pwm0_groups[] = {
+        "sirq0_mfp",
+        "rmii_txd0_mfp",
+        "rmii_rxd1_mfp",
+        "eram_a5_mfp",
+        "nand1_ceb3_mfp",
+};
+
+static const char * const pwm1_groups[] = {
+        "sirq1_mfp",
+        "rmii_txd1_mfp",
+        "rmii_rxd0_mfp",
+        "eram_a6_mfp",
+        "eram_a8_mfp",
+        "nand1_ceb0_mfp",
+};
+
+static const char * const pwm2_groups[] = {
+        "rmii_mdc_mfp",
+        "rmii_txen_mfp",
+        "eram_a9_mfp",
+        "eram_a11_mfp",
+};
+
+static const char * const pwm3_groups[] = {
+        "rmii_mdio_mfp",
+        "rmii_rxer_mfp",
+        "eram_a10_mfp",
+};
+
+static const char * const pwm4_groups[] = {
+        "pcm1_clk_mfp",
+        "spi0_ss_mfp",
+};
+
+static const char * const pwm5_groups[] = {
+        "pcm1_sync_mfp",
+        "spi0_miso_mfp",
+};
+
+static const char * const sd0_groups[] = {
+        "sd0_d0_mfp",
+        "sd0_d1_mfp",
+        "sd0_d2_d3_mfp",
+        "sd0_cmd_mfp",
+        "sd0_clk_mfp",
+};
+
+static const char * const sd1_groups[] = {
+        "sd1_d0_d3_mfp",
+        "sd1_cmd_clk_mfp",
+        "sd1_dummy",
+};
+
+static const char * const sd2_groups[] = {
+        "nand0_d0_ceb3_mfp",
+};
+
+static const char * const sd3_groups[] = {
+        "nand1_d0_ceb1_mfp",
+};
+
+static const char * const i2c0_groups[] = {
+        "i2c0_mfp",
+};
+
+static const char * const i2c1_groups[] = {
+        "i2c0_mfp",
+        "i2c1_dummy"
+};
+
+static const char * const i2c2_groups[] = {
+        "i2c2_dummy"
+};
+
+static const char * const i2c3_groups[] = {
+        "pcm1_in_out_mfp",
+        "spi0_sclk_mosi_mfp",
+};
+
+static const char * const i2c4_groups[] = {
+        "uart4_rx_tx_mfp",
+};
+
+static const char * const i2c5_groups[] = {
+        "uart0_rx_mfp",
+        "uart0_tx_mfp",
+};
+
+
+static const char * const lvds_groups[] = {
+        "lvds_oep_odn_mfp",
+        "lvds_ocp_obn_mfp",
+        "lvds_oap_oan_mfp",
+        "lvds_e_mfp",
+};
+
+static const char * const usb20_groups[] = {
+        "eram_a9_mfp",
+};
+
+static const char * const usb30_groups[] = {
+        "eram_a10_mfp",
+};
+
+static const char * const gpu_groups[] = {
+        "sd0_d0_mfp",
+        "sd0_d1_mfp",
+        "sd0_d2_d3_mfp",
+        "sd0_cmd_mfp",
+        "sd0_clk_mfp",
+};
+
+static const char * const mipi_csi0_groups[] = {
+        "csi0_dn0_dp3_mfp",
+};
+
+static const char * const mipi_csi1_groups[] = {
+        "csi1_dn0_cp_mfp",
+};
+
+static const char * const mipi_dsi_groups[] = {
+        "dsi_dp3_dn1_mfp",
+        "dsi_cp_dn0_mfp",
+        "dsi_dp2_dn2_mfp",
+        "mipi_dsi_dummy",
+};
+
+static const char * const nand0_groups[] = {
+        "nand0_d0_ceb3_mfp",
+        "nand0_dummy",
+};
+
+static const char * const nand1_groups[] = {
+        "nand1_d0_ceb1_mfp",
+        "nand1_ceb3_mfp",
+        "nand1_ceb0_mfp",
+        "nand1_dummy",
+};
+
+static const char * const spdif_groups[] = {
+        "uart0_tx_mfp",
+};
+
+static const char * const sirq0_groups[] = {
+        "sirq0_mfp",
+        "sirq0_dummy",
+};
+
+static const char * const sirq1_groups[] = {
+        "sirq1_mfp",
+        "sirq1_dummy",
+};
+
+static const char * const sirq2_groups[] = {
+        "sirq2_dummy",
+};
+
+#define FUNCTION(fname)                                 \
+        {                                               \
+                .name = #fname,                         \
+                .groups = fname##_groups,               \
+                .ngroups = ARRAY_SIZE(fname##_groups),  \
+        }
+
+static const struct owl_pinmux_func s900_functions[] = {
+        [S900_MUX_ERAM] = FUNCTION(eram),
+        [S900_MUX_ETH_RMII] = FUNCTION(eth_rmii),
+        [S900_MUX_ETH_SMII] = FUNCTION(eth_smii),
+        [S900_MUX_SPI0] = FUNCTION(spi0),
+        [S900_MUX_SPI1] = FUNCTION(spi1),
+        [S900_MUX_SPI2] = FUNCTION(spi2),
+        [S900_MUX_SPI3] = FUNCTION(spi3),
+        [S900_MUX_SENS0] = FUNCTION(sens0),
+        [S900_MUX_UART0] = FUNCTION(uart0),
+        [S900_MUX_UART1] = FUNCTION(uart1),
+        [S900_MUX_UART2] = FUNCTION(uart2),
+        [S900_MUX_UART3] = FUNCTION(uart3),
+        [S900_MUX_UART4] = FUNCTION(uart4),
+        [S900_MUX_UART5] = FUNCTION(uart5),
+        [S900_MUX_UART6] = FUNCTION(uart6),
+        [S900_MUX_I2S0] = FUNCTION(i2s0),
+        [S900_MUX_I2S1] = FUNCTION(i2s1),
+        [S900_MUX_PCM0] = FUNCTION(pcm0),
+        [S900_MUX_PCM1] = FUNCTION(pcm1),
+        [S900_MUX_JTAG] = FUNCTION(jtag),
+        [S900_MUX_PWM0] = FUNCTION(pwm0),
+        [S900_MUX_PWM1] = FUNCTION(pwm1),
+        [S900_MUX_PWM2] = FUNCTION(pwm2),
+        [S900_MUX_PWM3] = FUNCTION(pwm3),
+        [S900_MUX_PWM4] = FUNCTION(pwm4),
+        [S900_MUX_PWM5] = FUNCTION(pwm5),
+        [S900_MUX_SD0] = FUNCTION(sd0),
+        [S900_MUX_SD1] = FUNCTION(sd1),
+        [S900_MUX_SD2] = FUNCTION(sd2),
+        [S900_MUX_SD3] = FUNCTION(sd3),
+        [S900_MUX_I2C0] = FUNCTION(i2c0),
+        [S900_MUX_I2C1] = FUNCTION(i2c1),
+        [S900_MUX_I2C2] = FUNCTION(i2c2),
+        [S900_MUX_I2C3] = FUNCTION(i2c3),
+        [S900_MUX_I2C4] = FUNCTION(i2c4),
+        [S900_MUX_I2C5] = FUNCTION(i2c5),
+        [S900_MUX_LVDS] = FUNCTION(lvds),
+        [S900_MUX_USB30] = FUNCTION(usb30),
+        [S900_MUX_USB20] = FUNCTION(usb20),
+        [S900_MUX_GPU] = FUNCTION(gpu),
+        [S900_MUX_MIPI_CSI0] = FUNCTION(mipi_csi0),
+        [S900_MUX_MIPI_CSI1] = FUNCTION(mipi_csi1),
+        [S900_MUX_MIPI_DSI] = FUNCTION(mipi_dsi),
+        [S900_MUX_NAND0] = FUNCTION(nand0),
+        [S900_MUX_NAND1] = FUNCTION(nand1),
+        [S900_MUX_SPDIF] = FUNCTION(spdif),
+        [S900_MUX_SIRQ0] = FUNCTION(sirq0),
+        [S900_MUX_SIRQ1] = FUNCTION(sirq1),
+        [S900_MUX_SIRQ2] = FUNCTION(sirq2)
+};
+/* PAD PULL UP/DOWN CONFIGURES */
+#define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)                      \
+        {                                                               \
+                .reg = PAD_PULLCTL##pull_reg,                           \
+                .shift = pull_sft,                                      \
+                .width = pull_wdt,                                      \
+        }
+
+#define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt)        \
+        struct owl_pullctl pad_name##_pullctl_conf                      \
+                = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
+
+#define ST_CONF(st_reg, st_sft, st_wdt)                                 \
+        {                                                               \
+                .reg = PAD_ST##st_reg,                                  \
+                .shift = st_sft,                                        \
+                .width = st_wdt,                                        \
+        }
+
+#define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt)                   \
+        struct owl_st pad_name##_st_conf                                \
+                = ST_CONF(st_reg, st_sft, st_wdt)
+
+/* PAD_PULLCTL0 */
+static PAD_PULLCTL_CONF(ETH_RXER, 0, 18, 2);
+static PAD_PULLCTL_CONF(SIRQ0, 0, 16, 2);
+static PAD_PULLCTL_CONF(SIRQ1, 0, 14, 2);
+static PAD_PULLCTL_CONF(SIRQ2, 0, 12, 2);
+static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 10, 2);
+static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 2);
+static PAD_PULLCTL_CONF(ERAM_A5, 0, 6, 2);
+static PAD_PULLCTL_CONF(ERAM_A6, 0, 4, 2);
+static PAD_PULLCTL_CONF(ERAM_A7, 0, 2, 2);
+static PAD_PULLCTL_CONF(ERAM_A10, 0, 0, 2);
+
+/* PAD_PULLCTL1 */
+static PAD_PULLCTL_CONF(PCM1_IN, 1, 30, 2);
+static PAD_PULLCTL_CONF(PCM1_OUT, 1, 28, 2);
+static PAD_PULLCTL_CONF(SD0_D0, 1, 26, 2);
+static PAD_PULLCTL_CONF(SD0_D1, 1, 24, 2);
+static PAD_PULLCTL_CONF(SD0_D2, 1, 22, 2);
+static PAD_PULLCTL_CONF(SD0_D3, 1, 20, 2);
+static PAD_PULLCTL_CONF(SD0_CMD, 1, 18, 2);
+static PAD_PULLCTL_CONF(SD0_CLK, 1, 16, 2);
+static PAD_PULLCTL_CONF(SD1_CMD, 1, 14, 2);
+static PAD_PULLCTL_CONF(SD1_D0, 1, 12, 2);
+static PAD_PULLCTL_CONF(SD1_D1, 1, 10, 2);
+static PAD_PULLCTL_CONF(SD1_D2, 1, 8, 2);
+static PAD_PULLCTL_CONF(SD1_D3, 1, 6, 2);
+static PAD_PULLCTL_CONF(UART0_RX, 1, 4, 2);
+static PAD_PULLCTL_CONF(UART0_TX, 1, 2, 2);
+
+/* PAD_PULLCTL2 */
+static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 26, 2);
+static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 24, 2);
+static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 22, 2);
+static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 20, 2);
+static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 18, 2);
+static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 16, 2);
+static PAD_PULLCTL_CONF(NAND0_D0, 2, 15, 1);
+static PAD_PULLCTL_CONF(NAND0_D1, 2, 15, 1);
+static PAD_PULLCTL_CONF(NAND0_D2, 2, 15, 1);
+static PAD_PULLCTL_CONF(NAND0_D3, 2, 15, 1);
+static PAD_PULLCTL_CONF(NAND0_D4, 2, 15, 1);
+static PAD_PULLCTL_CONF(NAND0_D5, 2, 15, 1);
+static PAD_PULLCTL_CONF(NAND0_D6, 2, 15, 1);
+static PAD_PULLCTL_CONF(NAND0_D7, 2, 15, 1);
+static PAD_PULLCTL_CONF(NAND0_DQSN, 2, 14, 1);
+static PAD_PULLCTL_CONF(NAND0_DQS, 2, 13, 1);
+static PAD_PULLCTL_CONF(NAND1_D0, 2, 12, 1);
+static PAD_PULLCTL_CONF(NAND1_D1, 2, 12, 1);
+static PAD_PULLCTL_CONF(NAND1_D2, 2, 12, 1);
+static PAD_PULLCTL_CONF(NAND1_D3, 2, 12, 1);
+static PAD_PULLCTL_CONF(NAND1_D4, 2, 12, 1);
+static PAD_PULLCTL_CONF(NAND1_D5, 2, 12, 1);
+static PAD_PULLCTL_CONF(NAND1_D6, 2, 12, 1);
+static PAD_PULLCTL_CONF(NAND1_D7, 2, 12, 1);
+static PAD_PULLCTL_CONF(NAND1_DQSN, 2, 11, 1);
+static PAD_PULLCTL_CONF(NAND1_DQS, 2, 10, 1);
+static PAD_PULLCTL_CONF(SGPIO2, 2, 8, 2);
+static PAD_PULLCTL_CONF(SGPIO3, 2, 6, 2);
+static PAD_PULLCTL_CONF(UART4_RX, 2, 4, 2);
+static PAD_PULLCTL_CONF(UART4_TX, 2, 2, 2);
+
+/* PAD_ST0 */
+static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);
+static PAD_ST_CONF(UART0_RX, 0, 29, 1);
+static PAD_ST_CONF(ETH_MDC, 0, 28, 1);
+static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);
+static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);
+static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);
+static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);
+static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);
+static PAD_ST_CONF(SGPIO2, 0, 18, 1);
+static PAD_ST_CONF(SGPIO3, 0, 17, 1);
+static PAD_ST_CONF(UART4_TX, 0, 16, 1);
+static PAD_ST_CONF(I2S_D1, 0, 15, 1);
+static PAD_ST_CONF(UART0_TX, 0, 14, 1);
+static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1);
+static PAD_ST_CONF(SD0_CLK, 0, 12, 1);
+static PAD_ST_CONF(ERAM_A5, 0, 11, 1);
+static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);
+static PAD_ST_CONF(ERAM_A9, 0, 6, 1);
+static PAD_ST_CONF(LVDS_OEP, 0, 5, 1);
+static PAD_ST_CONF(LVDS_ODN, 0, 4, 1);
+static PAD_ST_CONF(LVDS_OAP, 0, 3, 1);
+static PAD_ST_CONF(I2S_BCLK1, 0, 2, 1);
+
+/* PAD_ST1 */
+static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);
+static PAD_ST_CONF(UART4_RX, 1, 28, 1);
+static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);
+static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);
+static PAD_ST_CONF(UART3_RX, 1, 25, 1);
+static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);
+static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);
+static PAD_ST_CONF(UART2_RX, 1, 22, 1);
+static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);
+static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);
+static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);
+static PAD_ST_CONF(ETH_RXER, 1, 18, 1);
+static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);
+static PAD_ST_CONF(LVDS_OCP, 1, 16, 1);
+static PAD_ST_CONF(LVDS_OBP, 1, 15, 1);
+static PAD_ST_CONF(LVDS_OBN, 1, 14, 1);
+static PAD_ST_CONF(PCM1_OUT, 1, 12, 1);
+static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);
+static PAD_ST_CONF(PCM1_IN, 1, 10, 1);
+static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);
+static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);
+static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);
+static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);
+static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);
+static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1);
+static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);
+static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
+static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
+static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
+
+#define PAD_INFO(name)                                                  \
+        {                                                               \
+                .pad = name,                                            \
+                .pullctl = NULL,                                        \
+                .st = NULL,                                             \
+        }
+
+#define PAD_INFO_ST(name)                                               \
+        {                                                               \
+                .pad = name,                                            \
+                .pullctl = NULL,                                        \
+                .st = &name##_st_conf,                                  \
+        }
+
+#define PAD_INFO_PULLCTL(name)                                          \
+        {                                                               \
+                .pad = name,                                            \
+                .pullctl = &name##_pullctl_conf,                        \
+                .st = NULL,                                             \
+        }
+
+#define PAD_INFO_PULLCTL_ST(name)                                       \
+        {                                                               \
+                .pad = name,                                            \
+                .pullctl = &name##_pullctl_conf,                        \
+                .st = &name##_st_conf,                                  \
+        }
+
+/* Pad info table */
+static struct owl_padinfo s900_padinfo[NUM_PADS] = {
+        [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
+        [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
+        [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),
+        [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER),
+        [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV),
+        [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),
+        [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0),
+        [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK),
+        [ETH_MDC] = PAD_INFO_ST(ETH_MDC),
+        [ETH_MDIO] = PAD_INFO(ETH_MDIO),
+        [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0),
+        [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1),
+        [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2),
+        [I2S_D0] = PAD_INFO(I2S_D0),
+        [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0),
+        [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0),
+        [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0),
+        [I2S_D1] = PAD_INFO_ST(I2S_D1),
+        [I2S_BCLK1] = PAD_INFO_ST(I2S_BCLK1),
+        [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1),
+        [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1),
+        [PCM1_IN] = PAD_INFO_PULLCTL_ST(PCM1_IN),
+        [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK),
+        [PCM1_SYNC] = PAD_INFO_ST(PCM1_SYNC),
+        [PCM1_OUT] = PAD_INFO_PULLCTL_ST(PCM1_OUT),
+        [ERAM_A5] = PAD_INFO_PULLCTL_ST(ERAM_A5),
+        [ERAM_A6] = PAD_INFO_PULLCTL(ERAM_A6),
+        [ERAM_A7] = PAD_INFO_PULLCTL(ERAM_A7),
+        [ERAM_A8] = PAD_INFO(ERAM_A8),
+        [ERAM_A9] = PAD_INFO_ST(ERAM_A9),
+        [ERAM_A10] = PAD_INFO_PULLCTL(ERAM_A10),
+        [ERAM_A11] = PAD_INFO(ERAM_A11),
+        [LVDS_OEP] = PAD_INFO_ST(LVDS_OEP),
+        [LVDS_OEN] = PAD_INFO(LVDS_OEN),
+        [LVDS_ODP] = PAD_INFO(LVDS_ODP),
+        [LVDS_ODN] = PAD_INFO_ST(LVDS_ODN),
+        [LVDS_OCP] = PAD_INFO_ST(LVDS_OCP),
+        [LVDS_OCN] = PAD_INFO(LVDS_OCN),
+        [LVDS_OBP] = PAD_INFO_ST(LVDS_OBP),
+        [LVDS_OBN] = PAD_INFO_ST(LVDS_OBN),
+        [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP),
+        [LVDS_OAN] = PAD_INFO(LVDS_OAN),
+        [LVDS_EEP] = PAD_INFO(LVDS_EEP),
+        [LVDS_EEN] = PAD_INFO(LVDS_EEN),
+        [LVDS_EDP] = PAD_INFO(LVDS_EDP),
+        [LVDS_EDN] = PAD_INFO(LVDS_EDN),
+        [LVDS_ECP] = PAD_INFO(LVDS_ECP),
+        [LVDS_ECN] = PAD_INFO(LVDS_ECN),
+        [LVDS_EBP] = PAD_INFO(LVDS_EBP),
+        [LVDS_EBN] = PAD_INFO(LVDS_EBN),
+        [LVDS_EAP] = PAD_INFO(LVDS_EAP),
+        [LVDS_EAN] = PAD_INFO(LVDS_EAN),
+        [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0),
+        [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1),
+        [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2),
+        [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3),
+        [SD1_D0] = PAD_INFO_PULLCTL(SD1_D0),
+        [SD1_D1] = PAD_INFO_PULLCTL(SD1_D1),
+        [SD1_D2] = PAD_INFO_PULLCTL(SD1_D2),
+        [SD1_D3] = PAD_INFO_PULLCTL(SD1_D3),
+        [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD),
+        [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK),
+        [SD1_CMD] = PAD_INFO_PULLCTL(SD1_CMD),
+        [SD1_CLK] = PAD_INFO(SD1_CLK),
+        [SPI0_SCLK] = PAD_INFO_PULLCTL_ST(SPI0_SCLK),
+        [SPI0_SS] = PAD_INFO_ST(SPI0_SS),
+        [SPI0_MISO] = PAD_INFO_ST(SPI0_MISO),
+        [SPI0_MOSI] = PAD_INFO_PULLCTL_ST(SPI0_MOSI),
+        [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX),
+        [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX),
+        [UART2_RX] = PAD_INFO_ST(UART2_RX),
+        [UART2_TX] = PAD_INFO(UART2_TX),
+        [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB),
+        [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB),
+        [UART3_RX] = PAD_INFO_ST(UART3_RX),
+        [UART3_TX] = PAD_INFO(UART3_TX),
+        [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB),
+        [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB),
+        [UART4_RX] = PAD_INFO_PULLCTL_ST(UART4_RX),
+        [UART4_TX] = PAD_INFO_PULLCTL_ST(UART4_TX),
+        [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK),
+        [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA),
+        [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK),
+        [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA),
+        [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK),
+        [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA),
+        [CSI0_DN0] = PAD_INFO(CSI0_DN0),
+        [CSI0_DP0] = PAD_INFO(CSI0_DP0),
+        [CSI0_DN1] = PAD_INFO(CSI0_DN1),
+        [CSI0_DP1] = PAD_INFO(CSI0_DP1),
+        [CSI0_CN] = PAD_INFO(CSI0_CN),
+        [CSI0_CP] = PAD_INFO(CSI0_CP),
+        [CSI0_DN2] = PAD_INFO(CSI0_DN2),
+        [CSI0_DP2] = PAD_INFO(CSI0_DP2),
+        [CSI0_DN3] = PAD_INFO(CSI0_DN3),
+        [CSI0_DP3] = PAD_INFO(CSI0_DP3),
+        [DSI_DP3] = PAD_INFO(DSI_DP3),
+        [DSI_DN3] = PAD_INFO(DSI_DN3),
+        [DSI_DP1] = PAD_INFO(DSI_DP1),
+        [DSI_DN1] = PAD_INFO(DSI_DN1),
+        [DSI_CP] = PAD_INFO(DSI_CP),
+        [DSI_CN] = PAD_INFO(DSI_CN),
+        [DSI_DP0] = PAD_INFO(DSI_DP0),
+        [DSI_DN0] = PAD_INFO(DSI_DN0),
+        [DSI_DP2] = PAD_INFO(DSI_DP2),
+        [DSI_DN2] = PAD_INFO(DSI_DN2),
+        [SENSOR0_PCLK] = PAD_INFO(SENSOR0_PCLK),
+        [CSI1_DN0] = PAD_INFO(CSI1_DN0),
+        [CSI1_DP0] = PAD_INFO(CSI1_DP0),
+        [CSI1_DN1] = PAD_INFO(CSI1_DN1),
+        [CSI1_DP1] = PAD_INFO(CSI1_DP1),
+        [CSI1_CN] = PAD_INFO(CSI1_CN),
+        [CSI1_CP] = PAD_INFO(CSI1_CP),
+        [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT),
+        [NAND0_D0] = PAD_INFO_PULLCTL(NAND0_D0),
+        [NAND0_D1] = PAD_INFO_PULLCTL(NAND0_D1),
+        [NAND0_D2] = PAD_INFO_PULLCTL(NAND0_D2),
+        [NAND0_D3] = PAD_INFO_PULLCTL(NAND0_D3),
+        [NAND0_D4] = PAD_INFO_PULLCTL(NAND0_D4),
+        [NAND0_D5] = PAD_INFO_PULLCTL(NAND0_D5),
+        [NAND0_D6] = PAD_INFO_PULLCTL(NAND0_D6),
+        [NAND0_D7] = PAD_INFO_PULLCTL(NAND0_D7),
+        [NAND0_DQS] = PAD_INFO_PULLCTL(NAND0_DQS),
+        [NAND0_DQSN] = PAD_INFO_PULLCTL(NAND0_DQSN),
+        [NAND0_ALE] = PAD_INFO(NAND0_ALE),
+        [NAND0_CLE] = PAD_INFO(NAND0_CLE),
+        [NAND0_CEB0] = PAD_INFO(NAND0_CEB0),
+        [NAND0_CEB1] = PAD_INFO(NAND0_CEB1),
+        [NAND0_CEB2] = PAD_INFO(NAND0_CEB2),
+        [NAND0_CEB3] = PAD_INFO(NAND0_CEB3),
+        [NAND1_D0] = PAD_INFO_PULLCTL(NAND1_D0),
+        [NAND1_D1] = PAD_INFO_PULLCTL(NAND1_D1),
+        [NAND1_D2] = PAD_INFO_PULLCTL(NAND1_D2),
+        [NAND1_D3] = PAD_INFO_PULLCTL(NAND1_D3),
+        [NAND1_D4] = PAD_INFO_PULLCTL(NAND1_D4),
+        [NAND1_D5] = PAD_INFO_PULLCTL(NAND1_D5),
+        [NAND1_D6] = PAD_INFO_PULLCTL(NAND1_D6),
+        [NAND1_D7] = PAD_INFO_PULLCTL(NAND1_D7),
+        [NAND1_DQS] = PAD_INFO_PULLCTL(NAND1_DQS),
+        [NAND1_DQSN] = PAD_INFO_PULLCTL(NAND1_DQSN),
+        [NAND1_ALE] = PAD_INFO(NAND1_ALE),
+        [NAND1_CLE] = PAD_INFO(NAND1_CLE),
+        [NAND1_CEB0] = PAD_INFO(NAND1_CEB0),
+        [NAND1_CEB1] = PAD_INFO(NAND1_CEB1),
+        [NAND1_CEB2] = PAD_INFO(NAND1_CEB2),
+        [NAND1_CEB3] = PAD_INFO(NAND1_CEB3),
+        [SGPIO0] = PAD_INFO(SGPIO0),
+        [SGPIO1] = PAD_INFO(SGPIO1),
+        [SGPIO2] = PAD_INFO_PULLCTL_ST(SGPIO2),
+        [SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
+};
+
+#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat)   \
+        [OWL_GPIO_PORT_##port] = {                              \
+                .offset = base,                                 \
+                .pins = count,                                  \
+                .outen = _outen,                                \
+                .inen = _inen,                                  \
+                .dat = _dat,                                    \
+        }
+
+static const struct owl_gpio_port s900_gpio_ports[] = {
+        OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8),
+        OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8),
+        OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8),
+        OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8),
+        OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8),
+        OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8)
+};
+
+static struct owl_pinctrl_soc_data s900_pinctrl_data = {
+        .padinfo = s900_padinfo,
+        .pins = (const struct pinctrl_pin_desc *)s900_pads,
+        .npins = ARRAY_SIZE(s900_pads),
+        .functions = s900_functions,
+        .nfunctions = ARRAY_SIZE(s900_functions),
+        .groups = s900_groups,
+        .ngroups = ARRAY_SIZE(s900_groups),
+        .ngpios = NUM_GPIOS,
+        .ports = s900_gpio_ports,
+        .nports = ARRAY_SIZE(s900_gpio_ports)
+};
+
+static int s900_pinctrl_probe(struct platform_device *pdev)
+{
+        return owl_pinctrl_probe(pdev, &s900_pinctrl_data);
+}
+
+static const struct of_device_id s900_pinctrl_of_match[] = {
+        { .compatible = "actions,s900-pinctrl", },
+        { }
+};
+
+static struct platform_driver s900_pinctrl_driver = {
+        .driver = {
+                .name = "pinctrl-s900",
+                .of_match_table = of_match_ptr(s900_pinctrl_of_match),
+        },
+        .probe = s900_pinctrl_probe,
+};
+
+static int __init s900_pinctrl_init(void)
+{
+        return platform_driver_register(&s900_pinctrl_driver);
+}
+arch_initcall(s900_pinctrl_init);
+
+static void __exit s900_pinctrl_exit(void)
+{
+        platform_driver_unregister(&s900_pinctrl_driver);
+}
+module_exit(s900_pinctrl_exit);
+
+MODULE_AUTHOR("Actions Semi Inc.");
+MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
+MODULE_DESCRIPTION("Actions Semi S900 SoC Pinctrl Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig
index e8c4e4f934a6..0f38d51f47c6 100644
--- a/drivers/pinctrl/bcm/Kconfig
+++ b/drivers/pinctrl/bcm/Kconfig
@@ -20,6 +20,7 @@ config PINCTRL_BCM2835
         bool
         select PINMUX
         select PINCONF
+        select GENERIC_PINCONF
         select GPIOLIB_IRQCHIP
 
 config PINCTRL_IPROC_GPIO
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index 785c366fd6d6..136ccaf53df8 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -36,11 +36,13 @@
 #include <linux/pinctrl/pinconf.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
 #include <linux/seq_file.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/types.h>
+#include <dt-bindings/pinctrl/bcm2835.h>
 
 #define MODULE_NAME "pinctrl-bcm2835"
 #define BCM2835_NUM_GPIOS 54
@@ -72,13 +74,9 @@
 
 enum bcm2835_pinconf_param {
         /* argument: bcm2835_pinconf_pull */
-        BCM2835_PINCONF_PARAM_PULL,
+        BCM2835_PINCONF_PARAM_PULL = (PIN_CONFIG_END + 1),
 };
 
-#define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
-#define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
-#define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
-
 struct bcm2835_pinctrl {
         struct device *dev;
         void __iomem *base;
@@ -213,14 +211,6 @@ static const char * const bcm2835_gpio_groups[] = {
 };
 
 enum bcm2835_fsel {
-        BCM2835_FSEL_GPIO_IN = 0,
-        BCM2835_FSEL_GPIO_OUT = 1,
-        BCM2835_FSEL_ALT0 = 4,
-        BCM2835_FSEL_ALT1 = 5,
-        BCM2835_FSEL_ALT2 = 6,
-        BCM2835_FSEL_ALT3 = 7,
-        BCM2835_FSEL_ALT4 = 3,
-        BCM2835_FSEL_ALT5 = 2,
         BCM2835_FSEL_COUNT = 8,
         BCM2835_FSEL_MASK = 0x7,
 };
@@ -714,7 +704,7 @@ static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
         configs = kzalloc(sizeof(*configs), GFP_KERNEL);
         if (!configs)
                 return -ENOMEM;
-        configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
+        configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
 
         map->type = PIN_MAP_TYPE_CONFIGS_PIN;
         map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
@@ -727,7 +717,7 @@ static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
 
 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
                 struct device_node *np,
-                struct pinctrl_map **map, unsigned *num_maps)
+                struct pinctrl_map **map, unsigned int *num_maps)
 {
         struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
         struct property *pins, *funcs, *pulls;
@@ -736,6 +726,12 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
         int i, err;
         u32 pin, func, pull;
 
+        /* Check for generic binding in this node */
+        err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
+        if (err || *num_maps)
+                return err;
+
+        /* Generic binding did not find anything continue with legacy parse */
         pins = of_find_property(np, "brcm,pins", NULL);
         if (!pins) {
                 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
@@ -917,37 +913,67 @@ static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
         return -ENOTSUPP;
 }
 
+static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
+                unsigned int pin, unsigned int arg)
+{
+        u32 off, bit;
+
+        off = GPIO_REG_OFFSET(pin);
+        bit = GPIO_REG_SHIFT(pin);
+
+        bcm2835_gpio_wr(pc, GPPUD, arg & 3);
+        /*
+         * BCM2835 datasheet say to wait 150 cycles, but not of what.
+         * But the VideoCore firmware delay for this operation
+         * based nearly on the same amount of VPU cycles and this clock
+         * runs at 250 MHz.
+         */
+        udelay(1);
+        bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
+        udelay(1);
+        bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
+}
+
 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
-                        unsigned pin, unsigned long *configs,
-                        unsigned num_configs)
+                        unsigned int pin, unsigned long *configs,
+                        unsigned int num_configs)
 {
         struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
-        enum bcm2835_pinconf_param param;
-        u16 arg;
-        u32 off, bit;
+        u32 param, arg;
         int i;
 
         for (i = 0; i < num_configs; i++) {
-                param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]);
-                arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]);
+                param = pinconf_to_config_param(configs[i]);
+                arg = pinconf_to_config_argument(configs[i]);
 
-                if (param != BCM2835_PINCONF_PARAM_PULL)
-                        return -EINVAL;
+                switch (param) {
+                /* Set legacy brcm,pull */
+                case BCM2835_PINCONF_PARAM_PULL:
+                        bcm2835_pull_config_set(pc, pin, arg);
+                        break;
 
-                off = GPIO_REG_OFFSET(pin);
-                bit = GPIO_REG_SHIFT(pin);
+                /* Set pull generic bindings */
+                case PIN_CONFIG_BIAS_DISABLE:
+                        bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
+                        break;
 
-                bcm2835_gpio_wr(pc, GPPUD, arg & 3);
-                /*
-                 * BCM2835 datasheet say to wait 150 cycles, but not of what.
-                 * But the VideoCore firmware delay for this operation
-                 * based nearly on the same amount of VPU cycles and this clock
-                 * runs at 250 MHz.
-                 */
-                udelay(1);
-                bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
-                udelay(1);
-                bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
+                case PIN_CONFIG_BIAS_PULL_DOWN:
+                        bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
+                        break;
+
+                case PIN_CONFIG_BIAS_PULL_UP:
+                        bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
+                        break;
+
+                /* Set output-high or output-low */
+                case PIN_CONFIG_OUTPUT:
+                        bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
+                        break;
+
+                default:
+                        return -EINVAL;
+
+                } /* switch param type */
         } /* for each config */
 
         return 0;
diff --git a/drivers/pinctrl/berlin/berlin-bg2.c b/drivers/pinctrl/berlin/berlin-bg2.c
index bf2e17d0d6e4..acbd413340e8 100644
--- a/drivers/pinctrl/berlin/berlin-bg2.c
+++ b/drivers/pinctrl/berlin/berlin-bg2.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Marvell Berlin BG2 pinctrl driver.
  *
  * Copyright (C) 2014 Marvell Technology Group Ltd.
  *
  * Antoine Ténart <antoine.tenart@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/init.h>
diff --git a/drivers/pinctrl/berlin/berlin-bg2cd.c b/drivers/pinctrl/berlin/berlin-bg2cd.c
index 9bee7bd1650f..c0f5d86d5d01 100644
--- a/drivers/pinctrl/berlin/berlin-bg2cd.c
+++ b/drivers/pinctrl/berlin/berlin-bg2cd.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Marvell Berlin BG2CD pinctrl driver.
  *
  * Copyright (C) 2014 Marvell Technology Group Ltd.
  *
  * Antoine Ténart <antoine.tenart@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/init.h>
diff --git a/drivers/pinctrl/berlin/berlin-bg2q.c b/drivers/pinctrl/berlin/berlin-bg2q.c
index eee6763f114c..20a3216ede07 100644
--- a/drivers/pinctrl/berlin/berlin-bg2q.c
+++ b/drivers/pinctrl/berlin/berlin-bg2q.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Marvell Berlin BG2Q pinctrl driver
  *
  * Copyright (C) 2014 Marvell Technology Group Ltd.
  *
  * Antoine Ténart <antoine.tenart@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/init.h>
diff --git a/drivers/pinctrl/berlin/berlin-bg4ct.c b/drivers/pinctrl/berlin/berlin-bg4ct.c
index e6740656ee7c..6a7fe929a68b 100644
--- a/drivers/pinctrl/berlin/berlin-bg4ct.c
+++ b/drivers/pinctrl/berlin/berlin-bg4ct.c
@@ -1,21 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Marvell berlin4ct pinctrl driver
  *
  * Copyright (C) 2015 Marvell Technology Group Ltd.
  *
  * Author: Jisheng Zhang <jszhang@marvell.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include <linux/init.h>
diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c
index cc3bd2efafe3..a620a8e8fa78 100644
--- a/drivers/pinctrl/berlin/berlin.c
+++ b/drivers/pinctrl/berlin/berlin.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Marvell Berlin SoC pinctrl core driver
  *
  * Copyright (C) 2014 Marvell Technology Group Ltd.
  *
  * Antoine Ténart <antoine.tenart@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #include <linux/io.h>
diff --git a/drivers/pinctrl/berlin/berlin.h b/drivers/pinctrl/berlin/berlin.h
index e9b30f95b03e..d7787754d1ed 100644
--- a/drivers/pinctrl/berlin/berlin.h
+++ b/drivers/pinctrl/berlin/berlin.h
@@ -1,13 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Marvell Berlin SoC pinctrl driver.
  *
  * Copyright (C) 2014 Marvell Technology Group Ltd.
  *
  * Antoine Ténart <antoine.tenart@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 #ifndef __PINCTRL_BERLIN_H
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 24aaddd760a0..e582a21cfe54 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -1,16 +1,11 @@
-/*
- * Core driver for the imx pin controller
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro Ltd.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Core driver for the imx pin controller
+//
+// Copyright (C) 2012 Freescale Semiconductor, Inc.
+// Copyright (C) 2012 Linaro Ltd.
+//
+// Author: Dong Aisheng <dong.aisheng@linaro.org>
 
 #include <linux/err.h>
 #include <linux/init.h>
@@ -371,7 +366,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
         unsigned long config;
 
         if (!pin_reg || pin_reg->conf_reg == -1) {
-                seq_printf(s, "N/A");
+                seq_puts(s, "N/A");
                 return;
         }
 
@@ -390,7 +385,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
         if (group > pctldev->num_groups)
                 return;
 
-        seq_printf(s, "\n");
+        seq_puts(s, "\n");
         grp = pinctrl_generic_get_group(pctldev, group);
         if (!grp)
                 return;
@@ -414,11 +409,18 @@ static const struct pinconf_ops imx_pinconf_ops = {
 };
 
 /*
- * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
- * 1 u32 CONFIG, so 24 types in total for each pin.
+ * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID
+ * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin.
+ * For generic_pinconf case, there's no extra u32 CONFIG.
+ *
+ * PIN_FUNC_ID format:
+ * Default:
+ *     <mux_reg conf_reg input_reg mux_mode input_val>
+ * SHARE_MUX_CONF_REG:
+ *     <mux_conf_reg input_reg mux_mode input_val>
  */
 #define FSL_PIN_SIZE 24
-#define SHARE_FSL_PIN_SIZE 20
+#define FSL_PIN_SHARE_SIZE 20
 
 static int imx_pinctrl_parse_groups(struct device_node *np,
                                     struct group_desc *grp,
@@ -434,7 +436,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
         dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name);
 
         if (info->flags & SHARE_MUX_CONF_REG)
-                pin_size = SHARE_FSL_PIN_SIZE;
+                pin_size = FSL_PIN_SHARE_SIZE;
         else
                 pin_size = FSL_PIN_SIZE;
 
@@ -617,7 +619,7 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
                 nfuncs = 1;
         } else {
                 nfuncs = of_get_child_count(np);
-                if (nfuncs <= 0) {
+                if (nfuncs == 0) {
                         dev_err(&pdev->dev, "no functions defined\n");
                         return -EINVAL;
                 }
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 038e8c0e5b96..4b8225ccb03a 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * IMX pinmux core definitions
  *
@@ -5,11 +6,6 @@
  * Copyright (C) 2012 Linaro Ltd.
  *
  * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
  */
 
 #ifndef __DRIVERS_PINCTRL_IMX_H
diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c
index a4e9f430d452..5af89de0ff02 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c
@@ -1,19 +1,14 @@
-/*
- * Core driver for the imx pin controller in imx1/21/27
- *
- * Copyright (C) 2013 Pengutronix
- * Author: Markus Pargmann <mpa@pengutronix.de>
- *
- * Based on pinctrl-imx.c:
- *      Author: Dong Aisheng <dong.aisheng@linaro.org>
- *      Copyright (C) 2012 Freescale Semiconductor, Inc.
- *      Copyright (C) 2012 Linaro Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Core driver for the imx pin controller in imx1/21/27
+//
+// Copyright (C) 2013 Pengutronix
+// Author: Markus Pargmann <mpa@pengutronix.de>
+//
+// Based on pinctrl-imx.c:
+//      Author: Dong Aisheng <dong.aisheng@linaro.org>
+//      Copyright (C) 2012 Freescale Semiconductor, Inc.
+//      Copyright (C) 2012 Linaro Ltd.
 
 #include <linux/bitops.h>
 #include <linux/err.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx1.c b/drivers/pinctrl/freescale/pinctrl-imx1.c
index fc8efc748734..faf770f13bc7 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx1.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx1.c
@@ -1,13 +1,8 @@
-/*
- * i.MX1 pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// i.MX1 pinctrl driver based on imx pinmux core
+//
+// Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 
 #include <linux/init.h>
 #include <linux/of.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx1.h b/drivers/pinctrl/freescale/pinctrl-imx1.h
index 174074308d6c..f1b9dabf7601 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx1.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx1.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * IMX pinmux core definitions
  *
@@ -5,11 +6,6 @@
  * Copyright (C) 2012 Linaro Ltd.
  *
  * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
  */
 
 #ifndef __DRIVERS_PINCTRL_IMX1_H
diff --git a/drivers/pinctrl/freescale/pinctrl-imx21.c b/drivers/pinctrl/freescale/pinctrl-imx21.c
index 73e26bc12f09..8a102275a053 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx21.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx21.c
@@ -1,13 +1,8 @@
-/*
- * i.MX21 pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// i.MX21 pinctrl driver based on imx pinmux core
+//
+// Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 
 #include <linux/init.h>
 #include <linux/of.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx23.c b/drivers/pinctrl/freescale/pinctrl-imx23.c
index c9405685971b..144020764a4b 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx23.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx23.c
@@ -1,16 +1,9 @@
-/*
- * Freescale i.MX23 pinctrl driver
- *
- * Author: Shawn Guo <shawn.guo@linaro.org>
- * Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Freescale i.MX23 pinctrl driver
+//
+// Author: Shawn Guo <shawn.guo@linaro.org>
+// Copyright 2012 Freescale Semiconductor, Inc.
 
 #include <linux/init.h>
 #include <linux/of_device.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c
index db6d9d1382f9..a899a398b6bb 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx25.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx25.c
@@ -1,19 +1,15 @@
-/*
- * imx25 pinctrl driver.
- *
- * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
- *
- * This driver was mostly copied from the imx51 pinctrl driver which has:
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro, Inc.
- *
- * Author: Denis Carikli <denis@eukrea.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// imx25 pinctrl driver.
+//
+// Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+//
+// This driver was mostly copied from the imx51 pinctrl driver which has:
+//
+// Copyright (C) 2012 Freescale Semiconductor, Inc.
+// Copyright (C) 2012 Linaro, Inc.
+//
+// Author: Denis Carikli <denis@eukrea.com>
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx27.c b/drivers/pinctrl/freescale/pinctrl-imx27.c
index e5992036fc6c..b4dfc1676cbc 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx27.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx27.c
@@ -1,15 +1,10 @@
-/*
- * imx27 pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2013 Pengutronix
- *
- * Author: Markus Pargmann <mpa@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// imx27 pinctrl driver based on imx pinmux core
+//
+// Copyright (C) 2013 Pengutronix
+//
+// Author: Markus Pargmann <mpa@pengutronix.de>
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx28.c b/drivers/pinctrl/freescale/pinctrl-imx28.c
index 87deb9ec938a..13730dd193f1 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx28.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx28.c
@@ -1,16 +1,9 @@
-/*
- * Freescale i.MX28 pinctrl driver
- *
- * Author: Shawn Guo <shawn.guo@linaro.org>
- * Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Freescale i.MX28 pinctrl driver
+//
+// Author: Shawn Guo <shawn.guo@linaro.org>
+// Copyright 2012 Freescale Semiconductor, Inc.
 
 #include <linux/init.h>
 #include <linux/of_device.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx35.c b/drivers/pinctrl/freescale/pinctrl-imx35.c
index 6927946ae4b5..871bb419e2f0 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx35.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx35.c
@@ -1,17 +1,13 @@
-/*
- * imx35 pinctrl driver.
- *
- * This driver was mostly copied from the imx51 pinctrl driver which has:
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro, Inc.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// imx35 pinctrl driver.
+//
+// This driver was mostly copied from the imx51 pinctrl driver which has:
+//
+// Copyright (C) 2012 Freescale Semiconductor, Inc.
+// Copyright (C) 2012 Linaro, Inc.
+//
+// Author: Dong Aisheng <dong.aisheng@linaro.org>
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx50.c b/drivers/pinctrl/freescale/pinctrl-imx50.c
index eb349b97290f..cf182c040e0b 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx50.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx50.c
@@ -1,15 +1,10 @@
-/*
- * imx50 pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// imx50 pinctrl driver based on imx pinmux core
+//
+// Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
+// Copyright (C) 2012 Freescale Semiconductor, Inc.
+// Copyright (C) 2012 Linaro, Inc.
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx51.c b/drivers/pinctrl/freescale/pinctrl-imx51.c
index 49acd991b5fb..e5c261e2bf1e 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx51.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx51.c
@@ -1,16 +1,11 @@
-/*
- * imx51 pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro, Inc.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// imx51 pinctrl driver based on imx pinmux core
+//
+// Copyright (C) 2012 Freescale Semiconductor, Inc.
+// Copyright (C) 2012 Linaro, Inc.
+//
+// Author: Dong Aisheng <dong.aisheng@linaro.org>
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx53.c b/drivers/pinctrl/freescale/pinctrl-imx53.c
index 6dd0c60eaea4..64c97aaf20c7 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx53.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx53.c
@@ -1,16 +1,11 @@
-/*
- * imx53 pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro, Inc.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// imx53 pinctrl driver based on imx pinmux core
+//
+// Copyright (C) 2012 Freescale Semiconductor, Inc.
+// Copyright (C) 2012 Linaro, Inc.
+//
+// Author: Dong Aisheng <dong.aisheng@linaro.org>
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6dl.c b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
index 91b85fc01de8..0858b4d79ed2 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6dl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
@@ -1,13 +1,9 @@
-/*
- * Freescale imx6dl pinctrl driver
- *
- * Author: Shawn Guo <shawn.guo@linaro.org>
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Freescale imx6dl pinctrl driver
+//
+// Author: Shawn Guo <shawn.guo@linaro.org>
+// Copyright (C) 2013 Freescale Semiconductor, Inc.
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6q.c b/drivers/pinctrl/freescale/pinctrl-imx6q.c
index 5f653d69d0f5..078ed6a331fd 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6q.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6q.c
@@ -1,16 +1,11 @@
-/*
- * imx6q pinctrl driver based on imx pinmux core
- *
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
- * Copyright (C) 2012 Linaro, Inc.
- *
- * Author: Dong Aisheng <dong.aisheng@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// imx6q pinctrl driver based on imx pinmux core
+//
+// Copyright (C) 2012 Freescale Semiconductor, Inc.
+// Copyright (C) 2012 Linaro, Inc.
+//
+// Author: Dong Aisheng <dong.aisheng@linaro.org>
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sl.c b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
index 1167dc273c04..9d2e6f987aa7 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6sl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
@@ -1,13 +1,9 @@
-/*
- * Freescale imx6sl pinctrl driver
- *
- * Author: Shawn Guo <shawn.guo@linaro.org>
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Freescale imx6sl pinctrl driver
+//
+// Author: Shawn Guo <shawn.guo@linaro.org>
+// Copyright (C) 2013 Freescale Semiconductor, Inc.
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sll.c b/drivers/pinctrl/freescale/pinctrl-imx6sll.c
index 0fbea9cf536d..0618f4d887fd 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6sll.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sll.c
@@ -1,9 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP.
- *
- */
+//
+// Copyright (C) 2016 Freescale Semiconductor, Inc.
+// Copyright 2017-2018 NXP.
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sx.c b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
index 15ea56c75f68..c7e2b1f94f01 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6sx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
@@ -1,13 +1,9 @@
-/*
- * Freescale imx6sx pinctrl driver
- *
- * Author: Anson Huang <Anson.Huang@freescale.com>
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Freescale imx6sx pinctrl driver
+//
+// Author: Anson Huang <Anson.Huang@freescale.com>
+// Copyright (C) 2014 Freescale Semiconductor, Inc.
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6ul.c b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
index 4580717ade19..7e37627c63f5 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6ul.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
@@ -1,13 +1,9 @@
-/*
- * Freescale imx6ul pinctrl driver
- *
- * Author: Anson Huang <Anson.Huang@freescale.com>
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Freescale imx6ul pinctrl driver
+//
+// Author: Anson Huang <Anson.Huang@freescale.com>
+// Copyright (C) 2015 Freescale Semiconductor, Inc.
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 0b0a2f33b06a..369d3e59fdd6 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -1,13 +1,9 @@
-/*
- * Freescale imx7d pinctrl driver
- *
- * Author: Anson Huang <Anson.Huang@freescale.com>
- * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Freescale imx7d pinctrl driver
+//
+// Author: Anson Huang <Anson.Huang@freescale.com>
+// Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
index f363e45fd246..f521bdb53f62 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
@@ -1,14 +1,9 @@
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright (C) 2017 NXP
- *
- * Author: Dong Aisheng <aisheng.dong@nxp.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2016 Freescale Semiconductor, Inc.
+// Copyright (C) 2017 NXP
+//
+// Author: Dong Aisheng <aisheng.dong@nxp.com>
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c
index 6852010a6d70..594f3e5ce9a9 100644
--- a/drivers/pinctrl/freescale/pinctrl-mxs.c
+++ b/drivers/pinctrl/freescale/pinctrl-mxs.c
@@ -1,13 +1,6 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Freescale Semiconductor, Inc.
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.h b/drivers/pinctrl/freescale/pinctrl-mxs.h
index 34dbf75208dc..ab9f834b03e6 100644
--- a/drivers/pinctrl/freescale/pinctrl-mxs.h
+++ b/drivers/pinctrl/freescale/pinctrl-mxs.h
@@ -1,12 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
  */
 
 #ifndef __PINCTRL_MXS_H
diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c
index c078f859ae15..37602b053ed2 100644
--- a/drivers/pinctrl/freescale/pinctrl-vf610.c
+++ b/drivers/pinctrl/freescale/pinctrl-vf610.c
@@ -1,13 +1,8 @@
-/*
- * VF610 pinctrl driver based on imx pinmux and pinconf core
- *
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// VF610 pinctrl driver based on imx pinmux and pinconf core
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
 
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index fee9225ca559..0f1019ae3993 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -1527,6 +1527,7 @@ static const struct dmi_system_id chv_no_valid_mask[] = {
                 .matches = {
                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
                         DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
+                        DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
                 },
         },
         {
@@ -1534,6 +1535,7 @@ static const struct dmi_system_id chv_no_valid_mask[] = {
                 .matches = {
                         DMI_MATCH(DMI_SYS_VENDOR, "HP"),
                         DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
+                        DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
                 },
         },
         {
@@ -1541,6 +1543,7 @@ static const struct dmi_system_id chv_no_valid_mask[] = {
                 .matches = {
                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
                         DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
+                        DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
                 },
         },
         {
@@ -1548,6 +1551,7 @@ static const struct dmi_system_id chv_no_valid_mask[] = {
                 .matches = {
                         DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
                         DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
+                        DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
                 },
         },
         {}
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 862c5dbc6977..9905dc672f6b 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -1,12 +1,18 @@
 menu "MediaTek pinctrl drivers"
         depends on ARCH_MEDIATEK || COMPILE_TEST
 
+config EINT_MTK
+        bool "MediaTek External Interrupt Support"
+        depends on PINCTRL_MTK || PINCTRL_MT7622 || COMPILE_TEST
+        select IRQ_DOMAIN
+
 config PINCTRL_MTK
         bool
         depends on OF
         select PINMUX
         select GENERIC_PINCONF
         select GPIOLIB
+        select EINT_MTK
         select OF_GPIO
 
 # For ARMv7 SoCs
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 7959e773533f..3de7156df345 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 # Core
+obj-$(CONFIG_EINT_MTK)          += mtk-eint.o
 obj-$(CONFIG_PINCTRL_MTK)       += pinctrl-mtk-common.o
 
 # SoC Drivers
diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c
new file mode 100644
index 000000000000..30f3316747e2
--- /dev/null
+++ b/drivers/pinctrl/mediatek/mtk-eint.c
@@ -0,0 +1,492 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2014-2018 MediaTek Inc.
+
+/*
+ * Library for MediaTek External Interrupt Support
+ *
+ * Author: Maoguang Meng <maoguang.meng@mediatek.com>
+ *         Sean Wang <sean.wang@mediatek.com>
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#include "mtk-eint.h"
+
+#define MTK_EINT_EDGE_SENSITIVE           0
+#define MTK_EINT_LEVEL_SENSITIVE          1
+#define MTK_EINT_DBNC_SET_DBNC_BITS       4
+#define MTK_EINT_DBNC_RST_BIT             (0x1 << 1)
+#define MTK_EINT_DBNC_SET_EN              (0x1 << 0)
+
+static const struct mtk_eint_regs mtk_generic_eint_regs = {
+        .stat      = 0x000,
+        .ack       = 0x040,
+        .mask      = 0x080,
+        .mask_set  = 0x0c0,
+        .mask_clr  = 0x100,
+        .sens      = 0x140,
+        .sens_set  = 0x180,
+        .sens_clr  = 0x1c0,
+        .soft      = 0x200,
+        .soft_set  = 0x240,
+        .soft_clr  = 0x280,
+        .pol       = 0x300,
+        .pol_set   = 0x340,
+        .pol_clr   = 0x380,
+        .dom_en    = 0x400,
+        .dbnc_ctrl = 0x500,
+        .dbnc_set  = 0x600,
+        .dbnc_clr  = 0x700,
+};
+
+static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
+                                         unsigned int eint_num,
+                                         unsigned int offset)
+{
+        unsigned int eint_base = 0;
+        void __iomem *reg;
+
+        if (eint_num >= eint->hw->ap_num)
+                eint_base = eint->hw->ap_num;
+
+        reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4;
+
+        return reg;
+}
+
+static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint,
+                                             unsigned int eint_num)
+{
+        unsigned int sens;
+        unsigned int bit = BIT(eint_num % 32);
+        void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
+                                                eint->regs->sens);
+
+        if (readl(reg) & bit)
+                sens = MTK_EINT_LEVEL_SENSITIVE;
+        else
+                sens = MTK_EINT_EDGE_SENSITIVE;
+
+        if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE)
+                return 1;
+        else
+                return 0;
+}
+
+static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq)
+{
+        int start_level, curr_level;
+        unsigned int reg_offset;
+        u32 mask = BIT(hwirq & 0x1f);
+        u32 port = (hwirq >> 5) & eint->hw->port_mask;
+        void __iomem *reg = eint->base + (port << 2);
+
+        curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq);
+
+        do {
+                start_level = curr_level;
+                if (start_level)
+                        reg_offset = eint->regs->pol_clr;
+                else
+                        reg_offset = eint->regs->pol_set;
+                writel(mask, reg + reg_offset);
+
+                curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl,
+                                                              hwirq);
+        } while (start_level != curr_level);
+
+        return start_level;
+}
+
+static void mtk_eint_mask(struct irq_data *d)
+{
+        struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+        u32 mask = BIT(d->hwirq & 0x1f);
+        void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
+                                                eint->regs->mask_set);
+
+        writel(mask, reg);
+}
+
+static void mtk_eint_unmask(struct irq_data *d)
+{
+        struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+        u32 mask = BIT(d->hwirq & 0x1f);
+        void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
+                                                eint->regs->mask_clr);
+
+        writel(mask, reg);
+
+        if (eint->dual_edge[d->hwirq])
+                mtk_eint_flip_edge(eint, d->hwirq);
+}
+
+static unsigned int mtk_eint_get_mask(struct mtk_eint *eint,
+                                      unsigned int eint_num)
+{
+        unsigned int bit = BIT(eint_num % 32);
+        void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
+                                                eint->regs->mask);
+
+        return !!(readl(reg) & bit);
+}
+
+static void mtk_eint_ack(struct irq_data *d)
+{
+        struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+        u32 mask = BIT(d->hwirq & 0x1f);
+        void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
+                                                eint->regs->ack);
+
+        writel(mask, reg);
+}
+
+static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
+{
+        struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+        u32 mask = BIT(d->hwirq & 0x1f);
+        void __iomem *reg;
+
+        if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
+            ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
+                dev_err(eint->dev,
+                        "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
+                        d->irq, d->hwirq, type);
+                return -EINVAL;
+        }
+
+        if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
+                eint->dual_edge[d->hwirq] = 1;
+        else
+                eint->dual_edge[d->hwirq] = 0;
+
+        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
+                reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);
+                writel(mask, reg);
+        } else {
+                reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set);
+                writel(mask, reg);
+        }
+
+        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
+                reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr);
+                writel(mask, reg);
+        } else {
+                reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set);
+                writel(mask, reg);
+        }
+
+        if (eint->dual_edge[d->hwirq])
+                mtk_eint_flip_edge(eint, d->hwirq);
+
+        return 0;
+}
+
+static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+        struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+        int shift = d->hwirq & 0x1f;
+        int reg = d->hwirq >> 5;
+
+        if (on)
+                eint->wake_mask[reg] |= BIT(shift);
+        else
+                eint->wake_mask[reg] &= ~BIT(shift);
+
+        return 0;
+}
+
+static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,
+                                     void __iomem *base, u32 *buf)
+{
+        int port;
+        void __iomem *reg;
+
+        for (port = 0; port < eint->hw->ports; port++) {
+                reg = base + (port << 2);
+                writel_relaxed(~buf[port], reg + eint->regs->mask_set);
+                writel_relaxed(buf[port], reg + eint->regs->mask_clr);
+        }
+}
+
+static void mtk_eint_chip_read_mask(const struct mtk_eint *eint,
+                                    void __iomem *base, u32 *buf)
+{
+        int port;
+        void __iomem *reg;
+
+        for (port = 0; port < eint->hw->ports; port++) {
+                reg = base + eint->regs->mask + (port << 2);
+                buf[port] = ~readl_relaxed(reg);
+                /* Mask is 0 when irq is enabled, and 1 when disabled. */
+        }
+}
+
+static int mtk_eint_irq_request_resources(struct irq_data *d)
+{
+        struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+        struct gpio_chip *gpio_c;
+        unsigned int gpio_n;
+        int err;
+
+        err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq,
+                                           &gpio_n, &gpio_c);
+        if (err < 0) {
+                dev_err(eint->dev, "Can not find pin\n");
+                return err;
+        }
+
+        err = gpiochip_lock_as_irq(gpio_c, gpio_n);
+        if (err < 0) {
+                dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n",
+                        irqd_to_hwirq(d));
+                return err;
+        }
+
+        err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq);
+        if (err < 0) {
+                dev_err(eint->dev, "Can not eint mode\n");
+                return err;
+        }
+
+        return 0;
+}
+
+static void mtk_eint_irq_release_resources(struct irq_data *d)
+{
+        struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
+        struct gpio_chip *gpio_c;
+        unsigned int gpio_n;
+
+        eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n,
+                                     &gpio_c);
+
+        gpiochip_unlock_as_irq(gpio_c, gpio_n);
+}
+
+static struct irq_chip mtk_eint_irq_chip = {
+        .name = "mt-eint",
+        .irq_disable = mtk_eint_mask,
+        .irq_mask = mtk_eint_mask,
+        .irq_unmask = mtk_eint_unmask,
+        .irq_ack = mtk_eint_ack,
+        .irq_set_type = mtk_eint_set_type,
+        .irq_set_wake = mtk_eint_irq_set_wake,
+        .irq_request_resources = mtk_eint_irq_request_resources,
+        .irq_release_resources = mtk_eint_irq_release_resources,
+};
+
+static unsigned int mtk_eint_hw_init(struct mtk_eint *eint)
+{
+        void __iomem *reg = eint->base + eint->regs->dom_en;
+        unsigned int i;
+
+        for (i = 0; i < eint->hw->ap_num; i += 32) {
+                writel(0xffffffff, reg);
+                reg += 4;
+        }
+
+        return 0;
+}
+
+static inline void
+mtk_eint_debounce_process(struct mtk_eint *eint, int index)
+{
+        unsigned int rst, ctrl_offset;
+        unsigned int bit, dbnc;
+
+        ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl;
+        dbnc = readl(eint->base + ctrl_offset);
+        bit = MTK_EINT_DBNC_SET_EN << ((index % 4) * 8);
+        if ((bit & dbnc) > 0) {
+                ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set;
+                rst = MTK_EINT_DBNC_RST_BIT << ((index % 4) * 8);
+                writel(rst, eint->base + ctrl_offset);
+        }
+}
+
+static void mtk_eint_irq_handler(struct irq_desc *desc)
+{
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct mtk_eint *eint = irq_desc_get_handler_data(desc);
+        unsigned int status, eint_num;
+        int offset, index, virq;
+        void __iomem *reg =  mtk_eint_get_offset(eint, 0, eint->regs->stat);
+        int dual_edge, start_level, curr_level;
+
+        chained_irq_enter(chip, desc);
+        for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32,
+             reg += 4) {
+                status = readl(reg);
+                while (status) {
+                        offset = __ffs(status);
+                        index = eint_num + offset;
+                        virq = irq_find_mapping(eint->domain, index);
+                        status &= ~BIT(offset);
+
+                        dual_edge = eint->dual_edge[index];
+                        if (dual_edge) {
+                                /*
+                                 * Clear soft-irq in case we raised it last
+                                 * time.
+                                 */
+                                writel(BIT(offset), reg - eint->regs->stat +
+                                       eint->regs->soft_clr);
+
+                                start_level =
+                                eint->gpio_xlate->get_gpio_state(eint->pctl,
+                                                                 index);
+                        }
+
+                        generic_handle_irq(virq);
+
+                        if (dual_edge) {
+                                curr_level = mtk_eint_flip_edge(eint, index);
+
+                                /*
+                                 * If level changed, we might lost one edge
+                                 * interrupt, raised it through soft-irq.
+                                 */
+                                if (start_level != curr_level)
+                                        writel(BIT(offset), reg -
+                                               eint->regs->stat +
+                                               eint->regs->soft_set);
+                        }
+
+                        if (index < eint->hw->db_cnt)
+                                mtk_eint_debounce_process(eint, index);
+                }
+        }
+        chained_irq_exit(chip, desc);
+}
+
+int mtk_eint_do_suspend(struct mtk_eint *eint)
+{
+        mtk_eint_chip_read_mask(eint, eint->base, eint->cur_mask);
+        mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);
+
+        return 0;
+}
+
+int mtk_eint_do_resume(struct mtk_eint *eint)
+{
+        mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask);
+
+        return 0;
+}
+
+int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num,
+                          unsigned int debounce)
+{
+        int virq, eint_offset;
+        unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
+                     dbnc;
+        static const unsigned int debounce_time[] = {500, 1000, 16000, 32000,
+                                                     64000, 128000, 256000};
+        struct irq_data *d;
+
+        virq = irq_find_mapping(eint->domain, eint_num);
+        eint_offset = (eint_num % 4) * 8;
+        d = irq_get_irq_data(virq);
+
+        set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set;
+        clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr;
+
+        if (!mtk_eint_can_en_debounce(eint, eint_num))
+                return -EINVAL;
+
+        dbnc = ARRAY_SIZE(debounce_time);
+        for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
+                if (debounce <= debounce_time[i]) {
+                        dbnc = i;
+                        break;
+                }
+        }
+
+        if (!mtk_eint_get_mask(eint, eint_num)) {
+                mtk_eint_mask(d);
+                unmask = 1;
+        } else {
+                unmask = 0;
+        }
+
+        clr_bit = 0xff << eint_offset;
+        writel(clr_bit, eint->base + clr_offset);
+
+        bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) <<
+                eint_offset;
+        rst = MTK_EINT_DBNC_RST_BIT << eint_offset;
+        writel(rst | bit, eint->base + set_offset);
+
+        /*
+         * Delay a while (more than 2T) to wait for hw debounce counter reset
+         * work correctly.
+         */
+        udelay(1);
+        if (unmask == 1)
+                mtk_eint_unmask(d);
+
+        return 0;
+}
+
+int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
+{
+        int irq;
+
+        irq = irq_find_mapping(eint->domain, eint_n);
+        if (!irq)
+                return -EINVAL;
+
+        return irq;
+}
+
+int mtk_eint_do_init(struct mtk_eint *eint)
+{
+        int i;
+
+        /* If clients don't assign a specific regs, let's use generic one */
+        if (!eint->regs)
+                eint->regs = &mtk_generic_eint_regs;
+
+        eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports,
+                                       sizeof(*eint->wake_mask), GFP_KERNEL);
+        if (!eint->wake_mask)
+                return -ENOMEM;
+
+        eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports,
+                                      sizeof(*eint->cur_mask), GFP_KERNEL);
+        if (!eint->cur_mask)
+                return -ENOMEM;
+
+        eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num,
+                                       sizeof(int), GFP_KERNEL);
+        if (!eint->dual_edge)
+                return -ENOMEM;
+
+        eint->domain = irq_domain_add_linear(eint->dev->of_node,
+                                             eint->hw->ap_num,
+                                             &irq_domain_simple_ops, NULL);
+        if (!eint->domain)
+                return -ENOMEM;
+
+        mtk_eint_hw_init(eint);
+        for (i = 0; i < eint->hw->ap_num; i++) {
+                int virq = irq_create_mapping(eint->domain, i);
+
+                irq_set_chip_and_handler(virq, &mtk_eint_irq_chip,
+                                         handle_level_irq);
+                irq_set_chip_data(virq, eint);
+        }
+
+        irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler,
+                                         eint);
+
+        return 0;
+}
diff --git a/drivers/pinctrl/mediatek/mtk-eint.h b/drivers/pinctrl/mediatek/mtk-eint.h
new file mode 100644
index 000000000000..c286a9b940f2
--- /dev/null
+++ b/drivers/pinctrl/mediatek/mtk-eint.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2014-2018 MediaTek Inc.
+ *
+ * Author: Maoguang Meng <maoguang.meng@mediatek.com>
+ *         Sean Wang <sean.wang@mediatek.com>
+ *
+ */
+#ifndef __MTK_EINT_H
+#define __MTK_EINT_H
+
+#include <linux/irqdomain.h>
+
+struct mtk_eint_regs {
+        unsigned int    stat;
+        unsigned int    ack;
+        unsigned int    mask;
+        unsigned int    mask_set;
+        unsigned int    mask_clr;
+        unsigned int    sens;
+        unsigned int    sens_set;
+        unsigned int    sens_clr;
+        unsigned int    soft;
+        unsigned int    soft_set;
+        unsigned int    soft_clr;
+        unsigned int    pol;
+        unsigned int    pol_set;
+        unsigned int    pol_clr;
+        unsigned int    dom_en;
+        unsigned int    dbnc_ctrl;
+        unsigned int    dbnc_set;
+        unsigned int    dbnc_clr;
+};
+
+struct mtk_eint_hw {
+        u8              port_mask;
+        u8              ports;
+        unsigned int    ap_num;
+        unsigned int    db_cnt;
+};
+
+struct mtk_eint;
+
+struct mtk_eint_xt {
+        int (*get_gpio_n)(void *data, unsigned long eint_n,
+                          unsigned int *gpio_n,
+                          struct gpio_chip **gpio_chip);
+        int (*get_gpio_state)(void *data, unsigned long eint_n);
+        int (*set_gpio_as_eint)(void *data, unsigned long eint_n);
+};
+
+struct mtk_eint {
+        struct device *dev;
+        void __iomem *base;
+        struct irq_domain *domain;
+        int irq;
+
+        int *dual_edge;
+        u32 *wake_mask;
+        u32 *cur_mask;
+
+        /* Used to fit into various EINT device */
+        const struct mtk_eint_hw *hw;
+        const struct mtk_eint_regs *regs;
+
+        /* Used to fit into various pinctrl device */
+        void *pctl;
+        const struct mtk_eint_xt *gpio_xlate;
+};
+
+#if IS_ENABLED(CONFIG_EINT_MTK)
+int mtk_eint_do_init(struct mtk_eint *eint);
+int mtk_eint_do_suspend(struct mtk_eint *eint);
+int mtk_eint_do_resume(struct mtk_eint *eint);
+int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n,
+                          unsigned int debounce);
+int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n);
+
+#else
+static inline int mtk_eint_do_init(struct mtk_eint *eint)
+{
+        return -EOPNOTSUPP;
+}
+
+static inline int mtk_eint_do_suspend(struct mtk_eint *eint)
+{
+        return -EOPNOTSUPP;
+}
+
+static inline int mtk_eint_do_resume(struct mtk_eint *eint)
+{
+        return -EOPNOTSUPP;
+}
+
+int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n,
+                          unsigned int debounce)
+{
+        return -EOPNOTSUPP;
+}
+
+int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
+{
+        return -EOPNOTSUPP;
+}
+#endif
+#endif /* __MTK_EINT_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
index f86f3b379607..e91c314f3b75 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
@@ -531,31 +531,12 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
         .port_shf = 4,
         .port_mask = 0x1f,
         .port_align = 4,
-        .eint_offsets = {
-                .name = "mt2701_eint",
-                .stat      = 0x000,
-                .ack       = 0x040,
-                .mask      = 0x080,
-                .mask_set  = 0x0c0,
-                .mask_clr  = 0x100,
-                .sens      = 0x140,
-                .sens_set  = 0x180,
-                .sens_clr  = 0x1c0,
-                .soft      = 0x200,
-                .soft_set  = 0x240,
-                .soft_clr  = 0x280,
-                .pol       = 0x300,
-                .pol_set   = 0x340,
-                .pol_clr   = 0x380,
-                .dom_en    = 0x400,
-                .dbnc_ctrl = 0x500,
-                .dbnc_set  = 0x600,
-                .dbnc_clr  = 0x700,
+        .eint_hw = {
                 .port_mask = 6,
                 .ports     = 6,
+                .ap_num    = 169,
+                .db_cnt    = 16,
         },
-        .ap_num = 169,
-        .db_cnt = 16,
 };
 
 static int mt2701_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
index 81e11f9e70f1..8398d55c01cb 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c
@@ -576,31 +576,12 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
         .port_shf = 4,
         .port_mask = 0xf,
         .port_align = 4,
-        .eint_offsets = {
-                .name = "mt2712_eint",
-                .stat      = 0x000,
-                .ack       = 0x040,
-                .mask      = 0x080,
-                .mask_set  = 0x0c0,
-                .mask_clr  = 0x100,
-                .sens      = 0x140,
-                .sens_set  = 0x180,
-                .sens_clr  = 0x1c0,
-                .soft      = 0x200,
-                .soft_set  = 0x240,
-                .soft_clr  = 0x280,
-                .pol       = 0x300,
-                .pol_set   = 0x340,
-                .pol_clr   = 0x380,
-                .dom_en    = 0x400,
-                .dbnc_ctrl = 0x500,
-                .dbnc_set  = 0x600,
-                .dbnc_clr  = 0x700,
+        .eint_hw = {
                 .port_mask = 0xf,
                 .ports     = 8,
+                .ap_num    = 229,
+                .db_cnt    = 40,
         },
-        .ap_num = 229,
-        .db_cnt = 40,
 };
 
 static int mt2712_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
index 06e8406c4440..ad6da1184c9f 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/mfd/syscon.h>
 #include <linux/of.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/pinctrl/pinctrl.h>
@@ -30,6 +31,7 @@
 #include "../core.h"
 #include "../pinconf.h"
 #include "../pinmux.h"
+#include "mtk-eint.h"
 
 #define PINCTRL_PINCTRL_DEV             KBUILD_MODNAME
 #define MTK_RANGE(_a)           { .range = (_a), .nranges = ARRAY_SIZE(_a), }
@@ -123,6 +125,8 @@ struct mtk_pin_soc {
         unsigned int                    ngrps;
         const struct function_desc      *funcs;
         unsigned int                    nfuncs;
+        const struct mtk_eint_regs      *eint_regs;
+        const struct mtk_eint_hw        *eint_hw;
 };
 
 struct mtk_pinctrl {
@@ -131,6 +135,7 @@ struct mtk_pinctrl {
         struct device                   *dev;
         struct gpio_chip                chip;
         const struct mtk_pin_soc        *soc;
+        struct mtk_eint                 *eint;
 };
 
 static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
@@ -913,6 +918,13 @@ static const struct pin_config_item mtk_conf_items[] = {
 };
 #endif
 
+static const struct mtk_eint_hw mt7622_eint_hw = {
+        .port_mask = 7,
+        .ports     = 7,
+        .ap_num    = ARRAY_SIZE(mt7622_pins),
+        .db_cnt    = 20,
+};
+
 static const struct mtk_pin_soc mt7622_data = {
         .reg_cal = mt7622_reg_cals,
         .pins = mt7622_pins,
@@ -921,6 +933,7 @@ static const struct mtk_pin_soc mt7622_data = {
         .ngrps = ARRAY_SIZE(mt7622_groups),
         .funcs = mt7622_functions,
         .nfuncs = ARRAY_SIZE(mt7622_functions),
+        .eint_hw = &mt7622_eint_hw,
 };
 
 static void mtk_w32(struct mtk_pinctrl *pctl, u32 reg, u32 val)
@@ -1441,6 +1454,32 @@ static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
         return pinctrl_gpio_direction_output(chip->base + gpio);
 }
 
+static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+        struct mtk_pinctrl *hw = gpiochip_get_data(chip);
+        unsigned long eint_n;
+
+        eint_n = offset;
+
+        return mtk_eint_find_irq(hw->eint, eint_n);
+}
+
+static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
+                               unsigned long config)
+{
+        struct mtk_pinctrl *hw = gpiochip_get_data(chip);
+        unsigned long eint_n;
+        u32 debounce;
+
+        if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
+                return -ENOTSUPP;
+
+        debounce = pinconf_to_config_argument(config);
+        eint_n = offset;
+
+        return mtk_eint_set_debounce(hw->eint, eint_n, debounce);
+}
+
 static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
 {
         struct gpio_chip *chip = &hw->chip;
@@ -1454,6 +1493,8 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
         chip->direction_output  = mtk_gpio_direction_output;
         chip->get               = mtk_gpio_get;
         chip->set               = mtk_gpio_set;
+        chip->to_irq            = mtk_gpio_to_irq,
+        chip->set_config        = mtk_gpio_set_config,
         chip->base              = -1;
         chip->ngpio             = hw->soc->npins;
         chip->of_node           = np;
@@ -1514,6 +1555,103 @@ static int mtk_build_functions(struct mtk_pinctrl *hw)
         return 0;
 }
 
+static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
+                             unsigned int *gpio_n,
+                             struct gpio_chip **gpio_chip)
+{
+        struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
+
+        *gpio_chip = &hw->chip;
+        *gpio_n = eint_n;
+
+        return 0;
+}
+
+static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
+{
+        struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
+        struct gpio_chip *gpio_chip;
+        unsigned int gpio_n;
+        int err;
+
+        err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
+        if (err)
+                return err;
+
+        return mtk_gpio_get(gpio_chip, gpio_n);
+}
+
+static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
+{
+        struct mtk_pinctrl *hw = (struct mtk_pinctrl *)data;
+        struct gpio_chip *gpio_chip;
+        unsigned int gpio_n;
+        int err;
+
+        err = mtk_xt_get_gpio_n(hw, eint_n, &gpio_n, &gpio_chip);
+        if (err)
+                return err;
+
+        err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_MODE,
+                               MTK_GPIO_MODE);
+        if (err)
+                return err;
+
+        err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_DIR, MTK_INPUT);
+        if (err)
+                return err;
+
+        err = mtk_hw_set_value(hw, gpio_n, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
+        if (err)
+                return err;
+
+        return 0;
+}
+
+static const struct mtk_eint_xt mtk_eint_xt = {
+        .get_gpio_n = mtk_xt_get_gpio_n,
+        .get_gpio_state = mtk_xt_get_gpio_state,
+        .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
+};
+
+static int
+mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        struct resource *res;
+
+        if (!IS_ENABLED(CONFIG_EINT_MTK))
+                return 0;
+
+        if (!of_property_read_bool(np, "interrupt-controller"))
+                return -ENODEV;
+
+        hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
+        if (!hw->eint)
+                return -ENOMEM;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint");
+        if (!res) {
+                dev_err(&pdev->dev, "Unable to get eint resource\n");
+                return -ENODEV;
+        }
+
+        hw->eint->base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(hw->eint->base))
+                return PTR_ERR(hw->eint->base);
+
+        hw->eint->irq = irq_of_parse_and_map(np, 0);
+        if (!hw->eint->irq)
+                return -EINVAL;
+
+        hw->eint->dev = &pdev->dev;
+        hw->eint->hw = hw->soc->eint_hw;
+        hw->eint->pctl = hw;
+        hw->eint->gpio_xlate = &mtk_eint_xt;
+
+        return mtk_eint_do_init(hw->eint);
+}
+
 static const struct of_device_id mtk_pinctrl_of_match[] = {
         { .compatible = "mediatek,mt7622-pinctrl", .data = &mt7622_data},
         { }
@@ -1577,6 +1715,11 @@ static int mtk_pinctrl_probe(struct platform_device *pdev)
                 return err;
         }
 
+        err = mtk_build_eint(hw, pdev);
+        if (err)
+                dev_warn(&pdev->dev,
+                         "Failed to add EINT, but pinctrl still can work\n");
+
         platform_set_drvdata(pdev, hw);
 
         return 0;
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c
index d76491574841..2e4cc9257e00 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c
@@ -300,31 +300,12 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
         .port_shf = 4,
         .port_mask = 0xf,
         .port_align = 4,
-        .eint_offsets = {
-                .name = "mt8127_eint",
-                .stat      = 0x000,
-                .ack       = 0x040,
-                .mask      = 0x080,
-                .mask_set  = 0x0c0,
-                .mask_clr  = 0x100,
-                .sens      = 0x140,
-                .sens_set  = 0x180,
-                .sens_clr  = 0x1c0,
-                .soft      = 0x200,
-                .soft_set  = 0x240,
-                .soft_clr  = 0x280,
-                .pol       = 0x300,
-                .pol_set   = 0x340,
-                .pol_clr   = 0x380,
-                .dom_en    = 0x400,
-                .dbnc_ctrl = 0x500,
-                .dbnc_set  = 0x600,
-                .dbnc_clr  = 0x700,
+        .eint_hw = {
                 .port_mask = 7,
                 .ports     = 6,
+                .ap_num    = 143,
+                .db_cnt    = 16,
         },
-        .ap_num = 143,
-        .db_cnt = 16,
 };
 
 static int mt8127_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
index d8c645f16f21..7f5edfaffdc5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
@@ -313,31 +313,12 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
         .port_shf = 4,
         .port_mask = 0xf,
         .port_align = 4,
-        .eint_offsets = {
-                .name = "mt8135_eint",
-                .stat      = 0x000,
-                .ack       = 0x040,
-                .mask      = 0x080,
-                .mask_set  = 0x0c0,
-                .mask_clr  = 0x100,
-                .sens      = 0x140,
-                .sens_set  = 0x180,
-                .sens_clr  = 0x1c0,
-                .soft      = 0x200,
-                .soft_set  = 0x240,
-                .soft_clr  = 0x280,
-                .pol       = 0x300,
-                .pol_set   = 0x340,
-                .pol_clr   = 0x380,
-                .dom_en    = 0x400,
-                .dbnc_ctrl = 0x500,
-                .dbnc_set  = 0x600,
-                .dbnc_clr  = 0x700,
+        .eint_hw = {
                 .port_mask = 7,
                 .ports     = 6,
+                .ap_num    = 192,
+                .db_cnt    = 16,
         },
-        .ap_num = 192,
-        .db_cnt = 16,
 };
 
 static int mt8135_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
index 8bfd427b9135..c449c9a043da 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
@@ -340,31 +340,12 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
         .port_shf = 4,
         .port_mask = 0xf,
         .port_align = 4,
-        .eint_offsets = {
-                .name = "mt8173_eint",
-                .stat      = 0x000,
-                .ack       = 0x040,
-                .mask      = 0x080,
-                .mask_set  = 0x0c0,
-                .mask_clr  = 0x100,
-                .sens      = 0x140,
-                .sens_set  = 0x180,
-                .sens_clr  = 0x1c0,
-                .soft      = 0x200,
-                .soft_set  = 0x240,
-                .soft_clr  = 0x280,
-                .pol       = 0x300,
-                .pol_set   = 0x340,
-                .pol_clr   = 0x380,
-                .dom_en    = 0x400,
-                .dbnc_ctrl = 0x500,
-                .dbnc_set  = 0x600,
-                .dbnc_clr  = 0x700,
+        .eint_hw = {
                 .port_mask = 7,
                 .ports     = 6,
+                .ap_num    = 224,
+                .db_cnt    = 16,
         },
-        .ap_num = 224,
-        .db_cnt = 16,
 };
 
 static int mt8173_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index c3975a04d1cd..b3799695d8db 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -38,6 +38,7 @@
 #include "../core.h"
 #include "../pinconf.h"
 #include "../pinctrl-utils.h"
+#include "mtk-eint.h"
 #include "pinctrl-mtk-common.h"
 
 #define MAX_GPIO_MODE_PER_REG 5
@@ -831,243 +832,38 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
 
 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
-        const struct mtk_desc_pin *pin;
         struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
-        int irq;
-
-        pin = pctl->devdata->pins + offset;
-        if (pin->eint.eintnum == NO_EINT_SUPPORT)
-                return -EINVAL;
-
-        irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
-        if (!irq)
-                return -EINVAL;
-
-        return irq;
-}
-
-static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
-{
-        struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
-        const struct mtk_desc_pin *pin;
-        int ret;
-
-        pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
-
-        if (!pin) {
-                dev_err(pctl->dev, "Can not find pin\n");
-                return -EINVAL;
-        }
-
-        ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
-        if (ret) {
-                dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
-                        irqd_to_hwirq(d));
-                return ret;
-        }
-
-        /* set mux to INT mode */
-        mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
-        /* set gpio direction to input */
-        mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number, true);
-        /* set input-enable */
-        mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1, PIN_CONFIG_INPUT_ENABLE);
-
-        return 0;
-}
-
-static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
-{
-        struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
-        const struct mtk_desc_pin *pin;
-
-        pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
-
-        if (!pin) {
-                dev_err(pctl->dev, "Can not find pin\n");
-                return;
-        }
-
-        gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
-}
-
-static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
-        unsigned int eint_num, unsigned int offset)
-{
-        unsigned int eint_base = 0;
-        void __iomem *reg;
-
-        if (eint_num >= pctl->devdata->ap_num)
-                eint_base = pctl->devdata->ap_num;
-
-        reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
-
-        return reg;
-}
-
-/*
- * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
- * @eint_num: the EINT number to setmtk_pinctrl
- */
-static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
-        unsigned int eint_num)
-{
-        unsigned int sens;
-        unsigned int bit = BIT(eint_num % 32);
-        const struct mtk_eint_offsets *eint_offsets =
-                &pctl->devdata->eint_offsets;
-
-        void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
-                        eint_offsets->sens);
-
-        if (readl(reg) & bit)
-                sens = MT_LEVEL_SENSITIVE;
-        else
-                sens = MT_EDGE_SENSITIVE;
-
-        if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
-                return 1;
-        else
-                return 0;
-}
-
-/*
- * mtk_eint_get_mask: To get the eint mask
- * @eint_num: the EINT number to get
- */
-static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
-        unsigned int eint_num)
-{
-        unsigned int bit = BIT(eint_num % 32);
-        const struct mtk_eint_offsets *eint_offsets =
-                &pctl->devdata->eint_offsets;
-
-        void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
-                        eint_offsets->mask);
-
-        return !!(readl(reg) & bit);
-}
-
-static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
-{
-        int start_level, curr_level;
-        unsigned int reg_offset;
-        const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
-        u32 mask = BIT(hwirq & 0x1f);
-        u32 port = (hwirq >> 5) & eint_offsets->port_mask;
-        void __iomem *reg = pctl->eint_reg_base + (port << 2);
         const struct mtk_desc_pin *pin;
-
-        pin = mtk_find_pin_by_eint_num(pctl, hwirq);
-        curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
-        do {
-                start_level = curr_level;
-                if (start_level)
-                        reg_offset = eint_offsets->pol_clr;
-                else
-                        reg_offset = eint_offsets->pol_set;
-                writel(mask, reg + reg_offset);
-
-                curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
-        } while (start_level != curr_level);
-
-        return start_level;
-}
-
-static void mtk_eint_mask(struct irq_data *d)
-{
-        struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
-        const struct mtk_eint_offsets *eint_offsets =
-                        &pctl->devdata->eint_offsets;
-        u32 mask = BIT(d->hwirq & 0x1f);
-        void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
-                        eint_offsets->mask_set);
-
-        writel(mask, reg);
-}
-
-static void mtk_eint_unmask(struct irq_data *d)
-{
-        struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
-        const struct mtk_eint_offsets *eint_offsets =
-                &pctl->devdata->eint_offsets;
-        u32 mask = BIT(d->hwirq & 0x1f);
-        void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
-                        eint_offsets->mask_clr);
-
-        writel(mask, reg);
-
-        if (pctl->eint_dual_edges[d->hwirq])
-                mtk_eint_flip_edge(pctl, d->hwirq);
-}
-
-static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
-        unsigned debounce)
-{
-        struct mtk_pinctrl *pctl = dev_get_drvdata(chip->parent);
-        int eint_num, virq, eint_offset;
-        unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
-        static const unsigned int debounce_time[] = {500, 1000, 16000, 32000, 64000,
-                                                128000, 256000};
-        const struct mtk_desc_pin *pin;
-        struct irq_data *d;
+        unsigned long eint_n;
 
         pin = pctl->devdata->pins + offset;
         if (pin->eint.eintnum == NO_EINT_SUPPORT)
                 return -EINVAL;
 
-        eint_num = pin->eint.eintnum;
-        virq = irq_find_mapping(pctl->domain, eint_num);
-        eint_offset = (eint_num % 4) * 8;
-        d = irq_get_irq_data(virq);
+        eint_n = pin->eint.eintnum;
 
-        set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
-        clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
-        if (!mtk_eint_can_en_debounce(pctl, eint_num))
-                return -ENOSYS;
-
-        dbnc = ARRAY_SIZE(debounce_time);
-        for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
-                if (debounce <= debounce_time[i]) {
-                        dbnc = i;
-                        break;
-                }
-        }
-
-        if (!mtk_eint_get_mask(pctl, eint_num)) {
-                mtk_eint_mask(d);
-                unmask = 1;
-        } else {
-                unmask = 0;
-        }
-
-        clr_bit = 0xff << eint_offset;
-        writel(clr_bit, pctl->eint_reg_base + clr_offset);
-
-        bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
-                eint_offset;
-        rst = EINT_DBNC_RST_BIT << eint_offset;
-        writel(rst | bit, pctl->eint_reg_base + set_offset);
-
-        /* Delay a while (more than 2T) to wait for hw debounce counter reset
-        work correctly */
-        udelay(1);
-        if (unmask == 1)
-                mtk_eint_unmask(d);
-
-        return 0;
+        return mtk_eint_find_irq(pctl->eint, eint_n);
 }
 
 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned offset,
                                unsigned long config)
 {
+        struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
+        const struct mtk_desc_pin *pin;
+        unsigned long eint_n;
         u32 debounce;
 
         if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
                 return -ENOTSUPP;
 
+        pin = pctl->devdata->pins + offset;
+        if (pin->eint.eintnum == NO_EINT_SUPPORT)
+                return -EINVAL;
+
         debounce = pinconf_to_config_argument(config);
-        return mtk_gpio_set_debounce(chip, offset, debounce);
+        eint_n = pin->eint.eintnum;
+
+        return mtk_eint_set_debounce(pctl->eint, eint_n, debounce);
 }
 
 static const struct gpio_chip mtk_gpio_chip = {
@@ -1084,117 +880,18 @@ static const struct gpio_chip mtk_gpio_chip = {
         .of_gpio_n_cells        = 2,
 };
 
-static int mtk_eint_set_type(struct irq_data *d,
-                                      unsigned int type)
-{
-        struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
-        const struct mtk_eint_offsets *eint_offsets =
-                &pctl->devdata->eint_offsets;
-        u32 mask = BIT(d->hwirq & 0x1f);
-        void __iomem *reg;
-
-        if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
-                ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
-                dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
-                        d->irq, d->hwirq, type);
-                return -EINVAL;
-        }
-
-        if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
-                pctl->eint_dual_edges[d->hwirq] = 1;
-        else
-                pctl->eint_dual_edges[d->hwirq] = 0;
-
-        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
-                reg = mtk_eint_get_offset(pctl, d->hwirq,
-                        eint_offsets->pol_clr);
-                writel(mask, reg);
-        } else {
-                reg = mtk_eint_get_offset(pctl, d->hwirq,
-                        eint_offsets->pol_set);
-                writel(mask, reg);
-        }
-
-        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                reg = mtk_eint_get_offset(pctl, d->hwirq,
-                        eint_offsets->sens_clr);
-                writel(mask, reg);
-        } else {
-                reg = mtk_eint_get_offset(pctl, d->hwirq,
-                        eint_offsets->sens_set);
-                writel(mask, reg);
-        }
-
-        if (pctl->eint_dual_edges[d->hwirq])
-                mtk_eint_flip_edge(pctl, d->hwirq);
-
-        return 0;
-}
-
-static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
-{
-        struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
-        int shift = d->hwirq & 0x1f;
-        int reg = d->hwirq >> 5;
-
-        if (on)
-                pctl->wake_mask[reg] |= BIT(shift);
-        else
-                pctl->wake_mask[reg] &= ~BIT(shift);
-
-        return 0;
-}
-
-static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip,
-                void __iomem *eint_reg_base, u32 *buf)
-{
-        int port;
-        void __iomem *reg;
-
-        for (port = 0; port < chip->ports; port++) {
-                reg = eint_reg_base + (port << 2);
-                writel_relaxed(~buf[port], reg + chip->mask_set);
-                writel_relaxed(buf[port], reg + chip->mask_clr);
-        }
-}
-
-static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip,
-                void __iomem *eint_reg_base, u32 *buf)
-{
-        int port;
-        void __iomem *reg;
-
-        for (port = 0; port < chip->ports; port++) {
-                reg = eint_reg_base + chip->mask + (port << 2);
-                buf[port] = ~readl_relaxed(reg);
-                /* Mask is 0 when irq is enabled, and 1 when disabled. */
-        }
-}
-
 static int mtk_eint_suspend(struct device *device)
 {
-        void __iomem *reg;
         struct mtk_pinctrl *pctl = dev_get_drvdata(device);
-        const struct mtk_eint_offsets *eint_offsets =
-                        &pctl->devdata->eint_offsets;
-
-        reg = pctl->eint_reg_base;
-        mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask);
-        mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask);
 
-        return 0;
+        return mtk_eint_do_suspend(pctl->eint);
 }
 
 static int mtk_eint_resume(struct device *device)
 {
         struct mtk_pinctrl *pctl = dev_get_drvdata(device);
-        const struct mtk_eint_offsets *eint_offsets =
-                        &pctl->devdata->eint_offsets;
-
-        mtk_eint_chip_write_mask(eint_offsets,
-                        pctl->eint_reg_base, pctl->cur_mask);
 
-        return 0;
+        return mtk_eint_do_resume(pctl->eint);
 }
 
 const struct dev_pm_ops mtk_eint_pm_ops = {
@@ -1202,117 +899,6 @@ const struct dev_pm_ops mtk_eint_pm_ops = {
         .resume_noirq = mtk_eint_resume,
 };
 
-static void mtk_eint_ack(struct irq_data *d)
-{
-        struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
-        const struct mtk_eint_offsets *eint_offsets =
-                &pctl->devdata->eint_offsets;
-        u32 mask = BIT(d->hwirq & 0x1f);
-        void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
-                        eint_offsets->ack);
-
-        writel(mask, reg);
-}
-
-static struct irq_chip mtk_pinctrl_irq_chip = {
-        .name = "mt-eint",
-        .irq_disable = mtk_eint_mask,
-        .irq_mask = mtk_eint_mask,
-        .irq_unmask = mtk_eint_unmask,
-        .irq_ack = mtk_eint_ack,
-        .irq_set_type = mtk_eint_set_type,
-        .irq_set_wake = mtk_eint_irq_set_wake,
-        .irq_request_resources = mtk_pinctrl_irq_request_resources,
-        .irq_release_resources = mtk_pinctrl_irq_release_resources,
-};
-
-static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
-{
-        const struct mtk_eint_offsets *eint_offsets =
-                &pctl->devdata->eint_offsets;
-        void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
-        unsigned int i;
-
-        for (i = 0; i < pctl->devdata->ap_num; i += 32) {
-                writel(0xffffffff, reg);
-                reg += 4;
-        }
-        return 0;
-}
-
-static inline void
-mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
-{
-        unsigned int rst, ctrl_offset;
-        unsigned int bit, dbnc;
-        const struct mtk_eint_offsets *eint_offsets =
-                &pctl->devdata->eint_offsets;
-
-        ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
-        dbnc = readl(pctl->eint_reg_base + ctrl_offset);
-        bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
-        if ((bit & dbnc) > 0) {
-                ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
-                rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
-                writel(rst, pctl->eint_reg_base + ctrl_offset);
-        }
-}
-
-static void mtk_eint_irq_handler(struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-        struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc);
-        unsigned int status, eint_num;
-        int offset, index, virq;
-        const struct mtk_eint_offsets *eint_offsets =
-                &pctl->devdata->eint_offsets;
-        void __iomem *reg =  mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
-        int dual_edges, start_level, curr_level;
-        const struct mtk_desc_pin *pin;
-
-        chained_irq_enter(chip, desc);
-        for (eint_num = 0;
-             eint_num < pctl->devdata->ap_num;
-             eint_num += 32, reg += 4) {
-                status = readl(reg);
-                while (status) {
-                        offset = __ffs(status);
-                        index = eint_num + offset;
-                        virq = irq_find_mapping(pctl->domain, index);
-                        status &= ~BIT(offset);
-
-                        dual_edges = pctl->eint_dual_edges[index];
-                        if (dual_edges) {
-                                /* Clear soft-irq in case we raised it
-                                   last time */
-                                writel(BIT(offset), reg - eint_offsets->stat +
-                                        eint_offsets->soft_clr);
-
-                                pin = mtk_find_pin_by_eint_num(pctl, index);
-                                start_level = mtk_gpio_get(pctl->chip,
-                                                           pin->pin.number);
-                        }
-
-                        generic_handle_irq(virq);
-
-                        if (dual_edges) {
-                                curr_level = mtk_eint_flip_edge(pctl, index);
-
-                                /* If level changed, we might lost one edge
-                                   interrupt, raised it through soft-irq */
-                                if (start_level != curr_level)
-                                        writel(BIT(offset), reg -
-                                                eint_offsets->stat +
-                                                eint_offsets->soft_set);
-                        }
-
-                        if (index < pctl->devdata->db_cnt)
-                                mtk_eint_debounce_process(pctl , index);
-                }
-        }
-        chained_irq_exit(chip, desc);
-}
-
 static int mtk_pctrl_build_state(struct platform_device *pdev)
 {
         struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
@@ -1345,6 +931,101 @@ static int mtk_pctrl_build_state(struct platform_device *pdev)
         return 0;
 }
 
+static int
+mtk_xt_get_gpio_n(void *data, unsigned long eint_n, unsigned int *gpio_n,
+                  struct gpio_chip **gpio_chip)
+{
+        struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
+        const struct mtk_desc_pin *pin;
+
+        pin = mtk_find_pin_by_eint_num(pctl, eint_n);
+        if (!pin)
+                return -EINVAL;
+
+        *gpio_chip = pctl->chip;
+        *gpio_n = pin->pin.number;
+
+        return 0;
+}
+
+static int mtk_xt_get_gpio_state(void *data, unsigned long eint_n)
+{
+        struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
+        const struct mtk_desc_pin *pin;
+
+        pin = mtk_find_pin_by_eint_num(pctl, eint_n);
+        if (!pin)
+                return -EINVAL;
+
+        return mtk_gpio_get(pctl->chip, pin->pin.number);
+}
+
+static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
+{
+        struct mtk_pinctrl *pctl = (struct mtk_pinctrl *)data;
+        const struct mtk_desc_pin *pin;
+
+        pin = mtk_find_pin_by_eint_num(pctl, eint_n);
+        if (!pin)
+                return -EINVAL;
+
+        /* set mux to INT mode */
+        mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
+        /* set gpio direction to input */
+        mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number,
+                                   true);
+        /* set input-enable */
+        mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1,
+                              PIN_CONFIG_INPUT_ENABLE);
+
+        return 0;
+}
+
+static const struct mtk_eint_xt mtk_eint_xt = {
+        .get_gpio_n = mtk_xt_get_gpio_n,
+        .get_gpio_state = mtk_xt_get_gpio_state,
+        .set_gpio_as_eint = mtk_xt_set_gpio_as_eint,
+};
+
+static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        struct resource *res;
+
+        if (!of_property_read_bool(np, "interrupt-controller"))
+                return -ENODEV;
+
+        pctl->eint = devm_kzalloc(pctl->dev, sizeof(*pctl->eint), GFP_KERNEL);
+        if (!pctl->eint)
+                return -ENOMEM;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "Unable to get eint resource\n");
+                return -ENODEV;
+        }
+
+        pctl->eint->base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(pctl->eint->base))
+                return PTR_ERR(pctl->eint->base);
+
+        pctl->eint->irq = irq_of_parse_and_map(np, 0);
+        if (!pctl->eint->irq)
+                return -EINVAL;
+
+        pctl->eint->dev = &pdev->dev;
+        /*
+         * If pctl->eint->regs == NULL, it would fall back into using a generic
+         * register map in mtk_eint_do_init calls.
+         */
+        pctl->eint->regs = pctl->devdata->eint_regs;
+        pctl->eint->hw = &pctl->devdata->eint_hw;
+        pctl->eint->pctl = pctl;
+        pctl->eint->gpio_xlate = &mtk_eint_xt;
+
+        return mtk_eint_do_init(pctl->eint);
+}
+
 int mtk_pctrl_init(struct platform_device *pdev,
                 const struct mtk_pinctrl_devdata *data,
                 struct regmap *regmap)
@@ -1353,8 +1034,7 @@ int mtk_pctrl_init(struct platform_device *pdev,
         struct mtk_pinctrl *pctl;
         struct device_node *np = pdev->dev.of_node, *node;
         struct property *prop;
-        struct resource *res;
-        int i, ret, irq, ports_buf;
+        int ret, i;
 
         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
         if (!pctl)
@@ -1441,70 +1121,10 @@ int mtk_pctrl_init(struct platform_device *pdev,
                 goto chip_error;
         }
 
-        if (!of_property_read_bool(np, "interrupt-controller"))
-                return 0;
-
-        /* Get EINT register base from dts. */
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
-                ret = -EINVAL;
-                goto chip_error;
-        }
-
-        pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
-        if (IS_ERR(pctl->eint_reg_base)) {
-                ret = -EINVAL;
-                goto chip_error;
-        }
-
-        ports_buf = pctl->devdata->eint_offsets.ports;
-        pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf,
-                                        sizeof(*pctl->wake_mask), GFP_KERNEL);
-        if (!pctl->wake_mask) {
-                ret = -ENOMEM;
-                goto chip_error;
-        }
-
-        pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf,
-                                        sizeof(*pctl->cur_mask), GFP_KERNEL);
-        if (!pctl->cur_mask) {
-                ret = -ENOMEM;
-                goto chip_error;
-        }
-
-        pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
-                                             sizeof(int), GFP_KERNEL);
-        if (!pctl->eint_dual_edges) {
-                ret = -ENOMEM;
-                goto chip_error;
-        }
-
-        irq = irq_of_parse_and_map(np, 0);
-        if (!irq) {
-                dev_err(&pdev->dev, "couldn't parse and map irq\n");
-                ret = -EINVAL;
-                goto chip_error;
-        }
-
-        pctl->domain = irq_domain_add_linear(np,
-                pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
-        if (!pctl->domain) {
-                dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
-                ret = -ENOMEM;
+        ret = mtk_eint_init(pctl, pdev);
+        if (ret)
                 goto chip_error;
-        }
-
-        mtk_eint_init(pctl);
-        for (i = 0; i < pctl->devdata->ap_num; i++) {
-                int virq = irq_create_mapping(pctl->domain, i);
-
-                irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
-                        handle_level_irq);
-                irq_set_chip_data(virq, pctl);
-        }
 
-        irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
         return 0;
 
 chip_error:
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 8543bc478a1e..bf13eb0a68d6 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -19,6 +19,8 @@
 #include <linux/regmap.h>
 #include <linux/pinctrl/pinconf-generic.h>
 
+#include "mtk-eint.h"
+
 #define NO_EINT_SUPPORT    255
 #define MT_EDGE_SENSITIVE           0
 #define MT_LEVEL_SENSITIVE          1
@@ -258,9 +260,8 @@ struct mtk_pinctrl_devdata {
         unsigned char  port_shf;
         unsigned char  port_mask;
         unsigned char  port_align;
-        struct mtk_eint_offsets eint_offsets;
-        unsigned int    ap_num;
-        unsigned int    db_cnt;
+        struct mtk_eint_hw eint_hw;
+        struct mtk_eint_regs *eint_regs;
 };
 
 struct mtk_pinctrl {
@@ -274,11 +275,7 @@ struct mtk_pinctrl {
         const char          **grp_names;
         struct pinctrl_dev      *pctl_dev;
         const struct mtk_pinctrl_devdata  *devdata;
-        void __iomem            *eint_reg_base;
-        struct irq_domain       *domain;
-        int                     *eint_dual_edges;
-        u32 *wake_mask;
-        u32 *cur_mask;
+        struct mtk_eint *eint;
 };
 
 int mtk_pctrl_init(struct platform_device *pdev,
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c
index 99a6ceac8e53..46a0918bd284 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c
@@ -312,6 +312,47 @@ static const unsigned int pdm_din1_pins[] = {GPIOA_16};
 static const unsigned int pdm_din2_pins[] = {GPIOA_17};
 static const unsigned int pdm_din3_pins[] = {GPIOA_18};
 
+/* mclk */
+static const unsigned int mclk_c_pins[] = {GPIOA_0};
+static const unsigned int mclk_b_pins[] = {GPIOA_1};
+
+/* tdm */
+static const unsigned int tdma_sclk_pins[] = {GPIOX_12};
+static const unsigned int tdma_sclk_slv_pins[] = {GPIOX_12};
+static const unsigned int tdma_fs_pins[] = {GPIOX_13};
+static const unsigned int tdma_fs_slv_pins[] = {GPIOX_13};
+static const unsigned int tdma_din0_pins[] = {GPIOX_14};
+static const unsigned int tdma_dout0_x14_pins[] = {GPIOX_14};
+static const unsigned int tdma_dout0_x15_pins[] = {GPIOX_15};
+static const unsigned int tdma_dout1_pins[] = {GPIOX_15};
+static const unsigned int tdma_din1_pins[] = {GPIOX_15};
+
+static const unsigned int tdmc_sclk_pins[] = {GPIOA_2};
+static const unsigned int tdmc_sclk_slv_pins[] = {GPIOA_2};
+static const unsigned int tdmc_fs_pins[] = {GPIOA_3};
+static const unsigned int tdmc_fs_slv_pins[] = {GPIOA_3};
+static const unsigned int tdmc_din0_pins[] = {GPIOA_4};
+static const unsigned int tdmc_dout0_pins[] = {GPIOA_4};
+static const unsigned int tdmc_din1_pins[] = {GPIOA_5};
+static const unsigned int tdmc_dout1_pins[] = {GPIOA_5};
+static const unsigned int tdmc_din2_pins[] = {GPIOA_6};
+static const unsigned int tdmc_dout2_pins[] = {GPIOA_6};
+static const unsigned int tdmc_din3_pins[] = {GPIOA_7};
+static const unsigned int tdmc_dout3_pins[] = {GPIOA_7};
+
+static const unsigned int tdmb_sclk_pins[] = {GPIOA_8};
+static const unsigned int tdmb_sclk_slv_pins[] = {GPIOA_8};
+static const unsigned int tdmb_fs_pins[] = {GPIOA_9};
+static const unsigned int tdmb_fs_slv_pins[] = {GPIOA_9};
+static const unsigned int tdmb_din0_pins[] = {GPIOA_10};
+static const unsigned int tdmb_dout0_pins[] = {GPIOA_10};
+static const unsigned int tdmb_din1_pins[] = {GPIOA_11};
+static const unsigned int tdmb_dout1_pins[] = {GPIOA_11};
+static const unsigned int tdmb_din2_pins[] = {GPIOA_12};
+static const unsigned int tdmb_dout2_pins[] = {GPIOA_12};
+static const unsigned int tdmb_din3_pins[] = {GPIOA_13};
+static const unsigned int tdmb_dout3_pins[] = {GPIOA_13};
+
 static struct meson_pmx_group meson_axg_periphs_groups[] = {
         GPIO_GROUP(GPIOZ_0),
         GPIO_GROUP(GPIOZ_1),
@@ -495,6 +536,15 @@ static struct meson_pmx_group meson_axg_periphs_groups[] = {
         GROUP(eth_rx_dv_x, 4),
         GROUP(eth_mdio_x, 4),
         GROUP(eth_mdc_x, 4),
+        GROUP(tdma_sclk, 1),
+        GROUP(tdma_sclk_slv, 2),
+        GROUP(tdma_fs, 1),
+        GROUP(tdma_fs_slv, 2),
+        GROUP(tdma_din0, 1),
+        GROUP(tdma_dout0_x14, 2),
+        GROUP(tdma_dout0_x15, 1),
+        GROUP(tdma_dout1, 2),
+        GROUP(tdma_din1, 3),
 
         /* bank GPIOY */
         GROUP(eth_txd0_y, 1),
@@ -544,6 +594,32 @@ static struct meson_pmx_group meson_axg_periphs_groups[] = {
         GROUP(pdm_din1, 1),
         GROUP(pdm_din2, 1),
         GROUP(pdm_din3, 1),
+        GROUP(mclk_c, 1),
+        GROUP(mclk_b, 1),
+        GROUP(tdmc_sclk, 1),
+        GROUP(tdmc_sclk_slv, 2),
+        GROUP(tdmc_fs, 1),
+        GROUP(tdmc_fs_slv, 2),
+        GROUP(tdmc_din0, 2),
+        GROUP(tdmc_dout0, 1),
+        GROUP(tdmc_din1, 2),
+        GROUP(tdmc_dout1, 1),
+        GROUP(tdmc_din2, 2),
+        GROUP(tdmc_dout2, 1),
+        GROUP(tdmc_din3, 2),
+        GROUP(tdmc_dout3, 1),
+        GROUP(tdmb_sclk, 1),
+        GROUP(tdmb_sclk_slv, 2),
+        GROUP(tdmb_fs, 1),
+        GROUP(tdmb_fs_slv, 2),
+        GROUP(tdmb_din0, 2),
+        GROUP(tdmb_dout0, 1),
+        GROUP(tdmb_din1, 2),
+        GROUP(tdmb_dout1, 1),
+        GROUP(tdmb_din2, 2),
+        GROUP(tdmb_dout2, 1),
+        GROUP(tdmb_din3, 2),
+        GROUP(tdmb_dout3, 1),
 };
 
 /* uart_ao_a */
@@ -845,6 +921,32 @@ static const char * const jtag_ao_groups[] = {
         "jtag_ao_tdi", "jtag_ao_tdo", "jtag_ao_clk", "jtag_ao_tms",
 };
 
+static const char * const mclk_c_groups[] = {
+        "mclk_c",
+};
+
+static const char * const mclk_b_groups[] = {
+        "mclk_b",
+};
+
+static const char * const tdma_groups[] = {
+        "tdma_sclk", "tdma_sclk_slv", "tdma_fs", "tdma_fs_slv",
+        "tdma_din0", "tdma_dout0_x14", "tdma_dout0_x15", "tdma_dout1",
+        "tdma_din1",
+};
+
+static const char * const tdmc_groups[] = {
+        "tdmc_sclk", "tdmc_sclk_slv", "tdmc_fs", "tdmc_fs_slv",
+        "tdmc_din0", "tdmc_dout0", "tdmc_din1", "tdmc_dout1",
+        "tdmc_din2", "tdmc_dout2", "tdmc_din3", "tdmc_dout3",
+};
+
+static const char * const tdmb_groups[] = {
+        "tdmb_sclk", "tdmb_sclk_slv", "tdmb_fs", "tdmb_fs_slv",
+        "tdmb_din0", "tdmb_dout0", "tdmb_din1", "tdmb_dout1",
+        "tdmb_din2", "tdmb_dout2", "tdmb_din3", "tdmb_dout3",
+};
+
 static struct meson_pmx_func meson_axg_periphs_functions[] = {
         FUNCTION(gpio_periphs),
         FUNCTION(emmc),
@@ -870,6 +972,11 @@ static struct meson_pmx_func meson_axg_periphs_functions[] = {
         FUNCTION(spdif_in),
         FUNCTION(jtag_ee),
         FUNCTION(pdm),
+        FUNCTION(mclk_b),
+        FUNCTION(mclk_c),
+        FUNCTION(tdma),
+        FUNCTION(tdmb),
+        FUNCTION(tdmc),
 };
 
 static struct meson_pmx_func meson_axg_aobus_functions[] = {
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index 9079020259c5..2c97a2e07a5f 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -627,8 +627,8 @@ static const char * const sdio_groups[] = {
 };
 
 static const char * const nand_groups[] = {
-        "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
-        "nand_wen_clk", "nand_ren_wr", "nand_dqs",
+        "emmc_nand_d07", "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale",
+        "nand_cle", "nand_wen_clk", "nand_ren_wr", "nand_dqs",
 };
 
 static const char * const uart_a_groups[] = {
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index b3786cde963d..7dae1d7bf6b0 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -617,8 +617,8 @@ static const char * const sdio_groups[] = {
 };
 
 static const char * const nand_groups[] = {
-        "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
-        "nand_wen_clk", "nand_ren_wr", "nand_dqs",
+        "emmc_nand_d07", "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale",
+        "nand_cle", "nand_wen_clk", "nand_ren_wr", "nand_dqs",
 };
 
 static const char * const uart_a_groups[] = {
diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c
index 49c7ce03547b..c6d79315218f 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8.c
@@ -1,5 +1,5 @@
 /*
- * Pin controller and GPIO driver for Amlogic Meson8.
+ * Pin controller and GPIO driver for Amlogic Meson8 and Meson8m2.
  *
  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
  *
@@ -299,6 +299,10 @@ static const unsigned int spi_mosi_1_pins[]	= { GPIOZ_12 };
 static const unsigned int spi_miso_1_pins[]     = { GPIOZ_13 };
 static const unsigned int spi_ss2_1_pins[]      = { GPIOZ_14 };
 
+static const unsigned int eth_txd3_pins[]       = { GPIOZ_0 };
+static const unsigned int eth_txd2_pins[]       = { GPIOZ_1 };
+static const unsigned int eth_rxd3_pins[]       = { GPIOZ_2 };
+static const unsigned int eth_rxd2_pins[]       = { GPIOZ_3 };
 static const unsigned int eth_tx_clk_50m_pins[] = { GPIOZ_4 };
 static const unsigned int eth_tx_en_pins[]      = { GPIOZ_5 };
 static const unsigned int eth_txd1_pins[]       = { GPIOZ_6 };
@@ -650,6 +654,12 @@ static struct meson_pmx_group meson8_cbus_groups[] = {
         GROUP(eth_mdio,         6,      6),
         GROUP(eth_mdc,          6,      5),
 
+        /* NOTE: the following four groups are only available on Meson8m2: */
+        GROUP(eth_rxd2,         6,      3),
+        GROUP(eth_rxd3,         6,      2),
+        GROUP(eth_txd2,         6,      1),
+        GROUP(eth_txd3,         6,      0),
+
         GROUP(i2c_sda_a0,       5,      31),
         GROUP(i2c_sck_a0,       5,      30),
 
@@ -877,7 +887,8 @@ static const char * const spi_groups[] = {
 static const char * const ethernet_groups[] = {
         "eth_tx_clk_50m", "eth_tx_en", "eth_txd1",
         "eth_txd0", "eth_rx_clk_in", "eth_rx_dv",
-        "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc"
+        "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc", "eth_rxd2",
+        "eth_rxd3", "eth_txd2", "eth_txd3"
 };
 
 static const char * const i2c_a_groups[] = {
@@ -1080,6 +1091,14 @@ static const struct of_device_id meson8_pinctrl_dt_match[] = {
                 .compatible = "amlogic,meson8-aobus-pinctrl",
                 .data = &meson8_aobus_pinctrl_data,
         },
+        {
+                .compatible = "amlogic,meson8m2-cbus-pinctrl",
+                .data = &meson8_cbus_pinctrl_data,
+        },
+        {
+                .compatible = "amlogic,meson8m2-aobus-pinctrl",
+                .data = &meson8_aobus_pinctrl_data,
+        },
         { },
 };
 
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index 5b63248c8209..674ffdf8103c 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -214,18 +214,6 @@ static inline void armada_37xx_update_reg(unsigned int *reg,
         }
 }
 
-static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
-                                    const char *func)
-{
-        int f;
-
-        for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
-                if (!strcmp(grp->funcs[f], func))
-                        return f;
-
-        return -ENOTSUPP;
-}
-
 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
         struct armada_37xx_pinctrl *info, int pin, int *grp)
 {
@@ -344,10 +332,9 @@ static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
         dev_dbg(info->dev, "enable function %s group %s\n",
                 name, grp->name);
 
-        func = armada_37xx_get_func_reg(grp, name);
-
+        func = match_string(grp->funcs, NB_FUNCS, name);
         if (func < 0)
-                return func;
+                return -ENOTSUPP;
 
         val = grp->val[func];
 
@@ -679,12 +666,13 @@ static void armada_37xx_irq_handler(struct irq_desc *desc)
                                         writel(1 << hwirq,
                                                info->base +
                                                IRQ_STATUS + 4 * i);
-                                        continue;
+                                        goto update_status;
                                 }
                         }
 
                         generic_handle_irq(virq);
 
+update_status:
                         /* Update status in case a new IRQ appears */
                         spin_lock_irqsave(&info->irq_lock, flags);
                         status = readl_relaxed(info->base +
@@ -932,12 +920,12 @@ static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
                         struct armada_37xx_pin_group *gp = &info->groups[g];
                         int f;
 
-                        for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
-                                if (strcmp(gp->funcs[f], name) == 0) {
-                                        *groups = gp->name;
-                                        groups++;
-                                }
-                        }
+                        f = match_string(gp->funcs, NB_FUNCS, name);
+                        if (f < 0)
+                                continue;
+
+                        *groups = gp->name;
+                        groups++;
                 }
         }
         return 0;
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index b854f1ee5de5..5e828468e43d 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -431,40 +431,40 @@ static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = {
         MPP_MODE(19,
                  MPP_VAR_FUNCTION(0x0, "gpio", NULL,         V_98DX3236_PLUS),
                  MPP_VAR_FUNCTION(0x3, "uart1", "rxd",       V_98DX3236_PLUS),
-                 MPP_VAR_FUNCTION(0x4, "dev", "rb",          V_98DX3236_PLUS)),
+                 MPP_VAR_FUNCTION(0x4, "nand", "rb",         V_98DX3236_PLUS)),
         MPP_MODE(20,
                  MPP_VAR_FUNCTION(0x0, "gpo", NULL,          V_98DX3236_PLUS),
                  MPP_VAR_FUNCTION(0x4, "dev", "we0",         V_98DX3236_PLUS)),
         MPP_MODE(21,
                  MPP_VAR_FUNCTION(0x0, "gpo", NULL,          V_98DX3236_PLUS),
-                 MPP_VAR_FUNCTION(0x1, "dev", "ad0",         V_98DX3236_PLUS)),
+                 MPP_VAR_FUNCTION(0x4, "dev", "ad0",         V_98DX3236_PLUS)),
         MPP_MODE(22,
                  MPP_VAR_FUNCTION(0x0, "gpo", NULL,          V_98DX3236_PLUS),
-                 MPP_VAR_FUNCTION(0x1, "dev", "ad1",         V_98DX3236_PLUS)),
+                 MPP_VAR_FUNCTION(0x4, "dev", "ad1",         V_98DX3236_PLUS)),
         MPP_MODE(23,
                  MPP_VAR_FUNCTION(0x0, "gpo", NULL,          V_98DX3236_PLUS),
-                 MPP_VAR_FUNCTION(0x1, "dev", "ad2",         V_98DX3236_PLUS)),
+                 MPP_VAR_FUNCTION(0x4, "dev", "ad2",         V_98DX3236_PLUS)),
         MPP_MODE(24,
                  MPP_VAR_FUNCTION(0x0, "gpo", NULL,          V_98DX3236_PLUS),
-                 MPP_VAR_FUNCTION(0x1, "dev", "ad3",         V_98DX3236_PLUS)),
+                 MPP_VAR_FUNCTION(0x4, "dev", "ad3",         V_98DX3236_PLUS)),
         MPP_MODE(25,
                  MPP_VAR_FUNCTION(0x0, "gpo", NULL,          V_98DX3236_PLUS),
-                 MPP_VAR_FUNCTION(0x1, "dev", "ad4",         V_98DX3236_PLUS)),
+                 MPP_VAR_FUNCTION(0x4, "dev", "ad4",         V_98DX3236_PLUS)),
         MPP_MODE(26,
                  MPP_VAR_FUNCTION(0x0, "gpo", NULL,          V_98DX3236_PLUS),
-                 MPP_VAR_FUNCTION(0x1, "dev", "ad5",         V_98DX3236_PLUS)),
+                 MPP_VAR_FUNCTION(0x4, "dev", "ad5",         V_98DX3236_PLUS)),
         MPP_MODE(27,
                  MPP_VAR_FUNCTION(0x0, "gpo", NULL,          V_98DX3236_PLUS),
-                 MPP_VAR_FUNCTION(0x1, "dev", "ad6",         V_98DX3236_PLUS)),
+                 MPP_VAR_FUNCTION(0x4, "dev", "ad6",         V_98DX3236_PLUS)),
         MPP_MODE(28,
                  MPP_VAR_FUNCTION(0x0, "gpo", NULL,          V_98DX3236_PLUS),
-                 MPP_VAR_FUNCTION(0x1, "dev", "ad7",         V_98DX3236_PLUS)),
+                 MPP_VAR_FUNCTION(0x4, "dev", "ad7",         V_98DX3236_PLUS)),
         MPP_MODE(29,
                  MPP_VAR_FUNCTION(0x0, "gpo", NULL,          V_98DX3236_PLUS),
-                 MPP_VAR_FUNCTION(0x1, "dev", "a0",          V_98DX3236_PLUS)),
+                 MPP_VAR_FUNCTION(0x4, "dev", "a0",          V_98DX3236_PLUS)),
         MPP_MODE(30,
                  MPP_VAR_FUNCTION(0x0, "gpo", NULL,          V_98DX3236_PLUS),
-                 MPP_VAR_FUNCTION(0x1, "dev", "a1",          V_98DX3236_PLUS)),
+                 MPP_VAR_FUNCTION(0x4, "dev", "a1",          V_98DX3236_PLUS)),
         MPP_MODE(31,
                  MPP_VAR_FUNCTION(0x0, "gpio", NULL,         V_98DX3236_PLUS),
                  MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc",     V_98DX3236_PLUS),
diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
index 4b57a13758a4..bafb3d40545e 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -576,8 +576,10 @@ static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
                 for_each_child_of_node(np_config, np) {
                         ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
                                                     &reserved_maps, num_maps);
-                        if (ret < 0)
+                        if (ret < 0) {
+                                of_node_put(np);
                                 break;
+                        }
                 }
         }
 
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 3924779f5578..1882713e68f9 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -59,6 +59,7 @@
 #define GPIO_LS_SYNC            0x60
 
 enum rockchip_pinctrl_type {
+        PX30,
         RV1108,
         RK2928,
         RK3066B,
@@ -701,6 +702,66 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
         *bit = data->bit;
 }
 
+static struct rockchip_mux_route_data px30_mux_route_data[] = {
+        {
+                /* cif-d2m0 */
+                .bank_num = 2,
+                .pin = 0,
+                .func = 1,
+                .route_offset = 0x184,
+                .route_val = BIT(16 + 7),
+        }, {
+                /* cif-d2m1 */
+                .bank_num = 3,
+                .pin = 3,
+                .func = 3,
+                .route_offset = 0x184,
+                .route_val = BIT(16 + 7) | BIT(7),
+        }, {
+                /* pdm-m0 */
+                .bank_num = 3,
+                .pin = 22,
+                .func = 2,
+                .route_offset = 0x184,
+                .route_val = BIT(16 + 8),
+        }, {
+                /* pdm-m1 */
+                .bank_num = 2,
+                .pin = 22,
+                .func = 1,
+                .route_offset = 0x184,
+                .route_val = BIT(16 + 8) | BIT(8),
+        }, {
+                /* uart2-rxm0 */
+                .bank_num = 1,
+                .pin = 27,
+                .func = 2,
+                .route_offset = 0x184,
+                .route_val = BIT(16 + 10),
+        }, {
+                /* uart2-rxm1 */
+                .bank_num = 2,
+                .pin = 14,
+                .func = 2,
+                .route_offset = 0x184,
+                .route_val = BIT(16 + 10) | BIT(10),
+        }, {
+                /* uart3-rxm0 */
+                .bank_num = 0,
+                .pin = 17,
+                .func = 2,
+                .route_offset = 0x184,
+                .route_val = BIT(16 + 9),
+        }, {
+                /* uart3-rxm1 */
+                .bank_num = 1,
+                .pin = 15,
+                .func = 2,
+                .route_offset = 0x184,
+                .route_val = BIT(16 + 9) | BIT(9),
+        },
+};
+
 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
         {
                 /* spi-0 */
@@ -1202,6 +1263,97 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
         return ret;
 }
 
+#define PX30_PULL_PMU_OFFSET            0x10
+#define PX30_PULL_GRF_OFFSET            0x60
+#define PX30_PULL_BITS_PER_PIN          2
+#define PX30_PULL_PINS_PER_REG          8
+#define PX30_PULL_BANK_STRIDE           16
+
+static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+                                       int pin_num, struct regmap **regmap,
+                                       int *reg, u8 *bit)
+{
+        struct rockchip_pinctrl *info = bank->drvdata;
+
+        /* The first 32 pins of the first bank are located in PMU */
+        if (bank->bank_num == 0) {
+                *regmap = info->regmap_pmu;
+                *reg = PX30_PULL_PMU_OFFSET;
+        } else {
+                *regmap = info->regmap_base;
+                *reg = PX30_PULL_GRF_OFFSET;
+
+                /* correct the offset, as we're starting with the 2nd bank */
+                *reg -= 0x10;
+                *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
+        }
+
+        *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
+        *bit = (pin_num % PX30_PULL_PINS_PER_REG);
+        *bit *= PX30_PULL_BITS_PER_PIN;
+}
+
+#define PX30_DRV_PMU_OFFSET             0x20
+#define PX30_DRV_GRF_OFFSET             0xf0
+#define PX30_DRV_BITS_PER_PIN           2
+#define PX30_DRV_PINS_PER_REG           8
+#define PX30_DRV_BANK_STRIDE            16
+
+static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+                                      int pin_num, struct regmap **regmap,
+                                      int *reg, u8 *bit)
+{
+        struct rockchip_pinctrl *info = bank->drvdata;
+
+        /* The first 32 pins of the first bank are located in PMU */
+        if (bank->bank_num == 0) {
+                *regmap = info->regmap_pmu;
+                *reg = PX30_DRV_PMU_OFFSET;
+        } else {
+                *regmap = info->regmap_base;
+                *reg = PX30_DRV_GRF_OFFSET;
+
+                /* correct the offset, as we're starting with the 2nd bank */
+                *reg -= 0x10;
+                *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
+        }
+
+        *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
+        *bit = (pin_num % PX30_DRV_PINS_PER_REG);
+        *bit *= PX30_DRV_BITS_PER_PIN;
+}
+
+#define PX30_SCHMITT_PMU_OFFSET                 0x38
+#define PX30_SCHMITT_GRF_OFFSET                 0xc0
+#define PX30_SCHMITT_PINS_PER_PMU_REG           16
+#define PX30_SCHMITT_BANK_STRIDE                16
+#define PX30_SCHMITT_PINS_PER_GRF_REG           8
+
+static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+                                         int pin_num,
+                                         struct regmap **regmap,
+                                         int *reg, u8 *bit)
+{
+        struct rockchip_pinctrl *info = bank->drvdata;
+        int pins_per_reg;
+
+        if (bank->bank_num == 0) {
+                *regmap = info->regmap_pmu;
+                *reg = PX30_SCHMITT_PMU_OFFSET;
+                pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
+        } else {
+                *regmap = info->regmap_base;
+                *reg = PX30_SCHMITT_GRF_OFFSET;
+                pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
+                *reg += (bank->bank_num  - 1) * PX30_SCHMITT_BANK_STRIDE;
+        }
+
+        *reg += ((pin_num / pins_per_reg) * 4);
+        *bit = pin_num % pins_per_reg;
+
+        return 0;
+}
+
 #define RV1108_PULL_PMU_OFFSET          0x10
 #define RV1108_PULL_OFFSET              0x110
 #define RV1108_PULL_PINS_PER_REG        8
@@ -1798,6 +1950,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
                 return !(data & BIT(bit))
                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
                                 : PIN_CONFIG_BIAS_DISABLE;
+        case PX30:
         case RV1108:
         case RK3188:
         case RK3288:
@@ -1841,6 +1994,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
                         data |= BIT(bit);
                 ret = regmap_write(regmap, reg, data);
                 break;
+        case PX30:
         case RV1108:
         case RK3188:
         case RK3288:
@@ -2103,6 +2257,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
                                         pull == PIN_CONFIG_BIAS_DISABLE);
         case RK3066B:
                 return pull ? false : true;
+        case PX30:
         case RV1108:
         case RK3188:
         case RK3288:
@@ -2555,6 +2710,57 @@ static int rockchip_gpio_direction_output(struct gpio_chip *gc,
         return pinctrl_gpio_direction_output(gc->base + offset);
 }
 
+static void rockchip_gpio_set_debounce(struct gpio_chip *gc,
+                                       unsigned int offset, bool enable)
+{
+        struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
+        void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE;
+        unsigned long flags;
+        u32 data;
+
+        clk_enable(bank->clk);
+        raw_spin_lock_irqsave(&bank->slock, flags);
+
+        data = readl(reg);
+        if (enable)
+                data |= BIT(offset);
+        else
+                data &= ~BIT(offset);
+        writel(data, reg);
+
+        raw_spin_unlock_irqrestore(&bank->slock, flags);
+        clk_disable(bank->clk);
+}
+
+/*
+ * gpiolib set_config callback function. The setting of the pin
+ * mux function as 'gpio output' will be handled by the pinctrl subsystem
+ * interface.
+ */
+static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
+                                  unsigned long config)
+{
+        enum pin_config_param param = pinconf_to_config_param(config);
+
+        switch (param) {
+        case PIN_CONFIG_INPUT_DEBOUNCE:
+                rockchip_gpio_set_debounce(gc, offset, true);
+                /*
+                 * Rockchip's gpio could only support up to one period
+                 * of the debounce clock(pclk), which is far away from
+                 * satisftying the requirement, as pclk is usually near
+                 * 100MHz shared by all peripherals. So the fact is it
+                 * has crippled debounce capability could only be useful
+                 * to prevent any spurious glitches from waking up the system
+                 * if the gpio is conguired as wakeup interrupt source. Let's
+                 * still return -ENOTSUPP as before, to make sure the caller
+                 * of gpiod_set_debounce won't change its behaviour.
+                 */
+        default:
+                return -ENOTSUPP;
+        }
+}
+
 /*
  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
  * and a virtual IRQ, if not already present.
@@ -2580,6 +2786,7 @@ static const struct gpio_chip rockchip_gpiolib_chip = {
         .get_direction  = rockchip_gpio_get_direction,
         .direction_input = rockchip_gpio_direction_input,
         .direction_output = rockchip_gpio_direction_output,
+        .set_config = rockchip_gpio_set_config,
         .to_irq = rockchip_gpio_to_irq,
         .owner = THIS_MODULE,
 };
@@ -3237,6 +3444,43 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
         return 0;
 }
 
+static struct rockchip_pin_bank px30_pin_banks[] = {
+        PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
+                                             IOMUX_SOURCE_PMU,
+                                             IOMUX_SOURCE_PMU,
+                                             IOMUX_SOURCE_PMU
+                            ),
+        PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
+                                             IOMUX_WIDTH_4BIT,
+                                             IOMUX_WIDTH_4BIT,
+                                             IOMUX_WIDTH_4BIT
+                            ),
+        PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
+                                             IOMUX_WIDTH_4BIT,
+                                             IOMUX_WIDTH_4BIT,
+                                             IOMUX_WIDTH_4BIT
+                            ),
+        PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
+                                             IOMUX_WIDTH_4BIT,
+                                             IOMUX_WIDTH_4BIT,
+                                             IOMUX_WIDTH_4BIT
+                            ),
+};
+
+static struct rockchip_pin_ctrl px30_pin_ctrl = {
+                .pin_banks              = px30_pin_banks,
+                .nr_banks               = ARRAY_SIZE(px30_pin_banks),
+                .label                  = "PX30-GPIO",
+                .type                   = PX30,
+                .grf_mux_offset         = 0x0,
+                .pmu_mux_offset         = 0x0,
+                .iomux_routes           = px30_mux_route_data,
+                .niomux_routes          = ARRAY_SIZE(px30_mux_route_data),
+                .pull_calc_reg          = px30_calc_pull_reg_and_bit,
+                .drv_calc_reg           = px30_calc_drv_reg_and_bit,
+                .schmitt_calc_reg       = px30_calc_schmitt_reg_and_bit,
+};
+
 static struct rockchip_pin_bank rv1108_pin_banks[] = {
         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
                                              IOMUX_SOURCE_PMU,
@@ -3545,6 +3789,8 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
 };
 
 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
+        { .compatible = "rockchip,px30-pinctrl",
+                .data = &px30_pin_ctrl },
         { .compatible = "rockchip,rv1108-pinctrl",
                 .data = &rv1108_pin_ctrl },
         { .compatible = "rockchip,rk2928-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index a7c5eb39b1eb..9c3c00515aa0 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -144,6 +144,7 @@ struct pcs_soc_data {
  * struct pcs_device - pinctrl device instance
  * @res:        resources
  * @base:       virtual address of the controller
+ * @saved_vals: saved values for the controller
  * @size:       size of the ioremapped area
  * @dev:        device entry
  * @np:         device tree node
@@ -172,11 +173,13 @@ struct pcs_soc_data {
 struct pcs_device {
         struct resource *res;
         void __iomem *base;
+        void *saved_vals;
         unsigned size;
         struct device *dev;
         struct device_node *np;
         struct pinctrl_dev *pctl;
         unsigned flags;
+#define PCS_CONTEXT_LOSS_OFF    (1 << 3)
 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 #define PCS_FEAT_IRQ            (1 << 1)
 #define PCS_FEAT_PINCONF        (1 << 0)
@@ -1576,6 +1579,67 @@ static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
 }
 
 #ifdef CONFIG_PM
+static int pcs_save_context(struct pcs_device *pcs)
+{
+        int i, mux_bytes;
+        u64 *regsl;
+        u32 *regsw;
+        u16 *regshw;
+
+        mux_bytes = pcs->width / BITS_PER_BYTE;
+
+        if (!pcs->saved_vals)
+                pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
+
+        switch (pcs->width) {
+        case 64:
+                regsl = (u64 *)pcs->saved_vals;
+                for (i = 0; i < pcs->size / mux_bytes; i++)
+                        regsl[i] = pcs->read(pcs->base + i * mux_bytes);
+                break;
+        case 32:
+                regsw = (u32 *)pcs->saved_vals;
+                for (i = 0; i < pcs->size / mux_bytes; i++)
+                        regsw[i] = pcs->read(pcs->base + i * mux_bytes);
+                break;
+        case 16:
+                regshw = (u16 *)pcs->saved_vals;
+                for (i = 0; i < pcs->size / mux_bytes; i++)
+                        regshw[i] = pcs->read(pcs->base + i * mux_bytes);
+                break;
+        }
+
+        return 0;
+}
+
+static void pcs_restore_context(struct pcs_device *pcs)
+{
+        int i, mux_bytes;
+        u64 *regsl;
+        u32 *regsw;
+        u16 *regshw;
+
+        mux_bytes = pcs->width / BITS_PER_BYTE;
+
+        switch (pcs->width) {
+        case 64:
+                regsl = (u64 *)pcs->saved_vals;
+                for (i = 0; i < pcs->size / mux_bytes; i++)
+                        pcs->write(regsl[i], pcs->base + i * mux_bytes);
+                break;
+        case 32:
+                regsw = (u32 *)pcs->saved_vals;
+                for (i = 0; i < pcs->size / mux_bytes; i++)
+                        pcs->write(regsw[i], pcs->base + i * mux_bytes);
+                break;
+        case 16:
+                regshw = (u16 *)pcs->saved_vals;
+                for (i = 0; i < pcs->size / mux_bytes; i++)
+                        pcs->write(regshw[i], pcs->base + i * mux_bytes);
+                break;
+        }
+}
+
 static int pinctrl_single_suspend(struct platform_device *pdev,
                                         pm_message_t state)
 {
@@ -1585,6 +1649,9 @@ static int pinctrl_single_suspend(struct platform_device *pdev,
         if (!pcs)
                 return -EINVAL;
 
+        if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
+                pcs_save_context(pcs);
+
         return pinctrl_force_sleep(pcs->pctl);
 }
 
@@ -1596,6 +1663,9 @@ static int pinctrl_single_resume(struct platform_device *pdev)
         if (!pcs)
                 return -EINVAL;
 
+        if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
+                pcs_restore_context(pcs);
+
         return pinctrl_force_default(pcs->pctl);
 }
 #endif
@@ -1824,7 +1894,7 @@ static const struct pcs_soc_data pinctrl_single_dra7 = {
 };
 
 static const struct pcs_soc_data pinctrl_single_am437x = {
-        .flags = PCS_QUIRK_SHARED_IRQ,
+        .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
         .irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
         .irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
 };
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index ad80a17c9990..0e22f52b2a19 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -58,7 +58,10 @@ struct msm_pinctrl {
         struct device *dev;
         struct pinctrl_dev *pctrl;
         struct gpio_chip chip;
+        struct pinctrl_desc desc;
         struct notifier_block restart_nb;
+
+        struct irq_chip irq_chip;
         int irq;
 
         raw_spinlock_t lock;
@@ -390,13 +393,6 @@ static const struct pinconf_ops msm_pinconf_ops = {
         .pin_config_group_set   = msm_config_group_set,
 };
 
-static struct pinctrl_desc msm_pinctrl_desc = {
-        .pctlops = &msm_pinctrl_ops,
-        .pmxops = &msm_pinmux_ops,
-        .confops = &msm_pinconf_ops,
-        .owner = THIS_MODULE,
-};
-
 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
         const struct msm_pingroup *g;
@@ -506,29 +502,46 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
         int is_out;
         int drive;
         int pull;
-        u32 ctl_reg;
+        int val;
+        u32 ctl_reg, io_reg;
 
-        static const char * const pulls[] = {
+        static const char * const pulls_keeper[] = {
                 "no pull",
                 "pull down",
                 "keeper",
                 "pull up"
         };
 
+        static const char * const pulls_no_keeper[] = {
+                "no pull",
+                "pull down",
+                "pull up",
+        };
+
         if (!gpiochip_line_is_valid(chip, offset))
                 return;
 
         g = &pctrl->soc->groups[offset];
         ctl_reg = readl(pctrl->regs + g->ctl_reg);
+        io_reg = readl(pctrl->regs + g->io_reg);
 
         is_out = !!(ctl_reg & BIT(g->oe_bit));
         func = (ctl_reg >> g->mux_bit) & 7;
         drive = (ctl_reg >> g->drv_bit) & 7;
         pull = (ctl_reg >> g->pull_bit) & 3;
 
-        seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
+        if (is_out)
+                val = !!(io_reg & BIT(g->out_bit));
+        else
+                val = !!(io_reg & BIT(g->in_bit));
+
+        seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
+        seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
         seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-        seq_printf(s, " %s", pulls[pull]);
+        if (pctrl->soc->pull_no_keeper)
+                seq_printf(s, " %s", pulls_no_keeper[pull]);
+        else
+                seq_printf(s, " %s", pulls_keeper[pull]);
         seq_puts(s, "\n");
 }
 
@@ -776,15 +789,6 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
         return 0;
 }
 
-static struct irq_chip msm_gpio_irq_chip = {
-        .name           = "msmgpio",
-        .irq_mask       = msm_gpio_irq_mask,
-        .irq_unmask     = msm_gpio_irq_unmask,
-        .irq_ack        = msm_gpio_irq_ack,
-        .irq_set_type   = msm_gpio_irq_set_type,
-        .irq_set_wake   = msm_gpio_irq_set_wake,
-};
-
 static void msm_gpio_irq_handler(struct irq_desc *desc)
 {
         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
@@ -877,6 +881,13 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
         chip->of_node = pctrl->dev->of_node;
         chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl);
 
+        pctrl->irq_chip.name = "msmgpio";
+        pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
+        pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
+        pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
+        pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
+        pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
+
         ret = gpiochip_add_data(&pctrl->chip, pctrl);
         if (ret) {
                 dev_err(pctrl->dev, "Failed register gpiochip\n");
@@ -890,15 +901,28 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
                 return ret;
         }
 
-        ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
-        if (ret) {
-                dev_err(pctrl->dev, "Failed to add pin range\n");
-                gpiochip_remove(&pctrl->chip);
-                return ret;
+        /*
+         * For DeviceTree-supported systems, the gpio core checks the
+         * pinctrl's device node for the "gpio-ranges" property.
+         * If it is present, it takes care of adding the pin ranges
+         * for the driver. In this case the driver can skip ahead.
+         *
+         * In order to remain compatible with older, existing DeviceTree
+         * files which don't set the "gpio-ranges" property or systems that
+         * utilize ACPI the driver has to call gpiochip_add_pin_range().
+         */
+        if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
+                ret = gpiochip_add_pin_range(&pctrl->chip,
+                        dev_name(pctrl->dev), 0, 0, chip->ngpio);
+                if (ret) {
+                        dev_err(pctrl->dev, "Failed to add pin range\n");
+                        gpiochip_remove(&pctrl->chip);
+                        return ret;
+                }
         }
 
         ret = gpiochip_irqchip_add(chip,
-                                   &msm_gpio_irq_chip,
+                                   &pctrl->irq_chip,
                                    0,
                                    handle_edge_irq,
                                    IRQ_TYPE_NONE);
@@ -908,7 +932,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
                 return -ENOSYS;
         }
 
-        gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
+        gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq,
                                      msm_gpio_irq_handler);
 
         return 0;
@@ -979,11 +1003,15 @@ int msm_pinctrl_probe(struct platform_device *pdev,
                 return pctrl->irq;
         }
 
-        msm_pinctrl_desc.name = dev_name(&pdev->dev);
-        msm_pinctrl_desc.pins = pctrl->soc->pins;
-        msm_pinctrl_desc.npins = pctrl->soc->npins;
-        pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &msm_pinctrl_desc,
-                                             pctrl);
+        pctrl->desc.owner = THIS_MODULE;
+        pctrl->desc.pctlops = &msm_pinctrl_ops;
+        pctrl->desc.pmxops = &msm_pinmux_ops;
+        pctrl->desc.confops = &msm_pinconf_ops;
+        pctrl->desc.name = dev_name(&pdev->dev);
+        pctrl->desc.pins = pctrl->soc->pins;
+        pctrl->desc.npins = pctrl->soc->npins;
+
+        pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
         if (IS_ERR(pctrl->pctrl)) {
                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
                 return PTR_ERR(pctrl->pctrl);
diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index bb3ce5c3e18b..1dfbe42dd895 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -30,9 +30,7 @@
 
 #include "pinctrl-msm.h"
 
-static struct msm_pinctrl_soc_data qdf2xxx_pinctrl;
-
-/* A reasonable limit to the number of GPIOS */
+/* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */
 #define MAX_GPIOS       256
 
 /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
@@ -40,77 +38,111 @@ static struct msm_pinctrl_soc_data qdf2xxx_pinctrl;
 
 static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 {
+        struct msm_pinctrl_soc_data *pinctrl;
         struct pinctrl_pin_desc *pins;
         struct msm_pingroup *groups;
         char (*names)[NAME_SIZE];
         unsigned int i;
         u32 num_gpios;
+        unsigned int avail_gpios; /* The number of GPIOs we support */
+        u8 gpios[MAX_GPIOS];      /* An array of supported GPIOs */
         int ret;
 
         /* Query the number of GPIOs from ACPI */
         ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
         if (ret < 0) {
-                dev_warn(&pdev->dev, "missing num-gpios property\n");
+                dev_err(&pdev->dev, "missing 'num-gpios' property\n");
                 return ret;
         }
-
         if (!num_gpios || num_gpios > MAX_GPIOS) {
-                dev_warn(&pdev->dev, "invalid num-gpios property\n");
+                dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
+                return -ENODEV;
+        }
+
+        /* The number of GPIOs in the approved list */
+        ret = device_property_read_u8_array(&pdev->dev, "gpios", NULL, 0);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "missing 'gpios' property\n");
+                return ret;
+        }
+        /*
+         * The number of available GPIOs should be non-zero, and no
+         * more than the total number of GPIOS.
+         */
+        if (!ret || ret > num_gpios) {
+                dev_err(&pdev->dev, "invalid 'gpios' property\n");
                 return -ENODEV;
         }
+        avail_gpios = ret;
 
+        ret = device_property_read_u8_array(&pdev->dev, "gpios", gpios,
+                                            avail_gpios);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "could not read list of GPIOs\n");
+                return ret;
+        }
+
+        pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
         pins = devm_kcalloc(&pdev->dev, num_gpios,
                 sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
         groups = devm_kcalloc(&pdev->dev, num_gpios,
                 sizeof(struct msm_pingroup), GFP_KERNEL);
-        names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
+        names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);
 
-        if (!pins || !groups || !names)
+        if (!pinctrl || !pins || !groups || !names)
                 return -ENOMEM;
 
+        /*
+         * Initialize the array.  GPIOs not listed in the 'gpios' array
+         * still need a number, but nothing else.
+         */
         for (i = 0; i < num_gpios; i++) {
-                snprintf(names[i], NAME_SIZE, "gpio%u", i);
-
                 pins[i].number = i;
-                pins[i].name = names[i];
-
-                groups[i].npins = 1;
-                groups[i].name = names[i];
                 groups[i].pins = &pins[i].number;
+        }
 
-                groups[i].ctl_reg = 0x10000 * i;
-                groups[i].io_reg = 0x04 + 0x10000 * i;
-                groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
-                groups[i].intr_status_reg = 0x0c + 0x10000 * i;
-                groups[i].intr_target_reg = 0x08 + 0x10000 * i;
-
-                groups[i].mux_bit = 2;
-                groups[i].pull_bit = 0;
-                groups[i].drv_bit = 6;
-                groups[i].oe_bit = 9;
-                groups[i].in_bit = 0;
-                groups[i].out_bit = 1;
-                groups[i].intr_enable_bit = 0;
-                groups[i].intr_status_bit = 0;
-                groups[i].intr_target_bit = 5;
-                groups[i].intr_target_kpss_val = 1;
-                groups[i].intr_raw_status_bit = 4;
-                groups[i].intr_polarity_bit = 1;
-                groups[i].intr_detection_bit = 2;
-                groups[i].intr_detection_width = 2;
+        /* Populate the entries that are meant to be exposed as GPIOs. */
+        for (i = 0; i < avail_gpios; i++) {
+                unsigned int gpio = gpios[i];
+
+                groups[gpio].npins = 1;
+                snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
+                pins[gpio].name = names[i];
+                groups[gpio].name = names[i];
+
+                groups[gpio].ctl_reg = 0x10000 * gpio;
+                groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
+                groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
+                groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
+                groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
+
+                groups[gpio].mux_bit = 2;
+                groups[gpio].pull_bit = 0;
+                groups[gpio].drv_bit = 6;
+                groups[gpio].oe_bit = 9;
+                groups[gpio].in_bit = 0;
+                groups[gpio].out_bit = 1;
+                groups[gpio].intr_enable_bit = 0;
+                groups[gpio].intr_status_bit = 0;
+                groups[gpio].intr_target_bit = 5;
+                groups[gpio].intr_target_kpss_val = 1;
+                groups[gpio].intr_raw_status_bit = 4;
+                groups[gpio].intr_polarity_bit = 1;
+                groups[gpio].intr_detection_bit = 2;
+                groups[gpio].intr_detection_width = 2;
         }
 
-        qdf2xxx_pinctrl.pins = pins;
-        qdf2xxx_pinctrl.groups = groups;
-        qdf2xxx_pinctrl.npins = num_gpios;
-        qdf2xxx_pinctrl.ngroups = num_gpios;
-        qdf2xxx_pinctrl.ngpios = num_gpios;
+        pinctrl->pins = pins;
+        pinctrl->groups = groups;
+        pinctrl->npins = num_gpios;
+        pinctrl->ngroups = num_gpios;
+        pinctrl->ngpios = num_gpios;
 
-        return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
+        return msm_pinctrl_probe(pdev, pinctrl);
 }
 
 static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
-        {"QCOM8001"},
+        {"QCOM8002"},
         {},
 };
 MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig
index 11b5eeb14c4a..425fadd6c346 100644
--- a/drivers/pinctrl/samsung/Kconfig
+++ b/drivers/pinctrl/samsung/Kconfig
@@ -8,26 +8,20 @@ config PINCTRL_SAMSUNG
         select PINCONF
 
 config PINCTRL_EXYNOS
-        bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
+        bool "Pinctrl driver data for Samsung EXYNOS SoCs"
         depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210)
         select PINCTRL_SAMSUNG
         select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210)
         select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS
 
 config PINCTRL_EXYNOS_ARM
-        bool "ARMv7-specific pinctrl driver data for Exynos (except Exynos5440)" if COMPILE_TEST
+        bool "ARMv7-specific pinctrl driver data for Exynos" if COMPILE_TEST
         depends on PINCTRL_EXYNOS
 
 config PINCTRL_EXYNOS_ARM64
         bool "ARMv8-specific pinctrl driver data for Exynos" if COMPILE_TEST
         depends on PINCTRL_EXYNOS
 
-config PINCTRL_EXYNOS5440
-        bool "Samsung EXYNOS5440 SoC pinctrl driver"
-        depends on SOC_EXYNOS5440
-        select PINMUX
-        select PINCONF
-
 config PINCTRL_S3C24XX
         bool "Samsung S3C24XX SoC pinctrl driver"
         depends on ARCH_S3C24XX && OF
diff --git a/drivers/pinctrl/samsung/Makefile b/drivers/pinctrl/samsung/Makefile
index df426561d067..ed951df6a112 100644
--- a/drivers/pinctrl/samsung/Makefile
+++ b/drivers/pinctrl/samsung/Makefile
@@ -5,6 +5,5 @@ obj-$(CONFIG_PINCTRL_SAMSUNG)	+= pinctrl-samsung.o
 obj-$(CONFIG_PINCTRL_EXYNOS)    += pinctrl-exynos.o
 obj-$(CONFIG_PINCTRL_EXYNOS_ARM)        += pinctrl-exynos-arm.o
 obj-$(CONFIG_PINCTRL_EXYNOS_ARM64)      += pinctrl-exynos-arm64.o
-obj-$(CONFIG_PINCTRL_EXYNOS5440)        += pinctrl-exynos5440.o
 obj-$(CONFIG_PINCTRL_S3C24XX)   += pinctrl-s3c24xx.o
 obj-$(CONFIG_PINCTRL_S3C64XX)   += pinctrl-s3c64xx.o
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
index 90c274490181..d82820fc349a 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
@@ -88,6 +88,7 @@ static const struct samsung_retention_data s5pv210_retention_data __initconst =
 
 /* pin banks of s5pv210 pin-controller */
 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
@@ -105,12 +106,12 @@ static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
         EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
         EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
         EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
-        EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
         EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
         EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
         EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
         EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
+        EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
         EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
         EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
         EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
@@ -147,6 +148,7 @@ static atomic_t exynos_shared_retention_refcnt;
 
 /* pin banks of exynos3250 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb",  0x08),
@@ -158,6 +160,7 @@ static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst =
 
 /* pin banks of exynos3250 pin-controller 1 */
 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
         EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
         EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
@@ -232,6 +235,7 @@ const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = {
 
 /* pin banks of exynos4210 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
@@ -252,6 +256,7 @@ static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst =
 
 /* pin banks of exynos4210 pin-controller 1 */
 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
         EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
@@ -276,6 +281,7 @@ static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst =
 
 /* pin banks of exynos4210 pin-controller 2 */
 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
 };
 
@@ -346,6 +352,7 @@ const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = {
 
 /* pin banks of exynos4x12 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
@@ -363,6 +370,7 @@ static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst =
 
 /* pin banks of exynos4x12 pin-controller 1 */
 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
@@ -390,11 +398,13 @@ static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst =
 
 /* pin banks of exynos4x12 pin-controller 2 */
 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 };
 
 /* pin banks of exynos4x12 pin-controller 3 */
 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
@@ -449,6 +459,7 @@ const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = {
 
 /* pin banks of exynos5250 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
@@ -478,6 +489,7 @@ static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst =
 
 /* pin banks of exynos5250 pin-controller 1 */
 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
         EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
         EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
@@ -491,6 +503,7 @@ static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst =
 
 /* pin banks of exynos5250 pin-controller 2 */
 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
@@ -500,6 +513,7 @@ static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst =
 
 /* pin banks of exynos5250 pin-controller 3 */
 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 };
 
@@ -550,6 +564,7 @@ const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = {
 
 /* pin banks of exynos5260 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
         EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
@@ -575,6 +590,7 @@ static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst =
 
 /* pin banks of exynos5260 pin-controller 1 */
 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
@@ -584,6 +600,7 @@ static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst =
 
 /* pin banks of exynos5260 pin-controller 2 */
 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
 };
@@ -619,6 +636,7 @@ const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = {
 
 /* pin banks of exynos5410 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
@@ -630,7 +648,6 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst =
         EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
         EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
-        EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
         EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
@@ -641,6 +658,7 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst =
         EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
         EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
         EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
+        EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
         EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
         EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
         EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
@@ -658,6 +676,7 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst =
 
 /* pin banks of exynos5410 pin-controller 1 */
 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
@@ -671,6 +690,7 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst =
 
 /* pin banks of exynos5410 pin-controller 2 */
 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
@@ -680,6 +700,7 @@ static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst =
 
 /* pin banks of exynos5410 pin-controller 3 */
 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 };
 
@@ -727,6 +748,7 @@ const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = {
 
 /* pin banks of exynos5420 pin-controller 0 */
 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
@@ -736,6 +758,7 @@ static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst =
 
 /* pin banks of exynos5420 pin-controller 1 */
 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
@@ -753,6 +776,7 @@ static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst =
 
 /* pin banks of exynos5420 pin-controller 2 */
 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
         EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
         EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
@@ -765,6 +789,7 @@ static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst =
 
 /* pin banks of exynos5420 pin-controller 3 */
 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
@@ -778,6 +803,7 @@ static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst =
 
 /* pin banks of exynos5420 pin-controller 4 */
 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 };
 
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index 71c9d1d9f345..b6e56422a700 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -45,6 +45,7 @@ static atomic_t exynos_shared_retention_refcnt;
 
 /* pin banks of exynos5433 pin-controller - ALIVE */
 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
         EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
         EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
@@ -58,27 +59,32 @@ static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst =
 
 /* pin banks of exynos5433 pin-controller - AUD */
 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
         EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
 };
 
 /* pin banks of exynos5433 pin-controller - CPIF */
 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
 };
 
 /* pin banks of exynos5433 pin-controller - eSE */
 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
 };
 
 /* pin banks of exynos5433 pin-controller - FINGER */
 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
 };
 
 /* pin banks of exynos5433 pin-controller - FSYS */
 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
         EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
         EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
@@ -89,16 +95,19 @@ static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst =
 
 /* pin banks of exynos5433 pin-controller - IMEM */
 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
 };
 
 /* pin banks of exynos5433 pin-controller - NFC */
 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
 };
 
 /* pin banks of exynos5433 pin-controller - PERIC */
 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
         EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
         EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
@@ -120,6 +129,7 @@ static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst =
 
 /* pin banks of exynos5433 pin-controller - TOUCH */
 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
 };
 
@@ -267,6 +277,7 @@ const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = {
 
 /* pin banks of exynos7 pin-controller - ALIVE */
 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
         EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
         EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
@@ -275,6 +286,7 @@ static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
 
 /* pin banks of exynos7 pin-controller - BUS0 */
 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
         EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
@@ -294,31 +306,37 @@ static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
 
 /* pin banks of exynos7 pin-controller - NFC */
 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
 };
 
 /* pin banks of exynos7 pin-controller - TOUCH */
 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
 };
 
 /* pin banks of exynos7 pin-controller - FF */
 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
 };
 
 /* pin banks of exynos7 pin-controller - ESE */
 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
 };
 
 /* pin banks of exynos7 pin-controller - FSYS0 */
 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
 };
 
 /* pin banks of exynos7 pin-controller - FSYS1 */
 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
         EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
@@ -327,6 +345,7 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
 
 /* pin banks of exynos7 pin-controller - BUS1 */
 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
@@ -340,6 +359,7 @@ static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
 };
 
 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
+        /* Must start with EINTG banks, ordered by EINT group number. */
         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
 };
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index abd43aa7eb0d..da1ec13697e7 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -99,7 +99,7 @@
 
 #define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
         {                                                       \
-                .type           = &exynos5433_bank_type_alive,  \
+                .type           = &exynos5433_bank_type_off,    \
                 .pctl_offset    = reg,                          \
                 .nr_pins        = pins,                         \
                 .eint_type      = EINT_TYPE_WKUP,               \
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
deleted file mode 100644
index 3d8d5e812839..000000000000
--- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c
+++ /dev/null
@@ -1,1005 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-//
-// pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
-//
-// Author: Thomas Abraham <thomas.ab@samsung.com>
-//
-// Copyright (c) 2012 Samsung Electronics Co., Ltd.
-//              http://www.samsung.com
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/gpio/driver.h>
-#include <linux/device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/interrupt.h>
-#include <linux/irqdomain.h>
-#include <linux/of_irq.h>
-#include "../core.h"
-
-/* EXYNOS5440 GPIO and Pinctrl register offsets */
-#define GPIO_MUX                0x00
-#define GPIO_IE                 0x04
-#define GPIO_INT                0x08
-#define GPIO_TYPE               0x0C
-#define GPIO_VAL                0x10
-#define GPIO_OE                 0x14
-#define GPIO_IN                 0x18
-#define GPIO_PE                 0x1C
-#define GPIO_PS                 0x20
-#define GPIO_SR                 0x24
-#define GPIO_DS0                0x28
-#define GPIO_DS1                0x2C
-
-#define EXYNOS5440_MAX_PINS             23
-#define EXYNOS5440_MAX_GPIO_INT 8
-#define PIN_NAME_LENGTH         10
-
-#define GROUP_SUFFIX            "-grp"
-#define FUNCTION_SUFFIX         "-mux"
-
-/*
- * pin configuration type and its value are packed together into a 16-bits.
- * The upper 8-bits represent the configuration type and the lower 8-bits
- * hold the value of the configuration type.
- */
-#define PINCFG_TYPE_MASK                0xFF
-#define PINCFG_VALUE_SHIFT              8
-#define PINCFG_VALUE_MASK               (0xFF << PINCFG_VALUE_SHIFT)
-#define PINCFG_PACK(type, value)        (((value) << PINCFG_VALUE_SHIFT) | type)
-#define PINCFG_UNPACK_TYPE(cfg)         ((cfg) & PINCFG_TYPE_MASK)
-#define PINCFG_UNPACK_VALUE(cfg)        (((cfg) & PINCFG_VALUE_MASK) >> \
-                                                PINCFG_VALUE_SHIFT)
-
-/**
- * enum pincfg_type - possible pin configuration types supported.
- * @PINCFG_TYPE_PUD: Pull up/down configuration.
- * @PINCFG_TYPE_DRV: Drive strength configuration.
- * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
- * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
- */
-enum pincfg_type {
-        PINCFG_TYPE_PUD,
-        PINCFG_TYPE_DRV,
-        PINCFG_TYPE_SKEW_RATE,
-        PINCFG_TYPE_INPUT_TYPE
-};
-
-/**
- * struct exynos5440_pin_group: represent group of pins for pincfg setting.
- * @name: name of the pin group, used to lookup the group.
- * @pins: the pins included in this group.
- * @num_pins: number of pins included in this group.
- */
-struct exynos5440_pin_group {
-        const char              *name;
-        const unsigned int      *pins;
-        u8                      num_pins;
-};
-
-/**
- * struct exynos5440_pmx_func: represent a pin function.
- * @name: name of the pin function, used to lookup the function.
- * @groups: one or more names of pin groups that provide this function.
- * @num_groups: number of groups included in @groups.
- * @function: the function number to be programmed when selected.
- */
-struct exynos5440_pmx_func {
-        const char              *name;
-        const char              **groups;
-        u8                      num_groups;
-        unsigned long           function;
-};
-
-/**
- * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
- * @reg_base: ioremapped based address of the register space.
- * @gc: gpio chip registered with gpiolib.
- * @pin_groups: list of pin groups parsed from device tree.
- * @nr_groups: number of pin groups available.
- * @pmx_functions: list of pin functions parsed from device tree.
- * @nr_functions: number of pin functions available.
- * @range: gpio range to register with pinctrl
- */
-struct exynos5440_pinctrl_priv_data {
-        void __iomem                    *reg_base;
-        struct gpio_chip                *gc;
-        struct irq_domain               *irq_domain;
-
-        const struct exynos5440_pin_group       *pin_groups;
-        unsigned int                    nr_groups;
-        const struct exynos5440_pmx_func        *pmx_functions;
-        unsigned int                    nr_functions;
-        struct pinctrl_gpio_range       range;
-};
-
-/**
- * struct exynos5440_gpio_intr_data: private data for gpio interrupts.
- * @priv: driver's private runtime data.
- * @gpio_int: gpio interrupt number.
- */
-struct exynos5440_gpio_intr_data {
-        struct exynos5440_pinctrl_priv_data     *priv;
-        unsigned int                            gpio_int;
-};
-
-/* list of all possible config options supported */
-static struct pin_config {
-        char            *prop_cfg;
-        unsigned int    cfg_type;
-} pcfgs[] = {
-        { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
-        { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
-        { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
-        { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
-};
-
-/* check if the selector is a valid pin group selector */
-static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
-{
-        struct exynos5440_pinctrl_priv_data *priv;
-
-        priv = pinctrl_dev_get_drvdata(pctldev);
-        return priv->nr_groups;
-}
-
-/* return the name of the group selected by the group selector */
-static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
-                                                unsigned selector)
-{
-        struct exynos5440_pinctrl_priv_data *priv;
-
-        priv = pinctrl_dev_get_drvdata(pctldev);
-        return priv->pin_groups[selector].name;
-}
-
-/* return the pin numbers associated with the specified group */
-static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
-                unsigned selector, const unsigned **pins, unsigned *num_pins)
-{
-        struct exynos5440_pinctrl_priv_data *priv;
-
-        priv = pinctrl_dev_get_drvdata(pctldev);
-        *pins = priv->pin_groups[selector].pins;
-        *num_pins = priv->pin_groups[selector].num_pins;
-        return 0;
-}
-
-/* create pinctrl_map entries by parsing device tree nodes */
-static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
-                        struct device_node *np, struct pinctrl_map **maps,
-                        unsigned *nmaps)
-{
-        struct device *dev = pctldev->dev;
-        struct pinctrl_map *map;
-        unsigned long *cfg = NULL;
-        char *gname, *fname;
-        int cfg_cnt = 0, map_cnt = 0, idx = 0;
-
-        /* count the number of config options specfied in the node */
-        for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
-                if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
-                        cfg_cnt++;
-
-        /*
-         * Find out the number of map entries to create. All the config options
-         * can be accomadated into a single config map entry.
-         */
-        if (cfg_cnt)
-                map_cnt = 1;
-        if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
-                map_cnt++;
-        if (!map_cnt) {
-                dev_err(dev, "node %s does not have either config or function "
-                                "configurations\n", np->name);
-                return -EINVAL;
-        }
-
-        /* Allocate memory for pin-map entries */
-        map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
-        if (!map)
-                return -ENOMEM;
-        *nmaps = 0;
-
-        /*
-         * Allocate memory for pin group name. The pin group name is derived
-         * from the node name from which these map entries are be created.
-         */
-        gname = kasprintf(GFP_KERNEL, "%s%s", np->name, GROUP_SUFFIX);
-        if (!gname)
-                goto free_map;
-
-        /*
-         * don't have config options? then skip over to creating function
-         * map entries.
-         */
-        if (!cfg_cnt)
-                goto skip_cfgs;
-
-        /* Allocate memory for config entries */
-        cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
-        if (!cfg)
-                goto free_gname;
-
-        /* Prepare a list of config settings */
-        for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
-                u32 value;
-                if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
-                        cfg[cfg_cnt++] =
-                                PINCFG_PACK(pcfgs[idx].cfg_type, value);
-        }
-
-        /* create the config map entry */
-        map[*nmaps].data.configs.group_or_pin = gname;
-        map[*nmaps].data.configs.configs = cfg;
-        map[*nmaps].data.configs.num_configs = cfg_cnt;
-        map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
-        *nmaps += 1;
-
-skip_cfgs:
-        /* create the function map entry */
-        if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
-                fname = kasprintf(GFP_KERNEL,
-                                  "%s%s", np->name, FUNCTION_SUFFIX);
-                if (!fname)
-                        goto free_cfg;
-
-                map[*nmaps].data.mux.group = gname;
-                map[*nmaps].data.mux.function = fname;
-                map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
-                *nmaps += 1;
-        }
-
-        *maps = map;
-        return 0;
-
-free_cfg:
-        kfree(cfg);
-free_gname:
-        kfree(gname);
-free_map:
-        kfree(map);
-        return -ENOMEM;
-}
-
-/* free the memory allocated to hold the pin-map table */
-static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
-                             struct pinctrl_map *map, unsigned num_maps)
-{
-        int idx;
-
-        for (idx = 0; idx < num_maps; idx++) {
-                if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
-                        kfree(map[idx].data.mux.function);
-                        if (!idx)
-                                kfree(map[idx].data.mux.group);
-                } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
-                        kfree(map[idx].data.configs.configs);
-                        if (!idx)
-                                kfree(map[idx].data.configs.group_or_pin);
-                }
-        }
-
-        kfree(map);
-}
-
-/* list of pinctrl callbacks for the pinctrl core */
-static const struct pinctrl_ops exynos5440_pctrl_ops = {
-        .get_groups_count       = exynos5440_get_group_count,
-        .get_group_name         = exynos5440_get_group_name,
-        .get_group_pins         = exynos5440_get_group_pins,
-        .dt_node_to_map         = exynos5440_dt_node_to_map,
-        .dt_free_map            = exynos5440_dt_free_map,
-};
-
-/* check if the selector is a valid pin function selector */
-static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
-{
-        struct exynos5440_pinctrl_priv_data *priv;
-
-        priv = pinctrl_dev_get_drvdata(pctldev);
-        return priv->nr_functions;
-}
-
-/* return the name of the pin function specified */
-static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
-                                                unsigned selector)
-{
-        struct exynos5440_pinctrl_priv_data *priv;
-
-        priv = pinctrl_dev_get_drvdata(pctldev);
-        return priv->pmx_functions[selector].name;
-}
-
-/* return the groups associated for the specified function selector */
-static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
-                unsigned selector, const char * const **groups,
-                unsigned * const num_groups)
-{
-        struct exynos5440_pinctrl_priv_data *priv;
-
-        priv = pinctrl_dev_get_drvdata(pctldev);
-        *groups = priv->pmx_functions[selector].groups;
-        *num_groups = priv->pmx_functions[selector].num_groups;
-        return 0;
-}
-
-/* enable or disable a pinmux function */
-static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
-                                        unsigned group, bool enable)
-{
-        struct exynos5440_pinctrl_priv_data *priv;
-        void __iomem *base;
-        u32 function;
-        u32 data;
-
-        priv = pinctrl_dev_get_drvdata(pctldev);
-        base = priv->reg_base;
-        function = priv->pmx_functions[selector].function;
-
-        data = readl(base + GPIO_MUX);
-        if (enable)
-                data |= (1 << function);
-        else
-                data &= ~(1 << function);
-        writel(data, base + GPIO_MUX);
-}
-
-/* enable a specified pinmux by writing to registers */
-static int exynos5440_pinmux_set_mux(struct pinctrl_dev *pctldev,
-                                     unsigned selector,
-                                     unsigned group)
-{
-        exynos5440_pinmux_setup(pctldev, selector, group, true);
-        return 0;
-}
-
-/*
- * The calls to gpio_direction_output() and gpio_direction_input()
- * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
- * function called from the gpiolib interface).
- */
-static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
-                struct pinctrl_gpio_range *range, unsigned offset, bool input)
-{
-        return 0;
-}
-
-/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
-static const struct pinmux_ops exynos5440_pinmux_ops = {
-        .get_functions_count    = exynos5440_get_functions_count,
-        .get_function_name      = exynos5440_pinmux_get_fname,
-        .get_function_groups    = exynos5440_pinmux_get_groups,
-        .set_mux                = exynos5440_pinmux_set_mux,
-        .gpio_set_direction     = exynos5440_pinmux_gpio_set_direction,
-};
-
-/* set the pin config settings for a specified pin */
-static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
-                                unsigned long *configs,
-                                unsigned num_configs)
-{
-        struct exynos5440_pinctrl_priv_data *priv;
-        void __iomem *base;
-        enum pincfg_type cfg_type;
-        u32 cfg_value;
-        u32 data;
-        int i;
-
-        priv = pinctrl_dev_get_drvdata(pctldev);
-        base = priv->reg_base;
-
-        for (i = 0; i < num_configs; i++) {
-                cfg_type = PINCFG_UNPACK_TYPE(configs[i]);
-                cfg_value = PINCFG_UNPACK_VALUE(configs[i]);
-
-                switch (cfg_type) {
-                case PINCFG_TYPE_PUD:
-                        /* first set pull enable/disable bit */
-                        data = readl(base + GPIO_PE);
-                        data &= ~(1 << pin);
-                        if (cfg_value)
-                                data |= (1 << pin);
-                        writel(data, base + GPIO_PE);
-
-                        /* then set pull up/down bit */
-                        data = readl(base + GPIO_PS);
-                        data &= ~(1 << pin);
-                        if (cfg_value == 2)
-                                data |= (1 << pin);
-                        writel(data, base + GPIO_PS);
-                        break;
-
-                case PINCFG_TYPE_DRV:
-                        /* set the first bit of the drive strength */
-                        data = readl(base + GPIO_DS0);
-                        data &= ~(1 << pin);
-                        data |= ((cfg_value & 1) << pin);
-                        writel(data, base + GPIO_DS0);
-                        cfg_value >>= 1;
-
-                        /* set the second bit of the driver strength */
-                        data = readl(base + GPIO_DS1);
-                        data &= ~(1 << pin);
-                        data |= ((cfg_value & 1) << pin);
-                        writel(data, base + GPIO_DS1);
-                        break;
-                case PINCFG_TYPE_SKEW_RATE:
-                        data = readl(base + GPIO_SR);
-                        data &= ~(1 << pin);
-                        data |= ((cfg_value & 1) << pin);
-                        writel(data, base + GPIO_SR);
-                        break;
-                case PINCFG_TYPE_INPUT_TYPE:
-                        data = readl(base + GPIO_TYPE);
-                        data &= ~(1 << pin);
-                        data |= ((cfg_value & 1) << pin);
-                        writel(data, base + GPIO_TYPE);
-                        break;
-                default:
-                        WARN_ON(1);
-                        return -EINVAL;
-                }
-        } /* for each config */
-
-        return 0;
-}
-
-/* get the pin config settings for a specified pin */
-static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
-                                        unsigned long *config)
-{
-        struct exynos5440_pinctrl_priv_data *priv;
-        void __iomem *base;
-        enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
-        u32 data;
-
-        priv = pinctrl_dev_get_drvdata(pctldev);
-        base = priv->reg_base;
-
-        switch (cfg_type) {
-        case PINCFG_TYPE_PUD:
-                data = readl(base + GPIO_PE);
-                data = (data >> pin) & 1;
-                if (!data)
-                        *config = 0;
-                else
-                        *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
-                break;
-        case PINCFG_TYPE_DRV:
-                data = readl(base + GPIO_DS0);
-                data = (data >> pin) & 1;
-                *config = data;
-                data = readl(base + GPIO_DS1);
-                data = (data >> pin) & 1;
-                *config |= (data << 1);
-                break;
-        case PINCFG_TYPE_SKEW_RATE:
-                data = readl(base + GPIO_SR);
-                *config = (data >> pin) & 1;
-                break;
-        case PINCFG_TYPE_INPUT_TYPE:
-                data = readl(base + GPIO_TYPE);
-                *config = (data >> pin) & 1;
-                break;
-        default:
-                WARN_ON(1);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-/* set the pin config settings for a specified pin group */
-static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
-                        unsigned group, unsigned long *configs,
-                        unsigned num_configs)
-{
-        struct exynos5440_pinctrl_priv_data *priv;
-        const unsigned int *pins;
-        unsigned int cnt;
-
-        priv = pinctrl_dev_get_drvdata(pctldev);
-        pins = priv->pin_groups[group].pins;
-
-        for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
-                exynos5440_pinconf_set(pctldev, pins[cnt], configs,
-                                       num_configs);
-
-        return 0;
-}
-
-/* get the pin config settings for a specified pin group */
-static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
-                                unsigned int group, unsigned long *config)
-{
-        struct exynos5440_pinctrl_priv_data *priv;
-        const unsigned int *pins;
-
-        priv = pinctrl_dev_get_drvdata(pctldev);
-        pins = priv->pin_groups[group].pins;
-        exynos5440_pinconf_get(pctldev, pins[0], config);
-        return 0;
-}
-
-/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
-static const struct pinconf_ops exynos5440_pinconf_ops = {
-        .pin_config_get         = exynos5440_pinconf_get,
-        .pin_config_set         = exynos5440_pinconf_set,
-        .pin_config_group_get   = exynos5440_pinconf_group_get,
-        .pin_config_group_set   = exynos5440_pinconf_group_set,
-};
-
-/* gpiolib gpio_set callback function */
-static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
-{
-        struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc);
-        void __iomem *base = priv->reg_base;
-        u32 data;
-
-        data = readl(base + GPIO_VAL);
-        data &= ~(1 << offset);
-        if (value)
-                data |= 1 << offset;
-        writel(data, base + GPIO_VAL);
-}
-
-/* gpiolib gpio_get callback function */
-static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
-{
-        struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc);
-        void __iomem *base = priv->reg_base;
-        u32 data;
-
-        data = readl(base + GPIO_IN);
-        data >>= offset;
-        data &= 1;
-        return data;
-}
-
-/* gpiolib gpio_direction_input callback function */
-static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
-{
-        struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc);
-        void __iomem *base = priv->reg_base;
-        u32 data;
-
-        /* first disable the data output enable on this pin */
-        data = readl(base + GPIO_OE);
-        data &= ~(1 << offset);
-        writel(data, base + GPIO_OE);
-
-        /* now enable input on this pin */
-        data =  readl(base + GPIO_IE);
-        data |= 1 << offset;
-        writel(data, base + GPIO_IE);
-        return 0;
-}
-
-/* gpiolib gpio_direction_output callback function */
-static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
-                                                        int value)
-{
-        struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc);
-        void __iomem *base = priv->reg_base;
-        u32 data;
-
-        exynos5440_gpio_set(gc, offset, value);
-
-        /* first disable the data input enable on this pin */
-        data = readl(base + GPIO_IE);
-        data &= ~(1 << offset);
-        writel(data, base + GPIO_IE);
-
-        /* now enable output on this pin */
-        data =  readl(base + GPIO_OE);
-        data |= 1 << offset;
-        writel(data, base + GPIO_OE);
-        return 0;
-}
-
-/* gpiolib gpio_to_irq callback function */
-static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
-{
-        struct exynos5440_pinctrl_priv_data *priv = gpiochip_get_data(gc);
-        unsigned int virq;
-
-        if (offset < 16 || offset > 23)
-                return -ENXIO;
-
-        if (!priv->irq_domain)
-                return -ENXIO;
-
-        virq = irq_create_mapping(priv->irq_domain, offset - 16);
-        return virq ? : -ENXIO;
-}
-
-/* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
-static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
-                        struct device_node *cfg_np, unsigned int **pin_list,
-                        unsigned int *npins)
-{
-        struct device *dev = &pdev->dev;
-        struct property *prop;
-
-        prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
-        if (!prop)
-                return -ENOENT;
-
-        *npins = prop->length / sizeof(unsigned long);
-        if (!*npins) {
-                dev_err(dev, "invalid pin list in %s node", cfg_np->name);
-                return -EINVAL;
-        }
-
-        *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
-        if (!*pin_list)
-                return -ENOMEM;
-
-        return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
-                        *pin_list, *npins);
-}
-
-/*
- * Parse the information about all the available pin groups and pin functions
- * from device node of the pin-controller.
- */
-static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
-                                struct exynos5440_pinctrl_priv_data *priv)
-{
-        struct device *dev = &pdev->dev;
-        struct device_node *dev_np = dev->of_node;
-        struct device_node *cfg_np;
-        struct exynos5440_pin_group *groups, *grp;
-        struct exynos5440_pmx_func *functions, *func;
-        unsigned *pin_list;
-        unsigned int npins, grp_cnt, func_idx = 0;
-        char *gname, *fname;
-        int ret;
-
-        grp_cnt = of_get_child_count(dev_np);
-        if (!grp_cnt)
-                return -EINVAL;
-
-        groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
-        if (!groups)
-                return -EINVAL;
-
-        grp = groups;
-
-        functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
-        if (!functions)
-                return -EINVAL;
-
-        func = functions;
-
-        /*
-         * Iterate over all the child nodes of the pin controller node
-         * and create pin groups and pin function lists.
-         */
-        for_each_child_of_node(dev_np, cfg_np) {
-                u32 function;
-
-                ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
-                                        &pin_list, &npins);
-                if (ret) {
-                        gname = NULL;
-                        goto skip_to_pin_function;
-                }
-
-                /* derive pin group name from the node name */
-                gname = devm_kasprintf(dev, GFP_KERNEL,
-                                       "%s%s", cfg_np->name, GROUP_SUFFIX);
-                if (!gname)
-                        return -ENOMEM;
-
-                grp->name = gname;
-                grp->pins = pin_list;
-                grp->num_pins = npins;
-                grp++;
-
-skip_to_pin_function:
-                ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
-                                                &function);
-                if (ret)
-                        continue;
-
-                /* derive function name from the node name */
-                fname = devm_kasprintf(dev, GFP_KERNEL,
-                                       "%s%s", cfg_np->name, FUNCTION_SUFFIX);
-                if (!fname)
-                        return -ENOMEM;
-
-                func->name = fname;
-                func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
-                if (!func->groups)
-                        return -ENOMEM;
-                func->groups[0] = gname;
-                func->num_groups = gname ? 1 : 0;
-                func->function = function;
-                func++;
-                func_idx++;
-        }
-
-        priv->pin_groups = groups;
-        priv->nr_groups = grp_cnt;
-        priv->pmx_functions = functions;
-        priv->nr_functions = func_idx;
-        return 0;
-}
-
-/* register the pinctrl interface with the pinctrl subsystem */
-static int exynos5440_pinctrl_register(struct platform_device *pdev,
-                                struct exynos5440_pinctrl_priv_data *priv)
-{
-        struct device *dev = &pdev->dev;
-        struct pinctrl_desc *ctrldesc;
-        struct pinctrl_dev *pctl_dev;
-        struct pinctrl_pin_desc *pindesc, *pdesc;
-        char *pin_names;
-        int pin, ret;
-
-        ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
-        if (!ctrldesc)
-                return -ENOMEM;
-
-        ctrldesc->name = "exynos5440-pinctrl";
-        ctrldesc->owner = THIS_MODULE;
-        ctrldesc->pctlops = &exynos5440_pctrl_ops;
-        ctrldesc->pmxops = &exynos5440_pinmux_ops;
-        ctrldesc->confops = &exynos5440_pinconf_ops;
-
-        pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
-                                EXYNOS5440_MAX_PINS, GFP_KERNEL);
-        if (!pindesc)
-                return -ENOMEM;
-        ctrldesc->pins = pindesc;
-        ctrldesc->npins = EXYNOS5440_MAX_PINS;
-
-        /* dynamically populate the pin number and pin name for pindesc */
-        for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
-                pdesc->number = pin;
-
-        /*
-         * allocate space for storing the dynamically generated names for all
-         * the pins which belong to this pin-controller.
-         */
-        pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
-                                        ctrldesc->npins, GFP_KERNEL);
-        if (!pin_names)
-                return -ENOMEM;
-
-        /* for each pin, set the name of the pin */
-        for (pin = 0; pin < ctrldesc->npins; pin++) {
-                snprintf(pin_names, 6, "gpio%02d", pin);
-                pdesc = pindesc + pin;
-                pdesc->name = pin_names;
-                pin_names += PIN_NAME_LENGTH;
-        }
-
-        ret = exynos5440_pinctrl_parse_dt(pdev, priv);
-        if (ret)
-                return ret;
-
-        pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, priv);
-        if (IS_ERR(pctl_dev)) {
-                dev_err(&pdev->dev, "could not register pinctrl driver\n");
-                return PTR_ERR(pctl_dev);
-        }
-
-        priv->range.name = "exynos5440-pctrl-gpio-range";
-        priv->range.id = 0;
-        priv->range.base = 0;
-        priv->range.npins = EXYNOS5440_MAX_PINS;
-        priv->range.gc = priv->gc;
-        pinctrl_add_gpio_range(pctl_dev, &priv->range);
-        return 0;
-}
-
-/* register the gpiolib interface with the gpiolib subsystem */
-static int exynos5440_gpiolib_register(struct platform_device *pdev,
-                                struct exynos5440_pinctrl_priv_data *priv)
-{
-        struct gpio_chip *gc;
-        int ret;
-
-        gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
-        if (!gc)
-                return -ENOMEM;
-
-        priv->gc = gc;
-        gc->base = 0;
-        gc->ngpio = EXYNOS5440_MAX_PINS;
-        gc->parent = &pdev->dev;
-        gc->set = exynos5440_gpio_set;
-        gc->get = exynos5440_gpio_get;
-        gc->direction_input = exynos5440_gpio_direction_input;
-        gc->direction_output = exynos5440_gpio_direction_output;
-        gc->to_irq = exynos5440_gpio_to_irq;
-        gc->label = "gpiolib-exynos5440";
-        gc->owner = THIS_MODULE;
-        ret = gpiochip_add_data(gc, priv);
-        if (ret) {
-                dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
-                                        "code: %d\n", gc->label, ret);
-                return ret;
-        }
-
-        return 0;
-}
-
-/* unregister the gpiolib interface with the gpiolib subsystem */
-static int exynos5440_gpiolib_unregister(struct platform_device *pdev,
-                                struct exynos5440_pinctrl_priv_data *priv)
-{
-        gpiochip_remove(priv->gc);
-        return 0;
-}
-
-static void exynos5440_gpio_irq_unmask(struct irq_data *irqd)
-{
-        struct exynos5440_pinctrl_priv_data *d;
-        unsigned long gpio_int;
-
-        d = irq_data_get_irq_chip_data(irqd);
-        gpio_int = readl(d->reg_base + GPIO_INT);
-        gpio_int |= 1 << irqd->hwirq;
-        writel(gpio_int, d->reg_base + GPIO_INT);
-}
-
-static void exynos5440_gpio_irq_mask(struct irq_data *irqd)
-{
-        struct exynos5440_pinctrl_priv_data *d;
-        unsigned long gpio_int;
-
-        d = irq_data_get_irq_chip_data(irqd);
-        gpio_int = readl(d->reg_base + GPIO_INT);
-        gpio_int &= ~(1 << irqd->hwirq);
-        writel(gpio_int, d->reg_base + GPIO_INT);
-}
-
-/* irq_chip for gpio interrupts */
-static struct irq_chip exynos5440_gpio_irq_chip = {
-        .name           = "exynos5440_gpio_irq_chip",
-        .irq_unmask     = exynos5440_gpio_irq_unmask,
-        .irq_mask       = exynos5440_gpio_irq_mask,
-};
-
-/* interrupt handler for GPIO interrupts 0..7 */
-static irqreturn_t exynos5440_gpio_irq(int irq, void *data)
-{
-        struct exynos5440_gpio_intr_data *intd = data;
-        struct exynos5440_pinctrl_priv_data *d = intd->priv;
-        int virq;
-
-        virq = irq_linear_revmap(d->irq_domain, intd->gpio_int);
-        if (!virq)
-                return IRQ_NONE;
-        generic_handle_irq(virq);
-        return IRQ_HANDLED;
-}
-
-static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq,
-                                        irq_hw_number_t hw)
-{
-        struct exynos5440_pinctrl_priv_data *d = h->host_data;
-
-        irq_set_chip_data(virq, d);
-        irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip,
-                                        handle_level_irq);
-        return 0;
-}
-
-/* irq domain callbacks for gpio interrupt controller */
-static const struct irq_domain_ops exynos5440_gpio_irqd_ops = {
-        .map    = exynos5440_gpio_irq_map,
-        .xlate  = irq_domain_xlate_twocell,
-};
-
-/* setup handling of gpio interrupts */
-static int exynos5440_gpio_irq_init(struct platform_device *pdev,
-                                struct exynos5440_pinctrl_priv_data *priv)
-{
-        struct device *dev = &pdev->dev;
-        struct exynos5440_gpio_intr_data *intd;
-        int i, irq, ret;
-
-        intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT,
-                                        GFP_KERNEL);
-        if (!intd)
-                return -ENOMEM;
-
-        for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) {
-                irq = irq_of_parse_and_map(dev->of_node, i);
-                if (irq <= 0) {
-                        dev_err(dev, "irq parsing failed\n");
-                        return -EINVAL;
-                }
-
-                intd->gpio_int = i;
-                intd->priv = priv;
-                ret = devm_request_irq(dev, irq, exynos5440_gpio_irq,
-                                        0, dev_name(dev), intd++);
-                if (ret) {
-                        dev_err(dev, "irq request failed\n");
-                        return -ENXIO;
-                }
-        }
-
-        priv->irq_domain = irq_domain_add_linear(dev->of_node,
-                                EXYNOS5440_MAX_GPIO_INT,
-                                &exynos5440_gpio_irqd_ops, priv);
-        if (!priv->irq_domain) {
-                dev_err(dev, "failed to create irq domain\n");
-                return -ENXIO;
-        }
-
-        return 0;
-}
-
-static int exynos5440_pinctrl_probe(struct platform_device *pdev)
-{
-        struct device *dev = &pdev->dev;
-        struct exynos5440_pinctrl_priv_data *priv;
-        struct resource *res;
-        int ret;
-
-        if (!dev->of_node) {
-                dev_err(dev, "device tree node not found\n");
-                return -ENODEV;
-        }
-
-        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-        if (!priv)
-                return -ENOMEM;
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
-        if (IS_ERR(priv->reg_base))
-                return PTR_ERR(priv->reg_base);
-
-        ret = exynos5440_gpiolib_register(pdev, priv);
-        if (ret)
-                return ret;
-
-        ret = exynos5440_pinctrl_register(pdev, priv);
-        if (ret) {
-                exynos5440_gpiolib_unregister(pdev, priv);
-                return ret;
-        }
-
-        ret = exynos5440_gpio_irq_init(pdev, priv);
-        if (ret) {
-                dev_err(dev, "failed to setup gpio interrupts\n");
-                return ret;
-        }
-
-        platform_set_drvdata(pdev, priv);
-        dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
-        return 0;
-}
-
-static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
-        { .compatible = "samsung,exynos5440-pinctrl" },
-        {},
-};
-
-static struct platform_driver exynos5440_pinctrl_driver = {
-        .probe          = exynos5440_pinctrl_probe,
-        .driver = {
-                .name   = "exynos5440-pinctrl",
-                .of_match_table = exynos5440_pinctrl_dt_match,
-                .suppress_bind_attrs = true,
-        },
-};
-
-static int __init exynos5440_pinctrl_drv_register(void)
-{
-        return platform_driver_register(&exynos5440_pinctrl_driver);
-}
-postcore_initcall(exynos5440_pinctrl_drv_register);
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 336e88d7bdb9..618945a0fd38 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -279,6 +279,32 @@ static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev,
         return 0;
 }
 
+#ifdef CONFIG_DEBUG_FS
+/* Forward declaration which can be used by samsung_pin_dbg_show */
+static int samsung_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
+                                        unsigned long *config);
+static const char * const reg_names[] = {"CON", "DAT", "PUD", "DRV", "CON_PDN",
+                                         "PUD_PDN"};
+
+static void samsung_pin_dbg_show(struct pinctrl_dev *pctldev,
+                                struct seq_file *s, unsigned int pin)
+{
+        enum pincfg_type cfg_type;
+        unsigned long config;
+        int ret;
+
+        for (cfg_type = 0; cfg_type < PINCFG_TYPE_NUM; cfg_type++) {
+                config = PINCFG_PACK(cfg_type, 0);
+                ret = samsung_pinconf_get(pctldev, pin, &config);
+                if (ret < 0)
+                        continue;
+
+                seq_printf(s, " %s(0x%lx)", reg_names[cfg_type],
+                           PINCFG_UNPACK_VALUE(config));
+        }
+}
+#endif
+
 /* list of pinctrl callbacks for the pinctrl core */
 static const struct pinctrl_ops samsung_pctrl_ops = {
         .get_groups_count       = samsung_get_group_count,
@@ -286,6 +312,9 @@ static const struct pinctrl_ops samsung_pctrl_ops = {
         .get_group_pins         = samsung_get_group_pins,
         .dt_node_to_map         = samsung_dt_node_to_map,
         .dt_free_map            = samsung_dt_free_map,
+#ifdef CONFIG_DEBUG_FS
+        .pin_dbg_show           = samsung_pin_dbg_show,
+#endif
 };
 
 /* check if the selector is a valid pin function selector */
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index c11b789ec583..43d950c16528 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -44,6 +44,11 @@ config PINCTRL_PFC_R8A7745
         depends on ARCH_R8A7745
         select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A77470
+        def_bool y
+        depends on ARCH_R8A77470
+        select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A7778
         def_bool y
         depends on ARCH_R8A7778
@@ -104,6 +109,11 @@ config PINCTRL_PFC_R8A77980
         depends on ARCH_R8A77980
         select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A77990
+        def_bool y
+        depends on ARCH_R8A77990
+        select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A77995
         def_bool y
         depends on ARCH_R8A77995
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 463775f28cf1..d0b29c51c159 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A73A4)	+= pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)       += pfc-r8a7740.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7743)       += pfc-r8a7791.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7745)       += pfc-r8a7794.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77470)      += pfc-r8a77470.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7778)       += pfc-r8a7778.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7779)       += pfc-r8a7779.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7790)       += pfc-r8a7790.o
@@ -19,6 +20,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7796)	+= pfc-r8a7796.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77965)      += pfc-r8a77965.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77970)      += pfc-r8a77970.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77980)      += pfc-r8a77980.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77990)      += pfc-r8a77990.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77995)      += pfc-r8a77995.o
 obj-$(CONFIG_PINCTRL_PFC_SH7203)        += pfc-sh7203.o
 obj-$(CONFIG_PINCTRL_PFC_SH7264)        += pfc-sh7264.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 74861b7b5b0d..eb06981538b4 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -503,6 +503,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
                 .data = &r8a7745_pinmux_info,
         },
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77470
+        {
+                .compatible = "renesas,pfc-r8a77470",
+                .data = &r8a77470_pinmux_info,
+        },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A7778
         {
                 .compatible = "renesas,pfc-r8a7778",
@@ -575,6 +581,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
                 .data = &r8a77980_pinmux_info,
         },
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A77990
+        {
+                .compatible = "renesas,pfc-r8a77990",
+                .data = &r8a77990_pinmux_info,
+        },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A77995
         {
                 .compatible = "renesas,pfc-r8a77995",
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
new file mode 100644
index 000000000000..9d3ed438ec7b
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
@@ -0,0 +1,2343 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R8A77470 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include <linux/kernel.h>
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx)                                           \
+        PORT_GP_23(0, fn, sfx),                                         \
+        PORT_GP_23(1, fn, sfx),                                         \
+        PORT_GP_32(2, fn, sfx),                                         \
+        PORT_GP_17(3, fn, sfx),                                         \
+        PORT_GP_1(3, 27, fn, sfx),                                      \
+        PORT_GP_1(3, 28, fn, sfx),                                      \
+        PORT_GP_1(3, 29, fn, sfx),                                      \
+        PORT_GP_26(4, fn, sfx),                                         \
+        PORT_GP_32(5, fn, sfx)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        GP_ALL(DATA),
+        PINMUX_DATA_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        GP_ALL(FN),
+
+        /* GPSR0 */
+        FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, FN_CLKOUT,
+        FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8, FN_IP0_15_12, FN_IP0_19_16,
+        FN_IP0_23_20, FN_IP0_27_24, FN_IP0_31_28, FN_MMC0_CLK_SDHI1_CLK,
+        FN_MMC0_CMD_SDHI1_CMD, FN_MMC0_D0_SDHI1_D0, FN_MMC0_D1_SDHI1_D1,
+        FN_MMC0_D2_SDHI1_D2, FN_MMC0_D3_SDHI1_D3, FN_IP1_3_0,
+        FN_IP1_7_4, FN_MMC0_D6, FN_MMC0_D7,
+
+        /* GPSR1 */
+        FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20, FN_IP1_27_24,
+        FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
+        FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24, FN_IP2_31_28, FN_IP3_3_0,
+        FN_IP3_7_4, FN_IP3_11_8, FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20,
+        FN_IP3_27_24, FN_IP3_31_28, FN_IP4_3_0,
+
+        /* GPSR2 */
+        FN_IP4_7_4, FN_IP4_11_8, FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20,
+        FN_IP4_27_24, FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8,
+        FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24, FN_IP5_31_28,
+        FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8, FN_IP6_15_12, FN_IP6_19_16,
+        FN_IP6_23_20, FN_IP6_27_24, FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4,
+        FN_IP7_11_8, FN_IP7_15_12, FN_IP7_19_16, FN_IP7_23_20, FN_IP7_27_24,
+        FN_IP7_31_28, FN_IP8_3_0,
+
+        /* GPSR3 */
+        FN_IP8_7_4, FN_IP8_11_8, FN_IP8_15_12, FN_IP8_19_16, FN_IP8_23_20,
+        FN_IP8_27_24, FN_IP8_31_28, FN_IP9_3_0, FN_IP9_7_4, FN_IP9_11_8,
+        FN_IP9_15_12, FN_IP9_19_16, FN_IP9_23_20, FN_IP9_27_24, FN_IP9_31_28,
+        FN_IP10_3_0, FN_IP10_7_4, FN_IP10_11_8, FN_IP10_15_12, FN_IP10_19_16,
+
+        /* GPSR4 */
+        FN_IP10_23_20, FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4,
+        FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20,
+        FN_IP11_27_24, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4, FN_IP12_11_8,
+        FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20, FN_IP12_27_24,
+        FN_IP12_31_28, FN_IP13_3_0, FN_IP13_7_4, FN_IP13_11_8, FN_IP13_15_12,
+        FN_IP13_19_16, FN_IP13_23_20, FN_IP13_27_24,
+
+        /* GPSR5 */
+        FN_IP13_31_28, FN_IP14_3_0, FN_IP14_7_4, FN_IP14_11_8, FN_IP14_15_12,
+        FN_IP14_19_16, FN_IP14_23_20, FN_IP14_27_24, FN_IP14_31_28,
+        FN_IP15_3_0, FN_IP15_7_4, FN_IP15_11_8, FN_IP15_15_12, FN_IP15_19_16,
+        FN_IP15_23_20, FN_IP15_27_24, FN_IP15_31_28, FN_IP16_3_0, FN_IP16_7_4,
+        FN_IP16_11_8, FN_IP16_15_12, FN_IP16_19_16, FN_IP16_23_20,
+        FN_IP16_27_24, FN_IP16_31_28, FN_IP17_3_0, FN_IP17_7_4, FN_IP17_11_8,
+        FN_IP17_15_12, FN_IP17_19_16, FN_IP17_23_20, FN_IP17_27_24,
+
+        /* IPSR0 */
+        FN_SD0_CLK, FN_SSI_SCK1_C, FN_RX3_C,
+        FN_SD0_CMD, FN_SSI_WS1_C, FN_TX3_C,
+        FN_SD0_DAT0, FN_SSI_SDATA1_C, FN_RX4_E,
+        FN_SD0_DAT1, FN_SSI_SCK0129_B, FN_TX4_E,
+        FN_SD0_DAT2, FN_SSI_WS0129_B, FN_RX5_E,
+        FN_SD0_DAT3, FN_SSI_SDATA0_B, FN_TX5_E,
+        FN_SD0_CD, FN_CAN0_RX_A,
+        FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A,
+
+        /* IPSR1 */
+        FN_MMC0_D4, FN_SD1_CD,
+        FN_MMC0_D5, FN_SD1_WP,
+        FN_D0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B,
+        FN_D1, FN_SDA3_B, FN_TX5_B, FN_MSIOF2_TXD_C, FN_SSI_WS5_B,
+        FN_D2, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, FN_MSIOF2_SCK_C, FN_SSI_SCK5_B,
+        FN_D3, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, FN_MSIOF2_SYNC_C,
+        FN_D4, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C,
+        FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B,
+
+        /* IPSR2 */
+        FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C,
+        FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
+        FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C,
+        FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D,
+        FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B,
+        FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B,
+        FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, FN_CAN_CLK_C,
+        FN_D13, FN_MSIOF2_SYNC_A, FN_RX4_C,
+
+        /* IPSR3 */
+        FN_D14, FN_MSIOF2_SS1, FN_TX4_C, FN_CAN1_RX_B, FN_AVB_AVTP_CAPTURE_A,
+        FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, FN_CAN1_TX_B, FN_IRQ2, FN_AVB_AVTP_MATCH_A,
+        FN_QSPI0_SPCLK, FN_WE0_N,
+        FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N,
+        FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N,
+        FN_QSPI0_IO2, FN_CS0_N,
+        FN_QSPI0_IO3, FN_RD_N,
+        FN_QSPI0_SSL, FN_WE1_N,
+
+        /* IPSR4 */
+        FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A,
+        FN_DU0_DR0, FN_RX5_C, FN_SCL2_D, FN_A0,
+        FN_DU0_DR1, FN_TX5_C, FN_SDA2_D, FN_A1,
+        FN_DU0_DR2, FN_RX0_D, FN_SCL0_E, FN_A2,
+        FN_DU0_DR3, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, FN_A3,
+        FN_DU0_DR4, FN_RX1_D, FN_A4,
+        FN_DU0_DR5, FN_TX1_D, FN_PWM1_B, FN_A5,
+        FN_DU0_DR6, FN_RX2_C, FN_A6,
+
+        /* IPSR5 */
+        FN_DU0_DR7, FN_TX2_C, FN_PWM2_B, FN_A7,
+        FN_DU0_DG0, FN_RX3_B, FN_SCL3_D, FN_A8,
+        FN_DU0_DG1, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, FN_A9,
+        FN_DU0_DG2, FN_RX4_D, FN_A10,
+        FN_DU0_DG3, FN_TX4_D, FN_PWM4_B, FN_A11,
+        FN_DU0_DG4, FN_HRX0_A, FN_A12,
+        FN_DU0_DG5, FN_HTX0_A, FN_PWM5_B, FN_A13,
+        FN_DU0_DG6, FN_HRX1_C, FN_A14,
+
+        /* IPSR6 */
+        FN_DU0_DG7, FN_HTX1_C, FN_PWM6_B, FN_A15,
+        FN_DU0_DB0, FN_SCL4_D, FN_CAN0_RX_C, FN_A16,
+        FN_DU0_DB1, FN_SDA4_D, FN_CAN0_TX_C, FN_A17,
+        FN_DU0_DB2, FN_HCTS0_N, FN_A18,
+        FN_DU0_DB3, FN_HRTS0_N, FN_A19,
+        FN_DU0_DB4, FN_HCTS1_N_C, FN_A20,
+        FN_DU0_DB5, FN_HRTS1_N_C, FN_A21,
+        FN_DU0_DB6, FN_A22,
+
+        /* IPSR7 */
+        FN_DU0_DB7, FN_A23,
+        FN_DU0_DOTCLKIN, FN_A24,
+        FN_DU0_DOTCLKOUT0, FN_A25,
+        FN_DU0_DOTCLKOUT1, FN_MSIOF2_RXD_B, FN_CS1_N_A26,
+        FN_DU0_EXHSYNC_DU0_HSYNC, FN_MSIOF2_TXD_B, FN_DREQ0_N,
+        FN_DU0_EXVSYNC_DU0_VSYNC, FN_MSIOF2_SYNC_B, FN_DACK0,
+        FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_MSIOF2_SCK_B, FN_DRACK0,
+        FN_DU0_DISP, FN_CAN1_RX_C,
+
+        /* IPSR8 */
+        FN_DU0_CDE, FN_CAN1_TX_C,
+        FN_VI1_CLK, FN_AVB_RX_CLK, FN_ETH_REF_CLK,
+        FN_VI1_DATA0, FN_AVB_RX_DV, FN_ETH_CRS_DV,
+        FN_VI1_DATA1, FN_AVB_RXD0, FN_ETH_RXD0,
+        FN_VI1_DATA2, FN_AVB_RXD1, FN_ETH_RXD1,
+        FN_VI1_DATA3, FN_AVB_RXD2, FN_ETH_MDIO,
+        FN_VI1_DATA4, FN_AVB_RXD3, FN_ETH_RX_ER,
+        FN_VI1_DATA5, FN_AVB_RXD4, FN_ETH_LINK,
+
+        /* IPSR9 */
+        FN_VI1_DATA6, FN_AVB_RXD5, FN_ETH_TXD1,
+        FN_VI1_DATA7, FN_AVB_RXD6, FN_ETH_TX_EN,
+        FN_VI1_CLKENB, FN_SCL3_A, FN_AVB_RXD7, FN_ETH_MAGIC,
+        FN_VI1_FIELD, FN_SDA3_A, FN_AVB_RX_ER, FN_ETH_TXD0,
+        FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, FN_AVB_GTXREFCLK, FN_ETH_MDC,
+        FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_CLK,
+        FN_VI1_DATA8, FN_SCL2_B, FN_AVB_TX_EN,
+        FN_VI1_DATA9, FN_SDA2_B, FN_AVB_TXD0,
+
+        /* IPSR10 */
+        FN_VI1_DATA10, FN_CAN0_RX_B, FN_AVB_TXD1,
+        FN_VI1_DATA11, FN_CAN0_TX_B, FN_AVB_TXD2,
+        FN_AVB_TXD3, FN_AUDIO_CLKA_B, FN_SSI_SCK1_D, FN_RX5_F, FN_MSIOF0_RXD_B,
+        FN_AVB_TXD4, FN_AUDIO_CLKB_B, FN_SSI_WS1_D, FN_TX5_F, FN_MSIOF0_TXD_B,
+        FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, FN_SSI_SDATA1_D, FN_MSIOF0_SCK_B,
+        FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6, FN_CAN1_RX_D, FN_MSIOF0_SYNC_B,
+        FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, FN_CAN1_TX_D, FN_DVC_MUTE,
+        FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, FN_SSI_SCK6_B, FN_VI0_G0,
+
+        /* IPSR11 */
+        FN_SDA1_A, FN_TX4_A, FN_DU1_DR1, FN_SSI_WS6_B, FN_VI0_G1,
+        FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
+        FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
+        FN_MSIOF0_SCK_A, FN_IRQ0, FN_DU1_DR4, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
+        FN_MSIOF0_SYNC_A, FN_PWM1_A, FN_DU1_DR5, FN_QSPI1_IO2, FN_SSI_SDATA7_B,
+        FN_MSIOF0_SS1_A, FN_DU1_DR6, FN_QSPI1_IO3, FN_SSI_SDATA8_B,
+        FN_MSIOF0_SS2_A, FN_DU1_DR7, FN_QSPI1_SSL,
+        FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A,
+
+        /* IPSR12 */
+        FN_HTX1_A, FN_SDA4_A, FN_DU1_DG1, FN_TX0_A,
+        FN_HCTS1_N_A, FN_PWM2_A, FN_DU1_DG2, FN_REMOCON_B,
+        FN_HRTS1_N_A, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1,
+        FN_SD2_CLK, FN_HSCK1, FN_DU1_DG4, FN_SSI_SCK1_B,
+        FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, FN_SSI_SCK2_B, FN_PWM3_A,
+        FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, FN_SSI_SDATA1_B,
+        FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
+        FN_SD2_DAT2, FN_RX2_A, FN_DU1_DB0, FN_SSI_SDATA2_B,
+
+        /* IPSR13 */
+        FN_SD2_DAT3, FN_TX2_A, FN_DU1_DB1, FN_SSI_WS9_B,
+        FN_SD2_CD, FN_SCIF2_SCK_A, FN_DU1_DB2, FN_SSI_SCK9_B,
+        FN_SD2_WP, FN_SCIF3_SCK, FN_DU1_DB3, FN_SSI_SDATA9_B,
+        FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B,
+        FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
+        FN_SCL2_A, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, FN_SSI_SCK4_B,
+        FN_SDA2_A, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
+        FN_SSI_SCK5_A, FN_DU1_DOTCLKOUT1,
+
+        /* IPSR14 */
+        FN_SSI_WS5_A, FN_SCL3_C, FN_DU1_DOTCLKIN,
+        FN_SSI_SDATA5_A, FN_SDA3_C, FN_DU1_DOTCLKOUT0,
+        FN_SSI_SCK6_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+        FN_SSI_WS6_A, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC,
+        FN_SSI_SDATA6_A, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC,
+        FN_SSI_SCK78_A, FN_SDA4_E, FN_DU1_DISP,
+        FN_SSI_WS78_A, FN_SCL4_E, FN_DU1_CDE,
+        FN_SSI_SDATA7_A, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_VI0_G5,
+
+        /* IPSR15 */
+        FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, FN_VI0_G6,
+        FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, FN_VI0_G7,
+        FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, FN_VI0_R0,
+        FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, FN_DACK1, FN_VI0_R1,
+        FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, FN_CAN1_RX_A, FN_DREQ1_N, FN_VI0_R2,
+        FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, FN_CAN1_TX_A, FN_DREQ2_N, FN_VI0_R3,
+        FN_SSI_SCK4_A, FN_AVB_MAGIC, FN_VI0_R4,
+        FN_SSI_WS4_A, FN_AVB_PHY_INT, FN_VI0_R5,
+
+        /* IPSR16 */
+        FN_SSI_SDATA4_A, FN_AVB_CRS, FN_VI0_R6,
+        FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, FN_DACK2, FN_VI0_CLK, FN_AVB_COL,
+        FN_SSI_SDATA8_A, FN_RX1_B, FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7,
+        FN_SSI_WS1_A, FN_TX1_B, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0,
+        FN_SSI_SDATA1_A, FN_HRX1_B, FN_VI0_DATA1_VI0_B1,
+        FN_SSI_SCK2_A, FN_HTX1_B, FN_AVB_TXD7, FN_VI0_DATA2_VI0_B2,
+        FN_SSI_WS2_A, FN_HCTS1_N_B, FN_AVB_TX_ER, FN_VI0_DATA3_VI0_B3,
+        FN_SSI_SDATA2_A, FN_HRTS1_N_B, FN_VI0_DATA4_VI0_B4,
+
+        /* IPSR17 */
+        FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, FN_EX_WAIT1, FN_VI0_DATA5_VI0_B5,
+        FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, FN_VI0_DATA6_VI0_B6,
+        FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, FN_VI0_DATA7_VI0_B7,
+        FN_AUDIO_CLKA_A, FN_SCL0_B, FN_VI0_CLKENB,
+        FN_AUDIO_CLKB_A, FN_SDA0_B, FN_VI0_FIELD,
+        FN_AUDIO_CLKC_A, FN_SCL4_B, FN_VI0_HSYNC_N,
+        FN_AUDIO_CLKOUT_A, FN_SDA4_B, FN_VI0_VSYNC_N,
+
+        /* MOD_SEL0 */
+        FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
+        FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
+        FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+        FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+        FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, FN_SEL_I2C04_4,
+        FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, FN_SEL_I2C03_4,
+        FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
+        FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4,
+        FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4,
+        FN_SEL_AVB_0, FN_SEL_AVB_1,
+
+        /* MOD_SEL1 */
+        FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+        FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, FN_SEL_SCIF5_4, FN_SEL_SCIF5_5,
+        FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, FN_SEL_SCIF4_4,
+        FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
+        FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
+        FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
+        FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+        FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+        FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2,
+        FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
+        FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
+        FN_SEL_RCN_0, FN_SEL_RCN_1,
+        FN_SEL_TMU2_0, FN_SEL_TMU2_1,
+        FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+        FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
+        FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
+
+        /* MOD_SEL2 */
+        FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2,
+        FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2,
+        FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+        FN_SEL_SSI8_0, FN_SEL_SSI8_1,
+        FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+        FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+        FN_SEL_SSI5_0, FN_SEL_SSI5_1,
+        FN_SEL_SSI4_0, FN_SEL_SSI4_1,
+        FN_SEL_SSI2_0, FN_SEL_SSI2_1,
+        FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
+        FN_SEL_SSI0_0, FN_SEL_SSI0_1,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+
+        USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
+        CLKOUT_MARK, MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
+        MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
+        MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D6_MARK,
+        MMC0_D7_MARK,
+
+        /* IPSR0 */
+        SD0_CLK_MARK, SSI_SCK1_C_MARK, RX3_C_MARK,
+        SD0_CMD_MARK, SSI_WS1_C_MARK, TX3_C_MARK,
+        SD0_DAT0_MARK, SSI_SDATA1_C_MARK, RX4_E_MARK,
+        SD0_DAT1_MARK, SSI_SCK0129_B_MARK, TX4_E_MARK,
+        SD0_DAT2_MARK, SSI_WS0129_B_MARK, RX5_E_MARK,
+        SD0_DAT3_MARK, SSI_SDATA0_B_MARK, TX5_E_MARK,
+        SD0_CD_MARK, CAN0_RX_A_MARK,
+        SD0_WP_MARK, IRQ7_MARK, CAN0_TX_A_MARK,
+
+        /* IPSR1 */
+        MMC0_D4_MARK, SD1_CD_MARK,
+        MMC0_D5_MARK, SD1_WP_MARK,
+        D0_MARK, SCL3_B_MARK, RX5_B_MARK, IRQ4_MARK, MSIOF2_RXD_C_MARK, SSI_SDATA5_B_MARK,
+        D1_MARK, SDA3_B_MARK, TX5_B_MARK, MSIOF2_TXD_C_MARK, SSI_WS5_B_MARK,
+        D2_MARK, RX4_B_MARK, SCL0_D_MARK, PWM1_C_MARK, MSIOF2_SCK_C_MARK, SSI_SCK5_B_MARK,
+        D3_MARK, TX4_B_MARK, SDA0_D_MARK, PWM0_A_MARK, MSIOF2_SYNC_C_MARK,
+        D4_MARK, IRQ3_MARK, TCLK1_A_MARK, PWM6_C_MARK,
+        D5_MARK, HRX2_MARK, SCL1_B_MARK, PWM2_C_MARK, TCLK2_B_MARK,
+
+        /* IPSR2 */
+        D6_MARK, HTX2_MARK, SDA1_B_MARK, PWM4_C_MARK,
+        D7_MARK, HSCK2_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
+        D8_MARK, HCTS2_N_MARK, RX1_C_MARK, SCL1_D_MARK, PWM3_C_MARK,
+        D9_MARK, HRTS2_N_MARK, TX1_C_MARK, SDA1_D_MARK,
+        D10_MARK, MSIOF2_RXD_A_MARK, HRX0_B_MARK,
+        D11_MARK, MSIOF2_TXD_A_MARK, HTX0_B_MARK,
+        D12_MARK, MSIOF2_SCK_A_MARK, HSCK0_MARK, CAN_CLK_C_MARK,
+        D13_MARK, MSIOF2_SYNC_A_MARK, RX4_C_MARK,
+
+        /* IPSR3 */
+        D14_MARK, MSIOF2_SS1_MARK, TX4_C_MARK, CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_A_MARK,
+        D15_MARK, MSIOF2_SS2_MARK, PWM4_A_MARK, CAN1_TX_B_MARK, IRQ2_MARK, AVB_AVTP_MATCH_A_MARK,
+        QSPI0_SPCLK_MARK, WE0_N_MARK,
+        QSPI0_MOSI_QSPI0_IO0_MARK, BS_N_MARK,
+        QSPI0_MISO_QSPI0_IO1_MARK, RD_WR_N_MARK,
+        QSPI0_IO2_MARK, CS0_N_MARK,
+        QSPI0_IO3_MARK, RD_N_MARK,
+        QSPI0_SSL_MARK, WE1_N_MARK,
+
+        /* IPSR4 */
+        EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_A_MARK,
+        DU0_DR0_MARK, RX5_C_MARK, SCL2_D_MARK, A0_MARK,
+        DU0_DR1_MARK, TX5_C_MARK, SDA2_D_MARK, A1_MARK,
+        DU0_DR2_MARK, RX0_D_MARK, SCL0_E_MARK, A2_MARK,
+        DU0_DR3_MARK, TX0_D_MARK, SDA0_E_MARK, PWM0_B_MARK, A3_MARK,
+        DU0_DR4_MARK, RX1_D_MARK, A4_MARK,
+        DU0_DR5_MARK, TX1_D_MARK, PWM1_B_MARK, A5_MARK,
+        DU0_DR6_MARK, RX2_C_MARK, A6_MARK,
+
+        /* IPSR5 */
+        DU0_DR7_MARK, TX2_C_MARK, PWM2_B_MARK, A7_MARK,
+        DU0_DG0_MARK, RX3_B_MARK, SCL3_D_MARK, A8_MARK,
+        DU0_DG1_MARK, TX3_B_MARK, SDA3_D_MARK, PWM3_B_MARK, A9_MARK,
+        DU0_DG2_MARK, RX4_D_MARK, A10_MARK,
+        DU0_DG3_MARK, TX4_D_MARK, PWM4_B_MARK, A11_MARK,
+        DU0_DG4_MARK, HRX0_A_MARK, A12_MARK,
+        DU0_DG5_MARK, HTX0_A_MARK, PWM5_B_MARK, A13_MARK,
+        DU0_DG6_MARK, HRX1_C_MARK, A14_MARK,
+
+        /* IPSR6 */
+        DU0_DG7_MARK, HTX1_C_MARK, PWM6_B_MARK, A15_MARK,
+        DU0_DB0_MARK, SCL4_D_MARK, CAN0_RX_C_MARK, A16_MARK,
+        DU0_DB1_MARK, SDA4_D_MARK, CAN0_TX_C_MARK, A17_MARK,
+        DU0_DB2_MARK, HCTS0_N_MARK, A18_MARK,
+        DU0_DB3_MARK, HRTS0_N_MARK, A19_MARK,
+        DU0_DB4_MARK, HCTS1_N_C_MARK, A20_MARK,
+        DU0_DB5_MARK, HRTS1_N_C_MARK, A21_MARK,
+        DU0_DB6_MARK, A22_MARK,
+
+        /* IPSR7 */
+        DU0_DB7_MARK, A23_MARK,
+        DU0_DOTCLKIN_MARK, A24_MARK,
+        DU0_DOTCLKOUT0_MARK, A25_MARK,
+        DU0_DOTCLKOUT1_MARK, MSIOF2_RXD_B_MARK, CS1_N_A26_MARK,
+        DU0_EXHSYNC_DU0_HSYNC_MARK, MSIOF2_TXD_B_MARK, DREQ0_N_MARK,
+        DU0_EXVSYNC_DU0_VSYNC_MARK, MSIOF2_SYNC_B_MARK, DACK0_MARK,
+        DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, MSIOF2_SCK_B_MARK, DRACK0_MARK,
+        DU0_DISP_MARK, CAN1_RX_C_MARK,
+
+        /* IPSR8 */
+        DU0_CDE_MARK, CAN1_TX_C_MARK,
+        VI1_CLK_MARK, AVB_RX_CLK_MARK, ETH_REF_CLK_MARK,
+        VI1_DATA0_MARK, AVB_RX_DV_MARK, ETH_CRS_DV_MARK,
+        VI1_DATA1_MARK, AVB_RXD0_MARK, ETH_RXD0_MARK,
+        VI1_DATA2_MARK, AVB_RXD1_MARK, ETH_RXD1_MARK,
+        VI1_DATA3_MARK, AVB_RXD2_MARK, ETH_MDIO_MARK,
+        VI1_DATA4_MARK, AVB_RXD3_MARK, ETH_RX_ER_MARK,
+        VI1_DATA5_MARK, AVB_RXD4_MARK, ETH_LINK_MARK,
+
+        /* IPSR9 */
+        VI1_DATA6_MARK, AVB_RXD5_MARK, ETH_TXD1_MARK,
+        VI1_DATA7_MARK, AVB_RXD6_MARK, ETH_TX_EN_MARK,
+        VI1_CLKENB_MARK, SCL3_A_MARK, AVB_RXD7_MARK, ETH_MAGIC_MARK,
+        VI1_FIELD_MARK, SDA3_A_MARK, AVB_RX_ER_MARK, ETH_TXD0_MARK,
+        VI1_HSYNC_N_MARK, RX0_B_MARK, SCL0_C_MARK, AVB_GTXREFCLK_MARK, ETH_MDC_MARK,
+        VI1_VSYNC_N_MARK, TX0_B_MARK, SDA0_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_CLK_MARK,
+        VI1_DATA8_MARK, SCL2_B_MARK, AVB_TX_EN_MARK,
+        VI1_DATA9_MARK, SDA2_B_MARK, AVB_TXD0_MARK,
+
+        /* IPSR10 */
+        VI1_DATA10_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK,
+        VI1_DATA11_MARK, CAN0_TX_B_MARK, AVB_TXD2_MARK,
+        AVB_TXD3_MARK, AUDIO_CLKA_B_MARK, SSI_SCK1_D_MARK, RX5_F_MARK, MSIOF0_RXD_B_MARK,
+        AVB_TXD4_MARK, AUDIO_CLKB_B_MARK, SSI_WS1_D_MARK, TX5_F_MARK, MSIOF0_TXD_B_MARK,
+        AVB_TXD5_MARK, SCIF_CLK_B_MARK, AUDIO_CLKC_B_MARK, SSI_SDATA1_D_MARK, MSIOF0_SCK_B_MARK,
+        SCL0_A_MARK, RX0_C_MARK, PWM5_A_MARK, TCLK1_B_MARK, AVB_TXD6_MARK, CAN1_RX_D_MARK, MSIOF0_SYNC_B_MARK,
+        SDA0_A_MARK, TX0_C_MARK, IRQ5_MARK, CAN_CLK_A_MARK, AVB_GTX_CLK_MARK, CAN1_TX_D_MARK, DVC_MUTE_MARK,
+        SCL1_A_MARK, RX4_A_MARK, PWM5_D_MARK, DU1_DR0_MARK, SSI_SCK6_B_MARK, VI0_G0_MARK,
+
+        /* IPSR11 */
+        SDA1_A_MARK, TX4_A_MARK, DU1_DR1_MARK, SSI_WS6_B_MARK, VI0_G1_MARK,
+        MSIOF0_RXD_A_MARK, RX5_A_MARK, SCL2_C_MARK, DU1_DR2_MARK, QSPI1_MOSI_QSPI1_IO0_MARK, SSI_SDATA6_B_MARK, VI0_G2_MARK,
+        MSIOF0_TXD_A_MARK, TX5_A_MARK, SDA2_C_MARK, DU1_DR3_MARK, QSPI1_MISO_QSPI1_IO1_MARK, SSI_WS78_B_MARK, VI0_G3_MARK,
+        MSIOF0_SCK_A_MARK, IRQ0_MARK, DU1_DR4_MARK, QSPI1_SPCLK_MARK, SSI_SCK78_B_MARK, VI0_G4_MARK,
+        MSIOF0_SYNC_A_MARK, PWM1_A_MARK, DU1_DR5_MARK, QSPI1_IO2_MARK, SSI_SDATA7_B_MARK,
+        MSIOF0_SS1_A_MARK, DU1_DR6_MARK, QSPI1_IO3_MARK, SSI_SDATA8_B_MARK,
+        MSIOF0_SS2_A_MARK, DU1_DR7_MARK, QSPI1_SSL_MARK,
+        HRX1_A_MARK, SCL4_A_MARK, PWM6_A_MARK, DU1_DG0_MARK, RX0_A_MARK,
+
+        /* IPSR12 */
+        HTX1_A_MARK, SDA4_A_MARK, DU1_DG1_MARK, TX0_A_MARK,
+        HCTS1_N_A_MARK, PWM2_A_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
+        HRTS1_N_A_MARK, DU1_DG3_MARK, SSI_WS1_B_MARK, IRQ1_MARK,
+        SD2_CLK_MARK, HSCK1_MARK, DU1_DG4_MARK, SSI_SCK1_B_MARK,
+        SD2_CMD_MARK, SCIF1_SCK_A_MARK, TCLK2_A_MARK, DU1_DG5_MARK, SSI_SCK2_B_MARK, PWM3_A_MARK,
+        SD2_DAT0_MARK, RX1_A_MARK, SCL1_E_MARK, DU1_DG6_MARK, SSI_SDATA1_B_MARK,
+        SD2_DAT1_MARK, TX1_A_MARK, SDA1_E_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
+        SD2_DAT2_MARK, RX2_A_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
+
+        /* IPSR13 */
+        SD2_DAT3_MARK, TX2_A_MARK, DU1_DB1_MARK, SSI_WS9_B_MARK,
+        SD2_CD_MARK, SCIF2_SCK_A_MARK, DU1_DB2_MARK, SSI_SCK9_B_MARK,
+        SD2_WP_MARK, SCIF3_SCK_MARK, DU1_DB3_MARK, SSI_SDATA9_B_MARK,
+        RX3_A_MARK, SCL1_C_MARK, MSIOF1_RXD_B_MARK, DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SDATA4_B_MARK,
+        TX3_A_MARK, SDA1_C_MARK, MSIOF1_TXD_B_MARK, DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
+        SCL2_A_MARK, MSIOF1_SCK_B_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, SSI_SCK4_B_MARK,
+        SDA2_A_MARK, MSIOF1_SYNC_B_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
+        SSI_SCK5_A_MARK, DU1_DOTCLKOUT1_MARK,
+
+        /* IPSR14 */
+        SSI_WS5_A_MARK, SCL3_C_MARK, DU1_DOTCLKIN_MARK,
+        SSI_SDATA5_A_MARK, SDA3_C_MARK, DU1_DOTCLKOUT0_MARK,
+        SSI_SCK6_A_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
+        SSI_WS6_A_MARK, SCL4_C_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
+        SSI_SDATA6_A_MARK, SDA4_C_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,
+        SSI_SCK78_A_MARK, SDA4_E_MARK, DU1_DISP_MARK,
+        SSI_WS78_A_MARK, SCL4_E_MARK, DU1_CDE_MARK,
+        SSI_SDATA7_A_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, VI0_G5_MARK,
+
+        /* IPSR15 */
+        SSI_SCK0129_A_MARK, MSIOF1_RXD_A_MARK, RX5_D_MARK, VI0_G6_MARK,
+        SSI_WS0129_A_MARK, MSIOF1_TXD_A_MARK, TX5_D_MARK, VI0_G7_MARK,
+        SSI_SDATA0_A_MARK, MSIOF1_SYNC_A_MARK, PWM0_C_MARK, VI0_R0_MARK,
+        SSI_SCK34_MARK, MSIOF1_SCK_A_MARK, AVB_MDC_MARK, DACK1_MARK, VI0_R1_MARK,
+        SSI_WS34_MARK, MSIOF1_SS1_A_MARK, AVB_MDIO_MARK, CAN1_RX_A_MARK, DREQ1_N_MARK, VI0_R2_MARK,
+        SSI_SDATA3_MARK, MSIOF1_SS2_A_MARK, AVB_LINK_MARK, CAN1_TX_A_MARK, DREQ2_N_MARK, VI0_R3_MARK,
+        SSI_SCK4_A_MARK, AVB_MAGIC_MARK, VI0_R4_MARK,
+        SSI_WS4_A_MARK, AVB_PHY_INT_MARK, VI0_R5_MARK,
+
+        /* IPSR16 */
+        SSI_SDATA4_A_MARK, AVB_CRS_MARK, VI0_R6_MARK,
+        SSI_SCK1_A_MARK, SCIF1_SCK_B_MARK, PWM1_D_MARK, IRQ9_MARK, REMOCON_A_MARK, DACK2_MARK, VI0_CLK_MARK, AVB_COL_MARK,
+        SSI_SDATA8_A_MARK, RX1_B_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_B_MARK, VI0_R7_MARK,
+        SSI_WS1_A_MARK, TX1_B_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_B_MARK, VI0_DATA0_VI0_B0_MARK,
+        SSI_SDATA1_A_MARK, HRX1_B_MARK, VI0_DATA1_VI0_B1_MARK,
+        SSI_SCK2_A_MARK, HTX1_B_MARK, AVB_TXD7_MARK, VI0_DATA2_VI0_B2_MARK,
+        SSI_WS2_A_MARK, HCTS1_N_B_MARK, AVB_TX_ER_MARK, VI0_DATA3_VI0_B3_MARK,
+        SSI_SDATA2_A_MARK, HRTS1_N_B_MARK, VI0_DATA4_VI0_B4_MARK,
+
+        /* IPSR17 */
+        SSI_SCK9_A_MARK, RX2_B_MARK, SCL3_E_MARK, EX_WAIT1_MARK, VI0_DATA5_VI0_B5_MARK,
+        SSI_WS9_A_MARK, TX2_B_MARK, SDA3_E_MARK, VI0_DATA6_VI0_B6_MARK,
+        SSI_SDATA9_A_MARK, SCIF2_SCK_B_MARK, PWM2_D_MARK, VI0_DATA7_VI0_B7_MARK,
+        AUDIO_CLKA_A_MARK, SCL0_B_MARK, VI0_CLKENB_MARK,
+        AUDIO_CLKB_A_MARK, SDA0_B_MARK, VI0_FIELD_MARK,
+        AUDIO_CLKC_A_MARK, SCL4_B_MARK, VI0_HSYNC_N_MARK,
+        AUDIO_CLKOUT_A_MARK, SDA4_B_MARK, VI0_VSYNC_N_MARK,
+
+        PINMUX_MARK_END,
+};
+
+static const u16 pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+        PINMUX_SINGLE(USB0_PWEN),
+        PINMUX_SINGLE(USB0_OVC),
+        PINMUX_SINGLE(USB1_PWEN),
+        PINMUX_SINGLE(USB1_OVC),
+        PINMUX_SINGLE(CLKOUT),
+        PINMUX_SINGLE(MMC0_CLK_SDHI1_CLK),
+        PINMUX_SINGLE(MMC0_CMD_SDHI1_CMD),
+        PINMUX_SINGLE(MMC0_D0_SDHI1_D0),
+        PINMUX_SINGLE(MMC0_D1_SDHI1_D1),
+        PINMUX_SINGLE(MMC0_D2_SDHI1_D2),
+        PINMUX_SINGLE(MMC0_D3_SDHI1_D3),
+        PINMUX_SINGLE(MMC0_D6),
+        PINMUX_SINGLE(MMC0_D7),
+
+        /* IPSR0 */
+        PINMUX_IPSR_GPSR(IP0_3_0, SD0_CLK),
+        PINMUX_IPSR_MSEL(IP0_3_0, SSI_SCK1_C, SEL_SSI1_2),
+        PINMUX_IPSR_MSEL(IP0_3_0, RX3_C, SEL_SCIF3_2),
+        PINMUX_IPSR_GPSR(IP0_7_4, SD0_CMD),
+        PINMUX_IPSR_MSEL(IP0_7_4, SSI_WS1_C, SEL_SSI1_2),
+        PINMUX_IPSR_MSEL(IP0_7_4, TX3_C, SEL_SCIF3_2),
+        PINMUX_IPSR_GPSR(IP0_11_8, SD0_DAT0),
+        PINMUX_IPSR_MSEL(IP0_11_8, SSI_SDATA1_C, SEL_SSI1_2),
+        PINMUX_IPSR_MSEL(IP0_11_8, RX4_E, SEL_SCIF4_4),
+        PINMUX_IPSR_GPSR(IP0_15_12, SD0_DAT1),
+        PINMUX_IPSR_MSEL(IP0_15_12, SSI_SCK0129_B, SEL_SSI0_1),
+        PINMUX_IPSR_MSEL(IP0_15_12, TX4_E, SEL_SCIF4_4),
+        PINMUX_IPSR_GPSR(IP0_19_16, SD0_DAT2),
+        PINMUX_IPSR_MSEL(IP0_19_16, SSI_WS0129_B, SEL_SSI0_1),
+        PINMUX_IPSR_MSEL(IP0_19_16, RX5_E, SEL_SCIF5_4),
+        PINMUX_IPSR_GPSR(IP0_23_20, SD0_DAT3),
+        PINMUX_IPSR_MSEL(IP0_23_20, SSI_SDATA0_B, SEL_SSI0_1),
+        PINMUX_IPSR_MSEL(IP0_23_20, TX5_E, SEL_SCIF5_4),
+        PINMUX_IPSR_GPSR(IP0_27_24, SD0_CD),
+        PINMUX_IPSR_MSEL(IP0_27_24, CAN0_RX_A, SEL_CAN0_0),
+        PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
+        PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
+        PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),
+
+        /* IPSR1 */
+        PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4),
+        PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD),
+        PINMUX_IPSR_GPSR(IP1_7_4, MMC0_D5),
+        PINMUX_IPSR_GPSR(IP1_7_4, SD1_WP),
+        PINMUX_IPSR_GPSR(IP1_11_8, D0),
+        PINMUX_IPSR_MSEL(IP1_11_8, SCL3_B, SEL_I2C03_1),
+        PINMUX_IPSR_MSEL(IP1_11_8, RX5_B, SEL_SCIF5_1),
+        PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
+        PINMUX_IPSR_MSEL(IP1_11_8, MSIOF2_RXD_C, SEL_MSIOF2_2),
+        PINMUX_IPSR_MSEL(IP1_11_8, SSI_SDATA5_B, SEL_SSI5_1),
+        PINMUX_IPSR_GPSR(IP1_15_12, D1),
+        PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
+        PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
+        PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
+        PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
+        PINMUX_IPSR_GPSR(IP1_19_16, D2),
+        PINMUX_IPSR_MSEL(IP1_19_16, RX4_B, SEL_SCIF4_1),
+        PINMUX_IPSR_MSEL(IP1_19_16, SCL0_D, SEL_I2C00_3),
+        PINMUX_IPSR_GPSR(IP1_19_16, PWM1_C),
+        PINMUX_IPSR_MSEL(IP1_19_16, MSIOF2_SCK_C, SEL_MSIOF2_2),
+        PINMUX_IPSR_MSEL(IP1_19_16, SSI_SCK5_B, SEL_SSI5_1),
+        PINMUX_IPSR_GPSR(IP1_23_20, D3),
+        PINMUX_IPSR_MSEL(IP1_23_20, TX4_B, SEL_SCIF4_1),
+        PINMUX_IPSR_MSEL(IP1_23_20, SDA0_D, SEL_I2C00_3),
+        PINMUX_IPSR_GPSR(IP1_23_20, PWM0_A),
+        PINMUX_IPSR_MSEL(IP1_23_20, MSIOF2_SYNC_C, SEL_MSIOF2_2),
+        PINMUX_IPSR_GPSR(IP1_27_24, D4),
+        PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
+        PINMUX_IPSR_MSEL(IP1_27_24, TCLK1_A, SEL_TMU1_0),
+        PINMUX_IPSR_GPSR(IP1_27_24, PWM6_C),
+        PINMUX_IPSR_GPSR(IP1_31_28, D5),
+        PINMUX_IPSR_GPSR(IP1_31_28, HRX2),
+        PINMUX_IPSR_MSEL(IP1_31_28, SCL1_B, SEL_I2C01_1),
+        PINMUX_IPSR_GPSR(IP1_31_28, PWM2_C),
+        PINMUX_IPSR_MSEL(IP1_31_28, TCLK2_B, SEL_TMU2_1),
+
+        /* IPSR2 */
+        PINMUX_IPSR_GPSR(IP2_3_0, D6),
+        PINMUX_IPSR_GPSR(IP2_3_0, HTX2),
+        PINMUX_IPSR_MSEL(IP2_3_0, SDA1_B, SEL_I2C01_1),
+        PINMUX_IPSR_GPSR(IP2_3_0, PWM4_C),
+        PINMUX_IPSR_GPSR(IP2_7_4, D7),
+        PINMUX_IPSR_GPSR(IP2_7_4, HSCK2),
+        PINMUX_IPSR_MSEL(IP2_7_4, SCIF1_SCK_C, SEL_SCIF1_2),
+        PINMUX_IPSR_GPSR(IP2_7_4, IRQ6),
+        PINMUX_IPSR_GPSR(IP2_7_4, PWM5_C),
+        PINMUX_IPSR_GPSR(IP2_11_8, D8),
+        PINMUX_IPSR_GPSR(IP2_11_8, HCTS2_N),
+        PINMUX_IPSR_MSEL(IP2_11_8, RX1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MSEL(IP2_11_8, SCL1_D, SEL_I2C01_3),
+        PINMUX_IPSR_GPSR(IP2_11_8, PWM3_C),
+        PINMUX_IPSR_GPSR(IP2_15_12, D9),
+        PINMUX_IPSR_GPSR(IP2_15_12, HRTS2_N),
+        PINMUX_IPSR_MSEL(IP2_15_12, TX1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MSEL(IP2_15_12, SDA1_D, SEL_I2C01_3),
+        PINMUX_IPSR_GPSR(IP2_19_16, D10),
+        PINMUX_IPSR_MSEL(IP2_19_16, MSIOF2_RXD_A, SEL_MSIOF2_0),
+        PINMUX_IPSR_MSEL(IP2_19_16, HRX0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_GPSR(IP2_23_20, D11),
+        PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_TXD_A, SEL_MSIOF2_0),
+        PINMUX_IPSR_MSEL(IP2_23_20, HTX0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_GPSR(IP2_27_24, D12),
+        PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SCK_A, SEL_MSIOF2_0),
+        PINMUX_IPSR_GPSR(IP2_27_24, HSCK0),
+        PINMUX_IPSR_MSEL(IP2_27_24, CAN_CLK_C, SEL_CANCLK_2),
+        PINMUX_IPSR_GPSR(IP2_31_28, D13),
+        PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
+        PINMUX_IPSR_MSEL(IP2_31_28, RX4_C, SEL_SCIF4_2),
+
+        /* IPSR3 */
+        PINMUX_IPSR_GPSR(IP3_3_0, D14),
+        PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SS1),
+        PINMUX_IPSR_MSEL(IP3_3_0, TX4_C, SEL_SCIF4_2),
+        PINMUX_IPSR_MSEL(IP3_3_0, CAN1_RX_B, SEL_CAN1_1),
+        PINMUX_IPSR_MSEL(IP3_3_0, AVB_AVTP_CAPTURE_A, SEL_AVB_0),
+        PINMUX_IPSR_GPSR(IP3_7_4, D15),
+        PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2),
+        PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A),
+        PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1),
+        PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
+        PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0),
+        PINMUX_IPSR_GPSR(IP3_11_8, QSPI0_SPCLK),
+        PINMUX_IPSR_GPSR(IP3_11_8, WE0_N),
+        PINMUX_IPSR_GPSR(IP3_15_12, QSPI0_MOSI_QSPI0_IO0),
+        PINMUX_IPSR_GPSR(IP3_15_12, BS_N),
+        PINMUX_IPSR_GPSR(IP3_19_16, QSPI0_MISO_QSPI0_IO1),
+        PINMUX_IPSR_GPSR(IP3_19_16, RD_WR_N),
+        PINMUX_IPSR_GPSR(IP3_23_20, QSPI0_IO2),
+        PINMUX_IPSR_GPSR(IP3_23_20, CS0_N),
+        PINMUX_IPSR_GPSR(IP3_27_24, QSPI0_IO3),
+        PINMUX_IPSR_GPSR(IP3_27_24, RD_N),
+        PINMUX_IPSR_GPSR(IP3_31_28, QSPI0_SSL),
+        PINMUX_IPSR_GPSR(IP3_31_28, WE1_N),
+
+        /* IPSR4 */
+        PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0),
+        PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1),
+        PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0),
+        PINMUX_IPSR_GPSR(IP4_7_4, DU0_DR0),
+        PINMUX_IPSR_MSEL(IP4_7_4, RX5_C, SEL_SCIF5_2),
+        PINMUX_IPSR_MSEL(IP4_7_4, SCL2_D, SEL_I2C02_3),
+        PINMUX_IPSR_GPSR(IP4_7_4, A0),
+        PINMUX_IPSR_GPSR(IP4_11_8, DU0_DR1),
+        PINMUX_IPSR_MSEL(IP4_11_8, TX5_C, SEL_SCIF5_2),
+        PINMUX_IPSR_MSEL(IP4_11_8, SDA2_D, SEL_I2C02_3),
+        PINMUX_IPSR_GPSR(IP4_11_8, A1),
+        PINMUX_IPSR_GPSR(IP4_15_12, DU0_DR2),
+        PINMUX_IPSR_MSEL(IP4_15_12, RX0_D, SEL_SCIF0_3),
+        PINMUX_IPSR_MSEL(IP4_15_12, SCL0_E, SEL_I2C00_4),
+        PINMUX_IPSR_GPSR(IP4_15_12, A2),
+        PINMUX_IPSR_GPSR(IP4_19_16, DU0_DR3),
+        PINMUX_IPSR_MSEL(IP4_19_16, TX0_D, SEL_SCIF0_3),
+        PINMUX_IPSR_MSEL(IP4_19_16, SDA0_E, SEL_I2C00_4),
+        PINMUX_IPSR_GPSR(IP4_19_16, PWM0_B),
+        PINMUX_IPSR_GPSR(IP4_19_16, A3),
+        PINMUX_IPSR_GPSR(IP4_23_20, DU0_DR4),
+        PINMUX_IPSR_MSEL(IP4_23_20, RX1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_GPSR(IP4_23_20, A4),
+        PINMUX_IPSR_GPSR(IP4_27_24, DU0_DR5),
+        PINMUX_IPSR_MSEL(IP4_27_24, TX1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_GPSR(IP4_27_24, PWM1_B),
+        PINMUX_IPSR_GPSR(IP4_27_24, A5),
+        PINMUX_IPSR_GPSR(IP4_31_28, DU0_DR6),
+        PINMUX_IPSR_MSEL(IP4_31_28, RX2_C, SEL_SCIF2_2),
+        PINMUX_IPSR_GPSR(IP4_31_28, A6),
+
+        /* IPSR5 */
+        PINMUX_IPSR_GPSR(IP5_3_0, DU0_DR7),
+        PINMUX_IPSR_MSEL(IP5_3_0, TX2_C, SEL_SCIF2_2),
+        PINMUX_IPSR_GPSR(IP5_3_0, PWM2_B),
+        PINMUX_IPSR_GPSR(IP5_3_0, A7),
+        PINMUX_IPSR_GPSR(IP5_7_4, DU0_DG0),
+        PINMUX_IPSR_MSEL(IP5_7_4, RX3_B, SEL_SCIF3_1),
+        PINMUX_IPSR_MSEL(IP5_7_4, SCL3_D, SEL_I2C03_3),
+        PINMUX_IPSR_GPSR(IP5_7_4, A8),
+        PINMUX_IPSR_GPSR(IP5_11_8, DU0_DG1),
+        PINMUX_IPSR_MSEL(IP5_11_8, TX3_B, SEL_SCIF3_1),
+        PINMUX_IPSR_MSEL(IP5_11_8, SDA3_D, SEL_I2C03_3),
+        PINMUX_IPSR_GPSR(IP5_11_8, PWM3_B),
+        PINMUX_IPSR_GPSR(IP5_11_8, A9),
+        PINMUX_IPSR_GPSR(IP5_15_12, DU0_DG2),
+        PINMUX_IPSR_MSEL(IP5_15_12, RX4_D, SEL_SCIF4_3),
+        PINMUX_IPSR_GPSR(IP5_15_12, A10),
+        PINMUX_IPSR_GPSR(IP5_19_16, DU0_DG3),
+        PINMUX_IPSR_MSEL(IP5_19_16, TX4_D, SEL_SCIF4_3),
+        PINMUX_IPSR_GPSR(IP5_19_16, PWM4_B),
+        PINMUX_IPSR_GPSR(IP5_19_16, A11),
+        PINMUX_IPSR_GPSR(IP5_23_20, DU0_DG4),
+        PINMUX_IPSR_MSEL(IP5_23_20, HRX0_A, SEL_HSCIF0_0),
+        PINMUX_IPSR_GPSR(IP5_23_20, A12),
+        PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5),
+        PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0),
+        PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B),
+        PINMUX_IPSR_GPSR(IP5_27_24, A13),
+        PINMUX_IPSR_GPSR(IP5_31_28, DU0_DG6),
+        PINMUX_IPSR_MSEL(IP5_31_28, HRX1_C, SEL_HSCIF1_2),
+        PINMUX_IPSR_GPSR(IP5_31_28, A14),
+
+        /* IPSR6 */
+        PINMUX_IPSR_GPSR(IP6_3_0, DU0_DG7),
+        PINMUX_IPSR_MSEL(IP6_3_0, HTX1_C, SEL_HSCIF1_2),
+        PINMUX_IPSR_GPSR(IP6_3_0, PWM6_B),
+        PINMUX_IPSR_GPSR(IP6_3_0, A15),
+        PINMUX_IPSR_GPSR(IP6_7_4, DU0_DB0),
+        PINMUX_IPSR_MSEL(IP6_7_4, SCL4_D, SEL_I2C04_3),
+        PINMUX_IPSR_MSEL(IP6_7_4, CAN0_RX_C, SEL_CAN0_2),
+        PINMUX_IPSR_GPSR(IP6_7_4, A16),
+        PINMUX_IPSR_GPSR(IP6_11_8, DU0_DB1),
+        PINMUX_IPSR_MSEL(IP6_11_8, SDA4_D, SEL_I2C04_3),
+        PINMUX_IPSR_MSEL(IP6_11_8, CAN0_TX_C, SEL_CAN0_2),
+        PINMUX_IPSR_GPSR(IP6_11_8, A17),
+        PINMUX_IPSR_GPSR(IP6_15_12, DU0_DB2),
+        PINMUX_IPSR_GPSR(IP6_15_12, HCTS0_N),
+        PINMUX_IPSR_GPSR(IP6_15_12, A18),
+        PINMUX_IPSR_GPSR(IP6_19_16, DU0_DB3),
+        PINMUX_IPSR_GPSR(IP6_19_16, HRTS0_N),
+        PINMUX_IPSR_GPSR(IP6_19_16, A19),
+        PINMUX_IPSR_GPSR(IP6_23_20, DU0_DB4),
+        PINMUX_IPSR_MSEL(IP6_23_20, HCTS1_N_C, SEL_HSCIF1_2),
+        PINMUX_IPSR_GPSR(IP6_23_20, A20),
+        PINMUX_IPSR_GPSR(IP6_27_24, DU0_DB5),
+        PINMUX_IPSR_MSEL(IP6_27_24, HRTS1_N_C, SEL_HSCIF1_2),
+        PINMUX_IPSR_GPSR(IP6_27_24, A21),
+        PINMUX_IPSR_GPSR(IP6_31_28, DU0_DB6),
+        PINMUX_IPSR_GPSR(IP6_31_28, A22),
+
+        /* IPSR7 */
+        PINMUX_IPSR_GPSR(IP7_3_0, DU0_DB7),
+        PINMUX_IPSR_GPSR(IP7_3_0, A23),
+        PINMUX_IPSR_GPSR(IP7_7_4, DU0_DOTCLKIN),
+        PINMUX_IPSR_GPSR(IP7_7_4, A24),
+        PINMUX_IPSR_GPSR(IP7_11_8, DU0_DOTCLKOUT0),
+        PINMUX_IPSR_GPSR(IP7_11_8, A25),
+        PINMUX_IPSR_GPSR(IP7_15_12, DU0_DOTCLKOUT1),
+        PINMUX_IPSR_MSEL(IP7_15_12, MSIOF2_RXD_B, SEL_MSIOF2_1),
+        PINMUX_IPSR_GPSR(IP7_15_12, CS1_N_A26),
+        PINMUX_IPSR_GPSR(IP7_19_16, DU0_EXHSYNC_DU0_HSYNC),
+        PINMUX_IPSR_MSEL(IP7_19_16, MSIOF2_TXD_B, SEL_MSIOF2_1),
+        PINMUX_IPSR_GPSR(IP7_19_16, DREQ0_N),
+        PINMUX_IPSR_GPSR(IP7_23_20, DU0_EXVSYNC_DU0_VSYNC),
+        PINMUX_IPSR_MSEL(IP7_23_20, MSIOF2_SYNC_B, SEL_MSIOF2_1),
+        PINMUX_IPSR_GPSR(IP7_23_20, DACK0),
+        PINMUX_IPSR_GPSR(IP7_27_24, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+        PINMUX_IPSR_MSEL(IP7_27_24, MSIOF2_SCK_B, SEL_MSIOF2_1),
+        PINMUX_IPSR_GPSR(IP7_27_24, DRACK0),
+        PINMUX_IPSR_GPSR(IP7_31_28, DU0_DISP),
+        PINMUX_IPSR_MSEL(IP7_31_28, CAN1_RX_C, SEL_CAN1_2),
+
+        /* IPSR8 */
+        PINMUX_IPSR_GPSR(IP8_3_0, DU0_CDE),
+        PINMUX_IPSR_MSEL(IP8_3_0, CAN1_TX_C, SEL_CAN1_2),
+        PINMUX_IPSR_GPSR(IP8_7_4, VI1_CLK),
+        PINMUX_IPSR_GPSR(IP8_7_4, AVB_RX_CLK),
+        PINMUX_IPSR_GPSR(IP8_7_4, ETH_REF_CLK),
+        PINMUX_IPSR_GPSR(IP8_11_8, VI1_DATA0),
+        PINMUX_IPSR_GPSR(IP8_11_8, AVB_RX_DV),
+        PINMUX_IPSR_GPSR(IP8_11_8, ETH_CRS_DV),
+        PINMUX_IPSR_GPSR(IP8_15_12, VI1_DATA1),
+        PINMUX_IPSR_GPSR(IP8_15_12, AVB_RXD0),
+        PINMUX_IPSR_GPSR(IP8_15_12, ETH_RXD0),
+        PINMUX_IPSR_GPSR(IP8_19_16, VI1_DATA2),
+        PINMUX_IPSR_GPSR(IP8_19_16, AVB_RXD1),
+        PINMUX_IPSR_GPSR(IP8_19_16, ETH_RXD1),
+        PINMUX_IPSR_GPSR(IP8_23_20, VI1_DATA3),
+        PINMUX_IPSR_GPSR(IP8_23_20, AVB_RXD2),
+        PINMUX_IPSR_GPSR(IP8_23_20, ETH_MDIO),
+        PINMUX_IPSR_GPSR(IP8_27_24, VI1_DATA4),
+        PINMUX_IPSR_GPSR(IP8_27_24, AVB_RXD3),
+        PINMUX_IPSR_GPSR(IP8_27_24, ETH_RX_ER),
+        PINMUX_IPSR_GPSR(IP8_31_28, VI1_DATA5),
+        PINMUX_IPSR_GPSR(IP8_31_28, AVB_RXD4),
+        PINMUX_IPSR_GPSR(IP8_31_28, ETH_LINK),
+
+        /* IPSR9 */
+        PINMUX_IPSR_GPSR(IP9_3_0, VI1_DATA6),
+        PINMUX_IPSR_GPSR(IP9_3_0, AVB_RXD5),
+        PINMUX_IPSR_GPSR(IP9_3_0, ETH_TXD1),
+        PINMUX_IPSR_GPSR(IP9_7_4, VI1_DATA7),
+        PINMUX_IPSR_GPSR(IP9_7_4, AVB_RXD6),
+        PINMUX_IPSR_GPSR(IP9_7_4, ETH_TX_EN),
+        PINMUX_IPSR_GPSR(IP9_11_8, VI1_CLKENB),
+        PINMUX_IPSR_MSEL(IP9_11_8, SCL3_A, SEL_I2C03_0),
+        PINMUX_IPSR_GPSR(IP9_11_8, AVB_RXD7),
+        PINMUX_IPSR_GPSR(IP9_11_8, ETH_MAGIC),
+        PINMUX_IPSR_GPSR(IP9_15_12, VI1_FIELD),
+        PINMUX_IPSR_MSEL(IP9_15_12, SDA3_A, SEL_I2C03_0),
+        PINMUX_IPSR_GPSR(IP9_15_12, AVB_RX_ER),
+        PINMUX_IPSR_GPSR(IP9_15_12, ETH_TXD0),
+        PINMUX_IPSR_GPSR(IP9_19_16, VI1_HSYNC_N),
+        PINMUX_IPSR_MSEL(IP9_19_16, RX0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_MSEL(IP9_19_16, SCL0_C, SEL_I2C00_2),
+        PINMUX_IPSR_GPSR(IP9_19_16, AVB_GTXREFCLK),
+        PINMUX_IPSR_GPSR(IP9_19_16, ETH_MDC),
+        PINMUX_IPSR_GPSR(IP9_23_20, VI1_VSYNC_N),
+        PINMUX_IPSR_MSEL(IP9_23_20, TX0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_MSEL(IP9_23_20, SDA0_C, SEL_I2C00_2),
+        PINMUX_IPSR_GPSR(IP9_23_20, AUDIO_CLKOUT_B),
+        PINMUX_IPSR_GPSR(IP9_23_20, AVB_TX_CLK),
+        PINMUX_IPSR_GPSR(IP9_27_24, VI1_DATA8),
+        PINMUX_IPSR_MSEL(IP9_27_24, SCL2_B, SEL_I2C02_1),
+        PINMUX_IPSR_GPSR(IP9_27_24, AVB_TX_EN),
+        PINMUX_IPSR_GPSR(IP9_31_28, VI1_DATA9),
+        PINMUX_IPSR_MSEL(IP9_31_28, SDA2_B, SEL_I2C02_1),
+        PINMUX_IPSR_GPSR(IP9_31_28, AVB_TXD0),
+
+        /* IPSR10 */
+        PINMUX_IPSR_GPSR(IP10_3_0, VI1_DATA10),
+        PINMUX_IPSR_MSEL(IP10_3_0, CAN0_RX_B, SEL_CAN0_1),
+        PINMUX_IPSR_GPSR(IP10_3_0, AVB_TXD1),
+        PINMUX_IPSR_GPSR(IP10_7_4, VI1_DATA11),
+        PINMUX_IPSR_MSEL(IP10_7_4, CAN0_TX_B, SEL_CAN0_1),
+        PINMUX_IPSR_GPSR(IP10_7_4, AVB_TXD2),
+        PINMUX_IPSR_GPSR(IP10_11_8, AVB_TXD3),
+        PINMUX_IPSR_MSEL(IP10_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
+        PINMUX_IPSR_MSEL(IP10_11_8, SSI_SCK1_D, SEL_SSI1_3),
+        PINMUX_IPSR_MSEL(IP10_11_8, RX5_F, SEL_SCIF5_5),
+        PINMUX_IPSR_MSEL(IP10_11_8, MSIOF0_RXD_B, SEL_MSIOF0_1),
+        PINMUX_IPSR_GPSR(IP10_15_12, AVB_TXD4),
+        PINMUX_IPSR_MSEL(IP10_15_12, AUDIO_CLKB_B, SEL_ADGB_1),
+        PINMUX_IPSR_MSEL(IP10_15_12, SSI_WS1_D, SEL_SSI1_3),
+        PINMUX_IPSR_MSEL(IP10_15_12, TX5_F, SEL_SCIF5_5),
+        PINMUX_IPSR_MSEL(IP10_15_12, MSIOF0_TXD_B, SEL_MSIOF0_1),
+        PINMUX_IPSR_GPSR(IP10_19_16, AVB_TXD5),
+        PINMUX_IPSR_MSEL(IP10_19_16, SCIF_CLK_B, SEL_SCIFCLK_1),
+        PINMUX_IPSR_MSEL(IP10_19_16, AUDIO_CLKC_B, SEL_ADGC_1),
+        PINMUX_IPSR_MSEL(IP10_19_16, SSI_SDATA1_D, SEL_SSI1_3),
+        PINMUX_IPSR_MSEL(IP10_19_16, MSIOF0_SCK_B, SEL_MSIOF0_1),
+        PINMUX_IPSR_MSEL(IP10_23_20, SCL0_A, SEL_I2C00_0),
+        PINMUX_IPSR_MSEL(IP10_23_20, RX0_C, SEL_SCIF0_2),
+        PINMUX_IPSR_GPSR(IP10_23_20, PWM5_A),
+        PINMUX_IPSR_MSEL(IP10_23_20, TCLK1_B, SEL_TMU1_1),
+        PINMUX_IPSR_GPSR(IP10_23_20, AVB_TXD6),
+        PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_D, SEL_CAN1_3),
+        PINMUX_IPSR_MSEL(IP10_23_20, MSIOF0_SYNC_B, SEL_MSIOF0_1),
+        PINMUX_IPSR_MSEL(IP10_27_24, SDA0_A, SEL_I2C00_0),
+        PINMUX_IPSR_MSEL(IP10_27_24, TX0_C, SEL_SCIF0_2),
+        PINMUX_IPSR_GPSR(IP10_27_24, IRQ5),
+        PINMUX_IPSR_MSEL(IP10_27_24, CAN_CLK_A, SEL_CANCLK_0),
+        PINMUX_IPSR_GPSR(IP10_27_24, AVB_GTX_CLK),
+        PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_D, SEL_CAN1_3),
+        PINMUX_IPSR_GPSR(IP10_27_24, DVC_MUTE),
+        PINMUX_IPSR_MSEL(IP10_31_28, SCL1_A, SEL_I2C01_0),
+        PINMUX_IPSR_MSEL(IP10_31_28, RX4_A, SEL_SCIF4_0),
+        PINMUX_IPSR_GPSR(IP10_31_28, PWM5_D),
+        PINMUX_IPSR_GPSR(IP10_31_28, DU1_DR0),
+        PINMUX_IPSR_MSEL(IP10_31_28, SSI_SCK6_B, SEL_SSI6_1),
+        PINMUX_IPSR_GPSR(IP10_31_28, VI0_G0),
+
+        /* IPSR11 */
+        PINMUX_IPSR_MSEL(IP11_3_0, SDA1_A, SEL_I2C01_0),
+        PINMUX_IPSR_MSEL(IP11_3_0, TX4_A, SEL_SCIF4_0),
+        PINMUX_IPSR_GPSR(IP11_3_0, DU1_DR1),
+        PINMUX_IPSR_MSEL(IP11_3_0, SSI_WS6_B, SEL_SSI6_1),
+        PINMUX_IPSR_GPSR(IP11_3_0, VI0_G1),
+        PINMUX_IPSR_MSEL(IP11_7_4, MSIOF0_RXD_A, SEL_MSIOF0_0),
+        PINMUX_IPSR_MSEL(IP11_7_4, RX5_A, SEL_SCIF5_0),
+        PINMUX_IPSR_MSEL(IP11_7_4, SCL2_C, SEL_I2C02_2),
+        PINMUX_IPSR_GPSR(IP11_7_4, DU1_DR2),
+        PINMUX_IPSR_GPSR(IP11_7_4, QSPI1_MOSI_QSPI1_IO0),
+        PINMUX_IPSR_MSEL(IP11_7_4, SSI_SDATA6_B, SEL_SSI6_1),
+        PINMUX_IPSR_GPSR(IP11_7_4, VI0_G2),
+        PINMUX_IPSR_MSEL(IP11_11_8, MSIOF0_TXD_A, SEL_MSIOF0_0),
+        PINMUX_IPSR_MSEL(IP11_11_8, TX5_A, SEL_SCIF5_0),
+        PINMUX_IPSR_MSEL(IP11_11_8, SDA2_C, SEL_I2C02_2),
+        PINMUX_IPSR_GPSR(IP11_11_8, DU1_DR3),
+        PINMUX_IPSR_GPSR(IP11_11_8, QSPI1_MISO_QSPI1_IO1),
+        PINMUX_IPSR_MSEL(IP11_11_8, SSI_WS78_B, SEL_SSI7_1),
+        PINMUX_IPSR_GPSR(IP11_11_8, VI0_G3),
+        PINMUX_IPSR_MSEL(IP11_15_12, MSIOF0_SCK_A, SEL_MSIOF0_0),
+        PINMUX_IPSR_GPSR(IP11_15_12, IRQ0),
+        PINMUX_IPSR_GPSR(IP11_15_12, DU1_DR4),
+        PINMUX_IPSR_GPSR(IP11_15_12, QSPI1_SPCLK),
+        PINMUX_IPSR_MSEL(IP11_15_12, SSI_SCK78_B, SEL_SSI7_1),
+        PINMUX_IPSR_GPSR(IP11_15_12, VI0_G4),
+        PINMUX_IPSR_MSEL(IP11_19_16, MSIOF0_SYNC_A, SEL_MSIOF0_0),
+        PINMUX_IPSR_GPSR(IP11_19_16, PWM1_A),
+        PINMUX_IPSR_GPSR(IP11_19_16, DU1_DR5),
+        PINMUX_IPSR_GPSR(IP11_19_16, QSPI1_IO2),
+        PINMUX_IPSR_MSEL(IP11_19_16, SSI_SDATA7_B, SEL_SSI7_1),
+        PINMUX_IPSR_MSEL(IP11_23_20, MSIOF0_SS1_A, SEL_MSIOF0_0),
+        PINMUX_IPSR_GPSR(IP11_23_20, DU1_DR6),
+        PINMUX_IPSR_GPSR(IP11_23_20, QSPI1_IO3),
+        PINMUX_IPSR_MSEL(IP11_23_20, SSI_SDATA8_B, SEL_SSI8_1),
+        PINMUX_IPSR_MSEL(IP11_27_24, MSIOF0_SS2_A, SEL_MSIOF0_0),
+        PINMUX_IPSR_GPSR(IP11_27_24, DU1_DR7),
+        PINMUX_IPSR_GPSR(IP11_27_24, QSPI1_SSL),
+        PINMUX_IPSR_MSEL(IP11_31_28, HRX1_A, SEL_HSCIF1_0),
+        PINMUX_IPSR_MSEL(IP11_31_28, SCL4_A, SEL_I2C04_0),
+        PINMUX_IPSR_GPSR(IP11_31_28, PWM6_A),
+        PINMUX_IPSR_GPSR(IP11_31_28, DU1_DG0),
+        PINMUX_IPSR_MSEL(IP11_31_28, RX0_A, SEL_SCIF0_0),
+
+        /* IPSR12 */
+        PINMUX_IPSR_MSEL(IP12_3_0, HTX1_A, SEL_HSCIF1_0),
+        PINMUX_IPSR_MSEL(IP12_3_0, SDA4_A, SEL_I2C04_0),
+        PINMUX_IPSR_GPSR(IP12_3_0, DU1_DG1),
+        PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0),
+        PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_A, SEL_HSCIF1_0),
+        PINMUX_IPSR_GPSR(IP12_7_4, PWM2_A),
+        PINMUX_IPSR_GPSR(IP12_7_4, DU1_DG2),
+        PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_B, SEL_RCN_1),
+        PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_A, SEL_HSCIF1_0),
+        PINMUX_IPSR_GPSR(IP12_11_8, DU1_DG3),
+        PINMUX_IPSR_MSEL(IP12_11_8, SSI_WS1_B, SEL_SSI1_1),
+        PINMUX_IPSR_GPSR(IP12_11_8, IRQ1),
+        PINMUX_IPSR_GPSR(IP12_15_12, SD2_CLK),
+        PINMUX_IPSR_GPSR(IP12_15_12, HSCK1),
+        PINMUX_IPSR_GPSR(IP12_15_12, DU1_DG4),
+        PINMUX_IPSR_MSEL(IP12_15_12, SSI_SCK1_B, SEL_SSI1_1),
+        PINMUX_IPSR_GPSR(IP12_19_16, SD2_CMD),
+        PINMUX_IPSR_MSEL(IP12_19_16, SCIF1_SCK_A, SEL_SCIF1_0),
+        PINMUX_IPSR_MSEL(IP12_19_16, TCLK2_A, SEL_TMU2_0),
+        PINMUX_IPSR_GPSR(IP12_19_16, DU1_DG5),
+        PINMUX_IPSR_MSEL(IP12_19_16, SSI_SCK2_B, SEL_SSI2_1),
+        PINMUX_IPSR_GPSR(IP12_19_16, PWM3_A),
+        PINMUX_IPSR_GPSR(IP12_23_20, SD2_DAT0),
+        PINMUX_IPSR_MSEL(IP12_23_20, RX1_A, SEL_SCIF1_0),
+        PINMUX_IPSR_MSEL(IP12_23_20, SCL1_E, SEL_I2C01_4),
+        PINMUX_IPSR_GPSR(IP12_23_20, DU1_DG6),
+        PINMUX_IPSR_MSEL(IP12_23_20, SSI_SDATA1_B, SEL_SSI1_1),
+        PINMUX_IPSR_GPSR(IP12_27_24, SD2_DAT1),
+        PINMUX_IPSR_MSEL(IP12_27_24, TX1_A, SEL_SCIF1_0),
+        PINMUX_IPSR_MSEL(IP12_27_24, SDA1_E, SEL_I2C01_4),
+        PINMUX_IPSR_GPSR(IP12_27_24, DU1_DG7),
+        PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS2_B, SEL_SSI2_1),
+        PINMUX_IPSR_GPSR(IP12_31_28, SD2_DAT2),
+        PINMUX_IPSR_MSEL(IP12_31_28, RX2_A, SEL_SCIF2_0),
+        PINMUX_IPSR_GPSR(IP12_31_28, DU1_DB0),
+        PINMUX_IPSR_MSEL(IP12_31_28, SSI_SDATA2_B, SEL_SSI2_1),
+
+        /* IPSR13 */
+        PINMUX_IPSR_GPSR(IP13_3_0, SD2_DAT3),
+        PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
+        PINMUX_IPSR_GPSR(IP13_3_0, DU1_DB1),
+        PINMUX_IPSR_MSEL(IP13_3_0, SSI_WS9_B, SEL_SSI9_1),
+        PINMUX_IPSR_GPSR(IP13_7_4, SD2_CD),
+        PINMUX_IPSR_MSEL(IP13_7_4, SCIF2_SCK_A, SEL_SCIF2_CLK_0),
+        PINMUX_IPSR_GPSR(IP13_7_4, DU1_DB2),
+        PINMUX_IPSR_MSEL(IP13_7_4, SSI_SCK9_B, SEL_SSI9_1),
+        PINMUX_IPSR_GPSR(IP13_11_8, SD2_WP),
+        PINMUX_IPSR_GPSR(IP13_11_8, SCIF3_SCK),
+        PINMUX_IPSR_GPSR(IP13_11_8, DU1_DB3),
+        PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA9_B, SEL_SSI9_1),
+        PINMUX_IPSR_MSEL(IP13_15_12, RX3_A, SEL_SCIF3_0),
+        PINMUX_IPSR_MSEL(IP13_15_12, SCL1_C, SEL_I2C01_2),
+        PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_B, SEL_MSIOF1_1),
+        PINMUX_IPSR_GPSR(IP13_15_12, DU1_DB4),
+        PINMUX_IPSR_MSEL(IP13_15_12, AUDIO_CLKA_C, SEL_ADGA_2),
+        PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA4_B, SEL_SSI4_1),
+        PINMUX_IPSR_MSEL(IP13_19_16, TX3_A, SEL_SCIF3_0),
+        PINMUX_IPSR_MSEL(IP13_19_16, SDA1_C, SEL_I2C01_2),
+        PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_B, SEL_MSIOF1_1),
+        PINMUX_IPSR_GPSR(IP13_19_16, DU1_DB5),
+        PINMUX_IPSR_MSEL(IP13_19_16, AUDIO_CLKB_C, SEL_ADGB_2),
+        PINMUX_IPSR_MSEL(IP13_19_16, SSI_WS4_B, SEL_SSI4_1),
+        PINMUX_IPSR_MSEL(IP13_23_20, SCL2_A, SEL_I2C02_0),
+        PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SCK_B, SEL_MSIOF1_1),
+        PINMUX_IPSR_GPSR(IP13_23_20, DU1_DB6),
+        PINMUX_IPSR_MSEL(IP13_23_20, AUDIO_CLKC_C, SEL_ADGC_2),
+        PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK4_B, SEL_SSI4_1),
+        PINMUX_IPSR_MSEL(IP13_27_24, SDA2_A, SEL_I2C02_0),
+        PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SYNC_B, SEL_MSIOF1_1),
+        PINMUX_IPSR_GPSR(IP13_27_24, DU1_DB7),
+        PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT_C),
+        PINMUX_IPSR_MSEL(IP13_31_28, SSI_SCK5_A, SEL_SSI5_0),
+        PINMUX_IPSR_GPSR(IP13_31_28, DU1_DOTCLKOUT1),
+
+        /* IPSR14 */
+        PINMUX_IPSR_MSEL(IP14_3_0, SSI_WS5_A, SEL_SSI5_0),
+        PINMUX_IPSR_MSEL(IP14_3_0, SCL3_C, SEL_I2C03_2),
+        PINMUX_IPSR_GPSR(IP14_3_0, DU1_DOTCLKIN),
+        PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA5_A, SEL_SSI5_0),
+        PINMUX_IPSR_MSEL(IP14_7_4, SDA3_C, SEL_I2C03_2),
+        PINMUX_IPSR_GPSR(IP14_7_4, DU1_DOTCLKOUT0),
+        PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK6_A, SEL_SSI6_0),
+        PINMUX_IPSR_GPSR(IP14_11_8, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+        PINMUX_IPSR_MSEL(IP14_15_12, SSI_WS6_A, SEL_SSI6_0),
+        PINMUX_IPSR_MSEL(IP14_15_12, SCL4_C, SEL_I2C04_2),
+        PINMUX_IPSR_GPSR(IP14_15_12, DU1_EXHSYNC_DU1_HSYNC),
+        PINMUX_IPSR_MSEL(IP14_19_16, SSI_SDATA6_A, SEL_SSI6_0),
+        PINMUX_IPSR_MSEL(IP14_19_16, SDA4_C, SEL_I2C04_2),
+        PINMUX_IPSR_GPSR(IP14_19_16, DU1_EXVSYNC_DU1_VSYNC),
+        PINMUX_IPSR_MSEL(IP14_23_20, SSI_SCK78_A, SEL_SSI7_0),
+        PINMUX_IPSR_MSEL(IP14_23_20, SDA4_E, SEL_I2C04_4),
+        PINMUX_IPSR_GPSR(IP14_23_20, DU1_DISP),
+        PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS78_A, SEL_SSI7_0),
+        PINMUX_IPSR_MSEL(IP14_27_24, SCL4_E, SEL_I2C04_4),
+        PINMUX_IPSR_GPSR(IP14_27_24, DU1_CDE),
+        PINMUX_IPSR_MSEL(IP14_31_28, SSI_SDATA7_A, SEL_SSI7_0),
+        PINMUX_IPSR_GPSR(IP14_31_28, IRQ8),
+        PINMUX_IPSR_MSEL(IP14_31_28, AUDIO_CLKA_D, SEL_ADGA_3),
+        PINMUX_IPSR_MSEL(IP14_31_28, CAN_CLK_D, SEL_CANCLK_3),
+        PINMUX_IPSR_GPSR(IP14_31_28, VI0_G5),
+
+        /* IPSR15 */
+        PINMUX_IPSR_MSEL(IP15_3_0, SSI_SCK0129_A, SEL_SSI0_0),
+        PINMUX_IPSR_MSEL(IP15_3_0, MSIOF1_RXD_A, SEL_MSIOF1_0),
+        PINMUX_IPSR_MSEL(IP15_3_0, RX5_D, SEL_SCIF5_3),
+        PINMUX_IPSR_GPSR(IP15_3_0, VI0_G6),
+        PINMUX_IPSR_MSEL(IP15_7_4, SSI_WS0129_A, SEL_SSI0_0),
+        PINMUX_IPSR_MSEL(IP15_7_4, MSIOF1_TXD_A, SEL_MSIOF1_0),
+        PINMUX_IPSR_MSEL(IP15_7_4, TX5_D, SEL_SCIF5_3),
+        PINMUX_IPSR_GPSR(IP15_7_4, VI0_G7),
+        PINMUX_IPSR_MSEL(IP15_11_8, SSI_SDATA0_A, SEL_SSI0_0),
+        PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SYNC_A, SEL_MSIOF1_0),
+        PINMUX_IPSR_GPSR(IP15_11_8, PWM0_C),
+        PINMUX_IPSR_GPSR(IP15_11_8, VI0_R0),
+        PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK34),
+        PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_A, SEL_MSIOF1_0),
+        PINMUX_IPSR_GPSR(IP15_15_12, AVB_MDC),
+        PINMUX_IPSR_GPSR(IP15_15_12, DACK1),
+        PINMUX_IPSR_GPSR(IP15_15_12, VI0_R1),
+        PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS34),
+        PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SS1_A, SEL_MSIOF1_0),
+        PINMUX_IPSR_GPSR(IP15_19_16, AVB_MDIO),
+        PINMUX_IPSR_MSEL(IP15_19_16, CAN1_RX_A, SEL_CAN1_0),
+        PINMUX_IPSR_GPSR(IP15_19_16, DREQ1_N),
+        PINMUX_IPSR_GPSR(IP15_19_16, VI0_R2),
+        PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA3),
+        PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SS2_A, SEL_MSIOF1_0),
+        PINMUX_IPSR_GPSR(IP15_23_20, AVB_LINK),
+        PINMUX_IPSR_MSEL(IP15_23_20, CAN1_TX_A, SEL_CAN1_0),
+        PINMUX_IPSR_GPSR(IP15_23_20, DREQ2_N),
+        PINMUX_IPSR_GPSR(IP15_23_20, VI0_R3),
+        PINMUX_IPSR_MSEL(IP15_27_24, SSI_SCK4_A, SEL_SSI4_0),
+        PINMUX_IPSR_GPSR(IP15_27_24, AVB_MAGIC),
+        PINMUX_IPSR_GPSR(IP15_27_24, VI0_R4),
+        PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS4_A, SEL_SSI4_0),
+        PINMUX_IPSR_GPSR(IP15_31_28, AVB_PHY_INT),
+        PINMUX_IPSR_GPSR(IP15_31_28, VI0_R5),
+
+        /* IPSR16 */
+        PINMUX_IPSR_MSEL(IP16_3_0, SSI_SDATA4_A, SEL_SSI4_0),
+        PINMUX_IPSR_GPSR(IP16_3_0, AVB_CRS),
+        PINMUX_IPSR_GPSR(IP16_3_0, VI0_R6),
+        PINMUX_IPSR_MSEL(IP16_7_4, SSI_SCK1_A, SEL_SSI1_0),
+        PINMUX_IPSR_MSEL(IP16_7_4, SCIF1_SCK_B, SEL_SCIF1_1),
+        PINMUX_IPSR_GPSR(IP16_7_4, PWM1_D),
+        PINMUX_IPSR_GPSR(IP16_7_4, IRQ9),
+        PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_RCN_0),
+        PINMUX_IPSR_GPSR(IP16_7_4, DACK2),
+        PINMUX_IPSR_GPSR(IP16_7_4, VI0_CLK),
+        PINMUX_IPSR_GPSR(IP16_7_4, AVB_COL),
+        PINMUX_IPSR_MSEL(IP16_11_8, SSI_SDATA8_A, SEL_SSI8_0),
+        PINMUX_IPSR_MSEL(IP16_11_8, RX1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_MSEL(IP16_11_8, CAN0_RX_D, SEL_CAN0_3),
+        PINMUX_IPSR_MSEL(IP16_11_8, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
+        PINMUX_IPSR_GPSR(IP16_11_8, VI0_R7),
+        PINMUX_IPSR_MSEL(IP16_15_12, SSI_WS1_A, SEL_SSI1_0),
+        PINMUX_IPSR_MSEL(IP16_15_12, TX1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_MSEL(IP16_15_12, CAN0_TX_D, SEL_CAN0_3),
+        PINMUX_IPSR_MSEL(IP16_15_12, AVB_AVTP_MATCH_B, SEL_AVB_1),
+        PINMUX_IPSR_GPSR(IP16_15_12, VI0_DATA0_VI0_B0),
+        PINMUX_IPSR_MSEL(IP16_19_16, SSI_SDATA1_A, SEL_SSI1_0),
+        PINMUX_IPSR_MSEL(IP16_19_16, HRX1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_GPSR(IP16_19_16, VI0_DATA1_VI0_B1),
+        PINMUX_IPSR_MSEL(IP16_23_20, SSI_SCK2_A, SEL_SSI2_0),
+        PINMUX_IPSR_MSEL(IP16_23_20, HTX1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_GPSR(IP16_23_20, AVB_TXD7),
+        PINMUX_IPSR_GPSR(IP16_23_20, VI0_DATA2_VI0_B2),
+        PINMUX_IPSR_MSEL(IP16_27_24, SSI_WS2_A, SEL_SSI2_0),
+        PINMUX_IPSR_MSEL(IP16_27_24, HCTS1_N_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_GPSR(IP16_27_24, AVB_TX_ER),
+        PINMUX_IPSR_GPSR(IP16_27_24, VI0_DATA3_VI0_B3),
+        PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA2_A, SEL_SSI2_0),
+        PINMUX_IPSR_MSEL(IP16_31_28, HRTS1_N_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_GPSR(IP16_31_28, VI0_DATA4_VI0_B4),
+
+        /* IPSR17 */
+        PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_A, SEL_SSI9_0),
+        PINMUX_IPSR_MSEL(IP17_3_0, RX2_B, SEL_SCIF2_1),
+        PINMUX_IPSR_MSEL(IP17_3_0, SCL3_E, SEL_I2C03_4),
+        PINMUX_IPSR_GPSR(IP17_3_0, EX_WAIT1),
+        PINMUX_IPSR_GPSR(IP17_3_0, VI0_DATA5_VI0_B5),
+        PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_A, SEL_SSI9_0),
+        PINMUX_IPSR_MSEL(IP17_7_4, TX2_B, SEL_SCIF2_1),
+        PINMUX_IPSR_MSEL(IP17_7_4, SDA3_E, SEL_I2C03_4),
+        PINMUX_IPSR_GPSR(IP17_7_4, VI0_DATA6_VI0_B6),
+        PINMUX_IPSR_MSEL(IP17_11_8, SSI_SDATA9_A, SEL_SSI9_0),
+        PINMUX_IPSR_GPSR(IP17_11_8, SCIF2_SCK_B),
+        PINMUX_IPSR_GPSR(IP17_11_8, PWM2_D),
+        PINMUX_IPSR_GPSR(IP17_11_8, VI0_DATA7_VI0_B7),
+        PINMUX_IPSR_MSEL(IP17_15_12, AUDIO_CLKA_A, SEL_ADGA_0),
+        PINMUX_IPSR_MSEL(IP17_15_12, SCL0_B, SEL_I2C00_1),
+        PINMUX_IPSR_GPSR(IP17_15_12, VI0_CLKENB),
+        PINMUX_IPSR_MSEL(IP17_19_16, AUDIO_CLKB_A, SEL_ADGB_0),
+        PINMUX_IPSR_MSEL(IP17_19_16, SDA0_B, SEL_I2C00_1),
+        PINMUX_IPSR_GPSR(IP17_19_16, VI0_FIELD),
+        PINMUX_IPSR_MSEL(IP17_23_20, AUDIO_CLKC_A, SEL_ADGC_0),
+        PINMUX_IPSR_MSEL(IP17_23_20, SCL4_B, SEL_I2C04_1),
+        PINMUX_IPSR_GPSR(IP17_23_20, VI0_HSYNC_N),
+        PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_A),
+        PINMUX_IPSR_MSEL(IP17_27_24, SDA4_B, SEL_I2C04_1),
+        PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N),
+};
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+        PINMUX_GPIO_GP_ALL(),
+};
+
+/* - MMC -------------------------------------------------------------------- */
+static const unsigned int mmc_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(0, 15),
+};
+static const unsigned int mmc_data1_mux[] = {
+        MMC0_D0_SDHI1_D0_MARK,
+};
+static const unsigned int mmc_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
+        RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
+};
+static const unsigned int mmc_data4_mux[] = {
+        MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
+        MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
+};
+static const unsigned int mmc_data8_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
+        RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
+        RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
+};
+static const unsigned int mmc_data8_mux[] = {
+        MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
+        MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
+        MMC0_D4_MARK, MMC0_D5_MARK,
+        MMC0_D6_MARK, MMC0_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+        MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
+};
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_a_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int scif0_data_a_mux[] = {
+        RX0_A_MARK, TX0_A_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int scif0_data_b_mux[] = {
+        RX0_B_MARK, TX0_B_MARK,
+};
+static const unsigned int scif0_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+static const unsigned int scif0_data_c_mux[] = {
+        RX0_C_MARK, TX0_C_MARK,
+};
+static const unsigned int scif0_data_d_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int scif0_data_d_mux[] = {
+        RX0_D_MARK, TX0_D_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_a_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
+};
+static const unsigned int scif1_data_a_mux[] = {
+        RX1_A_MARK, TX1_A_MARK,
+};
+static const unsigned int scif1_clk_a_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 15),
+};
+static const unsigned int scif1_clk_a_mux[] = {
+        SCIF1_SCK_A_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
+};
+static const unsigned int scif1_data_b_mux[] = {
+        RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 18),
+};
+static const unsigned int scif1_clk_b_mux[] = {
+        SCIF1_SCK_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int scif1_data_c_mux[] = {
+        RX1_C_MARK, TX1_C_MARK,
+};
+static const unsigned int scif1_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(1, 7),
+};
+static const unsigned int scif1_clk_c_mux[] = {
+        SCIF1_SCK_C_MARK,
+};
+static const unsigned int scif1_data_d_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int scif1_data_d_mux[] = {
+        RX1_D_MARK, TX1_D_MARK,
+};
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_a_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
+};
+static const unsigned int scif2_data_a_mux[] = {
+        RX2_A_MARK, TX2_A_MARK,
+};
+static const unsigned int scif2_clk_a_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scif2_clk_a_mux[] = {
+        SCIF2_SCK_A_MARK,
+};
+static const unsigned int scif2_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
+};
+static const unsigned int scif2_data_b_mux[] = {
+        RX2_B_MARK, TX2_B_MARK,
+};
+static const unsigned int scif2_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 27),
+};
+static const unsigned int scif2_clk_b_mux[] = {
+        SCIF2_SCK_B_MARK,
+};
+static const unsigned int scif2_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+};
+static const unsigned int scif2_data_c_mux[] = {
+        RX2_C_MARK, TX2_C_MARK,
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_a_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
+};
+static const unsigned int scif3_data_a_mux[] = {
+        RX3_A_MARK, TX3_A_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scif3_clk_mux[] = {
+        SCIF3_SCK_MARK,
+};
+static const unsigned int scif3_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int scif3_data_b_mux[] = {
+        RX3_B_MARK, TX3_B_MARK,
+};
+static const unsigned int scif3_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+};
+static const unsigned int scif3_data_c_mux[] = {
+        RX3_C_MARK, TX3_C_MARK,
+};
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_a_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+};
+static const unsigned int scif4_data_a_mux[] = {
+        RX4_A_MARK, TX4_A_MARK,
+};
+static const unsigned int scif4_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scif4_data_b_mux[] = {
+        RX4_B_MARK, TX4_B_MARK,
+};
+static const unsigned int scif4_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
+};
+static const unsigned int scif4_data_c_mux[] = {
+        RX4_C_MARK, TX4_C_MARK,
+};
+static const unsigned int scif4_data_d_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+};
+static const unsigned int scif4_data_d_mux[] = {
+        RX4_D_MARK, TX4_D_MARK,
+};
+static const unsigned int scif4_data_e_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scif4_data_e_mux[] = {
+        RX4_E_MARK, TX4_E_MARK,
+};
+/* - SCIF5 ------------------------------------------------------------------ */
+static const unsigned int scif5_data_a_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+static const unsigned int scif5_data_a_mux[] = {
+        RX5_A_MARK, TX5_A_MARK,
+};
+static const unsigned int scif5_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
+};
+static const unsigned int scif5_data_b_mux[] = {
+        RX5_B_MARK, TX5_B_MARK,
+};
+static const unsigned int scif5_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int scif5_data_c_mux[] = {
+        RX5_C_MARK, TX5_C_MARK,
+};
+static const unsigned int scif5_data_d_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int scif5_data_d_mux[] = {
+        RX5_D_MARK, TX5_D_MARK,
+};
+static const unsigned int scif5_data_e_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scif5_data_e_mux[] = {
+        RX5_E_MARK, TX5_E_MARK,
+};
+static const unsigned int scif5_data_f_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
+};
+static const unsigned int scif5_data_f_mux[] = {
+        RX5_F_MARK, TX5_F_MARK,
+};
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_a_pins[] = {
+        /* SCIF_CLK */
+        RCAR_GP_PIN(1, 22),
+};
+static const unsigned int scif_clk_a_mux[] = {
+        SCIF_CLK_A_MARK,
+};
+static const unsigned int scif_clk_b_pins[] = {
+        /* SCIF_CLK */
+        RCAR_GP_PIN(3, 29),
+};
+static const unsigned int scif_clk_b_mux[] = {
+        SCIF_CLK_B_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(mmc_data1),
+        SH_PFC_PIN_GROUP(mmc_data4),
+        SH_PFC_PIN_GROUP(mmc_data8),
+        SH_PFC_PIN_GROUP(mmc_ctrl),
+        SH_PFC_PIN_GROUP(scif0_data_a),
+        SH_PFC_PIN_GROUP(scif0_data_b),
+        SH_PFC_PIN_GROUP(scif0_data_c),
+        SH_PFC_PIN_GROUP(scif0_data_d),
+        SH_PFC_PIN_GROUP(scif1_data_a),
+        SH_PFC_PIN_GROUP(scif1_clk_a),
+        SH_PFC_PIN_GROUP(scif1_data_b),
+        SH_PFC_PIN_GROUP(scif1_clk_b),
+        SH_PFC_PIN_GROUP(scif1_data_c),
+        SH_PFC_PIN_GROUP(scif1_clk_c),
+        SH_PFC_PIN_GROUP(scif1_data_d),
+        SH_PFC_PIN_GROUP(scif2_data_a),
+        SH_PFC_PIN_GROUP(scif2_clk_a),
+        SH_PFC_PIN_GROUP(scif2_data_b),
+        SH_PFC_PIN_GROUP(scif2_clk_b),
+        SH_PFC_PIN_GROUP(scif2_data_c),
+        SH_PFC_PIN_GROUP(scif3_data_a),
+        SH_PFC_PIN_GROUP(scif3_clk),
+        SH_PFC_PIN_GROUP(scif3_data_b),
+        SH_PFC_PIN_GROUP(scif3_data_c),
+        SH_PFC_PIN_GROUP(scif4_data_a),
+        SH_PFC_PIN_GROUP(scif4_data_b),
+        SH_PFC_PIN_GROUP(scif4_data_c),
+        SH_PFC_PIN_GROUP(scif4_data_d),
+        SH_PFC_PIN_GROUP(scif4_data_e),
+        SH_PFC_PIN_GROUP(scif5_data_a),
+        SH_PFC_PIN_GROUP(scif5_data_b),
+        SH_PFC_PIN_GROUP(scif5_data_c),
+        SH_PFC_PIN_GROUP(scif5_data_d),
+        SH_PFC_PIN_GROUP(scif5_data_e),
+        SH_PFC_PIN_GROUP(scif5_data_f),
+        SH_PFC_PIN_GROUP(scif_clk_a),
+        SH_PFC_PIN_GROUP(scif_clk_b),
+};
+
+static const char * const mmc_groups[] = {
+        "mmc_data1",
+        "mmc_data4",
+        "mmc_data8",
+        "mmc_ctrl",
+};
+
+static const char * const scif0_groups[] = {
+        "scif0_data_a",
+        "scif0_data_b",
+        "scif0_data_c",
+        "scif0_data_d",
+};
+
+static const char * const scif1_groups[] = {
+        "scif1_data_a",
+        "scif1_clk_a",
+        "scif1_data_b",
+        "scif1_clk_b",
+        "scif1_data_c",
+        "scif1_clk_c",
+        "scif1_data_d",
+};
+
+static const char * const scif2_groups[] = {
+        "scif2_data_a",
+        "scif2_clk_a",
+        "scif2_data_b",
+        "scif2_clk_b",
+        "scif2_data_c",
+};
+
+static const char * const scif3_groups[] = {
+        "scif3_data_a",
+        "scif3_clk",
+        "scif3_data_b",
+        "scif3_data_c",
+};
+
+static const char * const scif4_groups[] = {
+        "scif4_data_a",
+        "scif4_data_b",
+        "scif4_data_c",
+        "scif4_data_d",
+        "scif4_data_e",
+};
+
+static const char * const scif5_groups[] = {
+        "scif5_data_a",
+        "scif5_data_b",
+        "scif5_data_c",
+        "scif5_data_d",
+        "scif5_data_e",
+        "scif5_data_f",
+};
+
+static const char * const scif_clk_groups[] = {
+        "scif_clk_a",
+        "scif_clk_b",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(mmc),
+        SH_PFC_FUNCTION(scif0),
+        SH_PFC_FUNCTION(scif1),
+        SH_PFC_FUNCTION(scif2),
+        SH_PFC_FUNCTION(scif3),
+        SH_PFC_FUNCTION(scif4),
+        SH_PFC_FUNCTION(scif5),
+        SH_PFC_FUNCTION(scif_clk),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_0_22_FN, FN_MMC0_D7,
+                GP_0_21_FN, FN_MMC0_D6,
+                GP_0_20_FN, FN_IP1_7_4,
+                GP_0_19_FN, FN_IP1_3_0,
+                GP_0_18_FN, FN_MMC0_D3_SDHI1_D3,
+                GP_0_17_FN, FN_MMC0_D2_SDHI1_D2,
+                GP_0_16_FN, FN_MMC0_D1_SDHI1_D1,
+                GP_0_15_FN, FN_MMC0_D0_SDHI1_D0,
+                GP_0_14_FN, FN_MMC0_CMD_SDHI1_CMD,
+                GP_0_13_FN, FN_MMC0_CLK_SDHI1_CLK,
+                GP_0_12_FN, FN_IP0_31_28,
+                GP_0_11_FN, FN_IP0_27_24,
+                GP_0_10_FN, FN_IP0_23_20,
+                GP_0_9_FN, FN_IP0_19_16,
+                GP_0_8_FN, FN_IP0_15_12,
+                GP_0_7_FN, FN_IP0_11_8,
+                GP_0_6_FN, FN_IP0_7_4,
+                GP_0_5_FN, FN_IP0_3_0,
+                GP_0_4_FN, FN_CLKOUT,
+                GP_0_3_FN, FN_USB1_OVC,
+                GP_0_2_FN, FN_USB1_PWEN,
+                GP_0_1_FN, FN_USB0_OVC,
+                GP_0_0_FN, FN_USB0_PWEN, }
+        },
+        { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_1_22_FN, FN_IP4_3_0,
+                GP_1_21_FN, FN_IP3_31_28,
+                GP_1_20_FN, FN_IP3_27_24,
+                GP_1_19_FN, FN_IP3_23_20,
+                GP_1_18_FN, FN_IP3_19_16,
+                GP_1_17_FN, FN_IP3_15_12,
+                GP_1_16_FN, FN_IP3_11_8,
+                GP_1_15_FN, FN_IP3_7_4,
+                GP_1_14_FN, FN_IP3_3_0,
+                GP_1_13_FN, FN_IP2_31_28,
+                GP_1_12_FN, FN_IP2_27_24,
+                GP_1_11_FN, FN_IP2_23_20,
+                GP_1_10_FN, FN_IP2_19_16,
+                GP_1_9_FN, FN_IP2_15_12,
+                GP_1_8_FN, FN_IP2_11_8,
+                GP_1_7_FN, FN_IP2_7_4,
+                GP_1_6_FN, FN_IP2_3_0,
+                GP_1_5_FN, FN_IP1_31_28,
+                GP_1_4_FN, FN_IP1_27_24,
+                GP_1_3_FN, FN_IP1_23_20,
+                GP_1_2_FN, FN_IP1_19_16,
+                GP_1_1_FN, FN_IP1_15_12,
+                GP_1_0_FN, FN_IP1_11_8, }
+        },
+        { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+                GP_2_31_FN, FN_IP8_3_0,
+                GP_2_30_FN, FN_IP7_31_28,
+                GP_2_29_FN, FN_IP7_27_24,
+                GP_2_28_FN, FN_IP7_23_20,
+                GP_2_27_FN, FN_IP7_19_16,
+                GP_2_26_FN, FN_IP7_15_12,
+                GP_2_25_FN, FN_IP7_11_8,
+                GP_2_24_FN, FN_IP7_7_4,
+                GP_2_23_FN, FN_IP7_3_0,
+                GP_2_22_FN, FN_IP6_31_28,
+                GP_2_21_FN, FN_IP6_27_24,
+                GP_2_20_FN, FN_IP6_23_20,
+                GP_2_19_FN, FN_IP6_19_16,
+                GP_2_18_FN, FN_IP6_15_12,
+                GP_2_17_FN, FN_IP6_11_8,
+                GP_2_16_FN, FN_IP6_7_4,
+                GP_2_15_FN, FN_IP6_3_0,
+                GP_2_14_FN, FN_IP5_31_28,
+                GP_2_13_FN, FN_IP5_27_24,
+                GP_2_12_FN, FN_IP5_23_20,
+                GP_2_11_FN, FN_IP5_19_16,
+                GP_2_10_FN, FN_IP5_15_12,
+                GP_2_9_FN, FN_IP5_11_8,
+                GP_2_8_FN, FN_IP5_7_4,
+                GP_2_7_FN, FN_IP5_3_0,
+                GP_2_6_FN, FN_IP4_31_28,
+                GP_2_5_FN, FN_IP4_27_24,
+                GP_2_4_FN, FN_IP4_23_20,
+                GP_2_3_FN, FN_IP4_19_16,
+                GP_2_2_FN, FN_IP4_15_12,
+                GP_2_1_FN, FN_IP4_11_8,
+                GP_2_0_FN, FN_IP4_7_4, }
+        },
+        { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+                0, 0,
+                0, 0,
+                GP_3_29_FN, FN_IP10_19_16,
+                GP_3_28_FN, FN_IP10_15_12,
+                GP_3_27_FN, FN_IP10_11_8,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_3_16_FN, FN_IP10_7_4,
+                GP_3_15_FN, FN_IP10_3_0,
+                GP_3_14_FN, FN_IP9_31_28,
+                GP_3_13_FN, FN_IP9_27_24,
+                GP_3_12_FN, FN_IP9_23_20,
+                GP_3_11_FN, FN_IP9_19_16,
+                GP_3_10_FN, FN_IP9_15_12,
+                GP_3_9_FN, FN_IP9_11_8,
+                GP_3_8_FN, FN_IP9_7_4,
+                GP_3_7_FN, FN_IP9_3_0,
+                GP_3_6_FN, FN_IP8_31_28,
+                GP_3_5_FN, FN_IP8_27_24,
+                GP_3_4_FN, FN_IP8_23_20,
+                GP_3_3_FN, FN_IP8_19_16,
+                GP_3_2_FN, FN_IP8_15_12,
+                GP_3_1_FN, FN_IP8_11_8,
+                GP_3_0_FN, FN_IP8_7_4, }
+        },
+        { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_4_25_FN, FN_IP13_27_24,
+                GP_4_24_FN, FN_IP13_23_20,
+                GP_4_23_FN, FN_IP13_19_16,
+                GP_4_22_FN, FN_IP13_15_12,
+                GP_4_21_FN, FN_IP13_11_8,
+                GP_4_20_FN, FN_IP13_7_4,
+                GP_4_19_FN, FN_IP13_3_0,
+                GP_4_18_FN, FN_IP12_31_28,
+                GP_4_17_FN, FN_IP12_27_24,
+                GP_4_16_FN, FN_IP12_23_20,
+                GP_4_15_FN, FN_IP12_19_16,
+                GP_4_14_FN, FN_IP12_15_12,
+                GP_4_13_FN, FN_IP12_11_8,
+                GP_4_12_FN, FN_IP12_7_4,
+                GP_4_11_FN, FN_IP12_3_0,
+                GP_4_10_FN, FN_IP11_31_28,
+                GP_4_9_FN, FN_IP11_27_24,
+                GP_4_8_FN, FN_IP11_23_20,
+                GP_4_7_FN, FN_IP11_19_16,
+                GP_4_6_FN, FN_IP11_15_12,
+                GP_4_5_FN, FN_IP11_11_8,
+                GP_4_4_FN, FN_IP11_7_4,
+                GP_4_3_FN, FN_IP11_3_0,
+                GP_4_2_FN, FN_IP10_31_28,
+                GP_4_1_FN, FN_IP10_27_24,
+                GP_4_0_FN, FN_IP10_23_20, }
+        },
+        { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+                GP_5_31_FN, FN_IP17_27_24,
+                GP_5_30_FN, FN_IP17_23_20,
+                GP_5_29_FN, FN_IP17_19_16,
+                GP_5_28_FN, FN_IP17_15_12,
+                GP_5_27_FN, FN_IP17_11_8,
+                GP_5_26_FN, FN_IP17_7_4,
+                GP_5_25_FN, FN_IP17_3_0,
+                GP_5_24_FN, FN_IP16_31_28,
+                GP_5_23_FN, FN_IP16_27_24,
+                GP_5_22_FN, FN_IP16_23_20,
+                GP_5_21_FN, FN_IP16_19_16,
+                GP_5_20_FN, FN_IP16_15_12,
+                GP_5_19_FN, FN_IP16_11_8,
+                GP_5_18_FN, FN_IP16_7_4,
+                GP_5_17_FN, FN_IP16_3_0,
+                GP_5_16_FN, FN_IP15_31_28,
+                GP_5_15_FN, FN_IP15_27_24,
+                GP_5_14_FN, FN_IP15_23_20,
+                GP_5_13_FN, FN_IP15_19_16,
+                GP_5_12_FN, FN_IP15_15_12,
+                GP_5_11_FN, FN_IP15_11_8,
+                GP_5_10_FN, FN_IP15_7_4,
+                GP_5_9_FN, FN_IP15_3_0,
+                GP_5_8_FN, FN_IP14_31_28,
+                GP_5_7_FN, FN_IP14_27_24,
+                GP_5_6_FN, FN_IP14_23_20,
+                GP_5_5_FN, FN_IP14_19_16,
+                GP_5_4_FN, FN_IP14_15_12,
+                GP_5_3_FN, FN_IP14_11_8,
+                GP_5_2_FN, FN_IP14_7_4,
+                GP_5_1_FN, FN_IP14_3_0,
+                GP_5_0_FN, FN_IP13_31_28, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP0_31_28 [4] */
+                FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_27_24 [4] */
+                FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_23_20 [4] */
+                FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_19_16 [4] */
+                FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_15_12 [4] */
+                FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_11_8 [4] */
+                FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_7_4 [4] */
+                FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_3_0 [4] */
+                FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP1_31_28 [4] */
+                FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_27_24 [4] */
+                FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_23_20 [4] */
+                FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A,
+                FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_19_16 [4] */
+                FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C,
+                FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_15_12 [4] */
+                FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C,
+                FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_11_8 [4] */
+                FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4,
+                FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_7_4 [4] */
+                FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_3_0 [4] */
+                FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP2_31_28 [4] */
+                FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP2_27_24 [4] */
+                FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_23_20 [4] */
+                FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP2_19_16 [4] */
+                FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP2_15_12 [4] */
+                FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_11_8 [4] */
+                FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_7_4 [4] */
+                FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_3_0 [4] */
+                FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP3_31_28 [4] */
+                FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0,
+                /* IP3_27_24 [4] */
+                FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0,
+                /* IP3_23_20 [4] */
+                FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0,
+                /* IP3_19_16 [4] */
+                FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0,
+                /* IP3_15_12 [4] */
+                FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0,
+                /* IP3_11_8 [4] */
+                FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0,
+                /* IP3_7_4 [4] */
+                FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2,
+                FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP3_3_0 [4] */
+                FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
+                0, FN_AVB_AVTP_CAPTURE_A,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP4_31_28 [4] */
+                FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP4_27_24 [4] */
+                FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP4_23_20 [4] */
+                FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0,
+                0, 0, 0, 0, 0,
+                /* IP4_19_16 [4] */
+                FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0,
+                FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP4_15_12 [4] */
+                FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP4_11_8 [4] */
+                FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP4_7_4 [4] */
+                FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP4_3_0 [4] */
+                FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP5_31_28 [4] */
+                FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14,  0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP5_27_24 [4] */
+                FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP5_23_20 [4] */
+                FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP5_19_16 [4] */
+                FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP5_15_12 [4] */
+                FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP5_11_8 [4] */
+                FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0,
+                FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP5_7_4 [4] */
+                FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP5_3_0 [4] */
+                FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP6_31_28 [4] */
+                FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP6_27_24 [4] */
+                FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0,
+                FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP6_23_20 [4] */
+                FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0,
+                FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP6_19_16 [4] */
+                FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP6_15_12 [4] */
+                FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP6_11_8 [4] */
+                FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP6_7_4 [4] */
+                FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP6_3_0 [4] */
+                FN_DU0_DG7, 0, FN_HTX1_C, 0,  FN_PWM6_B, 0, FN_A15,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP7_31_28 [4] */
+                FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0,
+                /* IP7_27_24 [4] */
+                FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B,
+                0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP7_23_20 [4] */
+                FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0,
+                0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP7_19_16 [4] */
+                FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0,
+                0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP7_15_12 [4] */
+                FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0,
+                FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP7_11_8 [4] */
+                FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0,
+                0, 0, 0, 0, 0,
+                /* IP7_7_4 [4] */
+                FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP7_3_0 [4] */
+                FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP8_31_28 [4] */
+                FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP8_27_24 [4] */
+                FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP8_23_20 [4] */
+                FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP8_19_16 [4] */
+                FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP8_15_12 [4] */
+                FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP8_11_8 [4] */
+                FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP8_7_4 [4] */
+                FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP8_3_0 [4] */
+                FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP9_31_28 [4] */
+                FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0,
+                /* IP9_27_24 [4] */
+                FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0,
+                /* IP9_23_20 [4] */
+                FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B,
+                FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP9_19_16 [4] */
+                FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK,
+                FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP9_15_12 [4] */
+                FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP9_11_8 [4] */
+                FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP9_7_4 [4] */
+                FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP9_3_0 [4] */
+                FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP10_31_28 [4] */
+                FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
+                FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP10_27_24 [4] */
+                FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK,
+                FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP10_23_20 [4] */
+                FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6,
+                FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP10_19_16 [4] */
+                FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0,
+                FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0,
+                0, 0,
+                /* IP10_15_12 [4] */
+                FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F,
+                FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP10_11_8 [4] */
+                FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F,
+                FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP10_7_4 [4] */
+                FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP10_3_0 [4] */
+                FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP11_31_28 [4] */
+                FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP11_27_24 [4] */
+                FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0,
+                FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP11_23_20 [4] */
+                FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0,
+                FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP11_19_16 [4] */
+                FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5,
+                0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0,
+                0, 0, 0, 0,
+                /* IP11_15_12 [4] */
+                FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4,
+                0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP11_11_8 [4] */
+                FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0,
+                FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP11_7_4 [4] */
+                FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0,
+                FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP11_3_0 [4] */
+                FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
+                FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP12_31_28 [4] */
+                FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP12_27_24 [4] */
+                FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP12_23_20 [4] */
+                FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6,
+                FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP12_19_16 [4] */
+                FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5,
+                FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP12_15_12 [4] */
+                FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP12_11_8 [4] */
+                FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP12_7_4 [4] */
+                FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP12_3_0 [4] */
+                FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP13_31_28 [4] */
+                FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0,
+                /* IP13_27_24 [4] */
+                FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP13_23_20 [4] */
+                FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C,
+                FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP13_19_16 [4] */
+                FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5,
+                FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP13_15_12 [4] */
+                FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4,
+                FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0,
+                /* IP13_11_8 [4] */
+                FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP13_7_4 [4] */
+                FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP13_3_0 [4] */
+                FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP14_31_28 [4] */
+                FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
+                FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP14_27_24 [4] */
+                FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0,
+                /* IP14_23_20 [4] */
+                FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP14_19_16 [4] */
+                FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP14_15_12 [4] */
+                FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP14_11_8 [4] */
+                FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP14_7_4 [4] */
+                FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP14_3_0 [4] */
+                FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP15_31_28 [4] */
+                FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP15_27_24 [4] */
+                FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                /* IP15_23_20 [4] */
+                FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A,
+                FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP15_19_16 [4] */
+                FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A,
+                FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP15_15_12 [4] */
+                FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1,
+                FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP15_11_8 [4] */
+                FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0,
+                FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP15_7_4 [4] */
+                FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0,
+                FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP15_3_0 [4] */
+                FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
+                FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP16_31_28 [4] */
+                FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
+                FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_27_24 [4] */
+                FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER,
+                FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_23_20 [4] */
+                FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7,
+                FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_19_16 [4] */
+                FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_15_12 [4] */
+                FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D,
+                FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0,
+                /* IP16_11_8 [4] */
+                FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D,
+                FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_7_4 [4] */
+                FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A,
+                FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_3_0 [4] */
+                FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
+                             4, 4, 4, 4, 4, 4, 4, 4) {
+                /* IP17_31_28 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP17_27_24 [4] */
+                FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
+                FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP17_23_20 [4] */
+                FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0,
+                FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP17_19_16 [4] */
+                FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0,
+                FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP17_15_12 [4] */
+                FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0,
+                FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP17_11_8 [4] */
+                FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0,
+                FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP17_7_4 [4] */
+                FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0,
+                FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP17_3_0 [4] */
+                FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
+                FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
+                             1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1, 3, 3,
+                                 1, 2, 3, 3, 1) {
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* SEL_ADGA [2] */
+                FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* SEL_CANCLK [2] */
+                FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
+                FN_SEL_CANCLK_3,
+                /* SEL_CAN1 [2] */
+                FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+                /* SEL_CAN0 [2] */
+                FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+                /* RESERVED [1] */
+                0, 0,
+                /* SEL_I2C04 [3] */
+                FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
+                FN_SEL_I2C04_4, 0, 0, 0,
+                /* SEL_I2C03 [3] */
+                FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
+                FN_SEL_I2C03_4, 0, 0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* SEL_I2C02 [2] */
+                FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
+                /* SEL_I2C01 [3] */
+                FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
+                FN_SEL_I2C01_4, 0, 0, 0,
+                /* SEL_I2C00 [3] */
+                FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
+                FN_SEL_I2C00_4, 0, 0, 0,
+                /* SEL_AVB [1] */
+                FN_SEL_AVB_0, FN_SEL_AVB_1, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
+                             1, 3, 3, 2, 2, 1, 2, 2,
+                             2, 1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 1) {
+                /* SEL_SCIFCLK [1] */
+                FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+                /* SEL_SCIF5 [3] */
+                FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
+                FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0,
+                /* SEL_SCIF4 [3] */
+                FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+                FN_SEL_SCIF4_4, 0, 0, 0,
+                /* SEL_SCIF3 [2] */
+                FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0,
+                /* SEL_SCIF2 [2] */
+                FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
+                /* SEL_SCIF2_CLK [1] */
+                FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
+                /* SEL_SCIF1 [2] */
+                FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+                /* SEL_SCIF0 [2] */
+                FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+                /* SEL_MSIOF2 [2] */
+                FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* SEL_MSIOF1 [1] */
+                FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
+                /* RESERVED [1] */
+                0, 0,
+                /* SEL_MSIOF0 [1] */
+                FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
+                /* SEL_RCN [1] */
+                FN_SEL_RCN_0, FN_SEL_RCN_1,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* SEL_TMU2 [1] */
+                FN_SEL_TMU2_0, FN_SEL_TMU2_1,
+                /* SEL_TMU1 [1] */
+                FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* SEL_HSCIF1 [2] */
+                FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
+                /* SEL_HSCIF0 [1] */
+                FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,}
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
+                             1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                                 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* SEL_ADGB [2] */
+                FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
+                /* SEL_ADGC [2] */
+                FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0,
+                /* SEL_SSI9 [2] */
+                FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0,
+                /* SEL_SSI8 [2] */
+                FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0,
+                /* SEL_SSI7 [2] */
+                FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0,
+                /* SEL_SSI6 [2] */
+                FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0,
+                /* SEL_SSI5 [2] */
+                FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0,
+                /* SEL_SSI4 [2] */
+                FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0,
+                /* SEL_SSI2 [2] */
+                FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0,
+                /* SEL_SSI1 [2] */
+                FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
+                /* SEL_SSI0 [2] */
+                FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, }
+        },
+        { },
+};
+
+#ifdef CONFIG_PINCTRL_PFC_R8A77470
+const struct sh_pfc_soc_info r8a77470_pinmux_info = {
+        .name = "r8a77470_pfc",
+        .unlock_reg = 0xe6060000, /* PMMR */
+
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .cfg_regs = pinmux_config_regs,
+
+        .pinmux_data = pinmux_data,
+        .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
+#endif
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index 82a1c411c952..a6c5d50557e6 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -1432,10 +1432,10 @@ static const u16 pinmux_data[] = {
 
 /*
  * Static pins can not be muxed between different functions but
- * still needs a mark entry in the pinmux list. Add each static
+ * still need mark entries in the pinmux list. Add each static
  * pin to the list without an associated function. The sh-pfc
- * core will do the right thing and skip trying to mux then pin
- * while still applying configuration to it
+ * core will do the right thing and skip trying to mux the pin
+ * while still applying configuration to it.
  */
 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
         PINMUX_STATIC
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 7100a2dd65f8..4f55b1562ad4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -1493,10 +1493,10 @@ static const u16 pinmux_data[] = {
 
 /*
  * Static pins can not be muxed between different functions but
- * still needs a mark entry in the pinmux list. Add each static
+ * still need mark entries in the pinmux list. Add each static
  * pin to the list without an associated function. The sh-pfc
- * core will do the right thing and skip trying to mux then pin
- * while still applying configuration to it
+ * core will do the right thing and skip trying to mux the pin
+ * while still applying configuration to it.
  */
 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
         PINMUX_STATIC
@@ -3122,7 +3122,7 @@ static const unsigned int msiof3_ss1_e_mux[] = {
         MSIOF3_SS1_E_MARK,
 };
 static const unsigned int msiof3_ss2_e_pins[] = {
-        /* SS1 */
+        /* SS2 */
         RCAR_GP_PIN(2, 0),
 };
 static const unsigned int msiof3_ss2_e_mux[] = {
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 4bc5b1f820c1..3ea133cfb241 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -1499,10 +1499,10 @@ static const u16 pinmux_data[] = {
 
 /*
  * Static pins can not be muxed between different functions but
- * still needs a mark entry in the pinmux list. Add each static
+ * still need mark entries in the pinmux list. Add each static
  * pin to the list without an associated function. The sh-pfc
- * core will do the right thing and skip trying to mux then pin
- * while still applying configuration to it
+ * core will do the right thing and skip trying to mux the pin
+ * while still applying configuration to it.
  */
 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
         PINMUX_STATIC
@@ -3122,7 +3122,7 @@ static const unsigned int msiof3_ss1_e_mux[] = {
         MSIOF3_SS1_E_MARK,
 };
 static const unsigned int msiof3_ss2_e_pins[] = {
-        /* SS1 */
+        /* SS2 */
         RCAR_GP_PIN(2, 0),
 };
 static const unsigned int msiof3_ss2_e_mux[] = {
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index cea9d0599c12..d2bbee656381 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.
+// SPDX-License-Identifier: GPL-2.0
 /*
  * R8A77965 processor support - PFC hardware block.
  *
@@ -1501,10 +1501,10 @@ static const u16 pinmux_data[] = {
 
 /*
  * Static pins can not be muxed between different functions but
- * still needs a mark entry in the pinmux list. Add each static
+ * still need mark entries in the pinmux list. Add each static
  * pin to the list without an associated function. The sh-pfc
- * core will do the right thing and skip trying to mux then pin
- * while still applying configuration to it
+ * core will do the right thing and skip trying to mux the pin
+ * while still applying configuration to it.
  */
 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
         PINMUX_STATIC
@@ -1662,6 +1662,153 @@ static const unsigned int avb_avtp_capture_b_mux[] = {
         AVB_AVTP_CAPTURE_B_MARK,
 };
 
+/* - DU --------------------------------------------------------------------- */
+static const unsigned int du_rgb666_pins[] = {
+        /* R[7:2], G[7:2], B[7:2] */
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
+        RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
+        RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+        RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
+        RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
+        RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
+};
+
+static const unsigned int du_rgb666_mux[] = {
+        DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
+        DU_DR3_MARK, DU_DR2_MARK,
+        DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
+        DU_DG3_MARK, DU_DG2_MARK,
+        DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
+        DU_DB3_MARK, DU_DB2_MARK,
+};
+
+static const unsigned int du_rgb888_pins[] = {
+        /* R[7:0], G[7:0], B[7:0] */
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
+        RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
+        RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
+        RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+        RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
+        RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
+        RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
+        RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
+        RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
+};
+
+static const unsigned int du_rgb888_mux[] = {
+        DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
+        DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
+        DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
+        DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
+        DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
+        DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
+};
+
+static const unsigned int du_clk_out_0_pins[] = {
+        /* CLKOUT */
+        RCAR_GP_PIN(1, 27),
+};
+
+static const unsigned int du_clk_out_0_mux[] = {
+        DU_DOTCLKOUT0_MARK
+};
+
+static const unsigned int du_clk_out_1_pins[] = {
+        /* CLKOUT */
+        RCAR_GP_PIN(2, 3),
+};
+
+static const unsigned int du_clk_out_1_mux[] = {
+        DU_DOTCLKOUT1_MARK
+};
+
+static const unsigned int du_sync_pins[] = {
+        /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
+        RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
+};
+
+static const unsigned int du_sync_mux[] = {
+        DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
+};
+
+static const unsigned int du_oddf_pins[] = {
+        /* EXDISP/EXODDF/EXCDE */
+        RCAR_GP_PIN(2, 2),
+};
+
+static const unsigned int du_oddf_mux[] = {
+        DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
+};
+
+static const unsigned int du_cde_pins[] = {
+        /* CDE */
+        RCAR_GP_PIN(2, 0),
+};
+
+static const unsigned int du_cde_mux[] = {
+        DU_CDE_MARK,
+};
+
+static const unsigned int du_disp_pins[] = {
+        /* DISP */
+        RCAR_GP_PIN(2, 1),
+};
+
+static const unsigned int du_disp_mux[] = {
+        DU_DISP_MARK,
+};
+
+/* - I2C -------------------------------------------------------------------- */
+static const unsigned int i2c1_a_pins[] = {
+        /* SDA, SCL */
+        RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int i2c1_a_mux[] = {
+        SDA1_A_MARK, SCL1_A_MARK,
+};
+static const unsigned int i2c1_b_pins[] = {
+        /* SDA, SCL */
+        RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
+};
+static const unsigned int i2c1_b_mux[] = {
+        SDA1_B_MARK, SCL1_B_MARK,
+};
+static const unsigned int i2c2_a_pins[] = {
+        /* SDA, SCL */
+        RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
+};
+static const unsigned int i2c2_a_mux[] = {
+        SDA2_A_MARK, SCL2_A_MARK,
+};
+static const unsigned int i2c2_b_pins[] = {
+        /* SDA, SCL */
+        RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int i2c2_b_mux[] = {
+        SDA2_B_MARK, SCL2_B_MARK,
+};
+static const unsigned int i2c6_a_pins[] = {
+        /* SDA, SCL */
+        RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
+};
+static const unsigned int i2c6_a_mux[] = {
+        SDA6_A_MARK, SCL6_A_MARK,
+};
+static const unsigned int i2c6_b_pins[] = {
+        /* SDA, SCL */
+        RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
+};
+static const unsigned int i2c6_b_mux[] = {
+        SDA6_B_MARK, SCL6_B_MARK,
+};
+static const unsigned int i2c6_c_pins[] = {
+        /* SDA, SCL */
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
+};
+static const unsigned int i2c6_c_mux[] = {
+        SDA6_C_MARK, SCL6_C_MARK,
+};
+
 /* - INTC-EX ---------------------------------------------------------------- */
 static const unsigned int intc_ex_irq0_pins[] = {
         /* IRQ0 */
@@ -1706,6 +1853,803 @@ static const unsigned int intc_ex_irq5_mux[] = {
         IRQ5_MARK,
 };
 
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 17),
+};
+static const unsigned int msiof0_clk_mux[] = {
+        MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(5, 18),
+};
+static const unsigned int msiof0_sync_mux[] = {
+        MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(5, 19),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+        MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(5, 21),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+        MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(5, 20),
+};
+static const unsigned int msiof0_txd_mux[] = {
+        MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(5, 22),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+        MSIOF0_RXD_MARK,
+};
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_a_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(6, 8),
+};
+static const unsigned int msiof1_clk_a_mux[] = {
+        MSIOF1_SCK_A_MARK,
+};
+static const unsigned int msiof1_sync_a_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(6, 9),
+};
+static const unsigned int msiof1_sync_a_mux[] = {
+        MSIOF1_SYNC_A_MARK,
+};
+static const unsigned int msiof1_ss1_a_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(6, 5),
+};
+static const unsigned int msiof1_ss1_a_mux[] = {
+        MSIOF1_SS1_A_MARK,
+};
+static const unsigned int msiof1_ss2_a_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(6, 6),
+};
+static const unsigned int msiof1_ss2_a_mux[] = {
+        MSIOF1_SS2_A_MARK,
+};
+static const unsigned int msiof1_txd_a_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(6, 7),
+};
+static const unsigned int msiof1_txd_a_mux[] = {
+        MSIOF1_TXD_A_MARK,
+};
+static const unsigned int msiof1_rxd_a_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(6, 10),
+};
+static const unsigned int msiof1_rxd_a_mux[] = {
+        MSIOF1_RXD_A_MARK,
+};
+static const unsigned int msiof1_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 9),
+};
+static const unsigned int msiof1_clk_b_mux[] = {
+        MSIOF1_SCK_B_MARK,
+};
+static const unsigned int msiof1_sync_b_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(5, 3),
+};
+static const unsigned int msiof1_sync_b_mux[] = {
+        MSIOF1_SYNC_B_MARK,
+};
+static const unsigned int msiof1_ss1_b_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(5, 4),
+};
+static const unsigned int msiof1_ss1_b_mux[] = {
+        MSIOF1_SS1_B_MARK,
+};
+static const unsigned int msiof1_ss2_b_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(5, 0),
+};
+static const unsigned int msiof1_ss2_b_mux[] = {
+        MSIOF1_SS2_B_MARK,
+};
+static const unsigned int msiof1_txd_b_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(5, 8),
+};
+static const unsigned int msiof1_txd_b_mux[] = {
+        MSIOF1_TXD_B_MARK,
+};
+static const unsigned int msiof1_rxd_b_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(5, 7),
+};
+static const unsigned int msiof1_rxd_b_mux[] = {
+        MSIOF1_RXD_B_MARK,
+};
+static const unsigned int msiof1_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(6, 17),
+};
+static const unsigned int msiof1_clk_c_mux[] = {
+        MSIOF1_SCK_C_MARK,
+};
+static const unsigned int msiof1_sync_c_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(6, 18),
+};
+static const unsigned int msiof1_sync_c_mux[] = {
+        MSIOF1_SYNC_C_MARK,
+};
+static const unsigned int msiof1_ss1_c_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(6, 21),
+};
+static const unsigned int msiof1_ss1_c_mux[] = {
+        MSIOF1_SS1_C_MARK,
+};
+static const unsigned int msiof1_ss2_c_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(6, 27),
+};
+static const unsigned int msiof1_ss2_c_mux[] = {
+        MSIOF1_SS2_C_MARK,
+};
+static const unsigned int msiof1_txd_c_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(6, 20),
+};
+static const unsigned int msiof1_txd_c_mux[] = {
+        MSIOF1_TXD_C_MARK,
+};
+static const unsigned int msiof1_rxd_c_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(6, 19),
+};
+static const unsigned int msiof1_rxd_c_mux[] = {
+        MSIOF1_RXD_C_MARK,
+};
+static const unsigned int msiof1_clk_d_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 12),
+};
+static const unsigned int msiof1_clk_d_mux[] = {
+        MSIOF1_SCK_D_MARK,
+};
+static const unsigned int msiof1_sync_d_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(5, 15),
+};
+static const unsigned int msiof1_sync_d_mux[] = {
+        MSIOF1_SYNC_D_MARK,
+};
+static const unsigned int msiof1_ss1_d_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(5, 16),
+};
+static const unsigned int msiof1_ss1_d_mux[] = {
+        MSIOF1_SS1_D_MARK,
+};
+static const unsigned int msiof1_ss2_d_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(5, 21),
+};
+static const unsigned int msiof1_ss2_d_mux[] = {
+        MSIOF1_SS2_D_MARK,
+};
+static const unsigned int msiof1_txd_d_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(5, 14),
+};
+static const unsigned int msiof1_txd_d_mux[] = {
+        MSIOF1_TXD_D_MARK,
+};
+static const unsigned int msiof1_rxd_d_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(5, 13),
+};
+static const unsigned int msiof1_rxd_d_mux[] = {
+        MSIOF1_RXD_D_MARK,
+};
+static const unsigned int msiof1_clk_e_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 0),
+};
+static const unsigned int msiof1_clk_e_mux[] = {
+        MSIOF1_SCK_E_MARK,
+};
+static const unsigned int msiof1_sync_e_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(3, 1),
+};
+static const unsigned int msiof1_sync_e_mux[] = {
+        MSIOF1_SYNC_E_MARK,
+};
+static const unsigned int msiof1_ss1_e_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(3, 4),
+};
+static const unsigned int msiof1_ss1_e_mux[] = {
+        MSIOF1_SS1_E_MARK,
+};
+static const unsigned int msiof1_ss2_e_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(3, 5),
+};
+static const unsigned int msiof1_ss2_e_mux[] = {
+        MSIOF1_SS2_E_MARK,
+};
+static const unsigned int msiof1_txd_e_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(3, 3),
+};
+static const unsigned int msiof1_txd_e_mux[] = {
+        MSIOF1_TXD_E_MARK,
+};
+static const unsigned int msiof1_rxd_e_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(3, 2),
+};
+static const unsigned int msiof1_rxd_e_mux[] = {
+        MSIOF1_RXD_E_MARK,
+};
+static const unsigned int msiof1_clk_f_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 23),
+};
+static const unsigned int msiof1_clk_f_mux[] = {
+        MSIOF1_SCK_F_MARK,
+};
+static const unsigned int msiof1_sync_f_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(5, 24),
+};
+static const unsigned int msiof1_sync_f_mux[] = {
+        MSIOF1_SYNC_F_MARK,
+};
+static const unsigned int msiof1_ss1_f_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(6, 1),
+};
+static const unsigned int msiof1_ss1_f_mux[] = {
+        MSIOF1_SS1_F_MARK,
+};
+static const unsigned int msiof1_ss2_f_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(6, 2),
+};
+static const unsigned int msiof1_ss2_f_mux[] = {
+        MSIOF1_SS2_F_MARK,
+};
+static const unsigned int msiof1_txd_f_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(6, 0),
+};
+static const unsigned int msiof1_txd_f_mux[] = {
+        MSIOF1_TXD_F_MARK,
+};
+static const unsigned int msiof1_rxd_f_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(5, 25),
+};
+static const unsigned int msiof1_rxd_f_mux[] = {
+        MSIOF1_RXD_F_MARK,
+};
+static const unsigned int msiof1_clk_g_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 6),
+};
+static const unsigned int msiof1_clk_g_mux[] = {
+        MSIOF1_SCK_G_MARK,
+};
+static const unsigned int msiof1_sync_g_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(3, 7),
+};
+static const unsigned int msiof1_sync_g_mux[] = {
+        MSIOF1_SYNC_G_MARK,
+};
+static const unsigned int msiof1_ss1_g_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(3, 10),
+};
+static const unsigned int msiof1_ss1_g_mux[] = {
+        MSIOF1_SS1_G_MARK,
+};
+static const unsigned int msiof1_ss2_g_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(3, 11),
+};
+static const unsigned int msiof1_ss2_g_mux[] = {
+        MSIOF1_SS2_G_MARK,
+};
+static const unsigned int msiof1_txd_g_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(3, 9),
+};
+static const unsigned int msiof1_txd_g_mux[] = {
+        MSIOF1_TXD_G_MARK,
+};
+static const unsigned int msiof1_rxd_g_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(3, 8),
+};
+static const unsigned int msiof1_rxd_g_mux[] = {
+        MSIOF1_RXD_G_MARK,
+};
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_a_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(1, 9),
+};
+static const unsigned int msiof2_clk_a_mux[] = {
+        MSIOF2_SCK_A_MARK,
+};
+static const unsigned int msiof2_sync_a_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(1, 8),
+};
+static const unsigned int msiof2_sync_a_mux[] = {
+        MSIOF2_SYNC_A_MARK,
+};
+static const unsigned int msiof2_ss1_a_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(1, 6),
+};
+static const unsigned int msiof2_ss1_a_mux[] = {
+        MSIOF2_SS1_A_MARK,
+};
+static const unsigned int msiof2_ss2_a_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(1, 7),
+};
+static const unsigned int msiof2_ss2_a_mux[] = {
+        MSIOF2_SS2_A_MARK,
+};
+static const unsigned int msiof2_txd_a_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(1, 11),
+};
+static const unsigned int msiof2_txd_a_mux[] = {
+        MSIOF2_TXD_A_MARK,
+};
+static const unsigned int msiof2_rxd_a_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(1, 10),
+};
+static const unsigned int msiof2_rxd_a_mux[] = {
+        MSIOF2_RXD_A_MARK,
+};
+static const unsigned int msiof2_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 4),
+};
+static const unsigned int msiof2_clk_b_mux[] = {
+        MSIOF2_SCK_B_MARK,
+};
+static const unsigned int msiof2_sync_b_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(0, 5),
+};
+static const unsigned int msiof2_sync_b_mux[] = {
+        MSIOF2_SYNC_B_MARK,
+};
+static const unsigned int msiof2_ss1_b_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(0, 0),
+};
+static const unsigned int msiof2_ss1_b_mux[] = {
+        MSIOF2_SS1_B_MARK,
+};
+static const unsigned int msiof2_ss2_b_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(0, 1),
+};
+static const unsigned int msiof2_ss2_b_mux[] = {
+        MSIOF2_SS2_B_MARK,
+};
+static const unsigned int msiof2_txd_b_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(0, 7),
+};
+static const unsigned int msiof2_txd_b_mux[] = {
+        MSIOF2_TXD_B_MARK,
+};
+static const unsigned int msiof2_rxd_b_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(0, 6),
+};
+static const unsigned int msiof2_rxd_b_mux[] = {
+        MSIOF2_RXD_B_MARK,
+};
+static const unsigned int msiof2_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 12),
+};
+static const unsigned int msiof2_clk_c_mux[] = {
+        MSIOF2_SCK_C_MARK,
+};
+static const unsigned int msiof2_sync_c_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(2, 11),
+};
+static const unsigned int msiof2_sync_c_mux[] = {
+        MSIOF2_SYNC_C_MARK,
+};
+static const unsigned int msiof2_ss1_c_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(2, 10),
+};
+static const unsigned int msiof2_ss1_c_mux[] = {
+        MSIOF2_SS1_C_MARK,
+};
+static const unsigned int msiof2_ss2_c_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(2, 9),
+};
+static const unsigned int msiof2_ss2_c_mux[] = {
+        MSIOF2_SS2_C_MARK,
+};
+static const unsigned int msiof2_txd_c_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(2, 14),
+};
+static const unsigned int msiof2_txd_c_mux[] = {
+        MSIOF2_TXD_C_MARK,
+};
+static const unsigned int msiof2_rxd_c_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(2, 13),
+};
+static const unsigned int msiof2_rxd_c_mux[] = {
+        MSIOF2_RXD_C_MARK,
+};
+static const unsigned int msiof2_clk_d_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 8),
+};
+static const unsigned int msiof2_clk_d_mux[] = {
+        MSIOF2_SCK_D_MARK,
+};
+static const unsigned int msiof2_sync_d_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(0, 9),
+};
+static const unsigned int msiof2_sync_d_mux[] = {
+        MSIOF2_SYNC_D_MARK,
+};
+static const unsigned int msiof2_ss1_d_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(0, 12),
+};
+static const unsigned int msiof2_ss1_d_mux[] = {
+        MSIOF2_SS1_D_MARK,
+};
+static const unsigned int msiof2_ss2_d_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(0, 13),
+};
+static const unsigned int msiof2_ss2_d_mux[] = {
+        MSIOF2_SS2_D_MARK,
+};
+static const unsigned int msiof2_txd_d_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(0, 11),
+};
+static const unsigned int msiof2_txd_d_mux[] = {
+        MSIOF2_TXD_D_MARK,
+};
+static const unsigned int msiof2_rxd_d_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(0, 10),
+};
+static const unsigned int msiof2_rxd_d_mux[] = {
+        MSIOF2_RXD_D_MARK,
+};
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_a_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 0),
+};
+static const unsigned int msiof3_clk_a_mux[] = {
+        MSIOF3_SCK_A_MARK,
+};
+static const unsigned int msiof3_sync_a_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(0, 1),
+};
+static const unsigned int msiof3_sync_a_mux[] = {
+        MSIOF3_SYNC_A_MARK,
+};
+static const unsigned int msiof3_ss1_a_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(0, 14),
+};
+static const unsigned int msiof3_ss1_a_mux[] = {
+        MSIOF3_SS1_A_MARK,
+};
+static const unsigned int msiof3_ss2_a_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(0, 15),
+};
+static const unsigned int msiof3_ss2_a_mux[] = {
+        MSIOF3_SS2_A_MARK,
+};
+static const unsigned int msiof3_txd_a_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(0, 3),
+};
+static const unsigned int msiof3_txd_a_mux[] = {
+        MSIOF3_TXD_A_MARK,
+};
+static const unsigned int msiof3_rxd_a_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(0, 2),
+};
+static const unsigned int msiof3_rxd_a_mux[] = {
+        MSIOF3_RXD_A_MARK,
+};
+static const unsigned int msiof3_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(1, 2),
+};
+static const unsigned int msiof3_clk_b_mux[] = {
+        MSIOF3_SCK_B_MARK,
+};
+static const unsigned int msiof3_sync_b_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(1, 0),
+};
+static const unsigned int msiof3_sync_b_mux[] = {
+        MSIOF3_SYNC_B_MARK,
+};
+static const unsigned int msiof3_ss1_b_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(1, 4),
+};
+static const unsigned int msiof3_ss1_b_mux[] = {
+        MSIOF3_SS1_B_MARK,
+};
+static const unsigned int msiof3_ss2_b_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(1, 5),
+};
+static const unsigned int msiof3_ss2_b_mux[] = {
+        MSIOF3_SS2_B_MARK,
+};
+static const unsigned int msiof3_txd_b_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(1, 1),
+};
+static const unsigned int msiof3_txd_b_mux[] = {
+        MSIOF3_TXD_B_MARK,
+};
+static const unsigned int msiof3_rxd_b_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(1, 3),
+};
+static const unsigned int msiof3_rxd_b_mux[] = {
+        MSIOF3_RXD_B_MARK,
+};
+static const unsigned int msiof3_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(1, 12),
+};
+static const unsigned int msiof3_clk_c_mux[] = {
+        MSIOF3_SCK_C_MARK,
+};
+static const unsigned int msiof3_sync_c_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(1, 13),
+};
+static const unsigned int msiof3_sync_c_mux[] = {
+        MSIOF3_SYNC_C_MARK,
+};
+static const unsigned int msiof3_txd_c_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(1, 15),
+};
+static const unsigned int msiof3_txd_c_mux[] = {
+        MSIOF3_TXD_C_MARK,
+};
+static const unsigned int msiof3_rxd_c_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(1, 14),
+};
+static const unsigned int msiof3_rxd_c_mux[] = {
+        MSIOF3_RXD_C_MARK,
+};
+static const unsigned int msiof3_clk_d_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(1, 22),
+};
+static const unsigned int msiof3_clk_d_mux[] = {
+        MSIOF3_SCK_D_MARK,
+};
+static const unsigned int msiof3_sync_d_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(1, 23),
+};
+static const unsigned int msiof3_sync_d_mux[] = {
+        MSIOF3_SYNC_D_MARK,
+};
+static const unsigned int msiof3_ss1_d_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(1, 26),
+};
+static const unsigned int msiof3_ss1_d_mux[] = {
+        MSIOF3_SS1_D_MARK,
+};
+static const unsigned int msiof3_txd_d_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(1, 25),
+};
+static const unsigned int msiof3_txd_d_mux[] = {
+        MSIOF3_TXD_D_MARK,
+};
+static const unsigned int msiof3_rxd_d_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(1, 24),
+};
+static const unsigned int msiof3_rxd_d_mux[] = {
+        MSIOF3_RXD_D_MARK,
+};
+static const unsigned int msiof3_clk_e_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 3),
+};
+static const unsigned int msiof3_clk_e_mux[] = {
+        MSIOF3_SCK_E_MARK,
+};
+static const unsigned int msiof3_sync_e_pins[] = {
+        /* SYNC */
+        RCAR_GP_PIN(2, 2),
+};
+static const unsigned int msiof3_sync_e_mux[] = {
+        MSIOF3_SYNC_E_MARK,
+};
+static const unsigned int msiof3_ss1_e_pins[] = {
+        /* SS1 */
+        RCAR_GP_PIN(2, 1),
+};
+static const unsigned int msiof3_ss1_e_mux[] = {
+        MSIOF3_SS1_E_MARK,
+};
+static const unsigned int msiof3_ss2_e_pins[] = {
+        /* SS2 */
+        RCAR_GP_PIN(2, 0),
+};
+static const unsigned int msiof3_ss2_e_mux[] = {
+        MSIOF3_SS2_E_MARK,
+};
+static const unsigned int msiof3_txd_e_pins[] = {
+        /* TXD */
+        RCAR_GP_PIN(2, 5),
+};
+static const unsigned int msiof3_txd_e_mux[] = {
+        MSIOF3_TXD_E_MARK,
+};
+static const unsigned int msiof3_rxd_e_pins[] = {
+        /* RXD */
+        RCAR_GP_PIN(2, 4),
+};
+static const unsigned int msiof3_rxd_e_mux[] = {
+        MSIOF3_RXD_E_MARK,
+};
+
+/* - PWM0 --------------------------------------------------------------------*/
+static const unsigned int pwm0_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 6),
+};
+static const unsigned int pwm0_mux[] = {
+        PWM0_MARK,
+};
+/* - PWM1 --------------------------------------------------------------------*/
+static const unsigned int pwm1_a_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 7),
+};
+static const unsigned int pwm1_a_mux[] = {
+        PWM1_A_MARK,
+};
+static const unsigned int pwm1_b_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(1, 8),
+};
+static const unsigned int pwm1_b_mux[] = {
+        PWM1_B_MARK,
+};
+/* - PWM2 --------------------------------------------------------------------*/
+static const unsigned int pwm2_a_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 8),
+};
+static const unsigned int pwm2_a_mux[] = {
+        PWM2_A_MARK,
+};
+static const unsigned int pwm2_b_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(1, 11),
+};
+static const unsigned int pwm2_b_mux[] = {
+        PWM2_B_MARK,
+};
+/* - PWM3 --------------------------------------------------------------------*/
+static const unsigned int pwm3_a_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(1, 0),
+};
+static const unsigned int pwm3_a_mux[] = {
+        PWM3_A_MARK,
+};
+static const unsigned int pwm3_b_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 2),
+};
+static const unsigned int pwm3_b_mux[] = {
+        PWM3_B_MARK,
+};
+/* - PWM4 --------------------------------------------------------------------*/
+static const unsigned int pwm4_a_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(1, 1),
+};
+static const unsigned int pwm4_a_mux[] = {
+        PWM4_A_MARK,
+};
+static const unsigned int pwm4_b_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 3),
+};
+static const unsigned int pwm4_b_mux[] = {
+        PWM4_B_MARK,
+};
+/* - PWM5 --------------------------------------------------------------------*/
+static const unsigned int pwm5_a_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(1, 2),
+};
+static const unsigned int pwm5_a_mux[] = {
+        PWM5_A_MARK,
+};
+static const unsigned int pwm5_b_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 4),
+};
+static const unsigned int pwm5_b_mux[] = {
+        PWM5_B_MARK,
+};
+/* - PWM6 --------------------------------------------------------------------*/
+static const unsigned int pwm6_a_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(1, 3),
+};
+static const unsigned int pwm6_a_mux[] = {
+        PWM6_A_MARK,
+};
+static const unsigned int pwm6_b_pins[] = {
+        /* PWM */
+        RCAR_GP_PIN(2, 5),
+};
+static const unsigned int pwm6_b_mux[] = {
+        PWM6_B_MARK,
+};
+
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
         /* RX, TX */
@@ -1917,6 +2861,264 @@ static const unsigned int scif_clk_b_mux[] = {
         SCIF_CLK_B_MARK,
 };
 
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 2),
+};
+
+static const unsigned int sdhi0_data1_mux[] = {
+        SD0_DAT0_MARK,
+};
+
+static const unsigned int sdhi0_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+        RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+
+static const unsigned int sdhi0_data4_mux[] = {
+        SD0_DAT0_MARK, SD0_DAT1_MARK,
+        SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+
+static const unsigned int sdhi0_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+};
+
+static const unsigned int sdhi0_ctrl_mux[] = {
+        SD0_CLK_MARK, SD0_CMD_MARK,
+};
+
+static const unsigned int sdhi0_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 12),
+};
+
+static const unsigned int sdhi0_cd_mux[] = {
+        SD0_CD_MARK,
+};
+
+static const unsigned int sdhi0_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 13),
+};
+
+static const unsigned int sdhi0_wp_mux[] = {
+        SD0_WP_MARK,
+};
+
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 8),
+};
+
+static const unsigned int sdhi1_data1_mux[] = {
+        SD1_DAT0_MARK,
+};
+
+static const unsigned int sdhi1_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+
+static const unsigned int sdhi1_data4_mux[] = {
+        SD1_DAT0_MARK, SD1_DAT1_MARK,
+        SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+
+static const unsigned int sdhi1_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+
+static const unsigned int sdhi1_ctrl_mux[] = {
+        SD1_CLK_MARK, SD1_CMD_MARK,
+};
+
+static const unsigned int sdhi1_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 14),
+};
+
+static const unsigned int sdhi1_cd_mux[] = {
+        SD1_CD_MARK,
+};
+
+static const unsigned int sdhi1_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 15),
+};
+
+static const unsigned int sdhi1_wp_mux[] = {
+        SD1_WP_MARK,
+};
+
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(4, 2),
+};
+
+static const unsigned int sdhi2_data1_mux[] = {
+        SD2_DAT0_MARK,
+};
+
+static const unsigned int sdhi2_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
+        RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
+};
+
+static const unsigned int sdhi2_data4_mux[] = {
+        SD2_DAT0_MARK, SD2_DAT1_MARK,
+        SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+
+static const unsigned int sdhi2_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
+        RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
+        RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+
+static const unsigned int sdhi2_data8_mux[] = {
+        SD2_DAT0_MARK, SD2_DAT1_MARK,
+        SD2_DAT2_MARK, SD2_DAT3_MARK,
+        SD2_DAT4_MARK, SD2_DAT5_MARK,
+        SD2_DAT6_MARK, SD2_DAT7_MARK,
+};
+
+static const unsigned int sdhi2_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
+};
+
+static const unsigned int sdhi2_ctrl_mux[] = {
+        SD2_CLK_MARK, SD2_CMD_MARK,
+};
+
+static const unsigned int sdhi2_cd_a_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(4, 13),
+};
+
+static const unsigned int sdhi2_cd_a_mux[] = {
+        SD2_CD_A_MARK,
+};
+
+static const unsigned int sdhi2_cd_b_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(5, 10),
+};
+
+static const unsigned int sdhi2_cd_b_mux[] = {
+        SD2_CD_B_MARK,
+};
+
+static const unsigned int sdhi2_wp_a_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(4, 14),
+};
+
+static const unsigned int sdhi2_wp_a_mux[] = {
+        SD2_WP_A_MARK,
+};
+
+static const unsigned int sdhi2_wp_b_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(5, 11),
+};
+
+static const unsigned int sdhi2_wp_b_mux[] = {
+        SD2_WP_B_MARK,
+};
+
+static const unsigned int sdhi2_ds_pins[] = {
+        /* DS */
+        RCAR_GP_PIN(4, 6),
+};
+
+static const unsigned int sdhi2_ds_mux[] = {
+        SD2_DS_MARK,
+};
+
+/* - SDHI3 ------------------------------------------------------------------ */
+static const unsigned int sdhi3_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(4, 9),
+};
+
+static const unsigned int sdhi3_data1_mux[] = {
+        SD3_DAT0_MARK,
+};
+
+static const unsigned int sdhi3_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
+        RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+};
+
+static const unsigned int sdhi3_data4_mux[] = {
+        SD3_DAT0_MARK, SD3_DAT1_MARK,
+        SD3_DAT2_MARK, SD3_DAT3_MARK,
+};
+
+static const unsigned int sdhi3_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
+        RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
+        RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
+        RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+};
+
+static const unsigned int sdhi3_data8_mux[] = {
+        SD3_DAT0_MARK, SD3_DAT1_MARK,
+        SD3_DAT2_MARK, SD3_DAT3_MARK,
+        SD3_DAT4_MARK, SD3_DAT5_MARK,
+        SD3_DAT6_MARK, SD3_DAT7_MARK,
+};
+
+static const unsigned int sdhi3_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
+};
+
+static const unsigned int sdhi3_ctrl_mux[] = {
+        SD3_CLK_MARK, SD3_CMD_MARK,
+};
+
+static const unsigned int sdhi3_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(4, 15),
+};
+
+static const unsigned int sdhi3_cd_mux[] = {
+        SD3_CD_MARK,
+};
+
+static const unsigned int sdhi3_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(4, 16),
+};
+
+static const unsigned int sdhi3_wp_mux[] = {
+        SD3_WP_MARK,
+};
+
+static const unsigned int sdhi3_ds_pins[] = {
+        /* DS */
+        RCAR_GP_PIN(4, 17),
+};
+
+static const unsigned int sdhi3_ds_mux[] = {
+        SD3_DS_MARK,
+};
+
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_pins[] = {
         /* PWEN, OVC */
@@ -1959,12 +3161,139 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
         SH_PFC_PIN_GROUP(avb_avtp_match_b),
         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
+        SH_PFC_PIN_GROUP(du_rgb666),
+        SH_PFC_PIN_GROUP(du_rgb888),
+        SH_PFC_PIN_GROUP(du_clk_out_0),
+        SH_PFC_PIN_GROUP(du_clk_out_1),
+        SH_PFC_PIN_GROUP(du_sync),
+        SH_PFC_PIN_GROUP(du_oddf),
+        SH_PFC_PIN_GROUP(du_cde),
+        SH_PFC_PIN_GROUP(du_disp),
+        SH_PFC_PIN_GROUP(i2c1_a),
+        SH_PFC_PIN_GROUP(i2c1_b),
+        SH_PFC_PIN_GROUP(i2c2_a),
+        SH_PFC_PIN_GROUP(i2c2_b),
+        SH_PFC_PIN_GROUP(i2c6_a),
+        SH_PFC_PIN_GROUP(i2c6_b),
+        SH_PFC_PIN_GROUP(i2c6_c),
         SH_PFC_PIN_GROUP(intc_ex_irq0),
         SH_PFC_PIN_GROUP(intc_ex_irq1),
         SH_PFC_PIN_GROUP(intc_ex_irq2),
         SH_PFC_PIN_GROUP(intc_ex_irq3),
         SH_PFC_PIN_GROUP(intc_ex_irq4),
         SH_PFC_PIN_GROUP(intc_ex_irq5),
+        SH_PFC_PIN_GROUP(msiof0_clk),
+        SH_PFC_PIN_GROUP(msiof0_sync),
+        SH_PFC_PIN_GROUP(msiof0_ss1),
+        SH_PFC_PIN_GROUP(msiof0_ss2),
+        SH_PFC_PIN_GROUP(msiof0_txd),
+        SH_PFC_PIN_GROUP(msiof0_rxd),
+        SH_PFC_PIN_GROUP(msiof1_clk_a),
+        SH_PFC_PIN_GROUP(msiof1_sync_a),
+        SH_PFC_PIN_GROUP(msiof1_ss1_a),
+        SH_PFC_PIN_GROUP(msiof1_ss2_a),
+        SH_PFC_PIN_GROUP(msiof1_txd_a),
+        SH_PFC_PIN_GROUP(msiof1_rxd_a),
+        SH_PFC_PIN_GROUP(msiof1_clk_b),
+        SH_PFC_PIN_GROUP(msiof1_sync_b),
+        SH_PFC_PIN_GROUP(msiof1_ss1_b),
+        SH_PFC_PIN_GROUP(msiof1_ss2_b),
+        SH_PFC_PIN_GROUP(msiof1_txd_b),
+        SH_PFC_PIN_GROUP(msiof1_rxd_b),
+        SH_PFC_PIN_GROUP(msiof1_clk_c),
+        SH_PFC_PIN_GROUP(msiof1_sync_c),
+        SH_PFC_PIN_GROUP(msiof1_ss1_c),
+        SH_PFC_PIN_GROUP(msiof1_ss2_c),
+        SH_PFC_PIN_GROUP(msiof1_txd_c),
+        SH_PFC_PIN_GROUP(msiof1_rxd_c),
+        SH_PFC_PIN_GROUP(msiof1_clk_d),
+        SH_PFC_PIN_GROUP(msiof1_sync_d),
+        SH_PFC_PIN_GROUP(msiof1_ss1_d),
+        SH_PFC_PIN_GROUP(msiof1_ss2_d),
+        SH_PFC_PIN_GROUP(msiof1_txd_d),
+        SH_PFC_PIN_GROUP(msiof1_rxd_d),
+        SH_PFC_PIN_GROUP(msiof1_clk_e),
+        SH_PFC_PIN_GROUP(msiof1_sync_e),
+        SH_PFC_PIN_GROUP(msiof1_ss1_e),
+        SH_PFC_PIN_GROUP(msiof1_ss2_e),
+        SH_PFC_PIN_GROUP(msiof1_txd_e),
+        SH_PFC_PIN_GROUP(msiof1_rxd_e),
+        SH_PFC_PIN_GROUP(msiof1_clk_f),
+        SH_PFC_PIN_GROUP(msiof1_sync_f),
+        SH_PFC_PIN_GROUP(msiof1_ss1_f),
+        SH_PFC_PIN_GROUP(msiof1_ss2_f),
+        SH_PFC_PIN_GROUP(msiof1_txd_f),
+        SH_PFC_PIN_GROUP(msiof1_rxd_f),
+        SH_PFC_PIN_GROUP(msiof1_clk_g),
+        SH_PFC_PIN_GROUP(msiof1_sync_g),
+        SH_PFC_PIN_GROUP(msiof1_ss1_g),
+        SH_PFC_PIN_GROUP(msiof1_ss2_g),
+        SH_PFC_PIN_GROUP(msiof1_txd_g),
+        SH_PFC_PIN_GROUP(msiof1_rxd_g),
+        SH_PFC_PIN_GROUP(msiof2_clk_a),
+        SH_PFC_PIN_GROUP(msiof2_sync_a),
+        SH_PFC_PIN_GROUP(msiof2_ss1_a),
+        SH_PFC_PIN_GROUP(msiof2_ss2_a),
+        SH_PFC_PIN_GROUP(msiof2_txd_a),
+        SH_PFC_PIN_GROUP(msiof2_rxd_a),
+        SH_PFC_PIN_GROUP(msiof2_clk_b),
+        SH_PFC_PIN_GROUP(msiof2_sync_b),
+        SH_PFC_PIN_GROUP(msiof2_ss1_b),
+        SH_PFC_PIN_GROUP(msiof2_ss2_b),
+        SH_PFC_PIN_GROUP(msiof2_txd_b),
+        SH_PFC_PIN_GROUP(msiof2_rxd_b),
+        SH_PFC_PIN_GROUP(msiof2_clk_c),
+        SH_PFC_PIN_GROUP(msiof2_sync_c),
+        SH_PFC_PIN_GROUP(msiof2_ss1_c),
+        SH_PFC_PIN_GROUP(msiof2_ss2_c),
+        SH_PFC_PIN_GROUP(msiof2_txd_c),
+        SH_PFC_PIN_GROUP(msiof2_rxd_c),
+        SH_PFC_PIN_GROUP(msiof2_clk_d),
+        SH_PFC_PIN_GROUP(msiof2_sync_d),
+        SH_PFC_PIN_GROUP(msiof2_ss1_d),
+        SH_PFC_PIN_GROUP(msiof2_ss2_d),
+        SH_PFC_PIN_GROUP(msiof2_txd_d),
+        SH_PFC_PIN_GROUP(msiof2_rxd_d),
+        SH_PFC_PIN_GROUP(msiof3_clk_a),
+        SH_PFC_PIN_GROUP(msiof3_sync_a),
+        SH_PFC_PIN_GROUP(msiof3_ss1_a),
+        SH_PFC_PIN_GROUP(msiof3_ss2_a),
+        SH_PFC_PIN_GROUP(msiof3_txd_a),
+        SH_PFC_PIN_GROUP(msiof3_rxd_a),
+        SH_PFC_PIN_GROUP(msiof3_clk_b),
+        SH_PFC_PIN_GROUP(msiof3_sync_b),
+        SH_PFC_PIN_GROUP(msiof3_ss1_b),
+        SH_PFC_PIN_GROUP(msiof3_ss2_b),
+        SH_PFC_PIN_GROUP(msiof3_txd_b),
+        SH_PFC_PIN_GROUP(msiof3_rxd_b),
+        SH_PFC_PIN_GROUP(msiof3_clk_c),
+        SH_PFC_PIN_GROUP(msiof3_sync_c),
+        SH_PFC_PIN_GROUP(msiof3_txd_c),
+        SH_PFC_PIN_GROUP(msiof3_rxd_c),
+        SH_PFC_PIN_GROUP(msiof3_clk_d),
+        SH_PFC_PIN_GROUP(msiof3_sync_d),
+        SH_PFC_PIN_GROUP(msiof3_ss1_d),
+        SH_PFC_PIN_GROUP(msiof3_txd_d),
+        SH_PFC_PIN_GROUP(msiof3_rxd_d),
+        SH_PFC_PIN_GROUP(msiof3_clk_e),
+        SH_PFC_PIN_GROUP(msiof3_sync_e),
+        SH_PFC_PIN_GROUP(msiof3_ss1_e),
+        SH_PFC_PIN_GROUP(msiof3_ss2_e),
+        SH_PFC_PIN_GROUP(msiof3_txd_e),
+        SH_PFC_PIN_GROUP(msiof3_rxd_e),
+        SH_PFC_PIN_GROUP(pwm0),
+        SH_PFC_PIN_GROUP(pwm1_a),
+        SH_PFC_PIN_GROUP(pwm1_b),
+        SH_PFC_PIN_GROUP(pwm2_a),
+        SH_PFC_PIN_GROUP(pwm2_b),
+        SH_PFC_PIN_GROUP(pwm3_a),
+        SH_PFC_PIN_GROUP(pwm3_b),
+        SH_PFC_PIN_GROUP(pwm4_a),
+        SH_PFC_PIN_GROUP(pwm4_b),
+        SH_PFC_PIN_GROUP(pwm5_a),
+        SH_PFC_PIN_GROUP(pwm5_b),
+        SH_PFC_PIN_GROUP(pwm6_a),
+        SH_PFC_PIN_GROUP(pwm6_b),
         SH_PFC_PIN_GROUP(scif0_data),
         SH_PFC_PIN_GROUP(scif0_clk),
         SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1994,6 +3323,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(scif5_clk_b),
         SH_PFC_PIN_GROUP(scif_clk_a),
         SH_PFC_PIN_GROUP(scif_clk_b),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_data1),
+        SH_PFC_PIN_GROUP(sdhi1_data4),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi1_cd),
+        SH_PFC_PIN_GROUP(sdhi1_wp),
+        SH_PFC_PIN_GROUP(sdhi2_data1),
+        SH_PFC_PIN_GROUP(sdhi2_data4),
+        SH_PFC_PIN_GROUP(sdhi2_data8),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(sdhi2_cd_a),
+        SH_PFC_PIN_GROUP(sdhi2_wp_a),
+        SH_PFC_PIN_GROUP(sdhi2_cd_b),
+        SH_PFC_PIN_GROUP(sdhi2_wp_b),
+        SH_PFC_PIN_GROUP(sdhi2_ds),
+        SH_PFC_PIN_GROUP(sdhi3_data1),
+        SH_PFC_PIN_GROUP(sdhi3_data4),
+        SH_PFC_PIN_GROUP(sdhi3_data8),
+        SH_PFC_PIN_GROUP(sdhi3_ctrl),
+        SH_PFC_PIN_GROUP(sdhi3_cd),
+        SH_PFC_PIN_GROUP(sdhi3_wp),
+        SH_PFC_PIN_GROUP(sdhi3_ds),
         SH_PFC_PIN_GROUP(usb0),
         SH_PFC_PIN_GROUP(usb1),
         SH_PFC_PIN_GROUP(usb30),
@@ -2013,6 +3368,33 @@ static const char * const avb_groups[] = {
         "avb_avtp_capture_b",
 };
 
+static const char * const du_groups[] = {
+        "du_rgb666",
+        "du_rgb888",
+        "du_clk_out_0",
+        "du_clk_out_1",
+        "du_sync",
+        "du_oddf",
+        "du_cde",
+        "du_disp",
+};
+
+static const char * const i2c1_groups[] = {
+        "i2c1_a",
+        "i2c1_b",
+};
+
+static const char * const i2c2_groups[] = {
+        "i2c2_a",
+        "i2c2_b",
+};
+
+static const char * const i2c6_groups[] = {
+        "i2c6_a",
+        "i2c6_b",
+        "i2c6_c",
+};
+
 static const char * const intc_ex_groups[] = {
         "intc_ex_irq0",
         "intc_ex_irq1",
@@ -2022,6 +3404,151 @@ static const char * const intc_ex_groups[] = {
         "intc_ex_irq5",
 };
 
+static const char * const msiof0_groups[] = {
+        "msiof0_clk",
+        "msiof0_sync",
+        "msiof0_ss1",
+        "msiof0_ss2",
+        "msiof0_txd",
+        "msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+        "msiof1_clk_a",
+        "msiof1_sync_a",
+        "msiof1_ss1_a",
+        "msiof1_ss2_a",
+        "msiof1_txd_a",
+        "msiof1_rxd_a",
+        "msiof1_clk_b",
+        "msiof1_sync_b",
+        "msiof1_ss1_b",
+        "msiof1_ss2_b",
+        "msiof1_txd_b",
+        "msiof1_rxd_b",
+        "msiof1_clk_c",
+        "msiof1_sync_c",
+        "msiof1_ss1_c",
+        "msiof1_ss2_c",
+        "msiof1_txd_c",
+        "msiof1_rxd_c",
+        "msiof1_clk_d",
+        "msiof1_sync_d",
+        "msiof1_ss1_d",
+        "msiof1_ss2_d",
+        "msiof1_txd_d",
+        "msiof1_rxd_d",
+        "msiof1_clk_e",
+        "msiof1_sync_e",
+        "msiof1_ss1_e",
+        "msiof1_ss2_e",
+        "msiof1_txd_e",
+        "msiof1_rxd_e",
+        "msiof1_clk_f",
+        "msiof1_sync_f",
+        "msiof1_ss1_f",
+        "msiof1_ss2_f",
+        "msiof1_txd_f",
+        "msiof1_rxd_f",
+        "msiof1_clk_g",
+        "msiof1_sync_g",
+        "msiof1_ss1_g",
+        "msiof1_ss2_g",
+        "msiof1_txd_g",
+        "msiof1_rxd_g",
+};
+
+static const char * const msiof2_groups[] = {
+        "msiof2_clk_a",
+        "msiof2_sync_a",
+        "msiof2_ss1_a",
+        "msiof2_ss2_a",
+        "msiof2_txd_a",
+        "msiof2_rxd_a",
+        "msiof2_clk_b",
+        "msiof2_sync_b",
+        "msiof2_ss1_b",
+        "msiof2_ss2_b",
+        "msiof2_txd_b",
+        "msiof2_rxd_b",
+        "msiof2_clk_c",
+        "msiof2_sync_c",
+        "msiof2_ss1_c",
+        "msiof2_ss2_c",
+        "msiof2_txd_c",
+        "msiof2_rxd_c",
+        "msiof2_clk_d",
+        "msiof2_sync_d",
+        "msiof2_ss1_d",
+        "msiof2_ss2_d",
+        "msiof2_txd_d",
+        "msiof2_rxd_d",
+};
+
+static const char * const msiof3_groups[] = {
+        "msiof3_clk_a",
+        "msiof3_sync_a",
+        "msiof3_ss1_a",
+        "msiof3_ss2_a",
+        "msiof3_txd_a",
+        "msiof3_rxd_a",
+        "msiof3_clk_b",
+        "msiof3_sync_b",
+        "msiof3_ss1_b",
+        "msiof3_ss2_b",
+        "msiof3_txd_b",
+        "msiof3_rxd_b",
+        "msiof3_clk_c",
+        "msiof3_sync_c",
+        "msiof3_txd_c",
+        "msiof3_rxd_c",
+        "msiof3_clk_d",
+        "msiof3_sync_d",
+        "msiof3_ss1_d",
+        "msiof3_txd_d",
+        "msiof3_rxd_d",
+        "msiof3_clk_e",
+        "msiof3_sync_e",
+        "msiof3_ss1_e",
+        "msiof3_ss2_e",
+        "msiof3_txd_e",
+        "msiof3_rxd_e",
+};
+
+static const char * const pwm0_groups[] = {
+        "pwm0",
+};
+
+static const char * const pwm1_groups[] = {
+        "pwm1_a",
+        "pwm1_b",
+};
+
+static const char * const pwm2_groups[] = {
+        "pwm2_a",
+        "pwm2_b",
+};
+
+static const char * const pwm3_groups[] = {
+        "pwm3_a",
+        "pwm3_b",
+};
+
+static const char * const pwm4_groups[] = {
+        "pwm4_a",
+        "pwm4_b",
+};
+
+static const char * const pwm5_groups[] = {
+        "pwm5_a",
+        "pwm5_b",
+};
+
+static const char * const pwm6_groups[] = {
+        "pwm6_a",
+        "pwm6_b",
+};
+
 static const char * const scif0_groups[] = {
         "scif0_data",
         "scif0_clk",
@@ -2071,6 +3598,44 @@ static const char * const scif_clk_groups[] = {
         "scif_clk_b",
 };
 
+static const char * const sdhi0_groups[] = {
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_ctrl",
+        "sdhi0_cd",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_data1",
+        "sdhi1_data4",
+        "sdhi1_ctrl",
+        "sdhi1_cd",
+        "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_data1",
+        "sdhi2_data4",
+        "sdhi2_data8",
+        "sdhi2_ctrl",
+        "sdhi2_cd_a",
+        "sdhi2_wp_a",
+        "sdhi2_cd_b",
+        "sdhi2_wp_b",
+        "sdhi2_ds",
+};
+
+static const char * const sdhi3_groups[] = {
+        "sdhi3_data1",
+        "sdhi3_data4",
+        "sdhi3_data8",
+        "sdhi3_ctrl",
+        "sdhi3_cd",
+        "sdhi3_wp",
+        "sdhi3_ds",
+};
+
 static const char * const usb0_groups[] = {
         "usb0",
 };
@@ -2085,7 +3650,22 @@ static const char * const usb30_groups[] = {
 
 static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(avb),
+        SH_PFC_FUNCTION(du),
+        SH_PFC_FUNCTION(i2c1),
+        SH_PFC_FUNCTION(i2c2),
+        SH_PFC_FUNCTION(i2c6),
         SH_PFC_FUNCTION(intc_ex),
+        SH_PFC_FUNCTION(msiof0),
+        SH_PFC_FUNCTION(msiof1),
+        SH_PFC_FUNCTION(msiof2),
+        SH_PFC_FUNCTION(msiof3),
+        SH_PFC_FUNCTION(pwm0),
+        SH_PFC_FUNCTION(pwm1),
+        SH_PFC_FUNCTION(pwm2),
+        SH_PFC_FUNCTION(pwm3),
+        SH_PFC_FUNCTION(pwm4),
+        SH_PFC_FUNCTION(pwm5),
+        SH_PFC_FUNCTION(pwm6),
         SH_PFC_FUNCTION(scif0),
         SH_PFC_FUNCTION(scif1),
         SH_PFC_FUNCTION(scif2),
@@ -2093,6 +3673,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(scif4),
         SH_PFC_FUNCTION(scif5),
         SH_PFC_FUNCTION(scif_clk),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(sdhi3),
         SH_PFC_FUNCTION(usb0),
         SH_PFC_FUNCTION(usb1),
         SH_PFC_FUNCTION(usb30),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
index b1bb7263532b..b02caf316711 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
@@ -21,13 +21,15 @@
 #include "core.h"
 #include "sh_pfc.h"
 
+#define CFG_FLAGS SH_PFC_PIN_CFG_DRIVE_STRENGTH
+
 #define CPU_ALL_PORT(fn, sfx)                                           \
-        PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
-        PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
-        PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
-        PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),      \
-        PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH),       \
-        PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
+        PORT_GP_CFG_22(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+        PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS),                          \
+        PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+        PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+        PORT_GP_CFG_6(4,  fn, sfx, CFG_FLAGS),                          \
+        PORT_GP_CFG_15(5, fn, sfx, CFG_FLAGS)
 /*
  * F_() : just information
  * FM() : macro for FN_xxx / xxx_MARK
@@ -2382,18 +2384,31 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { },
 };
 
+enum ioctrl_regs {
+        IOCTRL30,
+        IOCTRL31,
+        IOCTRL32,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+        [IOCTRL30] = { 0xe6060380 },
+        [IOCTRL31] = { 0xe6060384 },
+        [IOCTRL32] = { 0xe6060388 },
+        { /* sentinel */ },
+};
+
 static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
                                    u32 *pocctrl)
 {
         int bit = pin & 0x1f;
 
-        *pocctrl = 0xe6060380;
+        *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
         if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
                 return bit;
         if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
                 return bit + 22;
 
-        *pocctrl += 4;
+        *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
         if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
                 return bit - 10;
         if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
@@ -2421,6 +2436,7 @@ const struct sh_pfc_soc_info r8a77970_pinmux_info = {
         .nr_functions = ARRAY_SIZE(pinmux_functions),
 
         .cfg_regs = pinmux_config_regs,
+        .ioctrl_regs = pinmux_ioctrl_regs,
 
         .pinmux_data = pinmux_data,
         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
index 84c8f1c2f1d1..3f6967331f64 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
@@ -19,10 +19,10 @@
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, sfx)   \
-        PORT_GP_22(0, fn, sfx), \
+        PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),  \
         PORT_GP_28(1, fn, sfx), \
-        PORT_GP_30(2, fn, sfx), \
-        PORT_GP_17(3, fn, sfx), \
+        PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),  \
+        PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
         PORT_GP_25(4, fn, sfx), \
         PORT_GP_15(5, fn, sfx)
 
@@ -2779,8 +2779,53 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         { },
 };
 
+enum ioctrl_regs {
+        IOCTRL30,
+        IOCTRL31,
+        IOCTRL32,
+        IOCTRL33,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+        [IOCTRL30] = { 0xe6060380, },
+        [IOCTRL31] = { 0xe6060384, },
+        [IOCTRL32] = { 0xe6060388, },
+        [IOCTRL33] = { 0xe606038c, },
+        { /* sentinel */ },
+};
+
+static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
+                                   u32 *pocctrl)
+{
+        int bit = pin & 0x1f;
+
+        *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
+        if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
+                return bit;
+        else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+                return bit + 22;
+
+        *pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
+        if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
+                return bit - 10;
+        if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
+            (pin >= RCAR_GP_PIN(3,  0) && pin <= RCAR_GP_PIN(3, 16)))
+                return bit + 7;
+
+        *pocctrl = pinmux_ioctrl_regs[IOCTRL32].reg;
+        if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
+                return pin - 25;
+
+        return -EINVAL;
+}
+
+static const struct sh_pfc_soc_operations pinmux_ops = {
+        .pin_to_pocctrl = r8a77980_pin_to_pocctrl,
+};
+
 const struct sh_pfc_soc_info r8a77980_pinmux_info = {
         .name = "r8a77980_pfc",
+        .ops = &pinmux_ops,
         .unlock_reg = 0xe6060000, /* PMMR */
 
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
@@ -2793,6 +2838,7 @@ const struct sh_pfc_soc_info r8a77980_pinmux_info = {
         .nr_functions = ARRAY_SIZE(pinmux_functions),
 
         .cfg_regs = pinmux_config_regs,
+        .ioctrl_regs = pinmux_ioctrl_regs,
 
         .pinmux_data = pinmux_data,
         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
new file mode 100644
index 000000000000..a68fd658aada
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -0,0 +1,2695 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R8A77990 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ *
+ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+ *
+ * R8A7796 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
+ */
+
+#include <linux/kernel.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \
+                   SH_PFC_PIN_CFG_PULL_DOWN)
+
+#define CPU_ALL_PORT(fn, sfx) \
+        PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
+        PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
+        PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
+        PORT_GP_CFG_16(3, fn, sfx, CFG_FLAGS), \
+        PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS), \
+        PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
+        PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS)
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_17        F_(SDA4,                IP7_27_24)
+#define GPSR0_16        F_(SCL4,                IP7_23_20)
+#define GPSR0_15        F_(D15,                 IP7_19_16)
+#define GPSR0_14        F_(D14,                 IP7_15_12)
+#define GPSR0_13        F_(D13,                 IP7_11_8)
+#define GPSR0_12        F_(D12,                 IP7_7_4)
+#define GPSR0_11        F_(D11,                 IP7_3_0)
+#define GPSR0_10        F_(D10,                 IP6_31_28)
+#define GPSR0_9         F_(D9,                  IP6_27_24)
+#define GPSR0_8         F_(D8,                  IP6_23_20)
+#define GPSR0_7         F_(D7,                  IP6_19_16)
+#define GPSR0_6         F_(D6,                  IP6_15_12)
+#define GPSR0_5         F_(D5,                  IP6_11_8)
+#define GPSR0_4         F_(D4,                  IP6_7_4)
+#define GPSR0_3         F_(D3,                  IP6_3_0)
+#define GPSR0_2         F_(D2,                  IP5_31_28)
+#define GPSR0_1         F_(D1,                  IP5_27_24)
+#define GPSR0_0         F_(D0,                  IP5_23_20)
+
+/* GPSR1 */
+#define GPSR1_22        F_(WE0_N,               IP5_19_16)
+#define GPSR1_21        F_(CS0_N,               IP5_15_12)
+#define GPSR1_20        FM(CLKOUT)
+#define GPSR1_19        F_(A19,                 IP5_11_8)
+#define GPSR1_18        F_(A18,                 IP5_7_4)
+#define GPSR1_17        F_(A17,                 IP5_3_0)
+#define GPSR1_16        F_(A16,                 IP4_31_28)
+#define GPSR1_15        F_(A15,                 IP4_27_24)
+#define GPSR1_14        F_(A14,                 IP4_23_20)
+#define GPSR1_13        F_(A13,                 IP4_19_16)
+#define GPSR1_12        F_(A12,                 IP4_15_12)
+#define GPSR1_11        F_(A11,                 IP4_11_8)
+#define GPSR1_10        F_(A10,                 IP4_7_4)
+#define GPSR1_9         F_(A9,                  IP4_3_0)
+#define GPSR1_8         F_(A8,                  IP3_31_28)
+#define GPSR1_7         F_(A7,                  IP3_27_24)
+#define GPSR1_6         F_(A6,                  IP3_23_20)
+#define GPSR1_5         F_(A5,                  IP3_19_16)
+#define GPSR1_4         F_(A4,                  IP3_15_12)
+#define GPSR1_3         F_(A3,                  IP3_11_8)
+#define GPSR1_2         F_(A2,                  IP3_7_4)
+#define GPSR1_1         F_(A1,                  IP3_3_0)
+#define GPSR1_0         F_(A0,                  IP2_31_28)
+
+/* GPSR2 */
+#define GPSR2_25        F_(EX_WAIT0,            IP2_27_24)
+#define GPSR2_24        F_(RD_WR_N,             IP2_23_20)
+#define GPSR2_23        F_(RD_N,                IP2_19_16)
+#define GPSR2_22        F_(BS_N,                IP2_15_12)
+#define GPSR2_21        FM(AVB_PHY_INT)
+#define GPSR2_20        F_(AVB_TXCREFCLK,       IP2_3_0)
+#define GPSR2_19        FM(AVB_RD3)
+#define GPSR2_18        F_(AVB_RD2,             IP1_31_28)
+#define GPSR2_17        F_(AVB_RD1,             IP1_27_24)
+#define GPSR2_16        F_(AVB_RD0,             IP1_23_20)
+#define GPSR2_15        FM(AVB_RXC)
+#define GPSR2_14        FM(AVB_RX_CTL)
+#define GPSR2_13        F_(RPC_RESET_N,         IP1_19_16)
+#define GPSR2_12        F_(RPC_INT_N,           IP1_15_12)
+#define GPSR2_11        F_(QSPI1_SSL,           IP1_11_8)
+#define GPSR2_10        F_(QSPI1_IO3,           IP1_7_4)
+#define GPSR2_9         F_(QSPI1_IO2,           IP1_3_0)
+#define GPSR2_8         F_(QSPI1_MISO_IO1,      IP0_31_28)
+#define GPSR2_7         F_(QSPI1_MOSI_IO0,      IP0_27_24)
+#define GPSR2_6         F_(QSPI1_SPCLK,         IP0_23_20)
+#define GPSR2_5         FM(QSPI0_SSL)
+#define GPSR2_4         F_(QSPI0_IO3,           IP0_19_16)
+#define GPSR2_3         F_(QSPI0_IO2,           IP0_15_12)
+#define GPSR2_2         F_(QSPI0_MISO_IO1,      IP0_11_8)
+#define GPSR2_1         F_(QSPI0_MOSI_IO0,      IP0_7_4)
+#define GPSR2_0         F_(QSPI0_SPCLK,         IP0_3_0)
+
+/* GPSR3 */
+#define GPSR3_15        F_(SD1_WP,              IP11_7_4)
+#define GPSR3_14        F_(SD1_CD,              IP11_3_0)
+#define GPSR3_13        F_(SD0_WP,              IP10_31_28)
+#define GPSR3_12        F_(SD0_CD,              IP10_27_24)
+#define GPSR3_11        F_(SD1_DAT3,            IP9_11_8)
+#define GPSR3_10        F_(SD1_DAT2,            IP9_7_4)
+#define GPSR3_9         F_(SD1_DAT1,            IP9_3_0)
+#define GPSR3_8         F_(SD1_DAT0,            IP8_31_28)
+#define GPSR3_7         F_(SD1_CMD,             IP8_27_24)
+#define GPSR3_6         F_(SD1_CLK,             IP8_23_20)
+#define GPSR3_5         F_(SD0_DAT3,            IP8_19_16)
+#define GPSR3_4         F_(SD0_DAT2,            IP8_15_12)
+#define GPSR3_3         F_(SD0_DAT1,            IP8_11_8)
+#define GPSR3_2         F_(SD0_DAT0,            IP8_7_4)
+#define GPSR3_1         F_(SD0_CMD,             IP8_3_0)
+#define GPSR3_0         F_(SD0_CLK,             IP7_31_28)
+
+/* GPSR4 */
+#define GPSR4_10        F_(SD3_DS,              IP10_23_20)
+#define GPSR4_9         F_(SD3_DAT7,            IP10_19_16)
+#define GPSR4_8         F_(SD3_DAT6,            IP10_15_12)
+#define GPSR4_7         F_(SD3_DAT5,            IP10_11_8)
+#define GPSR4_6         F_(SD3_DAT4,            IP10_7_4)
+#define GPSR4_5         F_(SD3_DAT3,            IP10_3_0)
+#define GPSR4_4         F_(SD3_DAT2,            IP9_31_28)
+#define GPSR4_3         F_(SD3_DAT1,            IP9_27_24)
+#define GPSR4_2         F_(SD3_DAT0,            IP9_23_20)
+#define GPSR4_1         F_(SD3_CMD,             IP9_19_16)
+#define GPSR4_0         F_(SD3_CLK,             IP9_15_12)
+
+/* GPSR5 */
+#define GPSR5_19        F_(MLB_DAT,             IP13_23_20)
+#define GPSR5_18        F_(MLB_SIG,             IP13_19_16)
+#define GPSR5_17        F_(MLB_CLK,             IP13_15_12)
+#define GPSR5_16        F_(SSI_SDATA9,          IP13_11_8)
+#define GPSR5_15        F_(MSIOF0_SS2,          IP13_7_4)
+#define GPSR5_14        F_(MSIOF0_SS1,          IP13_3_0)
+#define GPSR5_13        F_(MSIOF0_SYNC,         IP12_31_28)
+#define GPSR5_12        F_(MSIOF0_TXD,          IP12_27_24)
+#define GPSR5_11        F_(MSIOF0_RXD,          IP12_23_20)
+#define GPSR5_10        F_(MSIOF0_SCK,          IP12_19_16)
+#define GPSR5_9         F_(RX2_A,               IP12_15_12)
+#define GPSR5_8         F_(TX2_A,               IP12_11_8)
+#define GPSR5_7         F_(SCK2_A,              IP12_7_4)
+#define GPSR5_6         F_(TX1,                 IP12_3_0)
+#define GPSR5_5         F_(RX1,                 IP11_31_28)
+#define GPSR5_4         F_(RTS0_N_TANS_A,       IP11_23_20)
+#define GPSR5_3         F_(CTS0_N_A,            IP11_19_16)
+#define GPSR5_2         F_(TX0_A,               IP11_15_12)
+#define GPSR5_1         F_(RX0_A,               IP11_11_8)
+#define GPSR5_0         F_(SCK0_A,              IP11_27_24)
+
+/* GPSR6 */
+#define GPSR6_17        F_(USB30_PWEN,          IP15_27_24)
+#define GPSR6_16        F_(SSI_SDATA6,          IP15_19_16)
+#define GPSR6_15        F_(SSI_WS6,             IP15_15_12)
+#define GPSR6_14        F_(SSI_SCK6,            IP15_11_8)
+#define GPSR6_13        F_(SSI_SDATA5,          IP15_7_4)
+#define GPSR6_12        F_(SSI_WS5,             IP15_3_0)
+#define GPSR6_11        F_(SSI_SCK5,            IP14_31_28)
+#define GPSR6_10        F_(SSI_SDATA4,          IP14_27_24)
+#define GPSR6_9         F_(USB30_OVC,           IP15_31_28)
+#define GPSR6_8         F_(AUDIO_CLKA,          IP15_23_20)
+#define GPSR6_7         F_(SSI_SDATA3,          IP14_23_20)
+#define GPSR6_6         F_(SSI_WS349,           IP14_19_16)
+#define GPSR6_5         F_(SSI_SCK349,          IP14_15_12)
+#define GPSR6_4         F_(SSI_SDATA2,          IP14_11_8)
+#define GPSR6_3         F_(SSI_SDATA1,          IP14_7_4)
+#define GPSR6_2         F_(SSI_SDATA0,          IP14_3_0)
+#define GPSR6_1         F_(SSI_WS01239,         IP13_31_28)
+#define GPSR6_0         F_(SSI_SCK01239,        IP13_27_24)
+
+/* IPSRx */             /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */         /* 8 */         /* 9 - F */
+#define IP0_3_0         FM(QSPI0_SPCLK)         FM(HSCK4_A)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_7_4         FM(QSPI0_MOSI_IO0)      FM(HCTS4_N_A)           F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_11_8        FM(QSPI0_MISO_IO1)      FM(HRTS4_N_A)           F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_15_12       FM(QSPI0_IO2)           FM(HTX4_A)              F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_19_16       FM(QSPI0_IO3)           FM(HRX4_A)              F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_23_20       FM(QSPI1_SPCLK)         FM(RIF2_CLK_A)          FM(HSCK4_B)             FM(VI4_DATA0_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24       FM(QSPI1_MOSI_IO0)      FM(RIF2_SYNC_A)         FM(HTX4_B)              FM(VI4_DATA1_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28       FM(QSPI1_MISO_IO1)      FM(RIF2_D0_A)           FM(HRX4_B)              FM(VI4_DATA2_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_3_0         FM(QSPI1_IO2)           FM(RIF2_D1_A)           FM(HTX3_C)              FM(VI4_DATA3_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_7_4         FM(QSPI1_IO3)           FM(RIF3_CLK_A)          FM(HRX3_C)              FM(VI4_DATA4_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_11_8        FM(QSPI1_SSL)           FM(RIF3_SYNC_A)         FM(HSCK3_C)             FM(VI4_DATA5_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_15_12       FM(RPC_INT_N)           FM(RIF3_D0_A)           FM(HCTS3_N_C)           FM(VI4_DATA6_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_19_16       FM(RPC_RESET_N)         FM(RIF3_D1_A)           FM(HRTS3_N_C)           FM(VI4_DATA7_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_23_20       FM(AVB_RD0)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_27_24       FM(AVB_RD1)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1_31_28       FM(AVB_RD2)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_3_0         FM(AVB_TXCREFCLK)       F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_7_4         FM(AVB_MDIO)            F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_11_8        FM(AVB_MDC)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_15_12       FM(BS_N)                FM(PWM0_A)              FM(AVB_MAGIC)           FM(VI4_CLK)             F_(0, 0)                FM(TX3_C)       F_(0, 0)        FM(VI5_CLK_B)   F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_19_16       FM(RD_N)                FM(PWM1_A)              FM(AVB_LINK)            FM(VI4_FIELD)           F_(0, 0)                FM(RX3_C)       FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0)       F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20       FM(RD_WR_N)             FM(SCL7_A)              FM(AVB_AVTP_MATCH_A)    FM(VI4_VSYNC_N)         FM(TX5_B)               FM(SCK3_C)      FM(PWM5_A)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24       FM(EX_WAIT0)            FM(SDA7_A)              FM(AVB_AVTP_CAPTURE_A)  FM(VI4_HSYNC_N)         FM(RX5_B)               FM(PWM6_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_31_28       FM(A0)                  FM(IRQ0)                FM(PWM2_A)              FM(MSIOF3_SS1_B)        FM(VI5_CLK_A)           FM(DU_CDE)      FM(HRX3_D)      FM(IERX)        FM(QSTB_QHE)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_3_0         FM(A1)                  FM(IRQ1)                FM(PWM3_A)              FM(DU_DOTCLKIN1)        FM(VI5_DATA0_A)         FM(DU_DISP_CDE) FM(SDA6_B)      FM(IETX)        FM(QCPV_QDE)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_7_4         FM(A2)                  FM(IRQ2)                FM(AVB_AVTP_PPS)        FM(VI4_CLKENB)          FM(VI5_DATA1_A)         FM(DU_DISP)     FM(SCL6_B)      F_(0, 0)        FM(QSTVB_QVE)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_11_8        FM(A3)                  FM(CTS4_N_A)            FM(PWM4_A)              FM(VI4_DATA12)          F_(0, 0)                FM(DU_DOTCLKOUT0) FM(HTX3_D)    FM(IECLK)       FM(LCDOUT12)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_15_12       FM(A4)                  FM(RTS4_N_TANS_A)       FM(MSIOF3_SYNC_B)       FM(VI4_DATA8)           FM(PWM2_B)              FM(DU_DG4)      FM(RIF2_CLK_B)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_19_16       FM(A5)                  FM(SCK4_A)              FM(MSIOF3_SCK_B)        FM(VI4_DATA9)           FM(PWM3_B)              F_(0, 0)        FM(RIF2_SYNC_B) F_(0, 0)        FM(QPOLA)       F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_23_20       FM(A6)                  FM(RX4_A)               FM(MSIOF3_RXD_B)        FM(VI4_DATA10)          F_(0, 0)                F_(0, 0)        FM(RIF2_D0_B)   F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_27_24       FM(A7)                  FM(TX4_A)               FM(MSIOF3_TXD_B)        FM(VI4_DATA11)          F_(0, 0)                F_(0, 0)        FM(RIF2_D1_B)   F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3_31_28       FM(A8)                  FM(SDA6_A)              FM(RX3_B)               FM(HRX4_C)              FM(VI5_HSYNC_N_A)       FM(DU_HSYNC)    FM(VI4_DATA0_B) F_(0, 0)        FM(QSTH_QHS)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */             /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */         /* 8 */         /* 9 - F */
+#define IP4_3_0         FM(A9)                  FM(TX5_A)               FM(IRQ3)                FM(VI4_DATA16)          FM(VI5_VSYNC_N_A)       FM(DU_DG7)      F_(0, 0)        F_(0, 0)        FM(LCDOUT15)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_7_4         FM(A10)                 FM(IRQ4)                FM(MSIOF2_SYNC_B)       FM(VI4_DATA13)          FM(VI5_FIELD_A)         FM(DU_DG5)      FM(FSCLKST2_N_B) F_(0, 0)       FM(LCDOUT13)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_11_8        FM(A11)                 FM(SCL6_A)              FM(TX3_B)               FM(HTX4_C)              F_(0, 0)                FM(DU_VSYNC)    FM(VI4_DATA1_B) F_(0, 0)        FM(QSTVA_QVS)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_15_12       FM(A12)                 FM(RX5_A)               FM(MSIOF2_SS2_B)        FM(VI4_DATA17)          FM(VI5_DATA3_A)         FM(DU_DG6)      F_(0, 0)        F_(0, 0)        FM(LCDOUT14)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_19_16       FM(A13)                 FM(SCK5_A)              FM(MSIOF2_SCK_B)        FM(VI4_DATA14)          FM(HRX4_D)              FM(DU_DB2)      F_(0, 0)        F_(0, 0)        FM(LCDOUT2)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_23_20       FM(A14)                 FM(MSIOF1_SS1)          FM(MSIOF2_RXD_B)        FM(VI4_DATA15)          FM(HTX4_D)              FM(DU_DB3)      F_(0, 0)        F_(0, 0)        FM(LCDOUT3)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_27_24       FM(A15)                 FM(MSIOF1_SS2)          FM(MSIOF2_TXD_B)        FM(VI4_DATA18)          FM(VI5_DATA4_A)         FM(DU_DB4)      F_(0, 0)        F_(0, 0)        FM(LCDOUT4)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP4_31_28       FM(A16)                 FM(MSIOF1_SYNC)         FM(MSIOF2_SS1_B)        FM(VI4_DATA19)          FM(VI5_DATA5_A)         FM(DU_DB5)      F_(0, 0)        F_(0, 0)        FM(LCDOUT5)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_3_0         FM(A17)                 FM(MSIOF1_RXD)          F_(0, 0)                FM(VI4_DATA20)          FM(VI5_DATA6_A)         FM(DU_DB6)      F_(0, 0)        F_(0, 0)        FM(LCDOUT6)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_7_4         FM(A18)                 FM(MSIOF1_TXD)          F_(0, 0)                FM(VI4_DATA21)          FM(VI5_DATA7_A)         FM(DU_DB0)      F_(0, 0)        FM(HRX4_E)      FM(LCDOUT0)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_11_8        FM(A19)                 FM(MSIOF1_SCK)          F_(0, 0)                FM(VI4_DATA22)          FM(VI5_DATA2_A)         FM(DU_DB1)      F_(0, 0)        FM(HTX4_E)      FM(LCDOUT1)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_15_12       FM(CS0_N)               FM(SCL5)                F_(0, 0)                F_(0, 0)                F_(0, 0)                FM(DU_DR0)      FM(VI4_DATA2_B) F_(0, 0)        FM(LCDOUT16)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_19_16       FM(WE0_N)               FM(SDA5)                F_(0, 0)                F_(0, 0)                F_(0, 0)                FM(DU_DR1)      FM(VI4_DATA3_B) F_(0, 0)        FM(LCDOUT17)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_23_20       FM(D0)                  FM(MSIOF3_SCK_A)        F_(0, 0)                F_(0, 0)                F_(0, 0)                FM(DU_DR2)      FM(CTS4_N_C)    F_(0, 0)        FM(LCDOUT18)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_27_24       FM(D1)                  FM(MSIOF3_SYNC_A)       FM(SCK3_A)              FM(VI4_DATA23)          FM(VI5_CLKENB_A)        FM(DU_DB7)      FM(RTS4_N_TANS_C) F_(0, 0)      FM(LCDOUT7)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP5_31_28       FM(D2)                  FM(MSIOF3_RXD_A)        FM(RX5_C)               F_(0, 0)                FM(VI5_DATA14_A)        FM(DU_DR3)      FM(RX4_C)       F_(0, 0)        FM(LCDOUT19)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_3_0         FM(D3)                  FM(MSIOF3_TXD_A)        FM(TX5_C)               F_(0, 0)                FM(VI5_DATA15_A)        FM(DU_DR4)      FM(TX4_C)       F_(0, 0)        FM(LCDOUT20)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_7_4         FM(D4)                  FM(CANFD1_TX)           FM(HSCK3_B)             FM(CAN1_TX)             FM(RTS3_N_TANS_A)       FM(MSIOF3_SS2_A) F_(0, 0)       FM(VI5_DATA1_B) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_11_8        FM(D5)                  FM(RX3_A)               FM(HRX3_B)              F_(0, 0)                F_(0, 0)                FM(DU_DR5)      FM(VI4_DATA4_B) F_(0, 0)        FM(LCDOUT21)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_15_12       FM(D6)                  FM(TX3_A)               FM(HTX3_B)              F_(0, 0)                F_(0, 0)                FM(DU_DR6)      FM(VI4_DATA5_B) F_(0, 0)        FM(LCDOUT22)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_19_16       FM(D7)                  FM(CANFD1_RX)           FM(IRQ5)                FM(CAN1_RX)             FM(CTS3_N_A)            F_(0, 0)        F_(0, 0)        FM(VI5_DATA2_B) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_23_20       FM(D8)                  FM(MSIOF2_SCK_A)        FM(SCK4_B)              F_(0, 0)                FM(VI5_DATA12_A)        FM(DU_DR7)      FM(RIF3_CLK_B)  FM(HCTS3_N_E)   FM(LCDOUT23)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_27_24       FM(D9)                  FM(MSIOF2_SYNC_A)       F_(0, 0)                F_(0, 0)                FM(VI5_DATA10_A)        FM(DU_DG0)      FM(RIF3_SYNC_B) FM(HRX3_E)      FM(LCDOUT8)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP6_31_28       FM(D10)                 FM(MSIOF2_RXD_A)        F_(0, 0)                F_(0, 0)                FM(VI5_DATA13_A)        FM(DU_DG1)      FM(RIF3_D0_B)   FM(HTX3_E)      FM(LCDOUT9)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_3_0         FM(D11)                 FM(MSIOF2_TXD_A)        F_(0, 0)                F_(0, 0)                FM(VI5_DATA11_A)        FM(DU_DG2)      FM(RIF3_D1_B)   FM(HRTS3_N_E)   FM(LCDOUT10)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_7_4         FM(D12)                 FM(CANFD0_TX)           FM(TX4_B)               FM(CAN0_TX)             FM(VI5_DATA8_A)         F_(0, 0)        F_(0, 0)        FM(VI5_DATA3_B) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_11_8        FM(D13)                 FM(CANFD0_RX)           FM(RX4_B)               FM(CAN0_RX)             FM(VI5_DATA9_A)         FM(SCL7_B)      F_(0, 0)        FM(VI5_DATA4_B) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_15_12       FM(D14)                 FM(CAN_CLK)             FM(HRX3_A)              FM(MSIOF2_SS2_A)        F_(0, 0)                FM(SDA7_B)      F_(0, 0)        FM(VI5_DATA5_B) F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_19_16       FM(D15)                 FM(MSIOF2_SS1_A)        FM(HTX3_A)              FM(MSIOF3_SS1_A)        F_(0, 0)                FM(DU_DG3)      F_(0, 0)        F_(0, 0)        FM(LCDOUT11)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_23_20       FM(SCL4)                FM(CS1_N_A26)           F_(0, 0)                F_(0, 0)                F_(0, 0)                FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK)       F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_27_24       FM(SDA4)                FM(WE1_N)               F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB)       F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP7_31_28       FM(SD0_CLK)             FM(NFDATA8)             FM(SCL1_C)              FM(HSCK1_B)             FM(SDA2_E)              FM(FMCLK_B)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */             /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */         /* 8 */         /* 9 - F */
+#define IP8_3_0         FM(SD0_CMD)             FM(NFDATA9)             F_(0, 0)                FM(HRX1_B)              F_(0, 0)                FM(SPEEDIN_B)   F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_7_4         FM(SD0_DAT0)            FM(NFDATA10)            F_(0, 0)                FM(HTX1_B)              F_(0, 0)                FM(REMOCON_B)   F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_11_8        FM(SD0_DAT1)            FM(NFDATA11)            FM(SDA2_C)              FM(HCTS1_N_B)           F_(0, 0)                FM(FMIN_B)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_15_12       FM(SD0_DAT2)            FM(NFDATA12)            FM(SCL2_C)              FM(HRTS1_N_B)           F_(0, 0)                FM(BPFCLK_B)    F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_19_16       FM(SD0_DAT3)            FM(NFDATA13)            FM(SDA1_C)              FM(SCL2_E)              FM(SPEEDIN_C)           FM(REMOCON_C)   F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20       FM(SD1_CLK)             FM(NFDATA14_B)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_27_24       FM(SD1_CMD)             FM(NFDATA15_B)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_31_28       FM(SD1_DAT0)            FM(NFWP_N_B)            F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_3_0         FM(SD1_DAT1)            FM(NFCE_N_B)            F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_7_4         FM(SD1_DAT2)            FM(NFALE_B)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_11_8        FM(SD1_DAT3)            FM(NFRB_N_B)            F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_15_12       FM(SD3_CLK)             FM(NFWE_N)              F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_19_16       FM(SD3_CMD)             FM(NFRE_N)              F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_23_20       FM(SD3_DAT0)            FM(NFDATA0)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_27_24       FM(SD3_DAT1)            FM(NFDATA1)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_31_28       FM(SD3_DAT2)            FM(NFDATA2)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_3_0        FM(SD3_DAT3)            FM(NFDATA3)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_7_4        FM(SD3_DAT4)            FM(NFDATA4)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_11_8       FM(SD3_DAT5)            FM(NFDATA5)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_15_12      FM(SD3_DAT6)            FM(NFDATA6)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_19_16      FM(SD3_DAT7)            FM(NFDATA7)             F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_23_20      FM(SD3_DS)              FM(NFCLE)               F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_27_24      FM(SD0_CD)              FM(NFALE_A)             FM(SD3_CD)              FM(RIF0_CLK_B)          FM(SCL2_B)              FM(TCLK1_A)     FM(SSI_SCK2_B)  FM(TS_SCK0)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP10_31_28      FM(SD0_WP)              FM(NFRB_N_A)            FM(SD3_WP)              FM(RIF0_D0_B)           FM(SDA2_B)              FM(TCLK2_A)     FM(SSI_WS2_B)   FM(TS_SDAT0)    F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_3_0        FM(SD1_CD)              FM(NFCE_N_A)            FM(SSI_SCK1)            FM(RIF0_D1_B)           F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(TS_SDEN0)    F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_7_4        FM(SD1_WP)              FM(NFWP_N_A)            FM(SSI_WS1)             FM(RIF0_SYNC_B)         F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(TS_SPSYNC0)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_11_8       FM(RX0_A)               FM(HRX1_A)              FM(SSI_SCK2_A)          FM(RIF1_SYNC)           F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(TS_SCK1)     F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_15_12      FM(TX0_A)               FM(HTX1_A)              FM(SSI_WS2_A)           FM(RIF1_D0)             F_(0, 0)                F_(0, 0)        F_(0, 0)        FM(TS_SDAT1)    F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_19_16      FM(CTS0_N_A)            FM(NFDATA14_A)          FM(AUDIO_CLKOUT_A)      FM(RIF1_D1)             FM(SCIF_CLK_A)          FM(FMCLK_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_23_20      FM(RTS0_N_TANS_A)       FM(NFDATA15_A)          FM(AUDIO_CLKOUT1_A)     FM(RIF1_CLK)            FM(SCL2_A)              FM(FMIN_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_27_24      FM(SCK0_A)              FM(HSCK1_A)             FM(USB3HS0_ID)          FM(RTS1_N_TANS)         FM(SDA2_A)              FM(FMCLK_C)     F_(0, 0)        F_(0, 0)        FM(USB1_ID)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP11_31_28      FM(RX1)                 FM(HRX2_B)              FM(SSI_SCK9_B)          FM(AUDIO_CLKOUT1_B)     F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+/* IPSRx */             /* 0 */                 /* 1 */                 /* 2 */                 /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */         /* 8 */         /* 9 - F */
+#define IP12_3_0        FM(TX1)                 FM(HTX2_B)              FM(SSI_WS9_B)           FM(AUDIO_CLKOUT3_B)     F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_7_4        FM(SCK2_A)              FM(HSCK0_A)             FM(AUDIO_CLKB_A)        FM(CTS1_N)              FM(RIF0_CLK_A)          FM(REMOCON_A)   FM(SCIF_CLK_B)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_11_8       FM(TX2_A)               FM(HRX0_A)              FM(AUDIO_CLKOUT2_A)     F_(0, 0)                FM(SCL1_A)              F_(0, 0)        FM(FSO_CFE_0_N_A) FM(TS_SDEN1)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_15_12      FM(RX2_A)               FM(HTX0_A)              FM(AUDIO_CLKOUT3_A)     F_(0, 0)                FM(SDA1_A)              F_(0, 0)        FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0)       F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_19_16      FM(MSIOF0_SCK)          F_(0, 0)                FM(SSI_SCK78)           F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_23_20      FM(MSIOF0_RXD)          F_(0, 0)                FM(SSI_WS78)            F_(0, 0)                F_(0, 0)                FM(TX2_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_27_24      FM(MSIOF0_TXD)          F_(0, 0)                FM(SSI_SDATA7)          F_(0, 0)                F_(0, 0)                FM(RX2_B)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP12_31_28      FM(MSIOF0_SYNC)         FM(AUDIO_CLKOUT_B)      FM(SSI_SDATA8)          F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_3_0        FM(MSIOF0_SS1)          FM(HRX2_A)              FM(SSI_SCK4)            FM(HCTS0_N_A)           FM(BPFCLK_C)            FM(SPEEDIN_A)   F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_7_4        FM(MSIOF0_SS2)          FM(HTX2_A)              FM(SSI_WS4)             FM(HRTS0_N_A)           FM(FMIN_C)              FM(BPFCLK_A)    F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_11_8       FM(SSI_SDATA9)          F_(0, 0)                FM(AUDIO_CLKC_A)        FM(SCK1)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_15_12      FM(MLB_CLK)             FM(RX0_B)               F_(0, 0)                FM(RIF0_D0_A)           FM(SCL1_B)              FM(TCLK1_B)     F_(0, 0)        F_(0, 0)        FM(SIM0_RST_A)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_19_16      FM(MLB_SIG)             FM(SCK0_B)              F_(0, 0)                FM(RIF0_D1_A)           FM(SDA1_B)              FM(TCLK2_B)     F_(0, 0)        F_(0, 0)        FM(SIM0_D_A)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_23_20      FM(MLB_DAT)             FM(TX0_B)               F_(0, 0)                FM(RIF0_SYNC_A)         F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        FM(SIM0_CLK_A)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_27_24      FM(SSI_SCK01239)        F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_31_28      FM(SSI_WS01239)         F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_3_0        FM(SSI_SDATA0)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_7_4        FM(SSI_SDATA1)          FM(AUDIO_CLKC_B)        F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(PWM0_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_11_8       FM(SSI_SDATA2)          FM(AUDIO_CLKOUT2_B)     FM(SSI_SCK9_A)          F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(PWM1_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_15_12      FM(SSI_SCK349)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(PWM2_C)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_19_16      FM(SSI_WS349)           F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(PWM3_C)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_23_20      FM(SSI_SDATA3)          FM(AUDIO_CLKOUT1_C)     FM(AUDIO_CLKB_B)        F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(PWM4_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_27_24      FM(SSI_SDATA4)          F_(0, 0)                FM(SSI_WS9_A)           F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(PWM5_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP14_31_28      FM(SSI_SCK5)            FM(HRX0_B)              F_(0, 0)                FM(USB0_PWEN_B)         FM(SCL2_D)              F_(0, 0)        FM(PWM6_B)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_3_0        FM(SSI_WS5)             FM(HTX0_B)              F_(0, 0)                FM(USB0_OVC_B)          FM(SDA2_D)              F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_7_4        FM(SSI_SDATA5)          FM(HSCK0_B)             FM(AUDIO_CLKB_C)        FM(TPU0TO0)             F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_11_8       FM(SSI_SCK6)            FM(HSCK2_A)             FM(AUDIO_CLKC_C)        FM(TPU0TO1)             F_(0, 0)                F_(0, 0)        FM(FSO_CFE_0_N_B) F_(0, 0)      FM(SIM0_RST_B)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_15_12      FM(SSI_WS6)             FM(HCTS2_N_A)           FM(AUDIO_CLKOUT2_C)     FM(TPU0TO2)             FM(SDA1_D)              F_(0, 0)        FM(FSO_CFE_1_N_B) F_(0, 0)      FM(SIM0_D_B)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_19_16      FM(SSI_SDATA6)          FM(HRTS2_N_A)           FM(AUDIO_CLKOUT3_C)     FM(TPU0TO3)             FM(SCL1_D)              F_(0, 0)        FM(FSO_TOE_N_B) F_(0, 0)        FM(SIM0_CLK_B)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_23_20      FM(AUDIO_CLKA)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_27_24      FM(USB30_PWEN)          FM(USB0_PWEN_A)         F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP15_31_28      FM(USB30_OVC)           FM(USB0_OVC_A)          F_(0, 0)                F_(0, 0)                F_(0, 0)                F_(0, 0)        FM(FSO_TOE_N_A) F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+
+#define PINMUX_GPSR     \
+\
+                                                                                                         \
+                                                                                                         \
+                                                                                                         \
+                                                                                                         \
+                                                                                                         \
+                                                                                                         \
+                                GPSR2_25                                                                 \
+                                GPSR2_24                                                                 \
+                                GPSR2_23                                                                 \
+                GPSR1_22        GPSR2_22                                                                 \
+                GPSR1_21        GPSR2_21                                                                 \
+                GPSR1_20        GPSR2_20                                                                 \
+                GPSR1_19        GPSR2_19                                        GPSR5_19                 \
+                GPSR1_18        GPSR2_18                                        GPSR5_18                 \
+GPSR0_17        GPSR1_17        GPSR2_17                                        GPSR5_17        GPSR6_17 \
+GPSR0_16        GPSR1_16        GPSR2_16                                        GPSR5_16        GPSR6_16 \
+GPSR0_15        GPSR1_15        GPSR2_15        GPSR3_15                        GPSR5_15        GPSR6_15 \
+GPSR0_14        GPSR1_14        GPSR2_14        GPSR3_14                        GPSR5_14        GPSR6_14 \
+GPSR0_13        GPSR1_13        GPSR2_13        GPSR3_13                        GPSR5_13        GPSR6_13 \
+GPSR0_12        GPSR1_12        GPSR2_12        GPSR3_12                        GPSR5_12        GPSR6_12 \
+GPSR0_11        GPSR1_11        GPSR2_11        GPSR3_11                        GPSR5_11        GPSR6_11 \
+GPSR0_10        GPSR1_10        GPSR2_10        GPSR3_10        GPSR4_10        GPSR5_10        GPSR6_10 \
+GPSR0_9         GPSR1_9         GPSR2_9         GPSR3_9         GPSR4_9         GPSR5_9         GPSR6_9 \
+GPSR0_8         GPSR1_8         GPSR2_8         GPSR3_8         GPSR4_8         GPSR5_8         GPSR6_8 \
+GPSR0_7         GPSR1_7         GPSR2_7         GPSR3_7         GPSR4_7         GPSR5_7         GPSR6_7 \
+GPSR0_6         GPSR1_6         GPSR2_6         GPSR3_6         GPSR4_6         GPSR5_6         GPSR6_6 \
+GPSR0_5         GPSR1_5         GPSR2_5         GPSR3_5         GPSR4_5         GPSR5_5         GPSR6_5 \
+GPSR0_4         GPSR1_4         GPSR2_4         GPSR3_4         GPSR4_4         GPSR5_4         GPSR6_4 \
+GPSR0_3         GPSR1_3         GPSR2_3         GPSR3_3         GPSR4_3         GPSR5_3         GPSR6_3 \
+GPSR0_2         GPSR1_2         GPSR2_2         GPSR3_2         GPSR4_2         GPSR5_2         GPSR6_2 \
+GPSR0_1         GPSR1_1         GPSR2_1         GPSR3_1         GPSR4_1         GPSR5_1         GPSR6_1 \
+GPSR0_0         GPSR1_0         GPSR2_0         GPSR3_0         GPSR4_0         GPSR5_0         GPSR6_0
+
+#define PINMUX_IPSR                             \
+\
+FM(IP0_3_0)     IP0_3_0         FM(IP1_3_0)     IP1_3_0         FM(IP2_3_0)     IP2_3_0         FM(IP3_3_0)     IP3_3_0 \
+FM(IP0_7_4)     IP0_7_4         FM(IP1_7_4)     IP1_7_4         FM(IP2_7_4)     IP2_7_4         FM(IP3_7_4)     IP3_7_4 \
+FM(IP0_11_8)    IP0_11_8        FM(IP1_11_8)    IP1_11_8        FM(IP2_11_8)    IP2_11_8        FM(IP3_11_8)    IP3_11_8 \
+FM(IP0_15_12)   IP0_15_12       FM(IP1_15_12)   IP1_15_12       FM(IP2_15_12)   IP2_15_12       FM(IP3_15_12)   IP3_15_12 \
+FM(IP0_19_16)   IP0_19_16       FM(IP1_19_16)   IP1_19_16       FM(IP2_19_16)   IP2_19_16       FM(IP3_19_16)   IP3_19_16 \
+FM(IP0_23_20)   IP0_23_20       FM(IP1_23_20)   IP1_23_20       FM(IP2_23_20)   IP2_23_20       FM(IP3_23_20)   IP3_23_20 \
+FM(IP0_27_24)   IP0_27_24       FM(IP1_27_24)   IP1_27_24       FM(IP2_27_24)   IP2_27_24       FM(IP3_27_24)   IP3_27_24 \
+FM(IP0_31_28)   IP0_31_28       FM(IP1_31_28)   IP1_31_28       FM(IP2_31_28)   IP2_31_28       FM(IP3_31_28)   IP3_31_28 \
+\
+FM(IP4_3_0)     IP4_3_0         FM(IP5_3_0)     IP5_3_0         FM(IP6_3_0)     IP6_3_0         FM(IP7_3_0)     IP7_3_0 \
+FM(IP4_7_4)     IP4_7_4         FM(IP5_7_4)     IP5_7_4         FM(IP6_7_4)     IP6_7_4         FM(IP7_7_4)     IP7_7_4 \
+FM(IP4_11_8)    IP4_11_8        FM(IP5_11_8)    IP5_11_8        FM(IP6_11_8)    IP6_11_8        FM(IP7_11_8)    IP7_11_8 \
+FM(IP4_15_12)   IP4_15_12       FM(IP5_15_12)   IP5_15_12       FM(IP6_15_12)   IP6_15_12       FM(IP7_15_12)   IP7_15_12 \
+FM(IP4_19_16)   IP4_19_16       FM(IP5_19_16)   IP5_19_16       FM(IP6_19_16)   IP6_19_16       FM(IP7_19_16)   IP7_19_16 \
+FM(IP4_23_20)   IP4_23_20       FM(IP5_23_20)   IP5_23_20       FM(IP6_23_20)   IP6_23_20       FM(IP7_23_20)   IP7_23_20 \
+FM(IP4_27_24)   IP4_27_24       FM(IP5_27_24)   IP5_27_24       FM(IP6_27_24)   IP6_27_24       FM(IP7_27_24)   IP7_27_24 \
+FM(IP4_31_28)   IP4_31_28       FM(IP5_31_28)   IP5_31_28       FM(IP6_31_28)   IP6_31_28       FM(IP7_31_28)   IP7_31_28 \
+\
+FM(IP8_3_0)     IP8_3_0         FM(IP9_3_0)     IP9_3_0         FM(IP10_3_0)    IP10_3_0        FM(IP11_3_0)    IP11_3_0 \
+FM(IP8_7_4)     IP8_7_4         FM(IP9_7_4)     IP9_7_4         FM(IP10_7_4)    IP10_7_4        FM(IP11_7_4)    IP11_7_4 \
+FM(IP8_11_8)    IP8_11_8        FM(IP9_11_8)    IP9_11_8        FM(IP10_11_8)   IP10_11_8       FM(IP11_11_8)   IP11_11_8 \
+FM(IP8_15_12)   IP8_15_12       FM(IP9_15_12)   IP9_15_12       FM(IP10_15_12)  IP10_15_12      FM(IP11_15_12)  IP11_15_12 \
+FM(IP8_19_16)   IP8_19_16       FM(IP9_19_16)   IP9_19_16       FM(IP10_19_16)  IP10_19_16      FM(IP11_19_16)  IP11_19_16 \
+FM(IP8_23_20)   IP8_23_20       FM(IP9_23_20)   IP9_23_20       FM(IP10_23_20)  IP10_23_20      FM(IP11_23_20)  IP11_23_20 \
+FM(IP8_27_24)   IP8_27_24       FM(IP9_27_24)   IP9_27_24       FM(IP10_27_24)  IP10_27_24      FM(IP11_27_24)  IP11_27_24 \
+FM(IP8_31_28)   IP8_31_28       FM(IP9_31_28)   IP9_31_28       FM(IP10_31_28)  IP10_31_28      FM(IP11_31_28)  IP11_31_28 \
+\
+FM(IP12_3_0)    IP12_3_0        FM(IP13_3_0)    IP13_3_0        FM(IP14_3_0)    IP14_3_0        FM(IP15_3_0)    IP15_3_0 \
+FM(IP12_7_4)    IP12_7_4        FM(IP13_7_4)    IP13_7_4        FM(IP14_7_4)    IP14_7_4        FM(IP15_7_4)    IP15_7_4 \
+FM(IP12_11_8)   IP12_11_8       FM(IP13_11_8)   IP13_11_8       FM(IP14_11_8)   IP14_11_8       FM(IP15_11_8)   IP15_11_8 \
+FM(IP12_15_12)  IP12_15_12      FM(IP13_15_12)  IP13_15_12      FM(IP14_15_12)  IP14_15_12      FM(IP15_15_12)  IP15_15_12 \
+FM(IP12_19_16)  IP12_19_16      FM(IP13_19_16)  IP13_19_16      FM(IP14_19_16)  IP14_19_16      FM(IP15_19_16)  IP15_19_16 \
+FM(IP12_23_20)  IP12_23_20      FM(IP13_23_20)  IP13_23_20      FM(IP14_23_20)  IP14_23_20      FM(IP15_23_20)  IP15_23_20 \
+FM(IP12_27_24)  IP12_27_24      FM(IP13_27_24)  IP13_27_24      FM(IP14_27_24)  IP14_27_24      FM(IP15_27_24)  IP15_27_24 \
+FM(IP12_31_28)  IP12_31_28      FM(IP13_31_28)  IP13_31_28      FM(IP14_31_28)  IP14_31_28      FM(IP15_31_28)  IP15_31_28
+
+/* MOD_SEL0 */                  /* 0 */                         /* 1 */                         /* 2 */                         /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */
+#define MOD_SEL0_30_29          FM(SEL_ADGB_0)                  FM(SEL_ADGB_1)                  FM(SEL_ADGB_2)                  F_(0, 0)
+#define MOD_SEL0_28             FM(SEL_DRIF0_0)                 FM(SEL_DRIF0_1)
+#define MOD_SEL0_27_26          FM(SEL_FM_0)                    FM(SEL_FM_1)                    FM(SEL_FM_2)                    F_(0, 0)
+#define MOD_SEL0_25             FM(SEL_FSO_0)                   FM(SEL_FSO_1)
+#define MOD_SEL0_24             FM(SEL_HSCIF0_0)                FM(SEL_HSCIF0_1)
+#define MOD_SEL0_23             FM(SEL_HSCIF1_0)                FM(SEL_HSCIF1_1)
+#define MOD_SEL0_22             FM(SEL_HSCIF2_0)                FM(SEL_HSCIF2_1)
+#define MOD_SEL0_21_20          FM(SEL_I2C1_0)                  FM(SEL_I2C1_1)                  FM(SEL_I2C1_2)                  FM(SEL_I2C1_3)          FM(SEL_I2C1_4)          F_(0, 0)        F_(0, 0)        F_(0, 0)
+#define MOD_SEL0_19_18_17       FM(SEL_I2C2_0)                  FM(SEL_I2C2_1)                  FM(SEL_I2C2_2)                  FM(SEL_I2C2_3)          FM(SEL_I2C2_4)          F_(0, 0)        F_(0, 0)        F_(0, 0)
+#define MOD_SEL0_16             FM(SEL_NDFC_0)                  FM(SEL_NDFC_1)
+#define MOD_SEL0_15             FM(SEL_PWM0_0)                  FM(SEL_PWM0_1)
+#define MOD_SEL0_14             FM(SEL_PWM1_0)                  FM(SEL_PWM1_1)
+#define MOD_SEL0_13_12          FM(SEL_PWM2_0)                  FM(SEL_PWM2_1)                  FM(SEL_PWM2_2)                  F_(0, 0)
+#define MOD_SEL0_11_10          FM(SEL_PWM3_0)                  FM(SEL_PWM3_1)                  FM(SEL_PWM3_2)                  F_(0, 0)
+#define MOD_SEL0_9              FM(SEL_PWM4_0)                  FM(SEL_PWM4_1)
+#define MOD_SEL0_8              FM(SEL_PWM5_0)                  FM(SEL_PWM5_1)
+#define MOD_SEL0_7              FM(SEL_PWM6_0)                  FM(SEL_PWM6_1)
+#define MOD_SEL0_6_5            FM(SEL_REMOCON_0)               FM(SEL_REMOCON_1)               FM(SEL_REMOCON_2)               F_(0, 0)
+#define MOD_SEL0_4              FM(SEL_SCIF_0)                  FM(SEL_SCIF_1)
+#define MOD_SEL0_3              FM(SEL_SCIF0_0)                 FM(SEL_SCIF0_1)
+#define MOD_SEL0_2              FM(SEL_SCIF2_0)                 FM(SEL_SCIF2_1)
+#define MOD_SEL0_1_0            FM(SEL_SPEED_PULSE_IF_0)        FM(SEL_SPEED_PULSE_IF_1)        FM(SEL_SPEED_PULSE_IF_2)        F_(0, 0)
+
+/* MOD_SEL1 */                  /* 0 */                         /* 1 */                         /* 2 */                         /* 3 */                 /* 4 */                 /* 5 */         /* 6 */         /* 7 */
+#define MOD_SEL1_31             FM(SEL_SIMCARD_0)               FM(SEL_SIMCARD_1)
+#define MOD_SEL1_30             FM(SEL_SSI2_0)                  FM(SEL_SSI2_1)
+#define MOD_SEL1_29             FM(SEL_TIMER_TMU_0)             FM(SEL_TIMER_TMU_1)
+#define MOD_SEL1_28             FM(SEL_USB_20_CH0_0)            FM(SEL_USB_20_CH0_1)
+#define MOD_SEL1_26             FM(SEL_DRIF2_0)                 FM(SEL_DRIF2_1)
+#define MOD_SEL1_25             FM(SEL_DRIF3_0)                 FM(SEL_DRIF3_1)
+#define MOD_SEL1_24_23_22       FM(SEL_HSCIF3_0)                FM(SEL_HSCIF3_1)                FM(SEL_HSCIF3_2)                FM(SEL_HSCIF3_3)        FM(SEL_HSCIF3_4)        F_(0, 0)        F_(0, 0)        F_(0, 0)
+#define MOD_SEL1_21_20_19       FM(SEL_HSCIF4_0)                FM(SEL_HSCIF4_1)                FM(SEL_HSCIF4_2)                FM(SEL_HSCIF4_3)        FM(SEL_HSCIF4_4)        F_(0, 0)        F_(0, 0)        F_(0, 0)
+#define MOD_SEL1_18             FM(SEL_I2C6_0)                  FM(SEL_I2C6_1)
+#define MOD_SEL1_17             FM(SEL_I2C7_0)                  FM(SEL_I2C7_1)
+#define MOD_SEL1_16             FM(SEL_MSIOF2_0)                FM(SEL_MSIOF2_1)
+#define MOD_SEL1_15             FM(SEL_MSIOF3_0)                FM(SEL_MSIOF3_1)
+#define MOD_SEL1_14_13          FM(SEL_SCIF3_0)                 FM(SEL_SCIF3_1)                 FM(SEL_SCIF3_2)                 F_(0, 0)
+#define MOD_SEL1_12_11          FM(SEL_SCIF4_0)                 FM(SEL_SCIF4_1)                 FM(SEL_SCIF4_2)                 F_(0, 0)
+#define MOD_SEL1_10_9           FM(SEL_SCIF5_0)                 FM(SEL_SCIF5_1)                 FM(SEL_SCIF5_2)                 F_(0, 0)
+#define MOD_SEL1_8              FM(SEL_VIN4_0)                  FM(SEL_VIN4_1)
+#define MOD_SEL1_7              FM(SEL_VIN5_0)                  FM(SEL_VIN5_1)
+#define MOD_SEL1_6_5            FM(SEL_ADGC_0)                  FM(SEL_ADGC_1)                  FM(SEL_ADGC_2)                  F_(0, 0)
+#define MOD_SEL1_4              FM(SEL_SSI9_0)                  FM(SEL_SSI9_1)
+
+#define PINMUX_MOD_SELS \
+\
+                        MOD_SEL1_31 \
+MOD_SEL0_30_29          MOD_SEL1_30 \
+                        MOD_SEL1_29 \
+MOD_SEL0_28             MOD_SEL1_28 \
+MOD_SEL0_27_26 \
+                        MOD_SEL1_26 \
+MOD_SEL0_25             MOD_SEL1_25 \
+MOD_SEL0_24             MOD_SEL1_24_23_22 \
+MOD_SEL0_23 \
+MOD_SEL0_22 \
+MOD_SEL0_21_20          MOD_SEL1_21_20_19 \
+MOD_SEL0_19_18_17       MOD_SEL1_18 \
+                        MOD_SEL1_17 \
+MOD_SEL0_16             MOD_SEL1_16 \
+MOD_SEL0_15             MOD_SEL1_15 \
+MOD_SEL0_14             MOD_SEL1_14_13 \
+MOD_SEL0_13_12 \
+                        MOD_SEL1_12_11 \
+MOD_SEL0_11_10 \
+                        MOD_SEL1_10_9 \
+MOD_SEL0_9 \
+MOD_SEL0_8              MOD_SEL1_8 \
+MOD_SEL0_7              MOD_SEL1_7 \
+MOD_SEL0_6_5            MOD_SEL1_6_5 \
+MOD_SEL0_4              MOD_SEL1_4 \
+MOD_SEL0_3 \
+MOD_SEL0_2 \
+MOD_SEL0_1_0
+
+/*
+ * These pins are not able to be muxed but have other properties
+ * that can be set, such as pull-up/pull-down enable.
+ */
+#define PINMUX_STATIC \
+        FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
+        FM(AVB_TD3) \
+        FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
+        FM(ASEBRK) \
+        FM(MLB_REF)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        GP_ALL(DATA),
+        PINMUX_DATA_END,
+
+#define F_(x, y)
+#define FM(x)   FN_##x,
+        PINMUX_FUNCTION_BEGIN,
+        GP_ALL(FN),
+        PINMUX_GPSR
+        PINMUX_IPSR
+        PINMUX_MOD_SELS
+        PINMUX_FUNCTION_END,
+#undef F_
+#undef FM
+
+#define F_(x, y)
+#define FM(x)   x##_MARK,
+        PINMUX_MARK_BEGIN,
+        PINMUX_GPSR
+        PINMUX_IPSR
+        PINMUX_MOD_SELS
+        PINMUX_STATIC
+        PINMUX_MARK_END,
+#undef F_
+#undef FM
+};
+
+static const u16 pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(),
+
+        PINMUX_SINGLE(CLKOUT),
+        PINMUX_SINGLE(AVB_PHY_INT),
+        PINMUX_SINGLE(AVB_RD3),
+        PINMUX_SINGLE(AVB_RXC),
+        PINMUX_SINGLE(AVB_RX_CTL),
+        PINMUX_SINGLE(QSPI0_SSL),
+
+        /* IPSR0 */
+        PINMUX_IPSR_GPSR(IP0_3_0,               QSPI0_SPCLK),
+        PINMUX_IPSR_MSEL(IP0_3_0,               HSCK4_A,        SEL_HSCIF4_0),
+
+        PINMUX_IPSR_GPSR(IP0_7_4,               QSPI0_MOSI_IO0),
+        PINMUX_IPSR_MSEL(IP0_7_4,               HCTS4_N_A,      SEL_HSCIF4_0),
+
+        PINMUX_IPSR_GPSR(IP0_11_8,              QSPI0_MISO_IO1),
+        PINMUX_IPSR_MSEL(IP0_11_8,              HRTS4_N_A,      SEL_HSCIF4_0),
+
+        PINMUX_IPSR_GPSR(IP0_15_12,             QSPI0_IO2),
+        PINMUX_IPSR_GPSR(IP0_15_12,             HTX4_A),
+
+        PINMUX_IPSR_GPSR(IP0_19_16,             QSPI0_IO3),
+        PINMUX_IPSR_MSEL(IP0_19_16,             HRX4_A,         SEL_HSCIF4_0),
+
+        PINMUX_IPSR_GPSR(IP0_23_20,             QSPI1_SPCLK),
+        PINMUX_IPSR_MSEL(IP0_23_20,             RIF2_CLK_A,     SEL_DRIF2_0),
+        PINMUX_IPSR_MSEL(IP0_23_20,             HSCK4_B,        SEL_HSCIF4_1),
+        PINMUX_IPSR_MSEL(IP0_23_20,             VI4_DATA0_A,    SEL_VIN4_0),
+
+        PINMUX_IPSR_GPSR(IP0_27_24,             QSPI1_MOSI_IO0),
+        PINMUX_IPSR_MSEL(IP0_27_24,             RIF2_SYNC_A,    SEL_DRIF2_0),
+        PINMUX_IPSR_GPSR(IP0_27_24,             HTX4_B),
+        PINMUX_IPSR_MSEL(IP0_27_24,             VI4_DATA1_A,    SEL_VIN4_0),
+
+        PINMUX_IPSR_GPSR(IP0_31_28,             QSPI1_MISO_IO1),
+        PINMUX_IPSR_MSEL(IP0_31_28,             RIF2_D0_A,      SEL_DRIF2_0),
+        PINMUX_IPSR_MSEL(IP0_31_28,             HRX4_B,         SEL_HSCIF4_1),
+        PINMUX_IPSR_MSEL(IP0_31_28,             VI4_DATA2_A,    SEL_VIN4_0),
+
+        /* IPSR1 */
+        PINMUX_IPSR_GPSR(IP1_3_0,               QSPI1_IO2),
+        PINMUX_IPSR_MSEL(IP1_3_0,               RIF2_D1_A,      SEL_DRIF2_0),
+        PINMUX_IPSR_GPSR(IP1_3_0,               HTX3_C),
+        PINMUX_IPSR_MSEL(IP1_3_0,               VI4_DATA3_A,    SEL_VIN4_0),
+
+        PINMUX_IPSR_GPSR(IP1_7_4,               QSPI1_IO3),
+        PINMUX_IPSR_MSEL(IP1_7_4,               RIF3_CLK_A,     SEL_DRIF3_0),
+        PINMUX_IPSR_MSEL(IP1_7_4,               HRX3_C,         SEL_HSCIF3_2),
+        PINMUX_IPSR_MSEL(IP1_7_4,               VI4_DATA4_A,    SEL_VIN4_0),
+
+        PINMUX_IPSR_GPSR(IP1_11_8,              QSPI1_SSL),
+        PINMUX_IPSR_MSEL(IP1_11_8,              RIF3_SYNC_A,    SEL_DRIF3_0),
+        PINMUX_IPSR_MSEL(IP1_11_8,              HSCK3_C,        SEL_HSCIF3_2),
+        PINMUX_IPSR_MSEL(IP1_11_8,              VI4_DATA5_A,    SEL_VIN4_0),
+
+        PINMUX_IPSR_GPSR(IP1_15_12,             RPC_INT_N),
+        PINMUX_IPSR_MSEL(IP1_15_12,             RIF3_D0_A,      SEL_DRIF3_0),
+        PINMUX_IPSR_MSEL(IP1_15_12,             HCTS3_N_C,      SEL_HSCIF3_2),
+        PINMUX_IPSR_MSEL(IP1_15_12,             VI4_DATA6_A,    SEL_VIN4_0),
+
+        PINMUX_IPSR_GPSR(IP1_19_16,             RPC_RESET_N),
+        PINMUX_IPSR_MSEL(IP1_19_16,             RIF3_D1_A,      SEL_DRIF3_0),
+        PINMUX_IPSR_MSEL(IP1_19_16,             HRTS3_N_C,      SEL_HSCIF3_2),
+        PINMUX_IPSR_MSEL(IP1_19_16,             VI4_DATA7_A,    SEL_VIN4_0),
+
+        PINMUX_IPSR_GPSR(IP1_23_20,             AVB_RD0),
+
+        PINMUX_IPSR_GPSR(IP1_27_24,             AVB_RD1),
+
+        PINMUX_IPSR_GPSR(IP1_31_28,             AVB_RD2),
+
+        /* IPSR2 */
+        PINMUX_IPSR_GPSR(IP2_3_0,               AVB_TXCREFCLK),
+
+        PINMUX_IPSR_GPSR(IP2_7_4,               AVB_MDIO),
+
+        PINMUX_IPSR_GPSR(IP2_11_8,              AVB_MDC),
+
+        PINMUX_IPSR_GPSR(IP2_15_12,             BS_N),
+        PINMUX_IPSR_MSEL(IP2_15_12,             PWM0_A,         SEL_PWM0_0),
+        PINMUX_IPSR_GPSR(IP2_15_12,             AVB_MAGIC),
+        PINMUX_IPSR_GPSR(IP2_15_12,             VI4_CLK),
+        PINMUX_IPSR_GPSR(IP2_15_12,             TX3_C),
+        PINMUX_IPSR_MSEL(IP2_15_12,             VI5_CLK_B,      SEL_VIN5_1),
+
+        PINMUX_IPSR_GPSR(IP2_19_16,             RD_N),
+        PINMUX_IPSR_MSEL(IP2_19_16,             PWM1_A,         SEL_PWM1_0),
+        PINMUX_IPSR_GPSR(IP2_19_16,             AVB_LINK),
+        PINMUX_IPSR_GPSR(IP2_19_16,             VI4_FIELD),
+        PINMUX_IPSR_MSEL(IP2_19_16,             RX3_C,          SEL_SCIF3_2),
+        PINMUX_IPSR_GPSR(IP2_19_16,             FSCLKST2_N_A),
+        PINMUX_IPSR_MSEL(IP2_19_16,             VI5_DATA0_B,    SEL_VIN5_1),
+
+        PINMUX_IPSR_GPSR(IP2_23_20,             RD_WR_N),
+        PINMUX_IPSR_MSEL(IP2_23_20,             SCL7_A,         SEL_I2C7_0),
+        PINMUX_IPSR_GPSR(IP2_23_20,             AVB_AVTP_MATCH_A),
+        PINMUX_IPSR_GPSR(IP2_23_20,             VI4_VSYNC_N),
+        PINMUX_IPSR_GPSR(IP2_23_20,             TX5_B),
+        PINMUX_IPSR_MSEL(IP2_23_20,             SCK3_C,         SEL_SCIF3_2),
+        PINMUX_IPSR_MSEL(IP2_23_20,             PWM5_A,         SEL_PWM5_0),
+
+        PINMUX_IPSR_GPSR(IP2_27_24,             EX_WAIT0),
+        PINMUX_IPSR_MSEL(IP2_27_24,             SDA7_A,         SEL_I2C7_0),
+        PINMUX_IPSR_GPSR(IP2_27_24,             AVB_AVTP_CAPTURE_A),
+        PINMUX_IPSR_GPSR(IP2_27_24,             VI4_HSYNC_N),
+        PINMUX_IPSR_MSEL(IP2_27_24,             RX5_B,          SEL_SCIF5_1),
+        PINMUX_IPSR_MSEL(IP2_27_24,             PWM6_A,         SEL_PWM6_0),
+
+        PINMUX_IPSR_GPSR(IP2_31_28,             A0),
+        PINMUX_IPSR_GPSR(IP2_31_28,             IRQ0),
+        PINMUX_IPSR_MSEL(IP2_31_28,             PWM2_A,         SEL_PWM2_0),
+        PINMUX_IPSR_MSEL(IP2_31_28,             MSIOF3_SS1_B,   SEL_MSIOF3_1),
+        PINMUX_IPSR_MSEL(IP2_31_28,             VI5_CLK_A,      SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP2_31_28,             DU_CDE),
+        PINMUX_IPSR_MSEL(IP2_31_28,             HRX3_D,         SEL_HSCIF3_3),
+        PINMUX_IPSR_GPSR(IP2_31_28,             IERX),
+        PINMUX_IPSR_GPSR(IP2_31_28,             QSTB_QHE),
+
+        /* IPSR3 */
+        PINMUX_IPSR_GPSR(IP3_3_0,               A1),
+        PINMUX_IPSR_GPSR(IP3_3_0,               IRQ1),
+        PINMUX_IPSR_MSEL(IP3_3_0,               PWM3_A,         SEL_PWM3_0),
+        PINMUX_IPSR_GPSR(IP3_3_0,               DU_DOTCLKIN1),
+        PINMUX_IPSR_MSEL(IP3_3_0,               VI5_DATA0_A,    SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP3_3_0,               DU_DISP_CDE),
+        PINMUX_IPSR_MSEL(IP3_3_0,               SDA6_B,         SEL_I2C6_1),
+        PINMUX_IPSR_GPSR(IP3_3_0,               IETX),
+        PINMUX_IPSR_GPSR(IP3_3_0,               QCPV_QDE),
+
+        PINMUX_IPSR_GPSR(IP3_7_4,               A2),
+        PINMUX_IPSR_GPSR(IP3_7_4,               IRQ2),
+        PINMUX_IPSR_GPSR(IP3_7_4,               AVB_AVTP_PPS),
+        PINMUX_IPSR_GPSR(IP3_7_4,               VI4_CLKENB),
+        PINMUX_IPSR_MSEL(IP3_7_4,               VI5_DATA1_A,    SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP3_7_4,               DU_DISP),
+        PINMUX_IPSR_MSEL(IP3_7_4,               SCL6_B,         SEL_I2C6_1),
+        PINMUX_IPSR_GPSR(IP3_7_4,               QSTVB_QVE),
+
+        PINMUX_IPSR_GPSR(IP3_11_8,              A3),
+        PINMUX_IPSR_MSEL(IP3_11_8,              CTS4_N_A,       SEL_SCIF4_0),
+        PINMUX_IPSR_MSEL(IP3_11_8,              PWM4_A,         SEL_PWM4_0),
+        PINMUX_IPSR_GPSR(IP3_11_8,              VI4_DATA12),
+        PINMUX_IPSR_GPSR(IP3_11_8,              DU_DOTCLKOUT0),
+        PINMUX_IPSR_GPSR(IP3_11_8,              HTX3_D),
+        PINMUX_IPSR_GPSR(IP3_11_8,              IECLK),
+        PINMUX_IPSR_GPSR(IP3_11_8,              LCDOUT12),
+
+        PINMUX_IPSR_GPSR(IP3_15_12,             A4),
+        PINMUX_IPSR_MSEL(IP3_15_12,             RTS4_N_TANS_A,  SEL_SCIF4_0),
+        PINMUX_IPSR_MSEL(IP3_15_12,             MSIOF3_SYNC_B,  SEL_MSIOF3_1),
+        PINMUX_IPSR_GPSR(IP3_15_12,             VI4_DATA8),
+        PINMUX_IPSR_MSEL(IP3_15_12,             PWM2_B,         SEL_PWM2_1),
+        PINMUX_IPSR_GPSR(IP3_15_12,             DU_DG4),
+        PINMUX_IPSR_MSEL(IP3_15_12,             RIF2_CLK_B,     SEL_DRIF2_1),
+
+        PINMUX_IPSR_GPSR(IP3_19_16,             A5),
+        PINMUX_IPSR_MSEL(IP3_19_16,             SCK4_A,         SEL_SCIF4_0),
+        PINMUX_IPSR_MSEL(IP3_19_16,             MSIOF3_SCK_B,   SEL_MSIOF3_1),
+        PINMUX_IPSR_GPSR(IP3_19_16,             VI4_DATA9),
+        PINMUX_IPSR_MSEL(IP3_19_16,             PWM3_B,         SEL_PWM3_1),
+        PINMUX_IPSR_MSEL(IP3_19_16,             RIF2_SYNC_B,    SEL_DRIF2_1),
+        PINMUX_IPSR_GPSR(IP3_19_16,             QPOLA),
+
+        PINMUX_IPSR_GPSR(IP3_23_20,             A6),
+        PINMUX_IPSR_MSEL(IP3_23_20,             RX4_A,          SEL_SCIF4_0),
+        PINMUX_IPSR_MSEL(IP3_23_20,             MSIOF3_RXD_B,   SEL_MSIOF3_1),
+        PINMUX_IPSR_GPSR(IP3_23_20,             VI4_DATA10),
+        PINMUX_IPSR_MSEL(IP3_23_20,             RIF2_D0_B,      SEL_DRIF2_1),
+
+        PINMUX_IPSR_GPSR(IP3_27_24,             A7),
+        PINMUX_IPSR_GPSR(IP3_27_24,             TX4_A),
+        PINMUX_IPSR_GPSR(IP3_27_24,             MSIOF3_TXD_B),
+        PINMUX_IPSR_GPSR(IP3_27_24,             VI4_DATA11),
+        PINMUX_IPSR_MSEL(IP3_27_24,             RIF2_D1_B,      SEL_DRIF2_1),
+
+        PINMUX_IPSR_GPSR(IP3_31_28,             A8),
+        PINMUX_IPSR_MSEL(IP3_31_28,             SDA6_A,         SEL_I2C6_0),
+        PINMUX_IPSR_MSEL(IP3_31_28,             RX3_B,          SEL_SCIF3_1),
+        PINMUX_IPSR_MSEL(IP3_31_28,             HRX4_C,         SEL_HSCIF4_2),
+        PINMUX_IPSR_MSEL(IP3_31_28,             VI5_HSYNC_N_A,  SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP3_31_28,             DU_HSYNC),
+        PINMUX_IPSR_MSEL(IP3_31_28,             VI4_DATA0_B,    SEL_VIN4_1),
+        PINMUX_IPSR_GPSR(IP3_31_28,             QSTH_QHS),
+
+        /* IPSR4 */
+        PINMUX_IPSR_GPSR(IP4_3_0,               A9),
+        PINMUX_IPSR_GPSR(IP4_3_0,               TX5_A),
+        PINMUX_IPSR_GPSR(IP4_3_0,               IRQ3),
+        PINMUX_IPSR_GPSR(IP4_3_0,               VI4_DATA16),
+        PINMUX_IPSR_MSEL(IP4_3_0,               VI5_VSYNC_N_A,  SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP4_3_0,               DU_DG7),
+        PINMUX_IPSR_GPSR(IP4_3_0,               LCDOUT15),
+
+        PINMUX_IPSR_GPSR(IP4_7_4,               A10),
+        PINMUX_IPSR_GPSR(IP4_7_4,               IRQ4),
+        PINMUX_IPSR_MSEL(IP4_7_4,               MSIOF2_SYNC_B,  SEL_MSIOF2_1),
+        PINMUX_IPSR_GPSR(IP4_7_4,               VI4_DATA13),
+        PINMUX_IPSR_MSEL(IP4_7_4,               VI5_FIELD_A,    SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP4_7_4,               DU_DG5),
+        PINMUX_IPSR_GPSR(IP4_7_4,               FSCLKST2_N_B),
+        PINMUX_IPSR_GPSR(IP4_7_4,               LCDOUT13),
+
+        PINMUX_IPSR_GPSR(IP4_11_8,              A11),
+        PINMUX_IPSR_MSEL(IP4_11_8,              SCL6_A,         SEL_I2C6_0),
+        PINMUX_IPSR_GPSR(IP4_11_8,              TX3_B),
+        PINMUX_IPSR_GPSR(IP4_11_8,              HTX4_C),
+        PINMUX_IPSR_GPSR(IP4_11_8,              DU_VSYNC),
+        PINMUX_IPSR_MSEL(IP4_11_8,              VI4_DATA1_B,    SEL_VIN4_1),
+        PINMUX_IPSR_GPSR(IP4_11_8,              QSTVA_QVS),
+
+        PINMUX_IPSR_GPSR(IP4_15_12,             A12),
+        PINMUX_IPSR_MSEL(IP4_15_12,             RX5_A,          SEL_SCIF5_0),
+        PINMUX_IPSR_GPSR(IP4_15_12,             MSIOF2_SS2_B),
+        PINMUX_IPSR_GPSR(IP4_15_12,             VI4_DATA17),
+        PINMUX_IPSR_MSEL(IP4_15_12,             VI5_DATA3_A,    SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP4_15_12,             DU_DG6),
+        PINMUX_IPSR_GPSR(IP4_15_12,             LCDOUT14),
+
+        PINMUX_IPSR_GPSR(IP4_19_16,             A13),
+        PINMUX_IPSR_MSEL(IP4_19_16,             SCK5_A,         SEL_SCIF5_0),
+        PINMUX_IPSR_MSEL(IP4_19_16,             MSIOF2_SCK_B,   SEL_MSIOF2_1),
+        PINMUX_IPSR_GPSR(IP4_19_16,             VI4_DATA14),
+        PINMUX_IPSR_MSEL(IP4_19_16,             HRX4_D,         SEL_HSCIF4_3),
+        PINMUX_IPSR_GPSR(IP4_19_16,             DU_DB2),
+        PINMUX_IPSR_GPSR(IP4_19_16,             LCDOUT2),
+
+        PINMUX_IPSR_GPSR(IP4_23_20,             A14),
+        PINMUX_IPSR_GPSR(IP4_23_20,             MSIOF1_SS1),
+        PINMUX_IPSR_MSEL(IP4_23_20,             MSIOF2_RXD_B,   SEL_MSIOF2_1),
+        PINMUX_IPSR_GPSR(IP4_23_20,             VI4_DATA15),
+        PINMUX_IPSR_GPSR(IP4_23_20,             HTX4_D),
+        PINMUX_IPSR_GPSR(IP4_23_20,             DU_DB3),
+        PINMUX_IPSR_GPSR(IP4_23_20,             LCDOUT3),
+
+        PINMUX_IPSR_GPSR(IP4_27_24,             A15),
+        PINMUX_IPSR_GPSR(IP4_27_24,             MSIOF1_SS2),
+        PINMUX_IPSR_GPSR(IP4_27_24,             MSIOF2_TXD_B),
+        PINMUX_IPSR_GPSR(IP4_27_24,             VI4_DATA18),
+        PINMUX_IPSR_MSEL(IP4_27_24,             VI5_DATA4_A,    SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP4_27_24,             DU_DB4),
+        PINMUX_IPSR_GPSR(IP4_27_24,             LCDOUT4),
+
+        PINMUX_IPSR_GPSR(IP4_31_28,             A16),
+        PINMUX_IPSR_GPSR(IP4_31_28,             MSIOF1_SYNC),
+        PINMUX_IPSR_GPSR(IP4_31_28,             MSIOF2_SS1_B),
+        PINMUX_IPSR_GPSR(IP4_31_28,             VI4_DATA19),
+        PINMUX_IPSR_MSEL(IP4_31_28,             VI5_DATA5_A,    SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP4_31_28,             DU_DB5),
+        PINMUX_IPSR_GPSR(IP4_31_28,             LCDOUT5),
+
+        /* IPSR5 */
+        PINMUX_IPSR_GPSR(IP5_3_0,               A17),
+        PINMUX_IPSR_GPSR(IP5_3_0,               MSIOF1_RXD),
+        PINMUX_IPSR_GPSR(IP5_3_0,               VI4_DATA20),
+        PINMUX_IPSR_MSEL(IP5_3_0,               VI5_DATA6_A,    SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP5_3_0,               DU_DB6),
+        PINMUX_IPSR_GPSR(IP5_3_0,               LCDOUT6),
+
+        PINMUX_IPSR_GPSR(IP5_7_4,               A18),
+        PINMUX_IPSR_GPSR(IP5_7_4,               MSIOF1_TXD),
+        PINMUX_IPSR_GPSR(IP5_7_4,               VI4_DATA21),
+        PINMUX_IPSR_MSEL(IP5_7_4,               VI5_DATA7_A,    SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP5_7_4,               DU_DB0),
+        PINMUX_IPSR_MSEL(IP5_7_4,               HRX4_E,         SEL_HSCIF4_4),
+        PINMUX_IPSR_GPSR(IP5_7_4,               LCDOUT0),
+
+        PINMUX_IPSR_GPSR(IP5_11_8,              A19),
+        PINMUX_IPSR_GPSR(IP5_11_8,              MSIOF1_SCK),
+        PINMUX_IPSR_GPSR(IP5_11_8,              VI4_DATA22),
+        PINMUX_IPSR_MSEL(IP5_11_8,              VI5_DATA2_A,    SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP5_11_8,              DU_DB1),
+        PINMUX_IPSR_GPSR(IP5_11_8,              HTX4_E),
+        PINMUX_IPSR_GPSR(IP5_11_8,              LCDOUT1),
+
+        PINMUX_IPSR_GPSR(IP5_15_12,             CS0_N),
+        PINMUX_IPSR_GPSR(IP5_15_12,             SCL5),
+        PINMUX_IPSR_GPSR(IP5_15_12,             DU_DR0),
+        PINMUX_IPSR_MSEL(IP5_15_12,             VI4_DATA2_B,    SEL_VIN4_1),
+        PINMUX_IPSR_GPSR(IP5_15_12,             LCDOUT16),
+
+        PINMUX_IPSR_GPSR(IP5_19_16,             WE0_N),
+        PINMUX_IPSR_GPSR(IP5_19_16,             SDA5),
+        PINMUX_IPSR_GPSR(IP5_19_16,             DU_DR1),
+        PINMUX_IPSR_MSEL(IP5_19_16,             VI4_DATA3_B,    SEL_VIN4_1),
+        PINMUX_IPSR_GPSR(IP5_19_16,             LCDOUT17),
+
+        PINMUX_IPSR_GPSR(IP5_23_20,             D0),
+        PINMUX_IPSR_MSEL(IP5_23_20,             MSIOF3_SCK_A,   SEL_MSIOF3_0),
+        PINMUX_IPSR_GPSR(IP5_23_20,             DU_DR2),
+        PINMUX_IPSR_MSEL(IP5_23_20,             CTS4_N_C,       SEL_SCIF4_2),
+        PINMUX_IPSR_GPSR(IP5_23_20,             LCDOUT18),
+
+        PINMUX_IPSR_GPSR(IP5_27_24,             D1),
+        PINMUX_IPSR_MSEL(IP5_27_24,             MSIOF3_SYNC_A,  SEL_MSIOF3_0),
+        PINMUX_IPSR_MSEL(IP5_27_24,             SCK3_A,         SEL_SCIF3_0),
+        PINMUX_IPSR_GPSR(IP5_27_24,             VI4_DATA23),
+        PINMUX_IPSR_MSEL(IP5_27_24,             VI5_CLKENB_A,   SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP5_27_24,             DU_DB7),
+        PINMUX_IPSR_MSEL(IP5_27_24,             RTS4_N_TANS_C,  SEL_SCIF4_2),
+        PINMUX_IPSR_GPSR(IP5_27_24,             LCDOUT7),
+
+        PINMUX_IPSR_GPSR(IP5_31_28,             D2),
+        PINMUX_IPSR_MSEL(IP5_31_28,             MSIOF3_RXD_A,   SEL_MSIOF3_0),
+        PINMUX_IPSR_MSEL(IP5_31_28,             RX5_C,          SEL_SCIF5_2),
+        PINMUX_IPSR_MSEL(IP5_31_28,             VI5_DATA14_A,   SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP5_31_28,             DU_DR3),
+        PINMUX_IPSR_MSEL(IP5_31_28,             RX4_C,          SEL_SCIF4_2),
+        PINMUX_IPSR_GPSR(IP5_31_28,             LCDOUT19),
+
+        /* IPSR6 */
+        PINMUX_IPSR_GPSR(IP6_3_0,               D3),
+        PINMUX_IPSR_GPSR(IP6_3_0,               MSIOF3_TXD_A),
+        PINMUX_IPSR_GPSR(IP6_3_0,               TX5_C),
+        PINMUX_IPSR_MSEL(IP6_3_0,               VI5_DATA15_A,   SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP6_3_0,               DU_DR4),
+        PINMUX_IPSR_GPSR(IP6_3_0,               TX4_C),
+        PINMUX_IPSR_GPSR(IP6_3_0,               LCDOUT20),
+
+        PINMUX_IPSR_GPSR(IP6_7_4,               D4),
+        PINMUX_IPSR_GPSR(IP6_7_4,               CANFD1_TX),
+        PINMUX_IPSR_MSEL(IP6_7_4,               HSCK3_B,        SEL_HSCIF3_1),
+        PINMUX_IPSR_GPSR(IP6_7_4,               CAN1_TX),
+        PINMUX_IPSR_MSEL(IP6_7_4,               RTS3_N_TANS_A,  SEL_SCIF3_0),
+        PINMUX_IPSR_GPSR(IP6_7_4,               MSIOF3_SS2_A),
+        PINMUX_IPSR_MSEL(IP6_7_4,               VI5_DATA1_B,    SEL_VIN5_1),
+
+        PINMUX_IPSR_GPSR(IP6_11_8,              D5),
+        PINMUX_IPSR_MSEL(IP6_11_8,              RX3_A,          SEL_SCIF3_0),
+        PINMUX_IPSR_MSEL(IP6_11_8,              HRX3_B,         SEL_HSCIF3_1),
+        PINMUX_IPSR_GPSR(IP6_11_8,              DU_DR5),
+        PINMUX_IPSR_MSEL(IP6_11_8,              VI4_DATA4_B,    SEL_VIN4_1),
+        PINMUX_IPSR_GPSR(IP6_11_8,              LCDOUT21),
+
+        PINMUX_IPSR_GPSR(IP6_15_12,             D6),
+        PINMUX_IPSR_GPSR(IP6_15_12,             TX3_A),
+        PINMUX_IPSR_GPSR(IP6_15_12,             HTX3_B),
+        PINMUX_IPSR_GPSR(IP6_15_12,             DU_DR6),
+        PINMUX_IPSR_MSEL(IP6_15_12,             VI4_DATA5_B,    SEL_VIN4_1),
+        PINMUX_IPSR_GPSR(IP6_15_12,             LCDOUT22),
+
+        PINMUX_IPSR_GPSR(IP6_19_16,             D7),
+        PINMUX_IPSR_GPSR(IP6_19_16,             CANFD1_RX),
+        PINMUX_IPSR_GPSR(IP6_19_16,             IRQ5),
+        PINMUX_IPSR_GPSR(IP6_19_16,             CAN1_RX),
+        PINMUX_IPSR_MSEL(IP6_19_16,             CTS3_N_A,       SEL_SCIF3_0),
+        PINMUX_IPSR_MSEL(IP6_19_16,             VI5_DATA2_B,    SEL_VIN5_1),
+
+        PINMUX_IPSR_GPSR(IP6_23_20,             D8),
+        PINMUX_IPSR_MSEL(IP6_23_20,             MSIOF2_SCK_A,   SEL_MSIOF2_0),
+        PINMUX_IPSR_MSEL(IP6_23_20,             SCK4_B,         SEL_SCIF4_1),
+        PINMUX_IPSR_MSEL(IP6_23_20,             VI5_DATA12_A,   SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP6_23_20,             DU_DR7),
+        PINMUX_IPSR_MSEL(IP6_23_20,             RIF3_CLK_B,     SEL_DRIF3_1),
+        PINMUX_IPSR_MSEL(IP6_23_20,             HCTS3_N_E,      SEL_HSCIF3_4),
+        PINMUX_IPSR_GPSR(IP6_23_20,             LCDOUT23),
+
+        PINMUX_IPSR_GPSR(IP6_27_24,             D9),
+        PINMUX_IPSR_MSEL(IP6_27_24,             MSIOF2_SYNC_A,  SEL_MSIOF2_0),
+        PINMUX_IPSR_MSEL(IP6_27_24,             VI5_DATA10_A,   SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP6_27_24,             DU_DG0),
+        PINMUX_IPSR_MSEL(IP6_27_24,             RIF3_SYNC_B,    SEL_DRIF3_1),
+        PINMUX_IPSR_MSEL(IP6_27_24,             HRX3_E,         SEL_HSCIF3_4),
+        PINMUX_IPSR_GPSR(IP6_27_24,             LCDOUT8),
+
+        PINMUX_IPSR_GPSR(IP6_31_28,             D10),
+        PINMUX_IPSR_MSEL(IP6_31_28,             MSIOF2_RXD_A,   SEL_MSIOF2_0),
+        PINMUX_IPSR_MSEL(IP6_31_28,             VI5_DATA13_A,   SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP6_31_28,             DU_DG1),
+        PINMUX_IPSR_MSEL(IP6_31_28,             RIF3_D0_B,      SEL_DRIF3_1),
+        PINMUX_IPSR_GPSR(IP6_31_28,             HTX3_E),
+        PINMUX_IPSR_GPSR(IP6_31_28,             LCDOUT9),
+
+        /* IPSR7 */
+        PINMUX_IPSR_GPSR(IP7_3_0,               D11),
+        PINMUX_IPSR_GPSR(IP7_3_0,               MSIOF2_TXD_A),
+        PINMUX_IPSR_MSEL(IP7_3_0,               VI5_DATA11_A,   SEL_VIN5_0),
+        PINMUX_IPSR_GPSR(IP7_3_0,               DU_DG2),
+        PINMUX_IPSR_MSEL(IP7_3_0,               RIF3_D1_B,      SEL_DRIF3_1),
+        PINMUX_IPSR_MSEL(IP7_3_0,               HRTS3_N_E,      SEL_HSCIF3_4),
+        PINMUX_IPSR_GPSR(IP7_3_0,               LCDOUT10),
+
+        PINMUX_IPSR_GPSR(IP7_7_4,               D12),
+        PINMUX_IPSR_GPSR(IP7_7_4,               CANFD0_TX),
+        PINMUX_IPSR_GPSR(IP7_7_4,               TX4_B),
+        PINMUX_IPSR_GPSR(IP7_7_4,               CAN0_TX),
+        PINMUX_IPSR_MSEL(IP7_7_4,               VI5_DATA8_A,    SEL_VIN5_0),
+        PINMUX_IPSR_MSEL(IP7_7_4,               VI5_DATA3_B,    SEL_VIN5_1),
+
+        PINMUX_IPSR_GPSR(IP7_11_8,              D13),
+        PINMUX_IPSR_GPSR(IP7_11_8,              CANFD0_RX),
+        PINMUX_IPSR_MSEL(IP7_11_8,              RX4_B,          SEL_SCIF4_1),
+        PINMUX_IPSR_GPSR(IP7_11_8,              CAN0_RX),
+        PINMUX_IPSR_MSEL(IP7_11_8,              VI5_DATA9_A,    SEL_VIN5_0),
+        PINMUX_IPSR_MSEL(IP7_11_8,              SCL7_B,         SEL_I2C7_1),
+        PINMUX_IPSR_MSEL(IP7_11_8,              VI5_DATA4_B,    SEL_VIN5_1),
+
+        PINMUX_IPSR_GPSR(IP7_15_12,             D14),
+        PINMUX_IPSR_GPSR(IP7_15_12,             CAN_CLK),
+        PINMUX_IPSR_MSEL(IP7_15_12,             HRX3_A,         SEL_HSCIF3_0),
+        PINMUX_IPSR_GPSR(IP7_15_12,             MSIOF2_SS2_A),
+        PINMUX_IPSR_MSEL(IP7_15_12,             SDA7_B,         SEL_I2C7_1),
+        PINMUX_IPSR_MSEL(IP7_15_12,             VI5_DATA5_B,    SEL_VIN5_1),
+
+        PINMUX_IPSR_GPSR(IP7_19_16,             D15),
+        PINMUX_IPSR_GPSR(IP7_19_16,             MSIOF2_SS1_A),
+        PINMUX_IPSR_GPSR(IP7_19_16,             HTX3_A),
+        PINMUX_IPSR_GPSR(IP7_19_16,             MSIOF3_SS1_A),
+        PINMUX_IPSR_GPSR(IP7_19_16,             DU_DG3),
+        PINMUX_IPSR_GPSR(IP7_19_16,             LCDOUT11),
+
+        PINMUX_IPSR_GPSR(IP7_23_20,             SCL4),
+        PINMUX_IPSR_GPSR(IP7_23_20,             CS1_N_A26),
+        PINMUX_IPSR_GPSR(IP7_23_20,             DU_DOTCLKIN0),
+        PINMUX_IPSR_MSEL(IP7_23_20,             VI4_DATA6_B,    SEL_VIN4_1),
+        PINMUX_IPSR_MSEL(IP7_23_20,             VI5_DATA6_B,    SEL_VIN5_1),
+        PINMUX_IPSR_GPSR(IP7_23_20,             QCLK),
+
+        PINMUX_IPSR_GPSR(IP7_27_24,             SDA4),
+        PINMUX_IPSR_GPSR(IP7_27_24,             WE1_N),
+        PINMUX_IPSR_MSEL(IP7_27_24,             VI4_DATA7_B,    SEL_VIN4_1),
+        PINMUX_IPSR_MSEL(IP7_27_24,             VI5_DATA7_B,    SEL_VIN5_1),
+        PINMUX_IPSR_GPSR(IP7_27_24,             QPOLB),
+
+        PINMUX_IPSR_GPSR(IP7_31_28,             SD0_CLK),
+        PINMUX_IPSR_GPSR(IP7_31_28,             NFDATA8),
+        PINMUX_IPSR_MSEL(IP7_31_28,             SCL1_C,         SEL_I2C1_2),
+        PINMUX_IPSR_MSEL(IP7_31_28,             HSCK1_B,        SEL_HSCIF1_1),
+        PINMUX_IPSR_MSEL(IP7_31_28,             SDA2_E,         SEL_I2C2_4),
+        PINMUX_IPSR_MSEL(IP7_31_28,             FMCLK_B,        SEL_FM_1),
+
+        /* IPSR8 */
+        PINMUX_IPSR_GPSR(IP8_3_0,               SD0_CMD),
+        PINMUX_IPSR_GPSR(IP8_3_0,               NFDATA9),
+        PINMUX_IPSR_MSEL(IP8_3_0,               HRX1_B,         SEL_HSCIF1_1),
+        PINMUX_IPSR_MSEL(IP8_3_0,               SPEEDIN_B,      SEL_SPEED_PULSE_IF_1),
+
+        PINMUX_IPSR_GPSR(IP8_7_4,               SD0_DAT0),
+        PINMUX_IPSR_GPSR(IP8_7_4,               NFDATA10),
+        PINMUX_IPSR_GPSR(IP8_7_4,               HTX1_B),
+        PINMUX_IPSR_MSEL(IP8_7_4,               REMOCON_B,      SEL_REMOCON_1),
+
+        PINMUX_IPSR_GPSR(IP8_11_8,              SD0_DAT1),
+        PINMUX_IPSR_GPSR(IP8_11_8,              NFDATA11),
+        PINMUX_IPSR_MSEL(IP8_11_8,              SDA2_C,         SEL_I2C2_2),
+        PINMUX_IPSR_MSEL(IP8_11_8,              HCTS1_N_B,      SEL_HSCIF1_1),
+        PINMUX_IPSR_MSEL(IP8_11_8,              FMIN_B,         SEL_FM_1),
+
+        PINMUX_IPSR_GPSR(IP8_15_12,             SD0_DAT2),
+        PINMUX_IPSR_GPSR(IP8_15_12,             NFDATA12),
+        PINMUX_IPSR_MSEL(IP8_15_12,             SCL2_C,         SEL_I2C2_2),
+        PINMUX_IPSR_MSEL(IP8_15_12,             HRTS1_N_B,      SEL_HSCIF1_1),
+        PINMUX_IPSR_GPSR(IP8_15_12,             BPFCLK_B),
+
+        PINMUX_IPSR_GPSR(IP8_19_16,             SD0_DAT3),
+        PINMUX_IPSR_GPSR(IP8_19_16,             NFDATA13),
+        PINMUX_IPSR_MSEL(IP8_19_16,             SDA1_C,         SEL_I2C1_2),
+        PINMUX_IPSR_MSEL(IP8_19_16,             SCL2_E,         SEL_I2C2_4),
+        PINMUX_IPSR_MSEL(IP8_19_16,             SPEEDIN_C,      SEL_SPEED_PULSE_IF_2),
+        PINMUX_IPSR_MSEL(IP8_19_16,             REMOCON_C,      SEL_REMOCON_2),
+
+        PINMUX_IPSR_GPSR(IP8_23_20,             SD1_CLK),
+        PINMUX_IPSR_MSEL(IP8_23_20,             NFDATA14_B,     SEL_NDFC_1),
+
+        PINMUX_IPSR_GPSR(IP8_27_24,             SD1_CMD),
+        PINMUX_IPSR_MSEL(IP8_27_24,             NFDATA15_B,     SEL_NDFC_1),
+
+        PINMUX_IPSR_GPSR(IP8_31_28,             SD1_DAT0),
+        PINMUX_IPSR_MSEL(IP8_31_28,             NFWP_N_B,       SEL_NDFC_1),
+
+        /* IPSR9 */
+        PINMUX_IPSR_GPSR(IP9_3_0,               SD1_DAT1),
+        PINMUX_IPSR_MSEL(IP9_3_0,               NFCE_N_B,       SEL_NDFC_1),
+
+        PINMUX_IPSR_GPSR(IP9_7_4,               SD1_DAT2),
+        PINMUX_IPSR_MSEL(IP9_7_4,               NFALE_B,        SEL_NDFC_1),
+
+        PINMUX_IPSR_GPSR(IP9_11_8,              SD1_DAT3),
+        PINMUX_IPSR_MSEL(IP9_11_8,              NFRB_N_B,       SEL_NDFC_1),
+
+        PINMUX_IPSR_GPSR(IP9_15_12,             SD3_CLK),
+        PINMUX_IPSR_GPSR(IP9_15_12,             NFWE_N),
+
+        PINMUX_IPSR_GPSR(IP9_19_16,             SD3_CMD),
+        PINMUX_IPSR_GPSR(IP9_19_16,             NFRE_N),
+
+        PINMUX_IPSR_GPSR(IP9_23_20,             SD3_DAT0),
+        PINMUX_IPSR_GPSR(IP9_23_20,             NFDATA0),
+
+        PINMUX_IPSR_GPSR(IP9_27_24,             SD3_DAT1),
+        PINMUX_IPSR_GPSR(IP9_27_24,             NFDATA1),
+
+        PINMUX_IPSR_GPSR(IP9_31_28,             SD3_DAT2),
+        PINMUX_IPSR_GPSR(IP9_31_28,             NFDATA2),
+
+        /* IPSR10 */
+        PINMUX_IPSR_GPSR(IP10_3_0,              SD3_DAT3),
+        PINMUX_IPSR_GPSR(IP10_3_0,              NFDATA3),
+
+        PINMUX_IPSR_GPSR(IP10_7_4,              SD3_DAT4),
+        PINMUX_IPSR_GPSR(IP10_7_4,              NFDATA4),
+
+        PINMUX_IPSR_GPSR(IP10_11_8,             SD3_DAT5),
+        PINMUX_IPSR_GPSR(IP10_11_8,             NFDATA5),
+
+        PINMUX_IPSR_GPSR(IP10_15_12,            SD3_DAT6),
+        PINMUX_IPSR_GPSR(IP10_15_12,            NFDATA6),
+
+        PINMUX_IPSR_GPSR(IP10_19_16,            SD3_DAT7),
+        PINMUX_IPSR_GPSR(IP10_19_16,            NFDATA7),
+
+        PINMUX_IPSR_GPSR(IP10_23_20,            SD3_DS),
+        PINMUX_IPSR_GPSR(IP10_23_20,            NFCLE),
+
+        PINMUX_IPSR_GPSR(IP10_27_24,            SD0_CD),
+        PINMUX_IPSR_GPSR(IP10_27_24,            NFALE_A),
+        PINMUX_IPSR_GPSR(IP10_27_24,            SD3_CD),
+        PINMUX_IPSR_MSEL(IP10_27_24,            RIF0_CLK_B,     SEL_DRIF0_1),
+        PINMUX_IPSR_MSEL(IP10_27_24,            SCL2_B,         SEL_I2C2_1),
+        PINMUX_IPSR_MSEL(IP10_27_24,            TCLK1_A,        SEL_TIMER_TMU_0),
+        PINMUX_IPSR_MSEL(IP10_27_24,            SSI_SCK2_B,     SEL_SSI2_1),
+        PINMUX_IPSR_GPSR(IP10_27_24,            TS_SCK0),
+
+        PINMUX_IPSR_GPSR(IP10_31_28,            SD0_WP),
+        PINMUX_IPSR_GPSR(IP10_31_28,            NFRB_N_A),
+        PINMUX_IPSR_GPSR(IP10_31_28,            SD3_WP),
+        PINMUX_IPSR_MSEL(IP10_31_28,            RIF0_D0_B,      SEL_DRIF0_1),
+        PINMUX_IPSR_MSEL(IP10_31_28,            SDA2_B,         SEL_I2C2_1),
+        PINMUX_IPSR_MSEL(IP10_31_28,            TCLK2_A,        SEL_TIMER_TMU_0),
+        PINMUX_IPSR_MSEL(IP10_31_28,            SSI_WS2_B,      SEL_SSI2_1),
+        PINMUX_IPSR_GPSR(IP10_31_28,            TS_SDAT0),
+
+        /* IPSR11 */
+        PINMUX_IPSR_GPSR(IP11_3_0,              SD1_CD),
+        PINMUX_IPSR_MSEL(IP11_3_0,              NFCE_N_A,       SEL_NDFC_0),
+        PINMUX_IPSR_GPSR(IP11_3_0,              SSI_SCK1),
+        PINMUX_IPSR_MSEL(IP11_3_0,              RIF0_D1_B,      SEL_DRIF0_1),
+        PINMUX_IPSR_GPSR(IP11_3_0,              TS_SDEN0),
+
+        PINMUX_IPSR_GPSR(IP11_7_4,              SD1_WP),
+        PINMUX_IPSR_MSEL(IP11_7_4,              NFWP_N_A,       SEL_NDFC_0),
+        PINMUX_IPSR_GPSR(IP11_7_4,              SSI_WS1),
+        PINMUX_IPSR_MSEL(IP11_7_4,              RIF0_SYNC_B,    SEL_DRIF0_1),
+        PINMUX_IPSR_GPSR(IP11_7_4,              TS_SPSYNC0),
+
+        PINMUX_IPSR_MSEL(IP11_11_8,             RX0_A,          SEL_SCIF0_0),
+        PINMUX_IPSR_MSEL(IP11_11_8,             HRX1_A,         SEL_HSCIF1_0),
+        PINMUX_IPSR_MSEL(IP11_11_8,             SSI_SCK2_A,     SEL_SSI2_0),
+        PINMUX_IPSR_GPSR(IP11_11_8,             RIF1_SYNC),
+        PINMUX_IPSR_GPSR(IP11_11_8,             TS_SCK1),
+
+        PINMUX_IPSR_GPSR(IP11_15_12,            TX0_A),
+        PINMUX_IPSR_GPSR(IP11_15_12,            HTX1_A),
+        PINMUX_IPSR_MSEL(IP11_15_12,            SSI_WS2_A,      SEL_SSI2_0),
+        PINMUX_IPSR_GPSR(IP11_15_12,            RIF1_D0),
+        PINMUX_IPSR_GPSR(IP11_15_12,            TS_SDAT1),
+
+        PINMUX_IPSR_MSEL(IP11_19_16,            CTS0_N_A,       SEL_SCIF0_0),
+        PINMUX_IPSR_MSEL(IP11_19_16,            NFDATA14_A,     SEL_NDFC_0),
+        PINMUX_IPSR_GPSR(IP11_19_16,            AUDIO_CLKOUT_A),
+        PINMUX_IPSR_GPSR(IP11_19_16,            RIF1_D1),
+        PINMUX_IPSR_MSEL(IP11_19_16,            SCIF_CLK_A,     SEL_SCIF_0),
+        PINMUX_IPSR_MSEL(IP11_19_16,            FMCLK_A,        SEL_FM_0),
+
+        PINMUX_IPSR_MSEL(IP11_23_20,            RTS0_N_TANS_A,  SEL_SCIF0_0),
+        PINMUX_IPSR_MSEL(IP11_23_20,            NFDATA15_A,     SEL_NDFC_0),
+        PINMUX_IPSR_GPSR(IP11_23_20,            AUDIO_CLKOUT1_A),
+        PINMUX_IPSR_GPSR(IP11_23_20,            RIF1_CLK),
+        PINMUX_IPSR_MSEL(IP11_23_20,            SCL2_A,         SEL_I2C2_0),
+        PINMUX_IPSR_MSEL(IP11_23_20,            FMIN_A,         SEL_FM_0),
+
+        PINMUX_IPSR_MSEL(IP11_27_24,            SCK0_A,         SEL_SCIF0_0),
+        PINMUX_IPSR_MSEL(IP11_27_24,            HSCK1_A,        SEL_HSCIF1_0),
+        PINMUX_IPSR_GPSR(IP11_27_24,            USB3HS0_ID),
+        PINMUX_IPSR_GPSR(IP11_27_24,            RTS1_N_TANS),
+        PINMUX_IPSR_MSEL(IP11_27_24,            SDA2_A,         SEL_I2C2_0),
+        PINMUX_IPSR_MSEL(IP11_27_24,            FMCLK_C,        SEL_FM_2),
+        PINMUX_IPSR_GPSR(IP11_27_24,            USB1_ID),
+
+        PINMUX_IPSR_GPSR(IP11_31_28,            RX1),
+        PINMUX_IPSR_MSEL(IP11_31_28,            HRX2_B,         SEL_HSCIF2_1),
+        PINMUX_IPSR_MSEL(IP11_31_28,            SSI_SCK9_B,     SEL_SSI9_1),
+        PINMUX_IPSR_GPSR(IP11_31_28,            AUDIO_CLKOUT1_B),
+
+        /* IPSR12 */
+        PINMUX_IPSR_GPSR(IP12_3_0,              TX1),
+        PINMUX_IPSR_GPSR(IP12_3_0,              HTX2_B),
+        PINMUX_IPSR_MSEL(IP12_3_0,              SSI_WS9_B,      SEL_SSI9_1),
+        PINMUX_IPSR_GPSR(IP12_3_0,              AUDIO_CLKOUT3_B),
+
+        PINMUX_IPSR_GPSR(IP12_7_4,              SCK2_A),
+        PINMUX_IPSR_MSEL(IP12_7_4,              HSCK0_A,        SEL_HSCIF0_0),
+        PINMUX_IPSR_MSEL(IP12_7_4,              AUDIO_CLKB_A,   SEL_ADGB_0),
+        PINMUX_IPSR_GPSR(IP12_7_4,              CTS1_N),
+        PINMUX_IPSR_MSEL(IP12_7_4,              RIF0_CLK_A,     SEL_DRIF0_0),
+        PINMUX_IPSR_MSEL(IP12_7_4,              REMOCON_A,      SEL_REMOCON_0),
+        PINMUX_IPSR_MSEL(IP12_7_4,              SCIF_CLK_B,     SEL_SCIF_1),
+
+        PINMUX_IPSR_GPSR(IP12_11_8,             TX2_A),
+        PINMUX_IPSR_MSEL(IP12_11_8,             HRX0_A,         SEL_HSCIF0_0),
+        PINMUX_IPSR_GPSR(IP12_11_8,             AUDIO_CLKOUT2_A),
+        PINMUX_IPSR_MSEL(IP12_11_8,             SCL1_A,         SEL_I2C1_0),
+        PINMUX_IPSR_MSEL(IP12_11_8,             FSO_CFE_0_N_A,  SEL_FSO_0),
+        PINMUX_IPSR_GPSR(IP12_11_8,             TS_SDEN1),
+
+        PINMUX_IPSR_GPSR(IP12_15_12,            RX2_A),
+        PINMUX_IPSR_GPSR(IP12_15_12,            HTX0_A),
+        PINMUX_IPSR_GPSR(IP12_15_12,            AUDIO_CLKOUT3_A),
+        PINMUX_IPSR_MSEL(IP12_15_12,            SDA1_A,         SEL_I2C1_0),
+        PINMUX_IPSR_MSEL(IP12_15_12,            FSO_CFE_1_N_A,  SEL_FSO_0),
+        PINMUX_IPSR_GPSR(IP12_15_12,            TS_SPSYNC1),
+
+        PINMUX_IPSR_GPSR(IP12_19_16,            MSIOF0_SCK),
+        PINMUX_IPSR_GPSR(IP12_19_16,            SSI_SCK78),
+
+        PINMUX_IPSR_GPSR(IP12_23_20,            MSIOF0_RXD),
+        PINMUX_IPSR_GPSR(IP12_23_20,            SSI_WS78),
+        PINMUX_IPSR_GPSR(IP12_23_20,            TX2_B),
+
+        PINMUX_IPSR_GPSR(IP12_27_24,            MSIOF0_TXD),
+        PINMUX_IPSR_GPSR(IP12_27_24,            SSI_SDATA7),
+        PINMUX_IPSR_GPSR(IP12_27_24,            RX2_B),
+
+        PINMUX_IPSR_GPSR(IP12_31_28,            MSIOF0_SYNC),
+        PINMUX_IPSR_GPSR(IP12_31_28,            AUDIO_CLKOUT_B),
+        PINMUX_IPSR_GPSR(IP12_31_28,            SSI_SDATA8),
+
+        /* IPSR13 */
+        PINMUX_IPSR_GPSR(IP13_3_0,              MSIOF0_SS1),
+        PINMUX_IPSR_MSEL(IP13_3_0,              HRX2_A,         SEL_HSCIF2_0),
+        PINMUX_IPSR_GPSR(IP13_3_0,              SSI_SCK4),
+        PINMUX_IPSR_MSEL(IP13_3_0,              HCTS0_N_A,      SEL_HSCIF0_0),
+        PINMUX_IPSR_GPSR(IP13_3_0,              BPFCLK_C),
+        PINMUX_IPSR_MSEL(IP13_3_0,              SPEEDIN_A,      SEL_SPEED_PULSE_IF_0),
+
+        PINMUX_IPSR_GPSR(IP13_7_4,              MSIOF0_SS2),
+        PINMUX_IPSR_GPSR(IP13_7_4,              HTX2_A),
+        PINMUX_IPSR_GPSR(IP13_7_4,              SSI_WS4),
+        PINMUX_IPSR_MSEL(IP13_7_4,              HRTS0_N_A,      SEL_HSCIF0_0),
+        PINMUX_IPSR_MSEL(IP13_7_4,              FMIN_C,         SEL_FM_2),
+        PINMUX_IPSR_GPSR(IP13_7_4,              BPFCLK_A),
+
+        PINMUX_IPSR_GPSR(IP13_11_8,             SSI_SDATA9),
+        PINMUX_IPSR_MSEL(IP13_11_8,             AUDIO_CLKC_A,   SEL_ADGC_0),
+        PINMUX_IPSR_GPSR(IP13_11_8,             SCK1),
+
+        PINMUX_IPSR_GPSR(IP13_15_12,            MLB_CLK),
+        PINMUX_IPSR_MSEL(IP13_15_12,            RX0_B,          SEL_SCIF0_1),
+        PINMUX_IPSR_MSEL(IP13_15_12,            RIF0_D0_A,      SEL_DRIF0_0),
+        PINMUX_IPSR_MSEL(IP13_15_12,            SCL1_B,         SEL_I2C1_1),
+        PINMUX_IPSR_MSEL(IP13_15_12,            TCLK1_B,        SEL_TIMER_TMU_1),
+        PINMUX_IPSR_GPSR(IP13_15_12,            SIM0_RST_A),
+
+        PINMUX_IPSR_GPSR(IP13_19_16,            MLB_SIG),
+        PINMUX_IPSR_MSEL(IP13_19_16,            SCK0_B,         SEL_SCIF0_1),
+        PINMUX_IPSR_MSEL(IP13_19_16,            RIF0_D1_A,      SEL_DRIF0_0),
+        PINMUX_IPSR_MSEL(IP13_19_16,            SDA1_B,         SEL_I2C1_1),
+        PINMUX_IPSR_MSEL(IP13_19_16,            TCLK2_B,        SEL_TIMER_TMU_1),
+        PINMUX_IPSR_MSEL(IP13_19_16,            SIM0_D_A,       SEL_SIMCARD_0),
+
+        PINMUX_IPSR_GPSR(IP13_23_20,            MLB_DAT),
+        PINMUX_IPSR_GPSR(IP13_23_20,            TX0_B),
+        PINMUX_IPSR_MSEL(IP13_23_20,            RIF0_SYNC_A,    SEL_DRIF0_0),
+        PINMUX_IPSR_GPSR(IP13_23_20,            SIM0_CLK_A),
+
+        PINMUX_IPSR_GPSR(IP13_27_24,            SSI_SCK01239),
+
+        PINMUX_IPSR_GPSR(IP13_31_28,            SSI_WS01239),
+
+        /* IPSR14 */
+        PINMUX_IPSR_GPSR(IP14_3_0,              SSI_SDATA0),
+
+        PINMUX_IPSR_GPSR(IP14_7_4,              SSI_SDATA1),
+        PINMUX_IPSR_MSEL(IP14_7_4,              AUDIO_CLKC_B,   SEL_ADGC_1),
+        PINMUX_IPSR_MSEL(IP14_7_4,              PWM0_B,         SEL_PWM0_1),
+
+        PINMUX_IPSR_GPSR(IP14_11_8,             SSI_SDATA2),
+        PINMUX_IPSR_GPSR(IP14_11_8,             AUDIO_CLKOUT2_B),
+        PINMUX_IPSR_MSEL(IP14_11_8,             SSI_SCK9_A,     SEL_SSI9_0),
+        PINMUX_IPSR_MSEL(IP14_11_8,             PWM1_B,         SEL_PWM1_1),
+
+        PINMUX_IPSR_GPSR(IP14_15_12,            SSI_SCK349),
+        PINMUX_IPSR_MSEL(IP14_15_12,            PWM2_C,         SEL_PWM2_2),
+
+        PINMUX_IPSR_GPSR(IP14_19_16,            SSI_WS349),
+        PINMUX_IPSR_MSEL(IP14_19_16,            PWM3_C,         SEL_PWM3_2),
+
+        PINMUX_IPSR_GPSR(IP14_23_20,            SSI_SDATA3),
+        PINMUX_IPSR_GPSR(IP14_23_20,            AUDIO_CLKOUT1_C),
+        PINMUX_IPSR_MSEL(IP14_23_20,            AUDIO_CLKB_B,   SEL_ADGB_1),
+        PINMUX_IPSR_MSEL(IP14_23_20,            PWM4_B,         SEL_PWM4_1),
+
+        PINMUX_IPSR_GPSR(IP14_27_24,            SSI_SDATA4),
+        PINMUX_IPSR_MSEL(IP14_27_24,            SSI_WS9_A,      SEL_SSI9_0),
+        PINMUX_IPSR_MSEL(IP14_27_24,            PWM5_B,         SEL_PWM5_1),
+
+        PINMUX_IPSR_GPSR(IP14_31_28,            SSI_SCK5),
+        PINMUX_IPSR_MSEL(IP14_31_28,            HRX0_B,         SEL_HSCIF0_1),
+        PINMUX_IPSR_GPSR(IP14_31_28,            USB0_PWEN_B),
+        PINMUX_IPSR_MSEL(IP14_31_28,            SCL2_D,         SEL_I2C2_3),
+        PINMUX_IPSR_MSEL(IP14_31_28,            PWM6_B,         SEL_PWM6_1),
+
+        /* IPSR15 */
+        PINMUX_IPSR_GPSR(IP15_3_0,              SSI_WS5),
+        PINMUX_IPSR_GPSR(IP15_3_0,              HTX0_B),
+        PINMUX_IPSR_MSEL(IP15_3_0,              USB0_OVC_B,     SEL_USB_20_CH0_1),
+        PINMUX_IPSR_MSEL(IP15_3_0,              SDA2_D,         SEL_I2C2_3),
+
+        PINMUX_IPSR_GPSR(IP15_7_4,              SSI_SDATA5),
+        PINMUX_IPSR_MSEL(IP15_7_4,              HSCK0_B,        SEL_HSCIF0_1),
+        PINMUX_IPSR_MSEL(IP15_7_4,              AUDIO_CLKB_C,   SEL_ADGB_2),
+        PINMUX_IPSR_GPSR(IP15_7_4,              TPU0TO0),
+
+        PINMUX_IPSR_GPSR(IP15_11_8,             SSI_SCK6),
+        PINMUX_IPSR_MSEL(IP15_11_8,             HSCK2_A,        SEL_HSCIF2_0),
+        PINMUX_IPSR_MSEL(IP15_11_8,             AUDIO_CLKC_C,   SEL_ADGC_2),
+        PINMUX_IPSR_GPSR(IP15_11_8,             TPU0TO1),
+        PINMUX_IPSR_MSEL(IP15_11_8,             FSO_CFE_0_N_B,  SEL_FSO_1),
+        PINMUX_IPSR_GPSR(IP15_11_8,             SIM0_RST_B),
+
+        PINMUX_IPSR_GPSR(IP15_15_12,            SSI_WS6),
+        PINMUX_IPSR_MSEL(IP15_15_12,            HCTS2_N_A,      SEL_HSCIF2_0),
+        PINMUX_IPSR_GPSR(IP15_15_12,            AUDIO_CLKOUT2_C),
+        PINMUX_IPSR_GPSR(IP15_15_12,            TPU0TO2),
+        PINMUX_IPSR_MSEL(IP15_15_12,            SDA1_D,         SEL_I2C1_3),
+        PINMUX_IPSR_MSEL(IP15_15_12,            FSO_CFE_1_N_B,  SEL_FSO_1),
+        PINMUX_IPSR_MSEL(IP15_15_12,            SIM0_D_B,       SEL_SIMCARD_1),
+
+        PINMUX_IPSR_GPSR(IP15_19_16,            SSI_SDATA6),
+        PINMUX_IPSR_MSEL(IP15_19_16,            HRTS2_N_A,      SEL_HSCIF2_0),
+        PINMUX_IPSR_GPSR(IP15_19_16,            AUDIO_CLKOUT3_C),
+        PINMUX_IPSR_GPSR(IP15_19_16,            TPU0TO3),
+        PINMUX_IPSR_MSEL(IP15_19_16,            SCL1_D,         SEL_I2C1_3),
+        PINMUX_IPSR_MSEL(IP15_19_16,            FSO_TOE_N_B,    SEL_FSO_1),
+        PINMUX_IPSR_GPSR(IP15_19_16,            SIM0_CLK_B),
+
+        PINMUX_IPSR_GPSR(IP15_23_20,            AUDIO_CLKA),
+
+        PINMUX_IPSR_GPSR(IP15_27_24,            USB30_PWEN),
+        PINMUX_IPSR_GPSR(IP15_27_24,            USB0_PWEN_A),
+
+        PINMUX_IPSR_GPSR(IP15_31_28,            USB30_OVC),
+        PINMUX_IPSR_MSEL(IP15_31_28,            USB0_OVC_A,     SEL_USB_20_CH0_0),
+
+/*
+ * Static pins can not be muxed between different functions but
+ * still need mark entries in the pinmux list. Add each static
+ * pin to the list without an associated function. The sh-pfc
+ * core will do the right thing and skip trying to mux the pin
+ * while still applying configuration to it.
+ */
+#define FM(x)   PINMUX_DATA(x##_MARK, 0),
+        PINMUX_STATIC
+#undef FM
+};
+
+/*
+ * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
+ * Physical layout rows: A - AE, cols: 1 - 25.
+ */
+#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
+#define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
+#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
+#define PIN_NONE U16_MAX
+
+static const struct sh_pfc_pin pinmux_pins[] = {
+        PINMUX_GPIO_GP_ALL(),
+
+        /*
+         * Pins not associated with a GPIO port.
+         *
+         * The pin positions are different between different R8A77990
+         * packages, all that is needed for the pfc driver is a unique
+         * number for each pin. To this end use the pin layout from
+         * R8A77990 to calculate a unique number for each pin.
+         */
+        SH_PFC_PIN_NAMED_CFG('F',  1, TRST_N,           CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('F',  3, TMS,              CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('F',  4, TCK,              CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('G',  2, TDI,              CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('G',  3, FSCLKST_N,        CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('H',  1, ASEBRK,           CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('N',  1, AVB_TXC,          CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('N',  2, AVB_TD0,          CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('N',  3, AVB_TD1,          CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('N',  5, AVB_TD2,          CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('N',  6, AVB_TD3,          CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('P',  3, AVB_TX_CTL,       CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('P',  4, AVB_MDIO,         CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('P',  5, AVB_MDC,          CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF,          CFG_FLAGS),
+        SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
+};
+
+/* - EtherAVB --------------------------------------------------------------- */
+static const unsigned int avb_link_pins[] = {
+        /* AVB_LINK */
+        RCAR_GP_PIN(2, 23),
+};
+
+static const unsigned int avb_link_mux[] = {
+        AVB_LINK_MARK,
+};
+
+static const unsigned int avb_magic_pins[] = {
+        /* AVB_MAGIC */
+        RCAR_GP_PIN(2, 22),
+};
+
+static const unsigned int avb_magic_mux[] = {
+        AVB_MAGIC_MARK,
+};
+
+static const unsigned int avb_phy_int_pins[] = {
+        /* AVB_PHY_INT */
+        RCAR_GP_PIN(2, 21),
+};
+
+static const unsigned int avb_phy_int_mux[] = {
+        AVB_PHY_INT_MARK,
+};
+
+static const unsigned int avb_mii_pins[] = {
+        /*
+         * AVB_RX_CTL, AVB_RXC, AVB_RD0,
+         * AVB_RD1, AVB_RD2, AVB_RD3,
+         * AVB_TXCREFCLK
+         */
+        RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
+        RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
+        RCAR_GP_PIN(2, 20),
+};
+
+static const unsigned int avb_mii_mux[] = {
+        AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
+        AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
+        AVB_TXCREFCLK_MARK,
+};
+
+static const unsigned int avb_avtp_pps_pins[] = {
+        /* AVB_AVTP_PPS */
+        RCAR_GP_PIN(1, 2),
+};
+
+static const unsigned int avb_avtp_pps_mux[] = {
+        AVB_AVTP_PPS_MARK,
+};
+
+static const unsigned int avb_avtp_match_a_pins[] = {
+        /* AVB_AVTP_MATCH_A */
+        RCAR_GP_PIN(2, 24),
+};
+
+static const unsigned int avb_avtp_match_a_mux[] = {
+        AVB_AVTP_MATCH_A_MARK,
+};
+
+static const unsigned int avb_avtp_capture_a_pins[] = {
+        /* AVB_AVTP_CAPTURE_A */
+        RCAR_GP_PIN(2, 25),
+};
+
+static const unsigned int avb_avtp_capture_a_mux[] = {
+        AVB_AVTP_CAPTURE_A_MARK,
+};
+
+/* - I2C -------------------------------------------------------------------- */
+static const unsigned int i2c1_a_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+};
+
+static const unsigned int i2c1_a_mux[] = {
+        SCL1_A_MARK, SDA1_A_MARK,
+};
+
+static const unsigned int i2c1_b_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
+};
+
+static const unsigned int i2c1_b_mux[] = {
+        SCL1_B_MARK, SDA1_B_MARK,
+};
+
+static const unsigned int i2c1_c_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
+};
+
+static const unsigned int i2c1_c_mux[] = {
+        SCL1_C_MARK, SDA1_C_MARK,
+};
+
+static const unsigned int i2c1_d_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
+};
+
+static const unsigned int i2c1_d_mux[] = {
+        SCL1_D_MARK, SDA1_D_MARK,
+};
+
+static const unsigned int i2c2_a_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
+};
+
+static const unsigned int i2c2_a_mux[] = {
+        SCL2_A_MARK, SDA2_A_MARK,
+};
+
+static const unsigned int i2c2_b_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+
+static const unsigned int i2c2_b_mux[] = {
+        SCL2_B_MARK, SDA2_B_MARK,
+};
+
+static const unsigned int i2c2_c_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
+};
+
+static const unsigned int i2c2_c_mux[] = {
+        SCL2_C_MARK, SDA2_C_MARK,
+};
+
+static const unsigned int i2c2_d_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
+};
+
+static const unsigned int i2c2_d_mux[] = {
+        SCL2_D_MARK, SDA2_D_MARK,
+};
+
+static const unsigned int i2c2_e_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
+};
+
+static const unsigned int i2c2_e_mux[] = {
+        SCL2_E_MARK, SDA2_E_MARK,
+};
+
+static const unsigned int i2c4_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
+};
+
+static const unsigned int i2c4_mux[] = {
+        SCL4_MARK, SDA4_MARK,
+};
+
+static const unsigned int i2c5_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+};
+
+static const unsigned int i2c5_mux[] = {
+        SCL5_MARK, SDA5_MARK,
+};
+
+static const unsigned int i2c6_a_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
+};
+
+static const unsigned int i2c6_a_mux[] = {
+        SCL6_A_MARK, SDA6_A_MARK,
+};
+
+static const unsigned int i2c6_b_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
+};
+
+static const unsigned int i2c6_b_mux[] = {
+        SCL6_B_MARK, SDA6_B_MARK,
+};
+
+static const unsigned int i2c7_a_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
+};
+
+static const unsigned int i2c7_a_mux[] = {
+        SCL7_A_MARK, SDA7_A_MARK,
+};
+
+static const unsigned int i2c7_b_pins[] = {
+        /* SCL, SDA */
+        RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
+};
+
+static const unsigned int i2c7_b_mux[] = {
+        SCL7_B_MARK, SDA7_B_MARK,
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_a_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+
+static const unsigned int scif0_data_a_mux[] = {
+        RX0_A_MARK, TX0_A_MARK,
+};
+
+static const unsigned int scif0_clk_a_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 0),
+};
+
+static const unsigned int scif0_clk_a_mux[] = {
+        SCK0_A_MARK,
+};
+
+static const unsigned int scif0_ctrl_a_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
+};
+
+static const unsigned int scif0_ctrl_a_mux[] = {
+        RTS0_N_TANS_A_MARK, CTS0_N_A_MARK,
+};
+
+static const unsigned int scif0_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
+};
+
+static const unsigned int scif0_data_b_mux[] = {
+        RX0_B_MARK, TX0_B_MARK,
+};
+
+static const unsigned int scif0_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 18),
+};
+
+static const unsigned int scif0_clk_b_mux[] = {
+        SCK0_B_MARK,
+};
+
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+
+static const unsigned int scif1_data_mux[] = {
+        RX1_MARK, TX1_MARK,
+};
+
+static const unsigned int scif1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 16),
+};
+
+static const unsigned int scif1_clk_mux[] = {
+        SCK1_MARK,
+};
+
+static const unsigned int scif1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
+};
+
+static const unsigned int scif1_ctrl_mux[] = {
+        RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_a_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
+};
+
+static const unsigned int scif2_data_a_mux[] = {
+        RX2_A_MARK, TX2_A_MARK,
+};
+
+static const unsigned int scif2_clk_a_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 7),
+};
+
+static const unsigned int scif2_clk_a_mux[] = {
+        SCK2_A_MARK,
+};
+
+static const unsigned int scif2_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
+};
+
+static const unsigned int scif2_data_b_mux[] = {
+        RX2_B_MARK, TX2_B_MARK,
+};
+
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_a_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+};
+
+static const unsigned int scif3_data_a_mux[] = {
+        RX3_A_MARK, TX3_A_MARK,
+};
+
+static const unsigned int scif3_clk_a_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 1),
+};
+
+static const unsigned int scif3_clk_a_mux[] = {
+        SCK3_A_MARK,
+};
+
+static const unsigned int scif3_ctrl_a_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
+};
+
+static const unsigned int scif3_ctrl_a_mux[] = {
+        RTS3_N_TANS_A_MARK, CTS3_N_A_MARK,
+};
+
+static const unsigned int scif3_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
+};
+
+static const unsigned int scif3_data_b_mux[] = {
+        RX3_B_MARK, TX3_B_MARK,
+};
+
+static const unsigned int scif3_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
+};
+
+static const unsigned int scif3_data_c_mux[] = {
+        RX3_C_MARK, TX3_C_MARK,
+};
+
+static const unsigned int scif3_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 24),
+};
+
+static const unsigned int scif3_clk_c_mux[] = {
+        SCK3_C_MARK,
+};
+
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_a_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+
+static const unsigned int scif4_data_a_mux[] = {
+        RX4_A_MARK, TX4_A_MARK,
+};
+
+static const unsigned int scif4_clk_a_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(1, 5),
+};
+
+static const unsigned int scif4_clk_a_mux[] = {
+        SCK4_A_MARK,
+};
+
+static const unsigned int scif4_ctrl_a_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
+};
+
+static const unsigned int scif4_ctrl_a_mux[] = {
+        RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
+};
+
+static const unsigned int scif4_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
+};
+
+static const unsigned int scif4_data_b_mux[] = {
+        RX4_B_MARK, TX4_B_MARK,
+};
+
+static const unsigned int scif4_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 8),
+};
+
+static const unsigned int scif4_clk_b_mux[] = {
+        SCK4_B_MARK,
+};
+
+static const unsigned int scif4_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+};
+
+static const unsigned int scif4_data_c_mux[] = {
+        RX4_C_MARK, TX4_C_MARK,
+};
+
+static const unsigned int scif4_ctrl_c_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
+};
+
+static const unsigned int scif4_ctrl_c_mux[] = {
+        RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
+};
+
+/* - SCIF5 ------------------------------------------------------------------ */
+static const unsigned int scif5_data_a_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
+};
+
+static const unsigned int scif5_data_a_mux[] = {
+        RX5_A_MARK, TX5_A_MARK,
+};
+
+static const unsigned int scif5_clk_a_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(1, 13),
+};
+
+static const unsigned int scif5_clk_a_mux[] = {
+        SCK5_A_MARK,
+};
+
+static const unsigned int scif5_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
+};
+
+static const unsigned int scif5_data_b_mux[] = {
+        RX5_B_MARK, TX5_B_MARK,
+};
+
+static const unsigned int scif5_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+};
+
+static const unsigned int scif5_data_c_mux[] = {
+        RX5_C_MARK, TX5_C_MARK,
+};
+
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_a_pins[] = {
+        /* SCIF_CLK */
+        RCAR_GP_PIN(5, 3),
+};
+
+static const unsigned int scif_clk_a_mux[] = {
+        SCIF_CLK_A_MARK,
+};
+
+static const unsigned int scif_clk_b_pins[] = {
+        /* SCIF_CLK */
+        RCAR_GP_PIN(5, 7),
+};
+
+static const unsigned int scif_clk_b_mux[] = {
+        SCIF_CLK_B_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(avb_link),
+        SH_PFC_PIN_GROUP(avb_magic),
+        SH_PFC_PIN_GROUP(avb_phy_int),
+        SH_PFC_PIN_GROUP(avb_mii),
+        SH_PFC_PIN_GROUP(avb_avtp_pps),
+        SH_PFC_PIN_GROUP(avb_avtp_match_a),
+        SH_PFC_PIN_GROUP(avb_avtp_capture_a),
+        SH_PFC_PIN_GROUP(i2c1_a),
+        SH_PFC_PIN_GROUP(i2c1_b),
+        SH_PFC_PIN_GROUP(i2c1_c),
+        SH_PFC_PIN_GROUP(i2c1_d),
+        SH_PFC_PIN_GROUP(i2c2_a),
+        SH_PFC_PIN_GROUP(i2c2_b),
+        SH_PFC_PIN_GROUP(i2c2_c),
+        SH_PFC_PIN_GROUP(i2c2_d),
+        SH_PFC_PIN_GROUP(i2c2_e),
+        SH_PFC_PIN_GROUP(i2c4),
+        SH_PFC_PIN_GROUP(i2c5),
+        SH_PFC_PIN_GROUP(i2c6_a),
+        SH_PFC_PIN_GROUP(i2c6_b),
+        SH_PFC_PIN_GROUP(i2c7_a),
+        SH_PFC_PIN_GROUP(i2c7_b),
+        SH_PFC_PIN_GROUP(scif0_data_a),
+        SH_PFC_PIN_GROUP(scif0_clk_a),
+        SH_PFC_PIN_GROUP(scif0_ctrl_a),
+        SH_PFC_PIN_GROUP(scif0_data_b),
+        SH_PFC_PIN_GROUP(scif0_clk_b),
+        SH_PFC_PIN_GROUP(scif1_data),
+        SH_PFC_PIN_GROUP(scif1_clk),
+        SH_PFC_PIN_GROUP(scif1_ctrl),
+        SH_PFC_PIN_GROUP(scif2_data_a),
+        SH_PFC_PIN_GROUP(scif2_clk_a),
+        SH_PFC_PIN_GROUP(scif2_data_b),
+        SH_PFC_PIN_GROUP(scif3_data_a),
+        SH_PFC_PIN_GROUP(scif3_clk_a),
+        SH_PFC_PIN_GROUP(scif3_ctrl_a),
+        SH_PFC_PIN_GROUP(scif3_data_b),
+        SH_PFC_PIN_GROUP(scif3_data_c),
+        SH_PFC_PIN_GROUP(scif3_clk_c),
+        SH_PFC_PIN_GROUP(scif4_data_a),
+        SH_PFC_PIN_GROUP(scif4_clk_a),
+        SH_PFC_PIN_GROUP(scif4_ctrl_a),
+        SH_PFC_PIN_GROUP(scif4_data_b),
+        SH_PFC_PIN_GROUP(scif4_clk_b),
+        SH_PFC_PIN_GROUP(scif4_data_c),
+        SH_PFC_PIN_GROUP(scif4_ctrl_c),
+        SH_PFC_PIN_GROUP(scif5_data_a),
+        SH_PFC_PIN_GROUP(scif5_clk_a),
+        SH_PFC_PIN_GROUP(scif5_data_b),
+        SH_PFC_PIN_GROUP(scif5_data_c),
+        SH_PFC_PIN_GROUP(scif_clk_a),
+        SH_PFC_PIN_GROUP(scif_clk_b),
+};
+
+static const char * const avb_groups[] = {
+        "avb_link",
+        "avb_magic",
+        "avb_phy_int",
+        "avb_mii",
+        "avb_avtp_pps",
+        "avb_avtp_match_a",
+        "avb_avtp_capture_a",
+};
+
+static const char * const i2c1_groups[] = {
+        "i2c1_a",
+        "i2c1_b",
+        "i2c1_c",
+        "i2c1_d",
+};
+
+static const char * const i2c2_groups[] = {
+        "i2c2_a",
+        "i2c2_b",
+        "i2c2_c",
+        "i2c2_d",
+        "i2c2_e",
+};
+
+static const char * const i2c4_groups[] = {
+        "i2c4",
+};
+
+static const char * const i2c5_groups[] = {
+        "i2c5",
+};
+
+static const char * const i2c6_groups[] = {
+        "i2c6_a",
+        "i2c6_b",
+};
+
+static const char * const i2c7_groups[] = {
+        "i2c7_a",
+        "i2c7_b",
+};
+
+static const char * const scif0_groups[] = {
+        "scif0_data_a",
+        "scif0_clk_a",
+        "scif0_ctrl_a",
+        "scif0_data_b",
+        "scif0_clk_b",
+};
+
+static const char * const scif1_groups[] = {
+        "scif1_data",
+        "scif1_clk",
+        "scif1_ctrl",
+};
+
+static const char * const scif2_groups[] = {
+        "scif2_data_a",
+        "scif2_clk_a",
+        "scif2_data_b",
+};
+
+static const char * const scif3_groups[] = {
+        "scif3_data_a",
+        "scif3_clk_a",
+        "scif3_ctrl_a",
+        "scif3_data_b",
+        "scif3_data_c",
+        "scif3_clk_c",
+};
+
+static const char * const scif4_groups[] = {
+        "scif4_data_a",
+        "scif4_clk_a",
+        "scif4_ctrl_a",
+        "scif4_data_b",
+        "scif4_clk_b",
+        "scif4_data_c",
+        "scif4_ctrl_c",
+};
+
+static const char * const scif5_groups[] = {
+        "scif5_data_a",
+        "scif5_clk_a",
+        "scif5_data_b",
+        "scif5_data_c",
+};
+
+static const char * const scif_clk_groups[] = {
+        "scif_clk_a",
+        "scif_clk_b",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(avb),
+        SH_PFC_FUNCTION(i2c1),
+        SH_PFC_FUNCTION(i2c2),
+        SH_PFC_FUNCTION(i2c4),
+        SH_PFC_FUNCTION(i2c5),
+        SH_PFC_FUNCTION(i2c6),
+        SH_PFC_FUNCTION(i2c7),
+        SH_PFC_FUNCTION(scif0),
+        SH_PFC_FUNCTION(scif1),
+        SH_PFC_FUNCTION(scif2),
+        SH_PFC_FUNCTION(scif3),
+        SH_PFC_FUNCTION(scif4),
+        SH_PFC_FUNCTION(scif5),
+        SH_PFC_FUNCTION(scif_clk),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+#define F_(x, y)        FN_##y
+#define FM(x)           FN_##x
+        { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_0_17_FN,     GPSR0_17,
+                GP_0_16_FN,     GPSR0_16,
+                GP_0_15_FN,     GPSR0_15,
+                GP_0_14_FN,     GPSR0_14,
+                GP_0_13_FN,     GPSR0_13,
+                GP_0_12_FN,     GPSR0_12,
+                GP_0_11_FN,     GPSR0_11,
+                GP_0_10_FN,     GPSR0_10,
+                GP_0_9_FN,      GPSR0_9,
+                GP_0_8_FN,      GPSR0_8,
+                GP_0_7_FN,      GPSR0_7,
+                GP_0_6_FN,      GPSR0_6,
+                GP_0_5_FN,      GPSR0_5,
+                GP_0_4_FN,      GPSR0_4,
+                GP_0_3_FN,      GPSR0_3,
+                GP_0_2_FN,      GPSR0_2,
+                GP_0_1_FN,      GPSR0_1,
+                GP_0_0_FN,      GPSR0_0, }
+        },
+        { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_1_22_FN,     GPSR1_22,
+                GP_1_21_FN,     GPSR1_21,
+                GP_1_20_FN,     GPSR1_20,
+                GP_1_19_FN,     GPSR1_19,
+                GP_1_18_FN,     GPSR1_18,
+                GP_1_17_FN,     GPSR1_17,
+                GP_1_16_FN,     GPSR1_16,
+                GP_1_15_FN,     GPSR1_15,
+                GP_1_14_FN,     GPSR1_14,
+                GP_1_13_FN,     GPSR1_13,
+                GP_1_12_FN,     GPSR1_12,
+                GP_1_11_FN,     GPSR1_11,
+                GP_1_10_FN,     GPSR1_10,
+                GP_1_9_FN,      GPSR1_9,
+                GP_1_8_FN,      GPSR1_8,
+                GP_1_7_FN,      GPSR1_7,
+                GP_1_6_FN,      GPSR1_6,
+                GP_1_5_FN,      GPSR1_5,
+                GP_1_4_FN,      GPSR1_4,
+                GP_1_3_FN,      GPSR1_3,
+                GP_1_2_FN,      GPSR1_2,
+                GP_1_1_FN,      GPSR1_1,
+                GP_1_0_FN,      GPSR1_0, }
+        },
+        { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_2_25_FN,     GPSR2_25,
+                GP_2_24_FN,     GPSR2_24,
+                GP_2_23_FN,     GPSR2_23,
+                GP_2_22_FN,     GPSR2_22,
+                GP_2_21_FN,     GPSR2_21,
+                GP_2_20_FN,     GPSR2_20,
+                GP_2_19_FN,     GPSR2_19,
+                GP_2_18_FN,     GPSR2_18,
+                GP_2_17_FN,     GPSR2_17,
+                GP_2_16_FN,     GPSR2_16,
+                GP_2_15_FN,     GPSR2_15,
+                GP_2_14_FN,     GPSR2_14,
+                GP_2_13_FN,     GPSR2_13,
+                GP_2_12_FN,     GPSR2_12,
+                GP_2_11_FN,     GPSR2_11,
+                GP_2_10_FN,     GPSR2_10,
+                GP_2_9_FN,      GPSR2_9,
+                GP_2_8_FN,      GPSR2_8,
+                GP_2_7_FN,      GPSR2_7,
+                GP_2_6_FN,      GPSR2_6,
+                GP_2_5_FN,      GPSR2_5,
+                GP_2_4_FN,      GPSR2_4,
+                GP_2_3_FN,      GPSR2_3,
+                GP_2_2_FN,      GPSR2_2,
+                GP_2_1_FN,      GPSR2_1,
+                GP_2_0_FN,      GPSR2_0, }
+        },
+        { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_3_15_FN,     GPSR3_15,
+                GP_3_14_FN,     GPSR3_14,
+                GP_3_13_FN,     GPSR3_13,
+                GP_3_12_FN,     GPSR3_12,
+                GP_3_11_FN,     GPSR3_11,
+                GP_3_10_FN,     GPSR3_10,
+                GP_3_9_FN,      GPSR3_9,
+                GP_3_8_FN,      GPSR3_8,
+                GP_3_7_FN,      GPSR3_7,
+                GP_3_6_FN,      GPSR3_6,
+                GP_3_5_FN,      GPSR3_5,
+                GP_3_4_FN,      GPSR3_4,
+                GP_3_3_FN,      GPSR3_3,
+                GP_3_2_FN,      GPSR3_2,
+                GP_3_1_FN,      GPSR3_1,
+                GP_3_0_FN,      GPSR3_0, }
+        },
+        { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_4_10_FN,     GPSR4_10,
+                GP_4_9_FN,      GPSR4_9,
+                GP_4_8_FN,      GPSR4_8,
+                GP_4_7_FN,      GPSR4_7,
+                GP_4_6_FN,      GPSR4_6,
+                GP_4_5_FN,      GPSR4_5,
+                GP_4_4_FN,      GPSR4_4,
+                GP_4_3_FN,      GPSR4_3,
+                GP_4_2_FN,      GPSR4_2,
+                GP_4_1_FN,      GPSR4_1,
+                GP_4_0_FN,      GPSR4_0, }
+        },
+        { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_5_19_FN,     GPSR5_19,
+                GP_5_18_FN,     GPSR5_18,
+                GP_5_17_FN,     GPSR5_17,
+                GP_5_16_FN,     GPSR5_16,
+                GP_5_15_FN,     GPSR5_15,
+                GP_5_14_FN,     GPSR5_14,
+                GP_5_13_FN,     GPSR5_13,
+                GP_5_12_FN,     GPSR5_12,
+                GP_5_11_FN,     GPSR5_11,
+                GP_5_10_FN,     GPSR5_10,
+                GP_5_9_FN,      GPSR5_9,
+                GP_5_8_FN,      GPSR5_8,
+                GP_5_7_FN,      GPSR5_7,
+                GP_5_6_FN,      GPSR5_6,
+                GP_5_5_FN,      GPSR5_5,
+                GP_5_4_FN,      GPSR5_4,
+                GP_5_3_FN,      GPSR5_3,
+                GP_5_2_FN,      GPSR5_2,
+                GP_5_1_FN,      GPSR5_1,
+                GP_5_0_FN,      GPSR5_0, }
+        },
+        { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_6_17_FN,     GPSR6_17,
+                GP_6_16_FN,     GPSR6_16,
+                GP_6_15_FN,     GPSR6_15,
+                GP_6_14_FN,     GPSR6_14,
+                GP_6_13_FN,     GPSR6_13,
+                GP_6_12_FN,     GPSR6_12,
+                GP_6_11_FN,     GPSR6_11,
+                GP_6_10_FN,     GPSR6_10,
+                GP_6_9_FN,      GPSR6_9,
+                GP_6_8_FN,      GPSR6_8,
+                GP_6_7_FN,      GPSR6_7,
+                GP_6_6_FN,      GPSR6_6,
+                GP_6_5_FN,      GPSR6_5,
+                GP_6_4_FN,      GPSR6_4,
+                GP_6_3_FN,      GPSR6_3,
+                GP_6_2_FN,      GPSR6_2,
+                GP_6_1_FN,      GPSR6_1,
+                GP_6_0_FN,      GPSR6_0, }
+        },
+#undef F_
+#undef FM
+
+#define F_(x, y)        x,
+#define FM(x)           FN_##x,
+        { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
+                IP0_31_28
+                IP0_27_24
+                IP0_23_20
+                IP0_19_16
+                IP0_15_12
+                IP0_11_8
+                IP0_7_4
+                IP0_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
+                IP1_31_28
+                IP1_27_24
+                IP1_23_20
+                IP1_19_16
+                IP1_15_12
+                IP1_11_8
+                IP1_7_4
+                IP1_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
+                IP2_31_28
+                IP2_27_24
+                IP2_23_20
+                IP2_19_16
+                IP2_15_12
+                IP2_11_8
+                IP2_7_4
+                IP2_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
+                IP3_31_28
+                IP3_27_24
+                IP3_23_20
+                IP3_19_16
+                IP3_15_12
+                IP3_11_8
+                IP3_7_4
+                IP3_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
+                IP4_31_28
+                IP4_27_24
+                IP4_23_20
+                IP4_19_16
+                IP4_15_12
+                IP4_11_8
+                IP4_7_4
+                IP4_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
+                IP5_31_28
+                IP5_27_24
+                IP5_23_20
+                IP5_19_16
+                IP5_15_12
+                IP5_11_8
+                IP5_7_4
+                IP5_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
+                IP6_31_28
+                IP6_27_24
+                IP6_23_20
+                IP6_19_16
+                IP6_15_12
+                IP6_11_8
+                IP6_7_4
+                IP6_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
+                IP7_31_28
+                IP7_27_24
+                IP7_23_20
+                IP7_19_16
+                IP7_15_12
+                IP7_11_8
+                IP7_7_4
+                IP7_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
+                IP8_31_28
+                IP8_27_24
+                IP8_23_20
+                IP8_19_16
+                IP8_15_12
+                IP8_11_8
+                IP8_7_4
+                IP8_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
+                IP9_31_28
+                IP9_27_24
+                IP9_23_20
+                IP9_19_16
+                IP9_15_12
+                IP9_11_8
+                IP9_7_4
+                IP9_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
+                IP10_31_28
+                IP10_27_24
+                IP10_23_20
+                IP10_19_16
+                IP10_15_12
+                IP10_11_8
+                IP10_7_4
+                IP10_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
+                IP11_31_28
+                IP11_27_24
+                IP11_23_20
+                IP11_19_16
+                IP11_15_12
+                IP11_11_8
+                IP11_7_4
+                IP11_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
+                IP12_31_28
+                IP12_27_24
+                IP12_23_20
+                IP12_19_16
+                IP12_15_12
+                IP12_11_8
+                IP12_7_4
+                IP12_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
+                IP13_31_28
+                IP13_27_24
+                IP13_23_20
+                IP13_19_16
+                IP13_15_12
+                IP13_11_8
+                IP13_7_4
+                IP13_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
+                IP14_31_28
+                IP14_27_24
+                IP14_23_20
+                IP14_19_16
+                IP14_15_12
+                IP14_11_8
+                IP14_7_4
+                IP14_3_0 }
+        },
+        { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
+                IP15_31_28
+                IP15_27_24
+                IP15_23_20
+                IP15_19_16
+                IP15_15_12
+                IP15_11_8
+                IP15_7_4
+                IP15_3_0 }
+        },
+#undef F_
+#undef FM
+
+#define F_(x, y)        x,
+#define FM(x)           FN_##x,
+        { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
+                             1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1,
+                             1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) {
+                /* RESERVED 31 */
+                0, 0,
+                MOD_SEL0_30_29
+                MOD_SEL0_28
+                MOD_SEL0_27_26
+                MOD_SEL0_25
+                MOD_SEL0_24
+                MOD_SEL0_23
+                MOD_SEL0_22
+                MOD_SEL0_21_20
+                MOD_SEL0_19_18_17
+                MOD_SEL0_16
+                MOD_SEL0_15
+                MOD_SEL0_14
+                MOD_SEL0_13_12
+                MOD_SEL0_11_10
+                MOD_SEL0_9
+                MOD_SEL0_8
+                MOD_SEL0_7
+                MOD_SEL0_6_5
+                MOD_SEL0_4
+                MOD_SEL0_3
+                MOD_SEL0_2
+                MOD_SEL0_1_0 }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
+                             1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
+                             1, 2, 2, 2, 1, 1, 2, 1, 4) {
+                MOD_SEL1_31
+                MOD_SEL1_30
+                MOD_SEL1_29
+                MOD_SEL1_28
+                /* RESERVED 27 */
+                0, 0,
+                MOD_SEL1_26
+                MOD_SEL1_25
+                MOD_SEL1_24_23_22
+                MOD_SEL1_21_20_19
+                MOD_SEL1_18
+                MOD_SEL1_17
+                MOD_SEL1_16
+                MOD_SEL1_15
+                MOD_SEL1_14_13
+                MOD_SEL1_12_11
+                MOD_SEL1_10_9
+                MOD_SEL1_8
+                MOD_SEL1_7
+                MOD_SEL1_6_5
+                MOD_SEL1_4
+                /* RESERVED 3, 2, 1, 0  */
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { },
+};
+
+static const struct pinmux_bias_reg pinmux_bias_regs[] = {
+        { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
+                 [0] = RCAR_GP_PIN(2, 23),      /* RD# */
+                 [1] = RCAR_GP_PIN(2, 22),      /* BS# */
+                 [2] = RCAR_GP_PIN(2, 21),      /* AVB_PHY_INT */
+                 [3] = PIN_NUMBER('P', 5),      /* AVB_MDC */
+                 [4] = PIN_NUMBER('P', 4),      /* AVB_MDIO */
+                 [5] = RCAR_GP_PIN(2, 20),      /* AVB_TXCREFCLK */
+                 [6] = PIN_NUMBER('N', 6),      /* AVB_TD3 */
+                 [7] = PIN_NUMBER('N', 5),      /* AVB_TD2 */
+                 [8] = PIN_NUMBER('N', 3),      /* AVB_TD1 */
+                 [9] = PIN_NUMBER('N', 2),      /* AVB_TD0 */
+                [10] = PIN_NUMBER('N', 1),      /* AVB_TXC */
+                [11] = PIN_NUMBER('P', 3),      /* AVB_TX_CTL */
+                [12] = RCAR_GP_PIN(2, 19),      /* AVB_RD3 */
+                [13] = RCAR_GP_PIN(2, 18),      /* AVB_RD2 */
+                [14] = RCAR_GP_PIN(2, 17),      /* AVB_RD1 */
+                [15] = RCAR_GP_PIN(2, 16),      /* AVB_RD0 */
+                [16] = RCAR_GP_PIN(2, 15),      /* AVB_RXC */
+                [17] = RCAR_GP_PIN(2, 14),      /* AVB_RX_CTL */
+                [18] = RCAR_GP_PIN(2, 13),      /* RPC_RESET# */
+                [19] = RCAR_GP_PIN(2, 12),      /* RPC_INT# */
+                [20] = RCAR_GP_PIN(2, 11),      /* QSPI1_SSL */
+                [21] = RCAR_GP_PIN(2, 10),      /* QSPI1_IO3 */
+                [22] = RCAR_GP_PIN(2,  9),      /* QSPI1_IO2 */
+                [23] = RCAR_GP_PIN(2,  8),      /* QSPI1_MISO/IO1 */
+                [24] = RCAR_GP_PIN(2,  7),      /* QSPI1_MOSI/IO0 */
+                [25] = RCAR_GP_PIN(2,  6),      /* QSPI1_SPCLK */
+                [26] = RCAR_GP_PIN(2,  5),      /* QSPI0_SSL */
+                [27] = RCAR_GP_PIN(2,  4),      /* QSPI0_IO3 */
+                [28] = RCAR_GP_PIN(2,  3),      /* QSPI0_IO2 */
+                [29] = RCAR_GP_PIN(2,  2),      /* QSPI0_MISO/IO1 */
+                [30] = RCAR_GP_PIN(2,  1),      /* QSPI0_MOSI/IO0 */
+                [31] = RCAR_GP_PIN(2,  0),      /* QSPI0_SPCLK */
+        } },
+        { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
+                 [0] = RCAR_GP_PIN(0,  4),      /* D4 */
+                 [1] = RCAR_GP_PIN(0,  3),      /* D3 */
+                 [2] = RCAR_GP_PIN(0,  2),      /* D2 */
+                 [3] = RCAR_GP_PIN(0,  1),      /* D1 */
+                 [4] = RCAR_GP_PIN(0,  0),      /* D0 */
+                 [5] = RCAR_GP_PIN(1, 22),      /* WE0# */
+                 [6] = RCAR_GP_PIN(1, 21),      /* CS0# */
+                 [7] = RCAR_GP_PIN(1, 20),      /* CLKOUT */
+                 [8] = RCAR_GP_PIN(1, 19),      /* A19 */
+                 [9] = RCAR_GP_PIN(1, 18),      /* A18 */
+                [10] = RCAR_GP_PIN(1, 17),      /* A17 */
+                [11] = RCAR_GP_PIN(1, 16),      /* A16 */
+                [12] = RCAR_GP_PIN(1, 15),      /* A15 */
+                [13] = RCAR_GP_PIN(1, 14),      /* A14 */
+                [14] = RCAR_GP_PIN(1, 13),      /* A13 */
+                [15] = RCAR_GP_PIN(1, 12),      /* A12 */
+                [16] = RCAR_GP_PIN(1, 11),      /* A11 */
+                [17] = RCAR_GP_PIN(1, 10),      /* A10 */
+                [18] = RCAR_GP_PIN(1,  9),      /* A9 */
+                [19] = RCAR_GP_PIN(1,  8),      /* A8 */
+                [20] = RCAR_GP_PIN(1,  7),      /* A7 */
+                [21] = RCAR_GP_PIN(1,  6),      /* A6 */
+                [22] = RCAR_GP_PIN(1,  5),      /* A5 */
+                [23] = RCAR_GP_PIN(1,  4),      /* A4 */
+                [24] = RCAR_GP_PIN(1,  3),      /* A3 */
+                [25] = RCAR_GP_PIN(1,  2),      /* A2 */
+                [26] = RCAR_GP_PIN(1,  1),      /* A1 */
+                [27] = RCAR_GP_PIN(1,  0),      /* A0 */
+                [28] = PIN_NONE,
+                [29] = PIN_NONE,
+                [30] = RCAR_GP_PIN(2, 25),      /* PUEN_EX_WAIT0 */
+                [31] = RCAR_GP_PIN(2, 24),      /* PUEN_RD/WR# */
+        } },
+        { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
+                 [0] = RCAR_GP_PIN(3,  1),      /* SD0_CMD */
+                 [1] = RCAR_GP_PIN(3,  0),      /* SD0_CLK */
+                 [2] = PIN_NUMBER('H', 1),      /* ASEBRK */
+                 [3] = PIN_NONE,
+                 [4] = PIN_NUMBER('G', 2),      /* TDI */
+                 [5] = PIN_NUMBER('F', 3),      /* TMS */
+                 [6] = PIN_NUMBER('F', 4),      /* TCK */
+                 [7] = PIN_NUMBER('F', 1),      /* TRST# */
+                 [8] = PIN_NONE,
+                 [9] = PIN_NONE,
+                [10] = PIN_NONE,
+                [11] = PIN_NONE,
+                [12] = PIN_NONE,
+                [13] = PIN_NONE,
+                [14] = PIN_NONE,
+                [15] = PIN_NUMBER('G', 3),      /* FSCLKST# */
+                [16] = RCAR_GP_PIN(0, 17),      /* SDA4 */
+                [17] = RCAR_GP_PIN(0, 16),      /* SCL4 */
+                [18] = PIN_NONE,
+                [19] = PIN_NONE,
+                [20] = PIN_A_NUMBER('D', 3),    /* PRESETOUT# */
+                [21] = RCAR_GP_PIN(0, 15),      /* D15 */
+                [22] = RCAR_GP_PIN(0, 14),      /* D14 */
+                [23] = RCAR_GP_PIN(0, 13),      /* D13 */
+                [24] = RCAR_GP_PIN(0, 12),      /* D12 */
+                [25] = RCAR_GP_PIN(0, 11),      /* D11 */
+                [26] = RCAR_GP_PIN(0, 10),      /* D10 */
+                [27] = RCAR_GP_PIN(0,  9),      /* D9 */
+                [28] = RCAR_GP_PIN(0,  8),      /* D8 */
+                [29] = RCAR_GP_PIN(0,  7),      /* D7 */
+                [30] = RCAR_GP_PIN(0,  6),      /* D6 */
+                [31] = RCAR_GP_PIN(0,  5),      /* D5 */
+        } },
+        { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
+                 [0] = RCAR_GP_PIN(5,  0),      /* SCK0_A */
+                 [1] = RCAR_GP_PIN(5,  4),      /* RTS0#/TANS_A */
+                 [2] = RCAR_GP_PIN(5,  3),      /* CTS0#_A */
+                 [3] = RCAR_GP_PIN(5,  2),      /* TX0_A */
+                 [4] = RCAR_GP_PIN(5,  1),      /* RX0_A */
+                 [5] = PIN_NONE,
+                 [6] = PIN_NONE,
+                 [7] = RCAR_GP_PIN(3, 15),      /* SD1_WP */
+                 [8] = RCAR_GP_PIN(3, 14),      /* SD1_CD */
+                 [9] = RCAR_GP_PIN(3, 13),      /* SD0_WP */
+                [10] = RCAR_GP_PIN(3, 12),      /* SD0_CD */
+                [11] = RCAR_GP_PIN(4, 10),      /* SD3_DS */
+                [12] = RCAR_GP_PIN(4,  9),      /* SD3_DAT7 */
+                [13] = RCAR_GP_PIN(4,  8),      /* SD3_DAT6 */
+                [14] = RCAR_GP_PIN(4,  7),      /* SD3_DAT5 */
+                [15] = RCAR_GP_PIN(4,  6),      /* SD3_DAT4 */
+                [16] = RCAR_GP_PIN(4,  5),      /* SD3_DAT3 */
+                [17] = RCAR_GP_PIN(4,  4),      /* SD3_DAT2 */
+                [18] = RCAR_GP_PIN(4,  3),      /* SD3_DAT1 */
+                [19] = RCAR_GP_PIN(4,  2),      /* SD3_DAT0 */
+                [20] = RCAR_GP_PIN(4,  1),      /* SD3_CMD */
+                [21] = RCAR_GP_PIN(4,  0),      /* SD3_CLK */
+                [22] = RCAR_GP_PIN(3, 11),      /* SD1_DAT3 */
+                [23] = RCAR_GP_PIN(3, 10),      /* SD1_DAT2 */
+                [24] = RCAR_GP_PIN(3,  9),      /* SD1_DAT1 */
+                [25] = RCAR_GP_PIN(3,  8),      /* SD1_DAT0 */
+                [26] = RCAR_GP_PIN(3,  7),      /* SD1_CMD */
+                [27] = RCAR_GP_PIN(3,  6),      /* SD1_CLK */
+                [28] = RCAR_GP_PIN(3,  5),      /* SD0_DAT3 */
+                [29] = RCAR_GP_PIN(3,  4),      /* SD0_DAT2 */
+                [30] = RCAR_GP_PIN(3,  3),      /* SD0_DAT1 */
+                [31] = RCAR_GP_PIN(3,  2),      /* SD0_DAT0 */
+        } },
+        { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
+                 [0] = RCAR_GP_PIN(6,  8),      /* AUDIO_CLKA */
+                 [1] = RCAR_GP_PIN(6, 16),      /* SSI_SDATA6 */
+                 [2] = RCAR_GP_PIN(6, 15),      /* SSI_WS6 */
+                 [3] = RCAR_GP_PIN(6, 14),      /* SSI_SCK6 */
+                 [4] = RCAR_GP_PIN(6, 13),      /* SSI_SDATA5 */
+                 [5] = RCAR_GP_PIN(6, 12),      /* SSI_WS5 */
+                 [6] = RCAR_GP_PIN(6, 11),      /* SSI_SCK5 */
+                 [7] = RCAR_GP_PIN(6, 10),      /* SSI_SDATA4 */
+                 [8] = RCAR_GP_PIN(6,  7),      /* SSI_SDATA3 */
+                 [9] = RCAR_GP_PIN(6,  6),      /* SSI_WS349 */
+                [10] = RCAR_GP_PIN(6,  5),      /* SSI_SCK349 */
+                [11] = RCAR_GP_PIN(6,  4),      /* SSI_SDATA2 */
+                [12] = RCAR_GP_PIN(6,  3),      /* SSI_SDATA1 */
+                [13] = RCAR_GP_PIN(6,  2),      /* SSI_SDATA0 */
+                [14] = RCAR_GP_PIN(6,  1),      /* SSI_WS01239 */
+                [15] = RCAR_GP_PIN(6,  0),      /* SSI_SCK01239 */
+                [16] = PIN_NUMBER('T', 21),     /* MLB_REF */
+                [17] = RCAR_GP_PIN(5, 19),      /* MLB_DAT */
+                [18] = RCAR_GP_PIN(5, 18),      /* MLB_SIG */
+                [19] = RCAR_GP_PIN(5, 17),      /* MLB_CLK */
+                [20] = RCAR_GP_PIN(5, 16),      /* SSI_SDATA9 */
+                [21] = RCAR_GP_PIN(5, 15),      /* MSIOF0_SS2 */
+                [22] = RCAR_GP_PIN(5, 14),      /* MSIOF0_SS1 */
+                [23] = RCAR_GP_PIN(5, 13),      /* MSIOF0_SYNC */
+                [24] = RCAR_GP_PIN(5, 12),      /* MSIOF0_TXD */
+                [25] = RCAR_GP_PIN(5, 11),      /* MSIOF0_RXD */
+                [26] = RCAR_GP_PIN(5, 10),      /* MSIOF0_SCK */
+                [27] = RCAR_GP_PIN(5,  9),      /* RX2_A */
+                [28] = RCAR_GP_PIN(5,  8),      /* TX2_A */
+                [29] = RCAR_GP_PIN(5,  7),      /* SCK2_A */
+                [30] = RCAR_GP_PIN(5,  6),      /* TX1 */
+                [31] = RCAR_GP_PIN(5,  5),      /* RX1 */
+        } },
+        { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
+                 [0] = PIN_NONE,
+                 [1] = PIN_NONE,
+                 [2] = PIN_NONE,
+                 [3] = PIN_NONE,
+                 [4] = PIN_NONE,
+                 [5] = PIN_NONE,
+                 [6] = PIN_NONE,
+                 [7] = PIN_NONE,
+                 [8] = PIN_NONE,
+                 [9] = PIN_NONE,
+                [10] = PIN_NONE,
+                [11] = PIN_NONE,
+                [12] = PIN_NONE,
+                [13] = PIN_NONE,
+                [14] = PIN_NONE,
+                [15] = PIN_NONE,
+                [16] = PIN_NONE,
+                [17] = PIN_NONE,
+                [18] = PIN_NONE,
+                [19] = PIN_NONE,
+                [20] = PIN_NONE,
+                [21] = PIN_NONE,
+                [22] = PIN_NONE,
+                [23] = PIN_NONE,
+                [24] = PIN_NONE,
+                [25] = PIN_NONE,
+                [26] = PIN_NONE,
+                [27] = PIN_NONE,
+                [28] = PIN_NONE,
+                [29] = PIN_NONE,
+                [30] = RCAR_GP_PIN(6,  9),      /* PUEN_USB30_OVC */
+                [31] = RCAR_GP_PIN(6, 17),      /* PUEN_USB30_PWEN */
+        } },
+        { /* sentinel */ },
+};
+
+static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
+                                             unsigned int pin)
+{
+        const struct pinmux_bias_reg *reg;
+        unsigned int bit;
+
+        reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
+        if (!reg)
+                return PIN_CONFIG_BIAS_DISABLE;
+
+        if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
+                return PIN_CONFIG_BIAS_DISABLE;
+        else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
+                return PIN_CONFIG_BIAS_PULL_UP;
+        else
+                return PIN_CONFIG_BIAS_PULL_DOWN;
+}
+
+static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+                                     unsigned int bias)
+{
+        const struct pinmux_bias_reg *reg;
+        u32 enable, updown;
+        unsigned int bit;
+
+        reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
+        if (!reg)
+                return;
+
+        enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
+        if (bias != PIN_CONFIG_BIAS_DISABLE)
+                enable |= BIT(bit);
+
+        updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
+        if (bias == PIN_CONFIG_BIAS_PULL_UP)
+                updown |= BIT(bit);
+
+        sh_pfc_write(pfc, reg->pud, updown);
+        sh_pfc_write(pfc, reg->puen, enable);
+}
+
+static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
+        .get_bias = r8a77990_pinmux_get_bias,
+        .set_bias = r8a77990_pinmux_set_bias,
+};
+
+const struct sh_pfc_soc_info r8a77990_pinmux_info = {
+        .name = "r8a77990_pfc",
+        .ops = &r8a77990_pinmux_ops,
+        .unlock_reg = 0xe6060000, /* PMMR */
+
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .cfg_regs = pinmux_config_regs,
+        .bias_regs = pinmux_bias_regs,
+
+        .pinmux_data = pinmux_data,
+        .pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 7fad897cd9f5..3d0b31636d6d 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -274,6 +274,7 @@ extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
+extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
@@ -287,6 +288,7 @@ extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
+extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
 extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
@@ -415,9 +417,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
         PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg)
 #define PORT_GP_10(bank, fn, sfx)       PORT_GP_CFG_10(bank, fn, sfx, 0)
 
-#define PORT_GP_CFG_12(bank, fn, sfx, cfg)                              \
+#define PORT_GP_CFG_11(bank, fn, sfx, cfg)                              \
         PORT_GP_CFG_10(bank, fn, sfx, cfg),                             \
-        PORT_GP_CFG_1(bank, 10, fn, sfx, cfg),                          \
+        PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
+#define PORT_GP_11(bank, fn, sfx)       PORT_GP_CFG_11(bank, fn, sfx, 0)
+
+#define PORT_GP_CFG_12(bank, fn, sfx, cfg)                              \
+        PORT_GP_CFG_11(bank, fn, sfx, cfg),                             \
         PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
 #define PORT_GP_12(bank, fn, sfx)       PORT_GP_CFG_12(bank, fn, sfx, 0)
 
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 5de1f63b07bb..95282cda6cee 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -81,4 +81,8 @@ config PINCTRL_SUN50I_H6
         def_bool ARM64 && ARCH_SUNXI
         select PINCTRL_SUNXI
 
+config PINCTRL_SUN50I_H6_R
+        def_bool ARM64 && ARCH_SUNXI
+        select PINCTRL_SUNXI
+
 endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 3c4aec6611e9..adb8443aa55c 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -19,5 +19,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_H3_R)	+= pinctrl-sun8i-h3-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_V3S)         += pinctrl-sun8i-v3s.o
 obj-$(CONFIG_PINCTRL_SUN50I_H5)         += pinctrl-sun50i-h5.o
 obj-$(CONFIG_PINCTRL_SUN50I_H6)         += pinctrl-sun50i-h6.o
+obj-$(CONFIG_PINCTRL_SUN50I_H6_R)       += pinctrl-sun50i-h6-r.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)         += pinctrl-sun9i-a80.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80_R)       += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
new file mode 100644
index 000000000000..4557e18d5989
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner H6 R_PIO pin controller driver
+ *
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on pinctrl-sun6i-a31-r.c, which is:
+ *   Copyright (C) 2014 Boris Brezillon
+ *   Boris Brezillon <boris.brezillon@free-electrons.com>
+ *   Copyright (C) 2014 Maxime Ripard
+ *   Maxime Ripard <maxime.ripard@free-electrons.com>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/reset.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun50i_h6_r_pins[] = {
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x3, "s_i2c"),         /* SCK */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x3, "s_i2c"),         /* SDA */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_uart"),        /* TX */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_uart"),        /* RX */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_jtag"),        /* MS */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PL_EINT4 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_jtag"),        /* CK */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PL_EINT5 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_jtag"),        /* DO */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PL_EINT6 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_jtag"),        /* DI */
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PL_EINT7 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_pwm"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PL_EINT8 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_cir_rx"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PL_EINT9 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION(0x2, "s_w1"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
+        /* Hole */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),  /* PM_EINT0 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),  /* PM_EINT1 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2),   /* PM_EINT2 */
+                  SUNXI_FUNCTION(0x3, "1wire")),
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),  /* PM_EINT3 */
+        SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
+                  SUNXI_FUNCTION(0x0, "gpio_in"),
+                  SUNXI_FUNCTION(0x1, "gpio_out"),
+                  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),  /* PM_EINT4 */
+};
+
+static const struct sunxi_pinctrl_desc sun50i_h6_r_pinctrl_data = {
+        .pins = sun50i_h6_r_pins,
+        .npins = ARRAY_SIZE(sun50i_h6_r_pins),
+        .pin_base = PL_BASE,
+        .irq_banks = 2,
+};
+
+static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev)
+{
+        return sunxi_pinctrl_init(pdev,
+                                  &sun50i_h6_r_pinctrl_data);
+}
+
+static const struct of_device_id sun50i_h6_r_pinctrl_match[] = {
+        { .compatible = "allwinner,sun50i-h6-r-pinctrl", },
+        {}
+};
+
+static struct platform_driver sun50i_h6_r_pinctrl_driver = {
+        .probe  = sun50i_h6_r_pinctrl_probe,
+        .driver = {
+                .name           = "sun50i-h6-r-pinctrl",
+                .of_match_table = sun50i_h6_r_pinctrl_match,
+        },
+};
+builtin_platform_driver(sun50i_h6_r_pinctrl_driver);
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 72c718e66ebb..49c7c1499bc3 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -33,17 +33,6 @@
 #include "../pinctrl-utils.h"
 #include "pinctrl-tegra.h"
 
-struct tegra_pmx {
-        struct device *dev;
-        struct pinctrl_dev *pctl;
-
-        const struct tegra_pinctrl_soc_data *soc;
-        const char **group_pins;
-
-        int nbanks;
-        void __iomem **regs;
-};
-
 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
 {
         return readl(pmx->regs[bank] + reg);
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index 33b17cb1471e..aa33c20766c4 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -16,6 +16,17 @@
 #ifndef __PINMUX_TEGRA_H__
 #define __PINMUX_TEGRA_H__
 
+struct tegra_pmx {
+        struct device *dev;
+        struct pinctrl_dev *pctl;
+
+        const struct tegra_pinctrl_soc_data *soc;
+        const char **group_pins;
+
+        int nbanks;
+        void __iomem **regs;
+};
+
 enum tegra_pinconf_param {
         /* argument: tegra_pinconf_pull */
         TEGRA_PINCONF_PARAM_PULL,
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c
index 7e38ee9bae78..b6dd939d32cc 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra20.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c
@@ -19,6 +19,7 @@
  * more details.
  */
 
+#include <linux/clk-provider.h>
 #include <linux/init.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
@@ -2231,9 +2232,36 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
         .drvtype_in_mux = false,
 };
 
+static const char *cdev1_parents[] = {
+        "dev1_osc_div", "pll_a_out0", "pll_m_out1", "audio",
+};
+
+static const char *cdev2_parents[] = {
+        "dev2_osc_div", "hclk", "pclk", "pll_p_out4",
+};
+
+static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev)
+{
+        struct tegra_pmx *pmx = platform_get_drvdata(pdev);
+
+        clk_register_mux(NULL, "cdev1_mux", cdev1_parents, 4, 0,
+                         pmx->regs[1] + 0x8, 2, 2, CLK_MUX_READ_ONLY, NULL);
+
+        clk_register_mux(NULL, "cdev2_mux", cdev2_parents, 4, 0,
+                         pmx->regs[1] + 0x8, 4, 2, CLK_MUX_READ_ONLY, NULL);
+}
+
 static int tegra20_pinctrl_probe(struct platform_device *pdev)
 {
-        return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
+        int err;
+
+        err = tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
+        if (err)
+                return err;
+
+        tegra20_pinctrl_register_clock_muxes(pdev);
+
+        return 0;
 }
 
 static const struct of_device_id tegra20_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index 0976fbfecd50..58825f68b58b 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -481,6 +481,31 @@ static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
 static const unsigned ether_rmii_pins[] = {6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
                                            16, 17};
 static const int ether_rmii_muxvals[] = {4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4};
+static const unsigned hscin0_ci_pins[] = {102, 103, 104, 105, 106, 107, 108,
+                                          109, 110, 111, 112};
+static const int hscin0_ci_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
+static const unsigned hscin0_p_pins[] = {102, 103, 104, 105, 106, 107, 108, 109,
+                                         110, 111, 112};
+static const int hscin0_p_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned hscin0_s_pins[] = {116, 117, 118, 119};
+static const int hscin0_s_muxvals[] = {3, 3, 3, 3};
+static const unsigned hscin1_p_pins[] = {124, 125, 126, 127, 128, 129, 130, 131,
+                                         132, 133, 134};
+static const int hscin1_p_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned hscin1_s_pins[] = {120, 121, 122, 123};
+static const int hscin1_s_muxvals[] = {3, 3, 3, 3};
+static const unsigned hscin2_s_pins[] = {124, 125, 126, 127};
+static const int hscin2_s_muxvals[] = {3, 3, 3, 3};
+static const unsigned hscout0_ci_pins[] = {113, 114, 115, 116, 117, 118, 119,
+                                           120, 121, 122, 123};
+static const int hscout0_ci_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
+static const unsigned hscout0_p_pins[] = {113, 114, 115, 116, 117, 118, 119,
+                                          120, 121, 122, 123};
+static const int hscout0_p_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned hscout0_s_pins[] = {116, 117, 118, 119};
+static const int hscout0_s_muxvals[] = {4, 4, 4, 4};
+static const unsigned hscout1_s_pins[] = {120, 121, 122, 123};
+static const int hscout1_s_muxvals[] = {4, 4, 4, 4};
 static const unsigned i2c0_pins[] = {63, 64};
 static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {65, 66};
@@ -556,6 +581,16 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
         UNIPHIER_PINCTRL_GROUP(emmc),
         UNIPHIER_PINCTRL_GROUP(emmc_dat8),
         UNIPHIER_PINCTRL_GROUP(ether_rmii),
+        UNIPHIER_PINCTRL_GROUP(hscin0_ci),
+        UNIPHIER_PINCTRL_GROUP(hscin0_p),
+        UNIPHIER_PINCTRL_GROUP(hscin0_s),
+        UNIPHIER_PINCTRL_GROUP(hscin1_p),
+        UNIPHIER_PINCTRL_GROUP(hscin1_s),
+        UNIPHIER_PINCTRL_GROUP(hscin2_s),
+        UNIPHIER_PINCTRL_GROUP(hscout0_ci),
+        UNIPHIER_PINCTRL_GROUP(hscout0_p),
+        UNIPHIER_PINCTRL_GROUP(hscout0_s),
+        UNIPHIER_PINCTRL_GROUP(hscout1_s),
         UNIPHIER_PINCTRL_GROUP(i2c0),
         UNIPHIER_PINCTRL_GROUP(i2c1),
         UNIPHIER_PINCTRL_GROUP(i2c3),
@@ -583,6 +618,15 @@ static const char * const aout1_groups[] = {"aout1"};
 static const char * const aoutiec1_groups[] = {"aoutiec1"};
 static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
 static const char * const ether_rmii_groups[] = {"ether_rmii"};
+static const char * const hscin0_groups[] = {"hscin0_ci",
+                                             "hscin0_p",
+                                             "hscin0_s"};
+static const char * const hscin1_groups[] = {"hscin1_p", "hscin1_s"};
+static const char * const hscin2_groups[] = {"hscin2_s"};
+static const char * const hscout0_groups[] = {"hscout0_ci",
+                                              "hscout0_p",
+                                              "hscout0_s"};
+static const char * const hscout1_groups[] = {"hscout1_s"};
 static const char * const i2c0_groups[] = {"i2c0"};
 static const char * const i2c1_groups[] = {"i2c1"};
 static const char * const i2c3_groups[] = {"i2c3"};
@@ -603,6 +647,11 @@ static const struct uniphier_pinmux_function uniphier_ld11_functions[] = {
         UNIPHIER_PINMUX_FUNCTION(aoutiec1),
         UNIPHIER_PINMUX_FUNCTION(emmc),
         UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+        UNIPHIER_PINMUX_FUNCTION(hscin0),
+        UNIPHIER_PINMUX_FUNCTION(hscin1),
+        UNIPHIER_PINMUX_FUNCTION(hscin2),
+        UNIPHIER_PINMUX_FUNCTION(hscout0),
+        UNIPHIER_PINMUX_FUNCTION(hscout1),
         UNIPHIER_PINMUX_FUNCTION(i2c0),
         UNIPHIER_PINMUX_FUNCTION(i2c1),
         UNIPHIER_PINMUX_FUNCTION(i2c3),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index bf8f0c3bea5e..9f449b35e300 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -566,6 +566,33 @@ static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 static const unsigned ether_rmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 39,
                                            41, 42, 45};
 static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1};
+static const unsigned hscin0_ci_pins[] = {102, 103, 104, 105, 106, 107, 108,
+                                          109, 110, 111, 112};
+static const int hscin0_ci_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
+static const unsigned hscin0_p_pins[] = {102, 103, 104, 105, 106, 107, 108, 109,
+                                         110, 111, 112};
+static const int hscin0_p_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned hscin0_s_pins[] = {116, 117, 118, 119};
+static const int hscin0_s_muxvals[] = {3, 3, 3, 3};
+static const unsigned hscin1_p_pins[] = {124, 125, 126, 127, 128, 129, 130, 131,
+                                         132, 133, 134};
+static const int hscin1_p_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned hscin1_s_pins[] = {120, 121, 122, 123};
+static const int hscin1_s_muxvals[] = {3, 3, 3, 3};
+static const unsigned hscin2_s_pins[] = {124, 125, 126, 127};
+static const int hscin2_s_muxvals[] = {3, 3, 3, 3};
+static const unsigned hscin3_s_pins[] = {129, 130, 131, 132};
+static const int hscin3_s_muxvals[] = {3, 3, 3, 3};
+static const unsigned hscout0_ci_pins[] = {113, 114, 115, 116, 117, 118, 119,
+                                           120, 121, 122, 123};
+static const int hscout0_ci_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
+static const unsigned hscout0_p_pins[] = {113, 114, 115, 116, 117, 118, 119,
+                                          120, 121, 122, 123};
+static const int hscout0_p_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned hscout0_s_pins[] = {116, 117, 118, 119};
+static const int hscout0_s_muxvals[] = {4, 4, 4, 4};
+static const unsigned hscout1_s_pins[] = {120, 121, 122, 123};
+static const int hscout1_s_muxvals[] = {4, 4, 4, 4};
 static const unsigned i2c0_pins[] = {63, 64};
 static const int i2c0_muxvals[] = {0, 0};
 static const unsigned i2c1_pins[] = {65, 66};
@@ -641,6 +668,17 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
         UNIPHIER_PINCTRL_GROUP(emmc_dat8),
         UNIPHIER_PINCTRL_GROUP(ether_rgmii),
         UNIPHIER_PINCTRL_GROUP(ether_rmii),
+        UNIPHIER_PINCTRL_GROUP(hscin0_ci),
+        UNIPHIER_PINCTRL_GROUP(hscin0_p),
+        UNIPHIER_PINCTRL_GROUP(hscin0_s),
+        UNIPHIER_PINCTRL_GROUP(hscin1_p),
+        UNIPHIER_PINCTRL_GROUP(hscin1_s),
+        UNIPHIER_PINCTRL_GROUP(hscin2_s),
+        UNIPHIER_PINCTRL_GROUP(hscin3_s),
+        UNIPHIER_PINCTRL_GROUP(hscout0_ci),
+        UNIPHIER_PINCTRL_GROUP(hscout0_p),
+        UNIPHIER_PINCTRL_GROUP(hscout0_s),
+        UNIPHIER_PINCTRL_GROUP(hscout1_s),
         UNIPHIER_PINCTRL_GROUP(i2c0),
         UNIPHIER_PINCTRL_GROUP(i2c1),
         UNIPHIER_PINCTRL_GROUP(i2c3),
@@ -668,6 +706,16 @@ static const char * const aoutiec1_groups[] = {"aoutiec1"};
 static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
 static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
 static const char * const ether_rmii_groups[] = {"ether_rmii"};
+static const char * const hscin0_groups[] = {"hscin0_ci",
+                                             "hscin0_p",
+                                             "hscin0_s"};
+static const char * const hscin1_groups[] = {"hscin1_p", "hscin1_s"};
+static const char * const hscin2_groups[] = {"hscin2_s"};
+static const char * const hscin3_groups[] = {"hscin3_s"};
+static const char * const hscout0_groups[] = {"hscout0_ci",
+                                              "hscout0_p",
+                                              "hscout0_s"};
+static const char * const hscout1_groups[] = {"hscout1_s"};
 static const char * const i2c0_groups[] = {"i2c0"};
 static const char * const i2c1_groups[] = {"i2c1"};
 static const char * const i2c3_groups[] = {"i2c3"};
@@ -691,6 +739,12 @@ static const struct uniphier_pinmux_function uniphier_ld20_functions[] = {
         UNIPHIER_PINMUX_FUNCTION(emmc),
         UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
         UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+        UNIPHIER_PINMUX_FUNCTION(hscin0),
+        UNIPHIER_PINMUX_FUNCTION(hscin1),
+        UNIPHIER_PINMUX_FUNCTION(hscin2),
+        UNIPHIER_PINMUX_FUNCTION(hscin3),
+        UNIPHIER_PINMUX_FUNCTION(hscout0),
+        UNIPHIER_PINMUX_FUNCTION(hscout1),
         UNIPHIER_PINMUX_FUNCTION(i2c0),
         UNIPHIER_PINMUX_FUNCTION(i2c1),
         UNIPHIER_PINMUX_FUNCTION(i2c3),