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authorStefan Wahren <stefan.wahren@i2se.com>2017-12-11 15:39:11 -0500
committerMarc Zyngier <marc.zyngier@arm.com>2018-01-04 06:12:39 -0500
commitad83c7cb2f37fad01f53a8748c6f8067acb2968d (patch)
treeeef0dc8f968b64eb260e4c8e2360271c133153a3 /drivers
parent36464580e658019ac7be26a08c4679bee0454d2c (diff)
irqchip/irq-bcm2836: Add support for DT interrupt polarity
In order to properly define the polarity of the per-cpu interrupts, we need to support for a second property cell. But this must be optional to keep backward compatibility with old DT blobs. Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/irqchip/irq-bcm2836.c46
1 files changed, 28 insertions, 18 deletions
diff --git a/drivers/irqchip/irq-bcm2836.c b/drivers/irqchip/irq-bcm2836.c
index 667b9e14b032..dfe4a460340b 100644
--- a/drivers/irqchip/irq-bcm2836.c
+++ b/drivers/irqchip/irq-bcm2836.c
@@ -98,13 +98,35 @@ static struct irq_chip bcm2836_arm_irqchip_gpu = {
98 .irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq, 98 .irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
99}; 99};
100 100
101static void bcm2836_arm_irqchip_register_irq(int hwirq, struct irq_chip *chip) 101static int bcm2836_map(struct irq_domain *d, unsigned int irq,
102{ 102 irq_hw_number_t hw)
103 int irq = irq_create_mapping(intc.domain, hwirq); 103{
104 struct irq_chip *chip;
105
106 switch (hw) {
107 case LOCAL_IRQ_CNTPSIRQ:
108 case LOCAL_IRQ_CNTPNSIRQ:
109 case LOCAL_IRQ_CNTHPIRQ:
110 case LOCAL_IRQ_CNTVIRQ:
111 chip = &bcm2836_arm_irqchip_timer;
112 break;
113 case LOCAL_IRQ_GPU_FAST:
114 chip = &bcm2836_arm_irqchip_gpu;
115 break;
116 case LOCAL_IRQ_PMU_FAST:
117 chip = &bcm2836_arm_irqchip_pmu;
118 break;
119 default:
120 pr_warn_once("Unexpected hw irq: %lu\n", hw);
121 return -EINVAL;
122 }
104 123
105 irq_set_percpu_devid(irq); 124 irq_set_percpu_devid(irq);
106 irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq); 125 irq_domain_set_info(d, irq, hw, chip, d->host_data,
126 handle_percpu_devid_irq, NULL, NULL);
107 irq_set_status_flags(irq, IRQ_NOAUTOEN); 127 irq_set_status_flags(irq, IRQ_NOAUTOEN);
128
129 return 0;
108} 130}
109 131
110static void 132static void
@@ -165,7 +187,8 @@ static int bcm2836_cpu_dying(unsigned int cpu)
165#endif 187#endif
166 188
167static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = { 189static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
168 .xlate = irq_domain_xlate_onecell 190 .xlate = irq_domain_xlate_onetwocell,
191 .map = bcm2836_map,
169}; 192};
170 193
171static void 194static void
@@ -218,19 +241,6 @@ static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
218 if (!intc.domain) 241 if (!intc.domain)
219 panic("%pOF: unable to create IRQ domain\n", node); 242 panic("%pOF: unable to create IRQ domain\n", node);
220 243
221 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPSIRQ,
222 &bcm2836_arm_irqchip_timer);
223 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTPNSIRQ,
224 &bcm2836_arm_irqchip_timer);
225 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTHPIRQ,
226 &bcm2836_arm_irqchip_timer);
227 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_CNTVIRQ,
228 &bcm2836_arm_irqchip_timer);
229 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_GPU_FAST,
230 &bcm2836_arm_irqchip_gpu);
231 bcm2836_arm_irqchip_register_irq(LOCAL_IRQ_PMU_FAST,
232 &bcm2836_arm_irqchip_pmu);
233
234 bcm2836_arm_irqchip_smp_init(); 244 bcm2836_arm_irqchip_smp_init();
235 245
236 set_handle_irq(bcm2836_arm_irqchip_handle_irq); 246 set_handle_irq(bcm2836_arm_irqchip_handle_irq);