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authorPeter Meerwald <pmeerw@pmeerw.net>2012-08-22 15:42:00 -0400
committerJonathan Cameron <jic23@kernel.org>2012-09-03 15:26:40 -0400
commit91b4171f4e7e2d49aee54259b50e703e09bcff20 (patch)
tree9d2410de5c66b3b9472bea5ffdef2ef7d8f7eeaf /drivers
parent7c388ec1d4bc55b72802afbddb26ab87bc762438 (diff)
staging iio: lis3l02dq cleanup
fixes some typos, whitespace, comments Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/iio/accel/lis3l02dq.h12
-rw-r--r--drivers/staging/iio/accel/lis3l02dq_core.c4
-rw-r--r--drivers/staging/iio/accel/lis3l02dq_ring.c28
3 files changed, 22 insertions, 22 deletions
diff --git a/drivers/staging/iio/accel/lis3l02dq.h b/drivers/staging/iio/accel/lis3l02dq.h
index ae5f225b4bb2..ad5165854655 100644
--- a/drivers/staging/iio/accel/lis3l02dq.h
+++ b/drivers/staging/iio/accel/lis3l02dq.h
@@ -28,7 +28,7 @@
28/* Control Register (1 of 2) */ 28/* Control Register (1 of 2) */
29#define LIS3L02DQ_REG_CTRL_1_ADDR 0x20 29#define LIS3L02DQ_REG_CTRL_1_ADDR 0x20
30/* Power ctrl - either bit set corresponds to on*/ 30/* Power ctrl - either bit set corresponds to on*/
31#define LIS3L02DQ_REG_CTRL_1_PD_ON 0xC0 31#define LIS3L02DQ_REG_CTRL_1_PD_ON 0xC0
32 32
33/* Decimation Factor */ 33/* Decimation Factor */
34#define LIS3L02DQ_DEC_MASK 0x30 34#define LIS3L02DQ_DEC_MASK 0x30
@@ -73,14 +73,14 @@
73/* Interrupt related stuff */ 73/* Interrupt related stuff */
74#define LIS3L02DQ_REG_WAKE_UP_CFG_ADDR 0x23 74#define LIS3L02DQ_REG_WAKE_UP_CFG_ADDR 0x23
75 75
76/* Switch from or combination fo conditions to and */ 76/* Switch from or combination of conditions to and */
77#define LIS3L02DQ_REG_WAKE_UP_CFG_BOOLEAN_AND 0x80 77#define LIS3L02DQ_REG_WAKE_UP_CFG_BOOLEAN_AND 0x80
78 78
79/* Latch interrupt request, 79/* Latch interrupt request,
80 * if on ack must be given by reading the ack register */ 80 * if on ack must be given by reading the ack register */
81#define LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC 0x40 81#define LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC 0x40
82 82
83/* Z Interrupt on High (above threshold)*/ 83/* Z Interrupt on High (above threshold) */
84#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_HIGH 0x20 84#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_HIGH 0x20
85/* Z Interrupt on Low */ 85/* Z Interrupt on Low */
86#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_LOW 0x10 86#define LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_LOW 0x10
@@ -117,13 +117,13 @@
117#define LIS3L02DQ_REG_STATUS_Y_OVERRUN 0x20 117#define LIS3L02DQ_REG_STATUS_Y_OVERRUN 0x20
118#define LIS3L02DQ_REG_STATUS_X_OVERRUN 0x10 118#define LIS3L02DQ_REG_STATUS_X_OVERRUN 0x10
119/* XYZ new data available - first is all 3 available? */ 119/* XYZ new data available - first is all 3 available? */
120#define LIS3L02DQ_REG_STATUS_XYZ_NEW_DATA 0x08 120#define LIS3L02DQ_REG_STATUS_XYZ_NEW_DATA 0x08
121#define LIS3L02DQ_REG_STATUS_Z_NEW_DATA 0x04 121#define LIS3L02DQ_REG_STATUS_Z_NEW_DATA 0x04
122#define LIS3L02DQ_REG_STATUS_Y_NEW_DATA 0x02 122#define LIS3L02DQ_REG_STATUS_Y_NEW_DATA 0x02
123#define LIS3L02DQ_REG_STATUS_X_NEW_DATA 0x01 123#define LIS3L02DQ_REG_STATUS_X_NEW_DATA 0x01
124 124
125/* The accelerometer readings - low and high bytes. 125/* The accelerometer readings - low and high bytes.
126Form of high byte dependent on justification set in ctrl reg */ 126 * Form of high byte dependent on justification set in ctrl reg */
127#define LIS3L02DQ_REG_OUT_X_L_ADDR 0x28 127#define LIS3L02DQ_REG_OUT_X_L_ADDR 0x28
128#define LIS3L02DQ_REG_OUT_X_H_ADDR 0x29 128#define LIS3L02DQ_REG_OUT_X_H_ADDR 0x29
129#define LIS3L02DQ_REG_OUT_Y_L_ADDR 0x2A 129#define LIS3L02DQ_REG_OUT_Y_L_ADDR 0x2A
@@ -150,9 +150,9 @@ Form of high byte dependent on justification set in ctrl reg */
150 * struct lis3l02dq_state - device instance specific data 150 * struct lis3l02dq_state - device instance specific data
151 * @us: actual spi_device 151 * @us: actual spi_device
152 * @trig: data ready trigger registered with iio 152 * @trig: data ready trigger registered with iio
153 * @buf_lock: mutex to protect tx and rx
153 * @tx: transmit buffer 154 * @tx: transmit buffer
154 * @rx: receive buffer 155 * @rx: receive buffer
155 * @buf_lock: mutex to protect tx and rx
156 **/ 156 **/
157struct lis3l02dq_state { 157struct lis3l02dq_state {
158 struct spi_device *us; 158 struct spi_device *us;
diff --git a/drivers/staging/iio/accel/lis3l02dq_core.c b/drivers/staging/iio/accel/lis3l02dq_core.c
index 54ce17fca80e..0144afee9186 100644
--- a/drivers/staging/iio/accel/lis3l02dq_core.c
+++ b/drivers/staging/iio/accel/lis3l02dq_core.c
@@ -392,7 +392,7 @@ static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
392 dev_err(&st->us->dev, "problem with setup control register 1"); 392 dev_err(&st->us->dev, "problem with setup control register 1");
393 goto err_ret; 393 goto err_ret;
394 } 394 }
395 /* Repeat as sometimes doesn't work first time?*/ 395 /* Repeat as sometimes doesn't work first time? */
396 ret = lis3l02dq_spi_write_reg_8(indio_dev, 396 ret = lis3l02dq_spi_write_reg_8(indio_dev,
397 LIS3L02DQ_REG_CTRL_1_ADDR, 397 LIS3L02DQ_REG_CTRL_1_ADDR,
398 val); 398 val);
@@ -686,7 +686,7 @@ static int __devinit lis3l02dq_probe(struct spi_device *spi)
686 goto error_ret; 686 goto error_ret;
687 } 687 }
688 st = iio_priv(indio_dev); 688 st = iio_priv(indio_dev);
689 /* this is only used tor removal purposes */ 689 /* this is only used for removal purposes */
690 spi_set_drvdata(spi, indio_dev); 690 spi_set_drvdata(spi, indio_dev);
691 691
692 st->us = spi; 692 st->us = spi;
diff --git a/drivers/staging/iio/accel/lis3l02dq_ring.c b/drivers/staging/iio/accel/lis3l02dq_ring.c
index 18d108fd967a..7da2703885d6 100644
--- a/drivers/staging/iio/accel/lis3l02dq_ring.c
+++ b/drivers/staging/iio/accel/lis3l02dq_ring.c
@@ -14,7 +14,7 @@
14#include "lis3l02dq.h" 14#include "lis3l02dq.h"
15 15
16/** 16/**
17 * combine_8_to_16() utility function to munge to u8s into u16 17 * combine_8_to_16() utility function to munge two u8s into u16
18 **/ 18 **/
19static inline u16 combine_8_to_16(u8 lower, u8 upper) 19static inline u16 combine_8_to_16(u8 lower, u8 upper)
20{ 20{
@@ -49,7 +49,7 @@ static const u8 read_all_tx_array[] = {
49 49
50/** 50/**
51 * lis3l02dq_read_all() Reads all channels currently selected 51 * lis3l02dq_read_all() Reads all channels currently selected
52 * @st: device specific state 52 * @indio_dev: IIO device state
53 * @rx_array: (dma capable) receive array, must be at least 53 * @rx_array: (dma capable) receive array, must be at least
54 * 4*number of channels 54 * 4*number of channels
55 **/ 55 **/
@@ -170,22 +170,22 @@ __lis3l02dq_write_data_ready_config(struct iio_dev *indio_dev, bool state)
170 bool currentlyset; 170 bool currentlyset;
171 struct lis3l02dq_state *st = iio_priv(indio_dev); 171 struct lis3l02dq_state *st = iio_priv(indio_dev);
172 172
173/* Get the current event mask register */ 173 /* Get the current event mask register */
174 ret = lis3l02dq_spi_read_reg_8(indio_dev, 174 ret = lis3l02dq_spi_read_reg_8(indio_dev,
175 LIS3L02DQ_REG_CTRL_2_ADDR, 175 LIS3L02DQ_REG_CTRL_2_ADDR,
176 &valold); 176 &valold);
177 if (ret) 177 if (ret)
178 goto error_ret; 178 goto error_ret;
179/* Find out if data ready is already on */ 179 /* Find out if data ready is already on */
180 currentlyset 180 currentlyset
181 = valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION; 181 = valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
182 182
183/* Disable requested */ 183 /* Disable requested */
184 if (!state && currentlyset) { 184 if (!state && currentlyset) {
185 /* disable the data ready signal */ 185 /* Disable the data ready signal */
186 valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION; 186 valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
187 187
188 /* The double write is to overcome a hardware bug?*/ 188 /* The double write is to overcome a hardware bug? */
189 ret = lis3l02dq_spi_write_reg_8(indio_dev, 189 ret = lis3l02dq_spi_write_reg_8(indio_dev,
190 LIS3L02DQ_REG_CTRL_2_ADDR, 190 LIS3L02DQ_REG_CTRL_2_ADDR,
191 valold); 191 valold);
@@ -197,10 +197,10 @@ __lis3l02dq_write_data_ready_config(struct iio_dev *indio_dev, bool state)
197 if (ret) 197 if (ret)
198 goto error_ret; 198 goto error_ret;
199 st->trigger_on = false; 199 st->trigger_on = false;
200/* Enable requested */ 200 /* Enable requested */
201 } else if (state && !currentlyset) { 201 } else if (state && !currentlyset) {
202 /* if not set, enable requested */ 202 /* If not set, enable requested
203 /* first disable all events */ 203 * first disable all events */
204 ret = lis3l02dq_disable_all_events(indio_dev); 204 ret = lis3l02dq_disable_all_events(indio_dev);
205 if (ret < 0) 205 if (ret < 0)
206 goto error_ret; 206 goto error_ret;
@@ -239,7 +239,7 @@ static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
239 if (state == false) { 239 if (state == false) {
240 /* 240 /*
241 * A possible quirk with the handler is currently worked around 241 * A possible quirk with the handler is currently worked around
242 * by ensuring outstanding read events are cleared. 242 * by ensuring outstanding read events are cleared.
243 */ 243 */
244 ret = lis3l02dq_read_all(indio_dev, NULL); 244 ret = lis3l02dq_read_all(indio_dev, NULL);
245 } 245 }
@@ -250,7 +250,7 @@ static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
250} 250}
251 251
252/** 252/**
253 * lis3l02dq_trig_try_reen() try renabling irq for data rdy trigger 253 * lis3l02dq_trig_try_reen() try reenabling irq for data rdy trigger
254 * @trig: the datardy trigger 254 * @trig: the datardy trigger
255 */ 255 */
256static int lis3l02dq_trig_try_reen(struct iio_trigger *trig) 256static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
@@ -259,8 +259,8 @@ static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
259 struct lis3l02dq_state *st = iio_priv(indio_dev); 259 struct lis3l02dq_state *st = iio_priv(indio_dev);
260 int i; 260 int i;
261 261
262 /* If gpio still high (or high again) */ 262 /* If gpio still high (or high again)
263 /* In theory possible we will need to do this several times */ 263 * In theory possible we will need to do this several times */
264 for (i = 0; i < 5; i++) 264 for (i = 0; i < 5; i++)
265 if (gpio_get_value(irq_to_gpio(st->us->irq))) 265 if (gpio_get_value(irq_to_gpio(st->us->irq)))
266 lis3l02dq_read_all(indio_dev, NULL); 266 lis3l02dq_read_all(indio_dev, NULL);