OMAP: DSS2: Adding dss_features for independent core clk divider

In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div)
field. The lcd_div is common, for deciding the DISPC core functional clock
frequency, and the final pixel clock frequency for LCD display.

In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1
and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR.

The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core
functional clock configuration. For pixel clock configuration of primary and
secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used
respectively

Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

2 files changed, 4 insertions, 1 deletions

diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index ccae57b34f5c..dc170ad079f2 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -234,7 +234,8 @@ static struct omap_dss_features omap4_dss_features = {
 
         .has_feature    =
                 FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
-                FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1,
+                FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
+                FEAT_CORE_CLK_DIV,
 
         .num_mgrs = 3,
         .num_ovls = 3,
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index 65d6de7e0feb..569d1b295edd 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -36,6 +36,8 @@ enum dss_feat_id {
         FEAT_LINEBUFFERSPLIT    = 1 << 8,
         FEAT_ROWREPEATENABLE    = 1 << 9,
         FEAT_RESIZECONF         = 1 << 10,
+        /* Independent core clk divider */
+        FEAT_CORE_CLK_DIV       = 1 << 11,
 };
 
 /* DSS register field id */