Merge branch 'pci/host-designware' into next

* pci/host-designware:
  PCI: designware: Add driver for prototyping kits based on ARC SDP
  PCI: designware: Add default link up check if sub-driver doesn't override
  PCI: designware: Add generic dw_pcie_wait_for_link()
  ARC: Add PCI support

12 files changed, 203 insertions, 77 deletions

diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index be3f631c3f75..2154092ddee8 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_PCI_IOV) += iov.o
 # Some architectures use the generic PCI setup functions
 #
 obj-$(CONFIG_ALPHA) += setup-irq.o
+obj-$(CONFIG_ARC) += setup-irq.o
 obj-$(CONFIG_ARM) += setup-irq.o
 obj-$(CONFIG_ARM64) += setup-irq.o
 obj-$(CONFIG_UNICORE32) += setup-irq.o
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 4f8e951d7252..391623e516f0 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -16,6 +16,7 @@ config PCI_MVEBU
         depends on ARCH_MVEBU || ARCH_DOVE
         depends on OF
 
+
 config PCIE_XILINX_NWL
         bool "NWL PCIe Core"
         depends on ARCH_ZYNQMP
@@ -26,6 +27,17 @@ config PCIE_XILINX_NWL
          or End Point. The current option selection will only
          support root port enabling.
 
+config PCIE_DW_PLAT
+        bool "Platform bus based DesignWare PCIe Controller"
+        select PCIE_DW
+        ---help---
+         This selects the DesignWare PCIe controller support. Select this if
+         you have a PCIe controller on Platform bus.
+
+         If you have a controller with this interface, say Y or M here.
+
+         If unsure, say N.
+
 config PCIE_DW
         bool
 
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 2c7efd8e0762..3ccd743e20b9 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
+obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
diff --git a/drivers/pci/host/pci-dra7xx.c b/drivers/pci/host/pci-dra7xx.c
index 923607bdabc5..2ca3a1f30ebf 100644
--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
@@ -10,7 +10,6 @@
  * published by the Free Software Foundation.
  */
 
-#include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
@@ -108,7 +107,6 @@ static int dra7xx_pcie_establish_link(struct pcie_port *pp)
 {
         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
         u32 reg;
-        unsigned int retries;
 
         if (dw_pcie_link_up(pp)) {
                 dev_err(pp->dev, "link is already up\n");
@@ -119,14 +117,7 @@ static int dra7xx_pcie_establish_link(struct pcie_port *pp)
         reg |= LTSSM_EN;
         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
 
-        for (retries = 0; retries < 1000; retries++) {
-                if (dw_pcie_link_up(pp))
-                        return 0;
-                usleep_range(10, 20);
-        }
-
-        dev_err(pp->dev, "link is not up\n");
-        return -EINVAL;
+        return dw_pcie_wait_for_link(pp);
 }
 
 static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index d997d22d4231..219976103efc 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -318,7 +318,6 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
 {
         struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
         u32 val;
-        unsigned int retries;
 
         if (dw_pcie_link_up(pp)) {
                 dev_err(pp->dev, "Link already up\n");
@@ -357,13 +356,8 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
                           PCIE_APP_LTSSM_ENABLE);
 
         /* check if the link is up or not */
-        for (retries = 0; retries < 10; retries++) {
-                if (dw_pcie_link_up(pp)) {
-                        dev_info(pp->dev, "Link up\n");
-                        return 0;
-                }
-                mdelay(100);
-        }
+        if (!dw_pcie_wait_for_link(pp))
+                return 0;
 
         while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
                 val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);
@@ -372,8 +366,7 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
         /* power off phy */
         exynos_pcie_power_off_phy(pp);
 
-        dev_err(pp->dev, "PCIe Link Fail\n");
-        return -EINVAL;
+        return -ETIMEDOUT;
 }
 
 static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 8c9b3896d6f5..eb5a2755a164 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -357,33 +357,14 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
 
 static int imx6_pcie_wait_for_link(struct pcie_port *pp)
 {
-        unsigned int retries;
+        /* check if the link is up or not */
+        if (!dw_pcie_wait_for_link(pp))
+                return 0;
 
-        /*
-         * Test if the PHY reports that the link is up and also that the LTSSM
-         * training finished. There are three possible states of the link when
-         * this code is called:
-         * 1) The link is DOWN (unlikely)
-         *    The link didn't come up yet for some reason. This usually means
-         *    we have a real problem somewhere, if it happens with a peripheral
-         *    connected. This state calls for inspection of the DEBUG registers.
-         * 2) The link is UP, but still in LTSSM training
-         *    Wait for the training to finish, which should take a very short
-         *    time. If the training does not finish, we have a problem and we
-         *    need to inspect the DEBUG registers. If the training does finish,
-         *    the link is up and operating correctly.
-         * 3) The link is UP and no longer in LTSSM training
-         *    The link is up and operating correctly.
-         */
-        for (retries = 0; retries < 200; retries++) {
-                u32 reg = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
-                if ((reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
-                    !(reg & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
-                        return 0;
-                usleep_range(1000, 2000);
-        }
-
-        return -EINVAL;
+        dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
+                readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
+                readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
+        return -ETIMEDOUT;
 }
 
 static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c
index cd7034523f52..b71f55bb0315 100644
--- a/drivers/pci/host/pci-keystone.c
+++ b/drivers/pci/host/pci-keystone.c
@@ -97,17 +97,15 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
                 return 0;
         }
 
-        ks_dw_pcie_initiate_link_train(ks_pcie);
         /* check if the link is up or not */
-        for (retries = 0; retries < 200; retries++) {
-                if (dw_pcie_link_up(pp))
-                        return 0;
-                usleep_range(100, 1000);
+        for (retries = 0; retries < 5; retries++) {
                 ks_dw_pcie_initiate_link_train(ks_pcie);
+                if (!dw_pcie_wait_for_link(pp))
+                        return 0;
         }
 
         dev_err(pp->dev, "phy link never came up\n");
-        return -EINVAL;
+        return -ETIMEDOUT;
 }
 
 static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
diff --git a/drivers/pci/host/pcie-designware-plat.c b/drivers/pci/host/pcie-designware-plat.c
new file mode 100644
index 000000000000..b3500994d08a
--- /dev/null
+++ b/drivers/pci/host/pcie-designware-plat.c
@@ -0,0 +1,138 @@
+/*
+ * PCIe RC driver for Synopsys DesignWare Core
+ *
+ * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
+ *
+ * Authors: Joao Pinto <jpinto@synopsys.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/signal.h>
+#include <linux/types.h>
+
+#include "pcie-designware.h"
+
+struct dw_plat_pcie {
+        void __iomem            *mem_base;
+        struct pcie_port        pp;
+};
+
+static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg)
+{
+        struct pcie_port *pp = arg;
+
+        return dw_handle_msi_irq(pp);
+}
+
+static void dw_plat_pcie_host_init(struct pcie_port *pp)
+{
+        dw_pcie_setup_rc(pp);
+        dw_pcie_wait_for_link(pp);
+
+        if (IS_ENABLED(CONFIG_PCI_MSI))
+                dw_pcie_msi_init(pp);
+}
+
+static struct pcie_host_ops dw_plat_pcie_host_ops = {
+        .host_init = dw_plat_pcie_host_init,
+};
+
+static int dw_plat_add_pcie_port(struct pcie_port *pp,
+                                 struct platform_device *pdev)
+{
+        int ret;
+
+        pp->irq = platform_get_irq(pdev, 1);
+        if (pp->irq < 0)
+                return pp->irq;
+
+        if (IS_ENABLED(CONFIG_PCI_MSI)) {
+                pp->msi_irq = platform_get_irq(pdev, 0);
+                if (pp->msi_irq < 0)
+                        return pp->msi_irq;
+
+                ret = devm_request_irq(&pdev->dev, pp->msi_irq,
+                                        dw_plat_pcie_msi_irq_handler,
+                                        IRQF_SHARED, "dw-plat-pcie-msi", pp);
+                if (ret) {
+                        dev_err(&pdev->dev, "failed to request MSI IRQ\n");
+                        return ret;
+                }
+        }
+
+        pp->root_bus_nr = -1;
+        pp->ops = &dw_plat_pcie_host_ops;
+
+        ret = dw_pcie_host_init(pp);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to initialize host\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static int dw_plat_pcie_probe(struct platform_device *pdev)
+{
+        struct dw_plat_pcie *dw_plat_pcie;
+        struct pcie_port *pp;
+        struct resource *res;  /* Resource from DT */
+        int ret;
+
+        dw_plat_pcie = devm_kzalloc(&pdev->dev, sizeof(*dw_plat_pcie),
+                                        GFP_KERNEL);
+        if (!dw_plat_pcie)
+                return -ENOMEM;
+
+        pp = &dw_plat_pcie->pp;
+        pp->dev = &pdev->dev;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                return -ENODEV;
+
+        dw_plat_pcie->mem_base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(dw_plat_pcie->mem_base))
+                return PTR_ERR(dw_plat_pcie->mem_base);
+
+        pp->dbi_base = dw_plat_pcie->mem_base;
+
+        ret = dw_plat_add_pcie_port(pp, pdev);
+        if (ret < 0)
+                return ret;
+
+        platform_set_drvdata(pdev, dw_plat_pcie);
+        return 0;
+}
+
+static const struct of_device_id dw_plat_pcie_of_match[] = {
+        { .compatible = "snps,dw-pcie", },
+        {},
+};
+MODULE_DEVICE_TABLE(of, dw_plat_pcie_of_match);
+
+static struct platform_driver dw_plat_pcie_driver = {
+        .driver = {
+                .name   = "dw-pcie",
+                .of_match_table = dw_plat_pcie_of_match,
+        },
+        .probe = dw_plat_pcie_probe,
+};
+
+module_platform_driver(dw_plat_pcie_driver);
+
+MODULE_AUTHOR("Joao Pinto <Joao.Pinto@synopsys.com>");
+MODULE_DESCRIPTION("Synopsys PCIe host controller glue platform driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index f85f10d22049..a4cccd356304 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -22,6 +22,7 @@
 #include <linux/pci_regs.h>
 #include <linux/platform_device.h>
 #include <linux/types.h>
+#include <linux/delay.h>
 
 #include "pcie-designware.h"
 
@@ -69,6 +70,11 @@
 #define PCIE_ATU_FUNC(x)                (((x) & 0x7) << 16)
 #define PCIE_ATU_UPPER_TARGET           0x91C
 
+/* PCIe Port Logic registers */
+#define PLR_OFFSET                      0x700
+#define PCIE_PHY_DEBUG_R1               (PLR_OFFSET + 0x2c)
+#define PCIE_PHY_DEBUG_R1_LINK_UP       0x00000010
+
 static struct pci_ops dw_pcie_ops;
 
 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
@@ -380,12 +386,33 @@ static struct msi_controller dw_pcie_msi_chip = {
         .teardown_irq = dw_msi_teardown_irq,
 };
 
+int dw_pcie_wait_for_link(struct pcie_port *pp)
+{
+        int retries;
+
+        /* check if the link is up or not */
+        for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+                if (dw_pcie_link_up(pp)) {
+                        dev_info(pp->dev, "link up\n");
+                        return 0;
+                }
+                usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
+        }
+
+        dev_err(pp->dev, "phy link never came up\n");
+
+        return -ETIMEDOUT;
+}
+
 int dw_pcie_link_up(struct pcie_port *pp)
 {
+        u32 val;
+
         if (pp->ops->link_up)
                 return pp->ops->link_up(pp);
 
-        return 0;
+        val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
+        return val & PCIE_PHY_DEBUG_R1_LINK_UP;
 }
 
 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 2356d29e8527..f437f9b5be04 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -22,6 +22,11 @@
 #define MAX_MSI_IRQS                    32
 #define MAX_MSI_CTRLS                   (MAX_MSI_IRQS / 32)
 
+/* Parameters for the waiting for link up routine */
+#define LINK_WAIT_MAX_RETRIES           10
+#define LINK_WAIT_USLEEP_MIN            90000
+#define LINK_WAIT_USLEEP_MAX            100000
+
 struct pcie_port {
         struct device           *dev;
         u8                      root_bus_nr;
@@ -76,6 +81,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val);
 int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
+int dw_pcie_wait_for_link(struct pcie_port *pp);
 int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
diff --git a/drivers/pci/host/pcie-qcom.c b/drivers/pci/host/pcie-qcom.c
index e845fba19632..f2f90c50f75d 100644
--- a/drivers/pci/host/pcie-qcom.c
+++ b/drivers/pci/host/pcie-qcom.c
@@ -116,8 +116,6 @@ static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
 
 static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
 {
-        struct device *dev = pcie->dev;
-        unsigned int retries = 0;
         u32 val;
 
         if (dw_pcie_link_up(&pcie->pp))
@@ -128,15 +126,7 @@ static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
         val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
         writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
 
-        do {
-                if (dw_pcie_link_up(&pcie->pp))
-                        return 0;
-                usleep_range(250, 1000);
-        } while (retries < 200);
-
-        dev_warn(dev, "phy link never came up\n");
-
-        return -ETIMEDOUT;
+        return dw_pcie_wait_for_link(&pcie->pp);
 }
 
 static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
index a6cd8233e8c0..a4060b85ab23 100644
--- a/drivers/pci/host/pcie-spear13xx.c
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -13,7 +13,6 @@
  */
 
 #include <linux/clk.h>
-#include <linux/delay.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
@@ -149,7 +148,6 @@ static int spear13xx_pcie_establish_link(struct pcie_port *pp)
         struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
         struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
         u32 exp_cap_off = EXP_CAP_ID_OFFSET;
-        unsigned int retries;
 
         if (dw_pcie_link_up(pp)) {
                 dev_err(pp->dev, "link already up\n");
@@ -200,17 +198,7 @@ static int spear13xx_pcie_establish_link(struct pcie_port *pp)
                         | ((u32)1 << REG_TRANSLATION_ENABLE),
                         &app_reg->app_ctrl_0);
 
-        /* check if the link is up or not */
-        for (retries = 0; retries < 10; retries++) {
-                if (dw_pcie_link_up(pp)) {
-                        dev_info(pp->dev, "link up\n");
-                        return 0;
-                }
-                mdelay(100);
-        }
-
-        dev_err(pp->dev, "link Fail\n");
-        return -EINVAL;
+        return dw_pcie_wait_for_link(pp);
 }
 
 static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)