summaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2016-12-15 15:03:32 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2016-12-15 15:03:32 -0500
commit4d5b57e05a67c3cfd8e2b2a64ca356245a15b1c6 (patch)
treed8f3ea3bc3ccfe289f414bbe9a4bdd1e935d9228 /drivers
parent6df8b74b1720db1133ace0861cb6721bfe57819a (diff)
parent6f94ba20799b98c8badf047b184fb4cd7bc45e44 (diff)
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma
Pull rdma updates from Doug Ledford: "This is the complete update for the rdma stack for this release cycle. Most of it is typical driver and core updates, but there is the entirely new VMWare pvrdma driver. You may have noticed that there were changes in DaveM's pull request to the bnxt Ethernet driver to support a RoCE RDMA driver. The bnxt_re driver was tentatively set to be pulled in this release cycle, but it simply wasn't ready in time and was dropped (a few review comments still to address, and some multi-arch build issues like prefetch() not working across all arches). Summary: - shared mlx5 updates with net stack (will drop out on merge if Dave's tree has already been merged) - driver updates: cxgb4, hfi1, hns-roce, i40iw, mlx4, mlx5, qedr, rxe - debug cleanups - new connection rejection helpers - SRP updates - various misc fixes - new paravirt driver from vmware" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dledford/rdma: (210 commits) IB: Add vmw_pvrdma driver IB/mlx4: fix improper return value IB/ocrdma: fix bad initialization infiniband: nes: return value of skb_linearize should be handled MAINTAINERS: Update Intel RDMA RNIC driver maintainers MAINTAINERS: Remove Mitesh Ahuja from emulex maintainers IB/core: fix unmap_sg argument qede: fix general protection fault may occur on probe IB/mthca: Replace pci_pool_alloc by pci_pool_zalloc mlx5, calc_sq_size(): Make a debug message more informative mlx5: Remove a set-but-not-used variable mlx5: Use { } instead of { 0 } to init struct IB/srp: Make writing the add_target sysfs attr interruptible IB/srp: Make mapping failures easier to debug IB/srp: Make login failures easier to debug IB/srp: Introduce a local variable in srp_add_one() IB/srp: Fix CONFIG_DYNAMIC_DEBUG=n build IB/multicast: Check ib_find_pkey() return value IPoIB: Avoid reading an uninitialized member variable IB/mad: Fix an array index check ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/infiniband/Kconfig1
-rw-r--r--drivers/infiniband/core/agent.c1
-rw-r--r--drivers/infiniband/core/cache.c16
-rw-r--r--drivers/infiniband/core/cm.c72
-rw-r--r--drivers/infiniband/core/cma.c43
-rw-r--r--drivers/infiniband/core/core_priv.h3
-rw-r--r--drivers/infiniband/core/device.c5
-rw-r--r--drivers/infiniband/core/fmr_pool.c1
-rw-r--r--drivers/infiniband/core/iwcm.c21
-rw-r--r--drivers/infiniband/core/iwpm_msg.c1
-rw-r--r--drivers/infiniband/core/iwpm_util.c12
-rw-r--r--drivers/infiniband/core/mad.c46
-rw-r--r--drivers/infiniband/core/multicast.c7
-rw-r--r--drivers/infiniband/core/roce_gid_mgmt.c21
-rw-r--r--drivers/infiniband/core/ucm.c5
-rw-r--r--drivers/infiniband/core/ucma.c5
-rw-r--r--drivers/infiniband/core/umem.c2
-rw-r--r--drivers/infiniband/core/uverbs.h1
-rw-r--r--drivers/infiniband/core/uverbs_cmd.c229
-rw-r--r--drivers/infiniband/core/uverbs_main.c6
-rw-r--r--drivers/infiniband/core/verbs.c108
-rw-r--r--drivers/infiniband/hw/Makefile1
-rw-r--r--drivers/infiniband/hw/cxgb3/cxio_dbg.c20
-rw-r--r--drivers/infiniband/hw/cxgb3/iwch_provider.c3
-rw-r--r--drivers/infiniband/hw/cxgb4/device.c8
-rw-r--r--drivers/infiniband/hw/cxgb4/provider.c4
-rw-r--r--drivers/infiniband/hw/hfi1/affinity.c3
-rw-r--r--drivers/infiniband/hw/hfi1/affinity.h9
-rw-r--r--drivers/infiniband/hw/hfi1/chip.c9
-rw-r--r--drivers/infiniband/hw/hfi1/chip_registers.h3
-rw-r--r--drivers/infiniband/hw/hfi1/debugfs.c110
-rw-r--r--drivers/infiniband/hw/hfi1/driver.c3
-rw-r--r--drivers/infiniband/hw/hfi1/eprom.c211
-rw-r--r--drivers/infiniband/hw/hfi1/firmware.c156
-rw-r--r--drivers/infiniband/hw/hfi1/hfi.h144
-rw-r--r--drivers/infiniband/hw/hfi1/iowait.h8
-rw-r--r--drivers/infiniband/hw/hfi1/mad.c31
-rw-r--r--drivers/infiniband/hw/hfi1/mmu_rb.c2
-rw-r--r--drivers/infiniband/hw/hfi1/pio.c40
-rw-r--r--drivers/infiniband/hw/hfi1/pio.h38
-rw-r--r--drivers/infiniband/hw/hfi1/pio_copy.c22
-rw-r--r--drivers/infiniband/hw/hfi1/platform.c193
-rw-r--r--drivers/infiniband/hw/hfi1/platform.h127
-rw-r--r--drivers/infiniband/hw/hfi1/qp.c11
-rw-r--r--drivers/infiniband/hw/hfi1/rc.c60
-rw-r--r--drivers/infiniband/hw/hfi1/ruc.c44
-rw-r--r--drivers/infiniband/hw/hfi1/sdma.c18
-rw-r--r--drivers/infiniband/hw/hfi1/sdma.h12
-rw-r--r--drivers/infiniband/hw/hfi1/uc.c4
-rw-r--r--drivers/infiniband/hw/hfi1/ud.c4
-rw-r--r--drivers/infiniband/hw/hfi1/user_sdma.c60
-rw-r--r--drivers/infiniband/hw/hfi1/verbs.c209
-rw-r--r--drivers/infiniband/hw/hfi1/verbs.h16
-rw-r--r--drivers/infiniband/hw/hfi1/verbs_txreq.c13
-rw-r--r--drivers/infiniband/hw/hfi1/verbs_txreq.h1
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_ah.c3
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_alloc.c11
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_cmd.c8
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_cmd.h12
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_common.h44
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_cq.c46
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_device.h66
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_eq.c6
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_hem.c6
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_hw_v1.c1222
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_hw_v1.h74
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_main.c329
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_mr.c43
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_pd.c5
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_qp.c4
-rw-r--r--drivers/infiniband/hw/hns/hns_roce_user.h53
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw.h37
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_cm.c377
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_cm.h11
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_ctrl.c646
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_d.h25
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_hw.c61
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_main.c166
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_osdep.h8
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_p.h21
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_pble.c4
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_puda.c271
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_puda.h20
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_type.h98
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_uk.c40
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_user.h14
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_utils.c289
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_verbs.c238
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_verbs.h2
-rw-r--r--drivers/infiniband/hw/i40iw/i40iw_virtchnl.c33
-rw-r--r--drivers/infiniband/hw/mlx4/ah.c10
-rw-r--r--drivers/infiniband/hw/mlx4/alias_GUID.c4
-rw-r--r--drivers/infiniband/hw/mlx4/cm.c4
-rw-r--r--drivers/infiniband/hw/mlx4/mad.c58
-rw-r--r--drivers/infiniband/hw/mlx4/main.c49
-rw-r--r--drivers/infiniband/hw/mlx4/mcg.c5
-rw-r--r--drivers/infiniband/hw/mlx4/mlx4_ib.h3
-rw-r--r--drivers/infiniband/hw/mlx4/qp.c13
-rw-r--r--drivers/infiniband/hw/mlx5/ah.c25
-rw-r--r--drivers/infiniband/hw/mlx5/cq.c34
-rw-r--r--drivers/infiniband/hw/mlx5/main.c268
-rw-r--r--drivers/infiniband/hw/mlx5/mem.c7
-rw-r--r--drivers/infiniband/hw/mlx5/mlx5_ib.h12
-rw-r--r--drivers/infiniband/hw/mlx5/mr.c71
-rw-r--r--drivers/infiniband/hw/mlx5/qp.c131
-rw-r--r--drivers/infiniband/hw/mlx5/srq.c6
-rw-r--r--drivers/infiniband/hw/mthca/mthca_av.c6
-rw-r--r--drivers/infiniband/hw/mthca/mthca_provider.c4
-rw-r--r--drivers/infiniband/hw/mthca/mthca_reset.c4
-rw-r--r--drivers/infiniband/hw/nes/nes.c1
-rw-r--r--drivers/infiniband/hw/nes/nes_cm.c4
-rw-r--r--drivers/infiniband/hw/nes/nes_hw.c6
-rw-r--r--drivers/infiniband/hw/nes/nes_mgt.c10
-rw-r--r--drivers/infiniband/hw/nes/nes_nic.c84
-rw-r--r--drivers/infiniband/hw/nes/nes_verbs.c7
-rw-r--r--drivers/infiniband/hw/ocrdma/ocrdma_ah.c3
-rw-r--r--drivers/infiniband/hw/ocrdma/ocrdma_ah.h4
-rw-r--r--drivers/infiniband/hw/ocrdma/ocrdma_hw.c7
-rw-r--r--drivers/infiniband/hw/ocrdma/ocrdma_stats.c4
-rw-r--r--drivers/infiniband/hw/qedr/verbs.c27
-rw-r--r--drivers/infiniband/hw/qedr/verbs.h3
-rw-r--r--drivers/infiniband/hw/qib/qib_diag.c6
-rw-r--r--drivers/infiniband/hw/qib/qib_driver.c3
-rw-r--r--drivers/infiniband/hw/qib/qib_eeprom.c6
-rw-r--r--drivers/infiniband/hw/qib/qib_file_ops.c5
-rw-r--r--drivers/infiniband/hw/qib/qib_iba6120.c8
-rw-r--r--drivers/infiniband/hw/qib/qib_iba7220.c8
-rw-r--r--drivers/infiniband/hw/qib/qib_iba7322.c22
-rw-r--r--drivers/infiniband/hw/qib/qib_init.c47
-rw-r--r--drivers/infiniband/hw/qib/qib_rc.c44
-rw-r--r--drivers/infiniband/hw/qib/qib_ruc.c24
-rw-r--r--drivers/infiniband/hw/qib/qib_verbs.c33
-rw-r--r--drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c22
-rw-r--r--drivers/infiniband/hw/usnic/usnic_ib_verbs.c16
-rw-r--r--drivers/infiniband/hw/usnic/usnic_ib_verbs.h4
-rw-r--r--drivers/infiniband/hw/usnic/usnic_vnic.c22
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/Kconfig7
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/Makefile3
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma.h474
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_cmd.c119
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c425
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h586
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_doorbell.c127
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c1211
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_misc.c304
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_mr.c334
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c972
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_ring.h131
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c579
-rw-r--r--drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h436
-rw-r--r--drivers/infiniband/sw/rdmavt/cq.c64
-rw-r--r--drivers/infiniband/sw/rdmavt/mcast.c5
-rw-r--r--drivers/infiniband/sw/rdmavt/mr.c22
-rw-r--r--drivers/infiniband/sw/rdmavt/qp.c20
-rw-r--r--drivers/infiniband/sw/rdmavt/trace.h141
-rw-r--r--drivers/infiniband/sw/rdmavt/trace_mr.h112
-rw-r--r--drivers/infiniband/sw/rdmavt/trace_qp.h96
-rw-r--r--drivers/infiniband/sw/rdmavt/trace_rvt.h81
-rw-r--r--drivers/infiniband/sw/rdmavt/trace_tx.h132
-rw-r--r--drivers/infiniband/sw/rxe/rxe_comp.c9
-rw-r--r--drivers/infiniband/sw/rxe/rxe_loc.h2
-rw-r--r--drivers/infiniband/sw/rxe/rxe_mr.c3
-rw-r--r--drivers/infiniband/sw/rxe/rxe_net.c8
-rw-r--r--drivers/infiniband/sw/rxe/rxe_param.h2
-rw-r--r--drivers/infiniband/sw/rxe/rxe_pool.c1
-rw-r--r--drivers/infiniband/sw/rxe/rxe_recv.c11
-rw-r--r--drivers/infiniband/sw/rxe/rxe_req.c20
-rw-r--r--drivers/infiniband/sw/rxe/rxe_resp.c25
-rw-r--r--drivers/infiniband/sw/rxe/rxe_srq.c2
-rw-r--r--drivers/infiniband/sw/rxe/rxe_task.c19
-rw-r--r--drivers/infiniband/sw/rxe/rxe_task.h1
-rw-r--r--drivers/infiniband/sw/rxe/rxe_verbs.c21
-rw-r--r--drivers/infiniband/ulp/ipoib/ipoib_cm.c10
-rw-r--r--drivers/infiniband/ulp/ipoib/ipoib_ib.c5
-rw-r--r--drivers/infiniband/ulp/ipoib/ipoib_main.c5
-rw-r--r--drivers/infiniband/ulp/ipoib/ipoib_multicast.c7
-rw-r--r--drivers/infiniband/ulp/iser/iser_verbs.c5
-rw-r--r--drivers/infiniband/ulp/isert/ib_isert.c31
-rw-r--r--drivers/infiniband/ulp/srp/ib_srp.c48
-rw-r--r--drivers/infiniband/ulp/srpt/ib_srpt.c22
-rw-r--r--drivers/net/ethernet/qlogic/qede/qede_roce.c4
-rw-r--r--drivers/net/vmxnet3/vmxnet3_int.h3
-rw-r--r--drivers/nvme/host/rdma.c42
-rw-r--r--drivers/nvme/target/rdma.c3
184 files changed, 11682 insertions, 2648 deletions
diff --git a/drivers/infiniband/Kconfig b/drivers/infiniband/Kconfig
index fb3fb89640e5..670917387eda 100644
--- a/drivers/infiniband/Kconfig
+++ b/drivers/infiniband/Kconfig
@@ -73,6 +73,7 @@ source "drivers/infiniband/hw/mlx4/Kconfig"
73source "drivers/infiniband/hw/mlx5/Kconfig" 73source "drivers/infiniband/hw/mlx5/Kconfig"
74source "drivers/infiniband/hw/nes/Kconfig" 74source "drivers/infiniband/hw/nes/Kconfig"
75source "drivers/infiniband/hw/ocrdma/Kconfig" 75source "drivers/infiniband/hw/ocrdma/Kconfig"
76source "drivers/infiniband/hw/vmw_pvrdma/Kconfig"
76source "drivers/infiniband/hw/usnic/Kconfig" 77source "drivers/infiniband/hw/usnic/Kconfig"
77source "drivers/infiniband/hw/hns/Kconfig" 78source "drivers/infiniband/hw/hns/Kconfig"
78 79
diff --git a/drivers/infiniband/core/agent.c b/drivers/infiniband/core/agent.c
index 4fa524dfb6cf..11dacd97a667 100644
--- a/drivers/infiniband/core/agent.c
+++ b/drivers/infiniband/core/agent.c
@@ -156,7 +156,6 @@ int ib_agent_port_open(struct ib_device *device, int port_num)
156 /* Create new device info */ 156 /* Create new device info */
157 port_priv = kzalloc(sizeof *port_priv, GFP_KERNEL); 157 port_priv = kzalloc(sizeof *port_priv, GFP_KERNEL);
158 if (!port_priv) { 158 if (!port_priv) {
159 dev_err(&device->dev, "No memory for ib_agent_port_private\n");
160 ret = -ENOMEM; 159 ret = -ENOMEM;
161 goto error1; 160 goto error1;
162 } 161 }
diff --git a/drivers/infiniband/core/cache.c b/drivers/infiniband/core/cache.c
index 1a2984c28b95..ae04826e82fc 100644
--- a/drivers/infiniband/core/cache.c
+++ b/drivers/infiniband/core/cache.c
@@ -770,12 +770,8 @@ static int _gid_table_setup_one(struct ib_device *ib_dev)
770 int err = 0; 770 int err = 0;
771 771
772 table = kcalloc(ib_dev->phys_port_cnt, sizeof(*table), GFP_KERNEL); 772 table = kcalloc(ib_dev->phys_port_cnt, sizeof(*table), GFP_KERNEL);
773 773 if (!table)
774 if (!table) {
775 pr_warn("failed to allocate ib gid cache for %s\n",
776 ib_dev->name);
777 return -ENOMEM; 774 return -ENOMEM;
778 }
779 775
780 for (port = 0; port < ib_dev->phys_port_cnt; port++) { 776 for (port = 0; port < ib_dev->phys_port_cnt; port++) {
781 u8 rdma_port = port + rdma_start_port(ib_dev); 777 u8 rdma_port = port + rdma_start_port(ib_dev);
@@ -1170,14 +1166,13 @@ int ib_cache_setup_one(struct ib_device *device)
1170 GFP_KERNEL); 1166 GFP_KERNEL);
1171 if (!device->cache.pkey_cache || 1167 if (!device->cache.pkey_cache ||
1172 !device->cache.lmc_cache) { 1168 !device->cache.lmc_cache) {
1173 pr_warn("Couldn't allocate cache for %s\n", device->name); 1169 err = -ENOMEM;
1174 return -ENOMEM; 1170 goto free;
1175 } 1171 }
1176 1172
1177 err = gid_table_setup_one(device); 1173 err = gid_table_setup_one(device);
1178 if (err) 1174 if (err)
1179 /* Allocated memory will be cleaned in the release function */ 1175 goto free;
1180 return err;
1181 1176
1182 for (p = 0; p <= rdma_end_port(device) - rdma_start_port(device); ++p) 1177 for (p = 0; p <= rdma_end_port(device) - rdma_start_port(device); ++p)
1183 ib_cache_update(device, p + rdma_start_port(device)); 1178 ib_cache_update(device, p + rdma_start_port(device));
@@ -1192,6 +1187,9 @@ int ib_cache_setup_one(struct ib_device *device)
1192 1187
1193err: 1188err:
1194 gid_table_cleanup_one(device); 1189 gid_table_cleanup_one(device);
1190free:
1191 kfree(device->cache.pkey_cache);
1192 kfree(device->cache.lmc_cache);
1195 return err; 1193 return err;
1196} 1194}
1197 1195
diff --git a/drivers/infiniband/core/cm.c b/drivers/infiniband/core/cm.c
index 71c7c4c328ef..cf1edfa1cbac 100644
--- a/drivers/infiniband/core/cm.c
+++ b/drivers/infiniband/core/cm.c
@@ -57,6 +57,54 @@ MODULE_AUTHOR("Sean Hefty");
57MODULE_DESCRIPTION("InfiniBand CM"); 57MODULE_DESCRIPTION("InfiniBand CM");
58MODULE_LICENSE("Dual BSD/GPL"); 58MODULE_LICENSE("Dual BSD/GPL");
59 59
60static const char * const ibcm_rej_reason_strs[] = {
61 [IB_CM_REJ_NO_QP] = "no QP",
62 [IB_CM_REJ_NO_EEC] = "no EEC",
63 [IB_CM_REJ_NO_RESOURCES] = "no resources",
64 [IB_CM_REJ_TIMEOUT] = "timeout",
65 [IB_CM_REJ_UNSUPPORTED] = "unsupported",
66 [IB_CM_REJ_INVALID_COMM_ID] = "invalid comm ID",
67 [IB_CM_REJ_INVALID_COMM_INSTANCE] = "invalid comm instance",
68 [IB_CM_REJ_INVALID_SERVICE_ID] = "invalid service ID",
69 [IB_CM_REJ_INVALID_TRANSPORT_TYPE] = "invalid transport type",
70 [IB_CM_REJ_STALE_CONN] = "stale conn",
71 [IB_CM_REJ_RDC_NOT_EXIST] = "RDC not exist",
72 [IB_CM_REJ_INVALID_GID] = "invalid GID",
73 [IB_CM_REJ_INVALID_LID] = "invalid LID",
74 [IB_CM_REJ_INVALID_SL] = "invalid SL",
75 [IB_CM_REJ_INVALID_TRAFFIC_CLASS] = "invalid traffic class",
76 [IB_CM_REJ_INVALID_HOP_LIMIT] = "invalid hop limit",
77 [IB_CM_REJ_INVALID_PACKET_RATE] = "invalid packet rate",
78 [IB_CM_REJ_INVALID_ALT_GID] = "invalid alt GID",
79 [IB_CM_REJ_INVALID_ALT_LID] = "invalid alt LID",
80 [IB_CM_REJ_INVALID_ALT_SL] = "invalid alt SL",
81 [IB_CM_REJ_INVALID_ALT_TRAFFIC_CLASS] = "invalid alt traffic class",
82 [IB_CM_REJ_INVALID_ALT_HOP_LIMIT] = "invalid alt hop limit",
83 [IB_CM_REJ_INVALID_ALT_PACKET_RATE] = "invalid alt packet rate",
84 [IB_CM_REJ_PORT_CM_REDIRECT] = "port CM redirect",
85 [IB_CM_REJ_PORT_REDIRECT] = "port redirect",
86 [IB_CM_REJ_INVALID_MTU] = "invalid MTU",
87 [IB_CM_REJ_INSUFFICIENT_RESP_RESOURCES] = "insufficient resp resources",
88 [IB_CM_REJ_CONSUMER_DEFINED] = "consumer defined",
89 [IB_CM_REJ_INVALID_RNR_RETRY] = "invalid RNR retry",
90 [IB_CM_REJ_DUPLICATE_LOCAL_COMM_ID] = "duplicate local comm ID",
91 [IB_CM_REJ_INVALID_CLASS_VERSION] = "invalid class version",
92 [IB_CM_REJ_INVALID_FLOW_LABEL] = "invalid flow label",
93 [IB_CM_REJ_INVALID_ALT_FLOW_LABEL] = "invalid alt flow label",
94};
95
96const char *__attribute_const__ ibcm_reject_msg(int reason)
97{
98 size_t index = reason;
99
100 if (index < ARRAY_SIZE(ibcm_rej_reason_strs) &&
101 ibcm_rej_reason_strs[index])
102 return ibcm_rej_reason_strs[index];
103 else
104 return "unrecognized reason";
105}
106EXPORT_SYMBOL(ibcm_reject_msg);
107
60static void cm_add_one(struct ib_device *device); 108static void cm_add_one(struct ib_device *device);
61static void cm_remove_one(struct ib_device *device, void *client_data); 109static void cm_remove_one(struct ib_device *device, void *client_data);
62 110
@@ -1582,6 +1630,7 @@ static struct cm_id_private * cm_match_req(struct cm_work *work,
1582 struct cm_id_private *listen_cm_id_priv, *cur_cm_id_priv; 1630 struct cm_id_private *listen_cm_id_priv, *cur_cm_id_priv;
1583 struct cm_timewait_info *timewait_info; 1631 struct cm_timewait_info *timewait_info;
1584 struct cm_req_msg *req_msg; 1632 struct cm_req_msg *req_msg;
1633 struct ib_cm_id *cm_id;
1585 1634
1586 req_msg = (struct cm_req_msg *)work->mad_recv_wc->recv_buf.mad; 1635 req_msg = (struct cm_req_msg *)work->mad_recv_wc->recv_buf.mad;
1587 1636
@@ -1603,10 +1652,18 @@ static struct cm_id_private * cm_match_req(struct cm_work *work,
1603 timewait_info = cm_insert_remote_qpn(cm_id_priv->timewait_info); 1652 timewait_info = cm_insert_remote_qpn(cm_id_priv->timewait_info);
1604 if (timewait_info) { 1653 if (timewait_info) {
1605 cm_cleanup_timewait(cm_id_priv->timewait_info); 1654 cm_cleanup_timewait(cm_id_priv->timewait_info);
1655 cur_cm_id_priv = cm_get_id(timewait_info->work.local_id,
1656 timewait_info->work.remote_id);
1657
1606 spin_unlock_irq(&cm.lock); 1658 spin_unlock_irq(&cm.lock);
1607 cm_issue_rej(work->port, work->mad_recv_wc, 1659 cm_issue_rej(work->port, work->mad_recv_wc,
1608 IB_CM_REJ_STALE_CONN, CM_MSG_RESPONSE_REQ, 1660 IB_CM_REJ_STALE_CONN, CM_MSG_RESPONSE_REQ,
1609 NULL, 0); 1661 NULL, 0);
1662 if (cur_cm_id_priv) {
1663 cm_id = &cur_cm_id_priv->id;
1664 ib_send_cm_dreq(cm_id, NULL, 0);
1665 cm_deref_id(cur_cm_id_priv);
1666 }
1610 return NULL; 1667 return NULL;
1611 } 1668 }
1612 1669
@@ -1984,6 +2041,9 @@ static int cm_rep_handler(struct cm_work *work)
1984 struct cm_id_private *cm_id_priv; 2041 struct cm_id_private *cm_id_priv;
1985 struct cm_rep_msg *rep_msg; 2042 struct cm_rep_msg *rep_msg;
1986 int ret; 2043 int ret;
2044 struct cm_id_private *cur_cm_id_priv;
2045 struct ib_cm_id *cm_id;
2046 struct cm_timewait_info *timewait_info;
1987 2047
1988 rep_msg = (struct cm_rep_msg *)work->mad_recv_wc->recv_buf.mad; 2048 rep_msg = (struct cm_rep_msg *)work->mad_recv_wc->recv_buf.mad;
1989 cm_id_priv = cm_acquire_id(rep_msg->remote_comm_id, 0); 2049 cm_id_priv = cm_acquire_id(rep_msg->remote_comm_id, 0);
@@ -2018,16 +2078,26 @@ static int cm_rep_handler(struct cm_work *work)
2018 goto error; 2078 goto error;
2019 } 2079 }
2020 /* Check for a stale connection. */ 2080 /* Check for a stale connection. */
2021 if (cm_insert_remote_qpn(cm_id_priv->timewait_info)) { 2081 timewait_info = cm_insert_remote_qpn(cm_id_priv->timewait_info);
2082 if (timewait_info) {
2022 rb_erase(&cm_id_priv->timewait_info->remote_id_node, 2083 rb_erase(&cm_id_priv->timewait_info->remote_id_node,
2023 &cm.remote_id_table); 2084 &cm.remote_id_table);
2024 cm_id_priv->timewait_info->inserted_remote_id = 0; 2085 cm_id_priv->timewait_info->inserted_remote_id = 0;
2086 cur_cm_id_priv = cm_get_id(timewait_info->work.local_id,
2087 timewait_info->work.remote_id);
2088
2025 spin_unlock(&cm.lock); 2089 spin_unlock(&cm.lock);
2026 spin_unlock_irq(&cm_id_priv->lock); 2090 spin_unlock_irq(&cm_id_priv->lock);
2027 cm_issue_rej(work->port, work->mad_recv_wc, 2091 cm_issue_rej(work->port, work->mad_recv_wc,
2028 IB_CM_REJ_STALE_CONN, CM_MSG_RESPONSE_REP, 2092 IB_CM_REJ_STALE_CONN, CM_MSG_RESPONSE_REP,
2029 NULL, 0); 2093 NULL, 0);
2030 ret = -EINVAL; 2094 ret = -EINVAL;
2095 if (cur_cm_id_priv) {
2096 cm_id = &cur_cm_id_priv->id;
2097 ib_send_cm_dreq(cm_id, NULL, 0);
2098 cm_deref_id(cur_cm_id_priv);
2099 }
2100
2031 goto error; 2101 goto error;
2032 } 2102 }
2033 spin_unlock(&cm.lock); 2103 spin_unlock(&cm.lock);
diff --git a/drivers/infiniband/core/cma.c b/drivers/infiniband/core/cma.c
index 22fcf284dd8b..e7dcfac877ca 100644
--- a/drivers/infiniband/core/cma.c
+++ b/drivers/infiniband/core/cma.c
@@ -101,6 +101,49 @@ const char *__attribute_const__ rdma_event_msg(enum rdma_cm_event_type event)
101} 101}
102EXPORT_SYMBOL(rdma_event_msg); 102EXPORT_SYMBOL(rdma_event_msg);
103 103
104const char *__attribute_const__ rdma_reject_msg(struct rdma_cm_id *id,
105 int reason)
106{
107 if (rdma_ib_or_roce(id->device, id->port_num))
108 return ibcm_reject_msg(reason);
109
110 if (rdma_protocol_iwarp(id->device, id->port_num))
111 return iwcm_reject_msg(reason);
112
113 WARN_ON_ONCE(1);
114 return "unrecognized transport";
115}
116EXPORT_SYMBOL(rdma_reject_msg);
117
118bool rdma_is_consumer_reject(struct rdma_cm_id *id, int reason)
119{
120 if (rdma_ib_or_roce(id->device, id->port_num))
121 return reason == IB_CM_REJ_CONSUMER_DEFINED;
122
123 if (rdma_protocol_iwarp(id->device, id->port_num))
124 return reason == -ECONNREFUSED;
125
126 WARN_ON_ONCE(1);
127 return false;
128}
129EXPORT_SYMBOL(rdma_is_consumer_reject);
130
131const void *rdma_consumer_reject_data(struct rdma_cm_id *id,
132 struct rdma_cm_event *ev, u8 *data_len)
133{
134 const void *p;
135
136 if (rdma_is_consumer_reject(id, ev->status)) {
137 *data_len = ev->param.conn.private_data_len;
138 p = ev->param.conn.private_data;
139 } else {
140 *data_len = 0;
141 p = NULL;
142 }
143 return p;
144}
145EXPORT_SYMBOL(rdma_consumer_reject_data);
146
104static void cma_add_one(struct ib_device *device); 147static void cma_add_one(struct ib_device *device);
105static void cma_remove_one(struct ib_device *device, void *client_data); 148static void cma_remove_one(struct ib_device *device, void *client_data);
106 149
diff --git a/drivers/infiniband/core/core_priv.h b/drivers/infiniband/core/core_priv.h
index 0c0bea091de8..d29372624f3a 100644
--- a/drivers/infiniband/core/core_priv.h
+++ b/drivers/infiniband/core/core_priv.h
@@ -72,9 +72,6 @@ void ib_device_unregister_sysfs(struct ib_device *device);
72void ib_cache_setup(void); 72void ib_cache_setup(void);
73void ib_cache_cleanup(void); 73void ib_cache_cleanup(void);
74 74
75int ib_resolve_eth_dmac(struct ib_qp *qp,
76 struct ib_qp_attr *qp_attr, int *qp_attr_mask);
77
78typedef void (*roce_netdev_callback)(struct ib_device *device, u8 port, 75typedef void (*roce_netdev_callback)(struct ib_device *device, u8 port,
79 struct net_device *idev, void *cookie); 76 struct net_device *idev, void *cookie);
80 77
diff --git a/drivers/infiniband/core/device.c b/drivers/infiniband/core/device.c
index 760ef603a468..571974cd3919 100644
--- a/drivers/infiniband/core/device.c
+++ b/drivers/infiniband/core/device.c
@@ -254,11 +254,8 @@ static int add_client_context(struct ib_device *device, struct ib_client *client
254 unsigned long flags; 254 unsigned long flags;
255 255
256 context = kmalloc(sizeof *context, GFP_KERNEL); 256 context = kmalloc(sizeof *context, GFP_KERNEL);
257 if (!context) { 257 if (!context)
258 pr_warn("Couldn't allocate client context for %s/%s\n",
259 device->name, client->name);
260 return -ENOMEM; 258 return -ENOMEM;
261 }
262 259
263 context->client = client; 260 context->client = client;
264 context->data = NULL; 261 context->data = NULL;
diff --git a/drivers/infiniband/core/fmr_pool.c b/drivers/infiniband/core/fmr_pool.c
index cdbb1f1a6d97..cdfad5f26212 100644
--- a/drivers/infiniband/core/fmr_pool.c
+++ b/drivers/infiniband/core/fmr_pool.c
@@ -247,7 +247,6 @@ struct ib_fmr_pool *ib_create_fmr_pool(struct ib_pd *pd,
247 kmalloc(IB_FMR_HASH_SIZE * sizeof *pool->cache_bucket, 247 kmalloc(IB_FMR_HASH_SIZE * sizeof *pool->cache_bucket,
248 GFP_KERNEL); 248 GFP_KERNEL);
249 if (!pool->cache_bucket) { 249 if (!pool->cache_bucket) {
250 pr_warn(PFX "Failed to allocate cache in pool\n");
251 ret = -ENOMEM; 250 ret = -ENOMEM;
252 goto out_free_pool; 251 goto out_free_pool;
253 } 252 }
diff --git a/drivers/infiniband/core/iwcm.c b/drivers/infiniband/core/iwcm.c
index 5495e22839a7..31661b5c1743 100644
--- a/drivers/infiniband/core/iwcm.c
+++ b/drivers/infiniband/core/iwcm.c
@@ -59,6 +59,27 @@ MODULE_AUTHOR("Tom Tucker");
59MODULE_DESCRIPTION("iWARP CM"); 59MODULE_DESCRIPTION("iWARP CM");
60MODULE_LICENSE("Dual BSD/GPL"); 60MODULE_LICENSE("Dual BSD/GPL");
61 61
62static const char * const iwcm_rej_reason_strs[] = {
63 [ECONNRESET] = "reset by remote host",
64 [ECONNREFUSED] = "refused by remote application",
65 [ETIMEDOUT] = "setup timeout",
66};
67
68const char *__attribute_const__ iwcm_reject_msg(int reason)
69{
70 size_t index;
71
72 /* iWARP uses negative errnos */
73 index = -reason;
74
75 if (index < ARRAY_SIZE(iwcm_rej_reason_strs) &&
76 iwcm_rej_reason_strs[index])
77 return iwcm_rej_reason_strs[index];
78 else
79 return "unrecognized reason";
80}
81EXPORT_SYMBOL(iwcm_reject_msg);
82
62static struct ibnl_client_cbs iwcm_nl_cb_table[] = { 83static struct ibnl_client_cbs iwcm_nl_cb_table[] = {
63 [RDMA_NL_IWPM_REG_PID] = {.dump = iwpm_register_pid_cb}, 84 [RDMA_NL_IWPM_REG_PID] = {.dump = iwpm_register_pid_cb},
64 [RDMA_NL_IWPM_ADD_MAPPING] = {.dump = iwpm_add_mapping_cb}, 85 [RDMA_NL_IWPM_ADD_MAPPING] = {.dump = iwpm_add_mapping_cb},
diff --git a/drivers/infiniband/core/iwpm_msg.c b/drivers/infiniband/core/iwpm_msg.c
index 1c41b95cefec..a0e7c16d8bd8 100644
--- a/drivers/infiniband/core/iwpm_msg.c
+++ b/drivers/infiniband/core/iwpm_msg.c
@@ -604,7 +604,6 @@ int iwpm_remote_info_cb(struct sk_buff *skb, struct netlink_callback *cb)
604 } 604 }
605 rem_info = kzalloc(sizeof(struct iwpm_remote_info), GFP_ATOMIC); 605 rem_info = kzalloc(sizeof(struct iwpm_remote_info), GFP_ATOMIC);
606 if (!rem_info) { 606 if (!rem_info) {
607 pr_err("%s: Unable to allocate a remote info\n", __func__);
608 ret = -ENOMEM; 607 ret = -ENOMEM;
609 return ret; 608 return ret;
610 } 609 }
diff --git a/drivers/infiniband/core/iwpm_util.c b/drivers/infiniband/core/iwpm_util.c
index ade71e7f0131..3ef51a96bbf1 100644
--- a/drivers/infiniband/core/iwpm_util.c
+++ b/drivers/infiniband/core/iwpm_util.c
@@ -62,7 +62,6 @@ int iwpm_init(u8 nl_client)
62 sizeof(struct hlist_head), GFP_KERNEL); 62 sizeof(struct hlist_head), GFP_KERNEL);
63 if (!iwpm_hash_bucket) { 63 if (!iwpm_hash_bucket) {
64 ret = -ENOMEM; 64 ret = -ENOMEM;
65 pr_err("%s Unable to create mapinfo hash table\n", __func__);
66 goto init_exit; 65 goto init_exit;
67 } 66 }
68 iwpm_reminfo_bucket = kzalloc(IWPM_REMINFO_HASH_SIZE * 67 iwpm_reminfo_bucket = kzalloc(IWPM_REMINFO_HASH_SIZE *
@@ -70,7 +69,6 @@ int iwpm_init(u8 nl_client)
70 if (!iwpm_reminfo_bucket) { 69 if (!iwpm_reminfo_bucket) {
71 kfree(iwpm_hash_bucket); 70 kfree(iwpm_hash_bucket);
72 ret = -ENOMEM; 71 ret = -ENOMEM;
73 pr_err("%s Unable to create reminfo hash table\n", __func__);
74 goto init_exit; 72 goto init_exit;
75 } 73 }
76 } 74 }
@@ -128,10 +126,9 @@ int iwpm_create_mapinfo(struct sockaddr_storage *local_sockaddr,
128 if (!iwpm_valid_client(nl_client)) 126 if (!iwpm_valid_client(nl_client))
129 return ret; 127 return ret;
130 map_info = kzalloc(sizeof(struct iwpm_mapping_info), GFP_KERNEL); 128 map_info = kzalloc(sizeof(struct iwpm_mapping_info), GFP_KERNEL);
131 if (!map_info) { 129 if (!map_info)
132 pr_err("%s: Unable to allocate a mapping info\n", __func__);
133 return -ENOMEM; 130 return -ENOMEM;
134 } 131
135 memcpy(&map_info->local_sockaddr, local_sockaddr, 132 memcpy(&map_info->local_sockaddr, local_sockaddr,
136 sizeof(struct sockaddr_storage)); 133 sizeof(struct sockaddr_storage));
137 memcpy(&map_info->mapped_sockaddr, mapped_sockaddr, 134 memcpy(&map_info->mapped_sockaddr, mapped_sockaddr,
@@ -309,10 +306,9 @@ struct iwpm_nlmsg_request *iwpm_get_nlmsg_request(__u32 nlmsg_seq,
309 unsigned long flags; 306 unsigned long flags;
310 307
311 nlmsg_request = kzalloc(sizeof(struct iwpm_nlmsg_request), gfp); 308 nlmsg_request = kzalloc(sizeof(struct iwpm_nlmsg_request), gfp);
312 if (!nlmsg_request) { 309 if (!nlmsg_request)
313 pr_err("%s Unable to allocate a nlmsg_request\n", __func__);
314 return NULL; 310 return NULL;
315 } 311
316 spin_lock_irqsave(&iwpm_nlmsg_req_lock, flags); 312 spin_lock_irqsave(&iwpm_nlmsg_req_lock, flags);
317 list_add_tail(&nlmsg_request->inprocess_list, &iwpm_nlmsg_req_list); 313 list_add_tail(&nlmsg_request->inprocess_list, &iwpm_nlmsg_req_list);
318 spin_unlock_irqrestore(&iwpm_nlmsg_req_lock, flags); 314 spin_unlock_irqrestore(&iwpm_nlmsg_req_lock, flags);
diff --git a/drivers/infiniband/core/mad.c b/drivers/infiniband/core/mad.c
index 40cbd6bdb73b..a009f7132c73 100644
--- a/drivers/infiniband/core/mad.c
+++ b/drivers/infiniband/core/mad.c
@@ -769,7 +769,7 @@ static int handle_outgoing_dr_smp(struct ib_mad_agent_private *mad_agent_priv,
769 * If we are at the start of the LID routed part, don't update the 769 * If we are at the start of the LID routed part, don't update the
770 * hop_ptr or hop_cnt. See section 14.2.2, Vol 1 IB spec. 770 * hop_ptr or hop_cnt. See section 14.2.2, Vol 1 IB spec.
771 */ 771 */
772 if (opa && smp->class_version == OPA_SMP_CLASS_VERSION) { 772 if (opa && smp->class_version == OPA_SM_CLASS_VERSION) {
773 u32 opa_drslid; 773 u32 opa_drslid;
774 774
775 if ((opa_get_smp_direction(opa_smp) 775 if ((opa_get_smp_direction(opa_smp)
@@ -816,7 +816,6 @@ static int handle_outgoing_dr_smp(struct ib_mad_agent_private *mad_agent_priv,
816 local = kmalloc(sizeof *local, GFP_ATOMIC); 816 local = kmalloc(sizeof *local, GFP_ATOMIC);
817 if (!local) { 817 if (!local) {
818 ret = -ENOMEM; 818 ret = -ENOMEM;
819 dev_err(&device->dev, "No memory for ib_mad_local_private\n");
820 goto out; 819 goto out;
821 } 820 }
822 local->mad_priv = NULL; 821 local->mad_priv = NULL;
@@ -824,7 +823,6 @@ static int handle_outgoing_dr_smp(struct ib_mad_agent_private *mad_agent_priv,
824 mad_priv = alloc_mad_private(mad_size, GFP_ATOMIC); 823 mad_priv = alloc_mad_private(mad_size, GFP_ATOMIC);
825 if (!mad_priv) { 824 if (!mad_priv) {
826 ret = -ENOMEM; 825 ret = -ENOMEM;
827 dev_err(&device->dev, "No memory for local response MAD\n");
828 kfree(local); 826 kfree(local);
829 goto out; 827 goto out;
830 } 828 }
@@ -947,9 +945,6 @@ static int alloc_send_rmpp_list(struct ib_mad_send_wr_private *send_wr,
947 for (left = send_buf->data_len + pad; left > 0; left -= seg_size) { 945 for (left = send_buf->data_len + pad; left > 0; left -= seg_size) {
948 seg = kmalloc(sizeof (*seg) + seg_size, gfp_mask); 946 seg = kmalloc(sizeof (*seg) + seg_size, gfp_mask);
949 if (!seg) { 947 if (!seg) {
950 dev_err(&send_buf->mad_agent->device->dev,
951 "alloc_send_rmpp_segs: RMPP mem alloc failed for len %zd, gfp %#x\n",
952 sizeof (*seg) + seg_size, gfp_mask);
953 free_send_rmpp_list(send_wr); 948 free_send_rmpp_list(send_wr);
954 return -ENOMEM; 949 return -ENOMEM;
955 } 950 }
@@ -1362,12 +1357,7 @@ static int allocate_method_table(struct ib_mad_mgmt_method_table **method)
1362{ 1357{
1363 /* Allocate management method table */ 1358 /* Allocate management method table */
1364 *method = kzalloc(sizeof **method, GFP_ATOMIC); 1359 *method = kzalloc(sizeof **method, GFP_ATOMIC);
1365 if (!*method) { 1360 return (*method) ? 0 : (-ENOMEM);
1366 pr_err("No memory for ib_mad_mgmt_method_table\n");
1367 return -ENOMEM;
1368 }
1369
1370 return 0;
1371} 1361}
1372 1362
1373/* 1363/*
@@ -1458,8 +1448,6 @@ static int add_nonoui_reg_req(struct ib_mad_reg_req *mad_reg_req,
1458 /* Allocate management class table for "new" class version */ 1448 /* Allocate management class table for "new" class version */
1459 *class = kzalloc(sizeof **class, GFP_ATOMIC); 1449 *class = kzalloc(sizeof **class, GFP_ATOMIC);
1460 if (!*class) { 1450 if (!*class) {
1461 dev_err(&agent_priv->agent.device->dev,
1462 "No memory for ib_mad_mgmt_class_table\n");
1463 ret = -ENOMEM; 1451 ret = -ENOMEM;
1464 goto error1; 1452 goto error1;
1465 } 1453 }
@@ -1524,22 +1512,16 @@ static int add_oui_reg_req(struct ib_mad_reg_req *mad_reg_req,
1524 if (!*vendor_table) { 1512 if (!*vendor_table) {
1525 /* Allocate mgmt vendor class table for "new" class version */ 1513 /* Allocate mgmt vendor class table for "new" class version */
1526 vendor = kzalloc(sizeof *vendor, GFP_ATOMIC); 1514 vendor = kzalloc(sizeof *vendor, GFP_ATOMIC);
1527 if (!vendor) { 1515 if (!vendor)
1528 dev_err(&agent_priv->agent.device->dev,
1529 "No memory for ib_mad_mgmt_vendor_class_table\n");
1530 goto error1; 1516 goto error1;
1531 }
1532 1517
1533 *vendor_table = vendor; 1518 *vendor_table = vendor;
1534 } 1519 }
1535 if (!(*vendor_table)->vendor_class[vclass]) { 1520 if (!(*vendor_table)->vendor_class[vclass]) {
1536 /* Allocate table for this management vendor class */ 1521 /* Allocate table for this management vendor class */
1537 vendor_class = kzalloc(sizeof *vendor_class, GFP_ATOMIC); 1522 vendor_class = kzalloc(sizeof *vendor_class, GFP_ATOMIC);
1538 if (!vendor_class) { 1523 if (!vendor_class)
1539 dev_err(&agent_priv->agent.device->dev,
1540 "No memory for ib_mad_mgmt_vendor_class\n");
1541 goto error2; 1524 goto error2;
1542 }
1543 1525
1544 (*vendor_table)->vendor_class[vclass] = vendor_class; 1526 (*vendor_table)->vendor_class[vclass] = vendor_class;
1545 } 1527 }
@@ -1746,7 +1728,7 @@ find_mad_agent(struct ib_mad_port_private *port_priv,
1746 if (!class) 1728 if (!class)
1747 goto out; 1729 goto out;
1748 if (convert_mgmt_class(mad_hdr->mgmt_class) >= 1730 if (convert_mgmt_class(mad_hdr->mgmt_class) >=
1749 IB_MGMT_MAX_METHODS) 1731 ARRAY_SIZE(class->method_table))
1750 goto out; 1732 goto out;
1751 method = class->method_table[convert_mgmt_class( 1733 method = class->method_table[convert_mgmt_class(
1752 mad_hdr->mgmt_class)]; 1734 mad_hdr->mgmt_class)];
@@ -2167,7 +2149,7 @@ handle_smi(struct ib_mad_port_private *port_priv,
2167 struct ib_mad_hdr *mad_hdr = (struct ib_mad_hdr *)recv->mad; 2149 struct ib_mad_hdr *mad_hdr = (struct ib_mad_hdr *)recv->mad;
2168 2150
2169 if (opa && mad_hdr->base_version == OPA_MGMT_BASE_VERSION && 2151 if (opa && mad_hdr->base_version == OPA_MGMT_BASE_VERSION &&
2170 mad_hdr->class_version == OPA_SMI_CLASS_VERSION) 2152 mad_hdr->class_version == OPA_SM_CLASS_VERSION)
2171 return handle_opa_smi(port_priv, qp_info, wc, port_num, recv, 2153 return handle_opa_smi(port_priv, qp_info, wc, port_num, recv,
2172 response); 2154 response);
2173 2155
@@ -2238,11 +2220,8 @@ static void ib_mad_recv_done(struct ib_cq *cq, struct ib_wc *wc)
2238 2220
2239 mad_size = recv->mad_size; 2221 mad_size = recv->mad_size;
2240 response = alloc_mad_private(mad_size, GFP_KERNEL); 2222 response = alloc_mad_private(mad_size, GFP_KERNEL);
2241 if (!response) { 2223 if (!response)
2242 dev_err(&port_priv->device->dev,
2243 "%s: no memory for response buffer\n", __func__);
2244 goto out; 2224 goto out;
2245 }
2246 2225
2247 if (rdma_cap_ib_switch(port_priv->device)) 2226 if (rdma_cap_ib_switch(port_priv->device))
2248 port_num = wc->port_num; 2227 port_num = wc->port_num;
@@ -2869,8 +2848,6 @@ static int ib_mad_post_receive_mads(struct ib_mad_qp_info *qp_info,
2869 mad_priv = alloc_mad_private(port_mad_size(qp_info->port_priv), 2848 mad_priv = alloc_mad_private(port_mad_size(qp_info->port_priv),
2870 GFP_ATOMIC); 2849 GFP_ATOMIC);
2871 if (!mad_priv) { 2850 if (!mad_priv) {
2872 dev_err(&qp_info->port_priv->device->dev,
2873 "No memory for receive buffer\n");
2874 ret = -ENOMEM; 2851 ret = -ENOMEM;
2875 break; 2852 break;
2876 } 2853 }
@@ -2961,11 +2938,8 @@ static int ib_mad_port_start(struct ib_mad_port_private *port_priv)
2961 u16 pkey_index; 2938 u16 pkey_index;
2962 2939
2963 attr = kmalloc(sizeof *attr, GFP_KERNEL); 2940 attr = kmalloc(sizeof *attr, GFP_KERNEL);
2964 if (!attr) { 2941 if (!attr)
2965 dev_err(&port_priv->device->dev,
2966 "Couldn't kmalloc ib_qp_attr\n");
2967 return -ENOMEM; 2942 return -ENOMEM;
2968 }
2969 2943
2970 ret = ib_find_pkey(port_priv->device, port_priv->port_num, 2944 ret = ib_find_pkey(port_priv->device, port_priv->port_num,
2971 IB_DEFAULT_PKEY_FULL, &pkey_index); 2945 IB_DEFAULT_PKEY_FULL, &pkey_index);
@@ -3135,10 +3109,8 @@ static int ib_mad_port_open(struct ib_device *device,
3135 3109
3136 /* Create new device info */ 3110 /* Create new device info */
3137 port_priv = kzalloc(sizeof *port_priv, GFP_KERNEL); 3111 port_priv = kzalloc(sizeof *port_priv, GFP_KERNEL);
3138 if (!port_priv) { 3112 if (!port_priv)
3139 dev_err(&device->dev, "No memory for ib_mad_port_private\n");
3140 return -ENOMEM; 3113 return -ENOMEM;
3141 }
3142 3114
3143 port_priv->device = device; 3115 port_priv->device = device;
3144 port_priv->port_num = port_num; 3116 port_priv->port_num = port_num;
diff --git a/drivers/infiniband/core/multicast.c b/drivers/infiniband/core/multicast.c
index e51b739f6ea3..322cb67b07a9 100644
--- a/drivers/infiniband/core/multicast.c
+++ b/drivers/infiniband/core/multicast.c
@@ -518,8 +518,11 @@ static void join_handler(int status, struct ib_sa_mcmember_rec *rec,
518 process_join_error(group, status); 518 process_join_error(group, status);
519 else { 519 else {
520 int mgids_changed, is_mgid0; 520 int mgids_changed, is_mgid0;
521 ib_find_pkey(group->port->dev->device, group->port->port_num, 521
522 be16_to_cpu(rec->pkey), &pkey_index); 522 if (ib_find_pkey(group->port->dev->device,
523 group->port->port_num, be16_to_cpu(rec->pkey),
524 &pkey_index))
525 pkey_index = MCAST_INVALID_PKEY_INDEX;
523 526
524 spin_lock_irq(&group->port->lock); 527 spin_lock_irq(&group->port->lock);
525 if (group->state == MCAST_BUSY && 528 if (group->state == MCAST_BUSY &&
diff --git a/drivers/infiniband/core/roce_gid_mgmt.c b/drivers/infiniband/core/roce_gid_mgmt.c
index 3a64a0881882..0621f4455732 100644
--- a/drivers/infiniband/core/roce_gid_mgmt.c
+++ b/drivers/infiniband/core/roce_gid_mgmt.c
@@ -304,10 +304,9 @@ static void enum_netdev_ipv4_ips(struct ib_device *ib_dev,
304 for_ifa(in_dev) { 304 for_ifa(in_dev) {
305 struct sin_list *entry = kzalloc(sizeof(*entry), GFP_ATOMIC); 305 struct sin_list *entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
306 306
307 if (!entry) { 307 if (!entry)
308 pr_warn("roce_gid_mgmt: couldn't allocate entry for IPv4 update\n");
309 continue; 308 continue;
310 } 309
311 entry->ip.sin_family = AF_INET; 310 entry->ip.sin_family = AF_INET;
312 entry->ip.sin_addr.s_addr = ifa->ifa_address; 311 entry->ip.sin_addr.s_addr = ifa->ifa_address;
313 list_add_tail(&entry->list, &sin_list); 312 list_add_tail(&entry->list, &sin_list);
@@ -348,10 +347,8 @@ static void enum_netdev_ipv6_ips(struct ib_device *ib_dev,
348 list_for_each_entry(ifp, &in6_dev->addr_list, if_list) { 347 list_for_each_entry(ifp, &in6_dev->addr_list, if_list) {
349 struct sin6_list *entry = kzalloc(sizeof(*entry), GFP_ATOMIC); 348 struct sin6_list *entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
350 349
351 if (!entry) { 350 if (!entry)
352 pr_warn("roce_gid_mgmt: couldn't allocate entry for IPv6 update\n");
353 continue; 351 continue;
354 }
355 352
356 entry->sin6.sin6_family = AF_INET6; 353 entry->sin6.sin6_family = AF_INET6;
357 entry->sin6.sin6_addr = ifp->addr; 354 entry->sin6.sin6_addr = ifp->addr;
@@ -447,10 +444,8 @@ static int netdev_upper_walk(struct net_device *upper, void *data)
447 struct upper_list *entry = kmalloc(sizeof(*entry), GFP_ATOMIC); 444 struct upper_list *entry = kmalloc(sizeof(*entry), GFP_ATOMIC);
448 struct list_head *upper_list = data; 445 struct list_head *upper_list = data;
449 446
450 if (!entry) { 447 if (!entry)
451 pr_info("roce_gid_mgmt: couldn't allocate entry to delete ndev\n");
452 return 0; 448 return 0;
453 }
454 449
455 list_add_tail(&entry->list, upper_list); 450 list_add_tail(&entry->list, upper_list);
456 dev_hold(upper); 451 dev_hold(upper);
@@ -559,10 +554,8 @@ static int netdevice_queue_work(struct netdev_event_work_cmd *cmds,
559 struct netdev_event_work *ndev_work = 554 struct netdev_event_work *ndev_work =
560 kmalloc(sizeof(*ndev_work), GFP_KERNEL); 555 kmalloc(sizeof(*ndev_work), GFP_KERNEL);
561 556
562 if (!ndev_work) { 557 if (!ndev_work)
563 pr_warn("roce_gid_mgmt: can't allocate work for netdevice_event\n");
564 return NOTIFY_DONE; 558 return NOTIFY_DONE;
565 }
566 559
567 memcpy(ndev_work->cmds, cmds, sizeof(ndev_work->cmds)); 560 memcpy(ndev_work->cmds, cmds, sizeof(ndev_work->cmds));
568 for (i = 0; i < ARRAY_SIZE(ndev_work->cmds) && ndev_work->cmds[i].cb; i++) { 561 for (i = 0; i < ARRAY_SIZE(ndev_work->cmds) && ndev_work->cmds[i].cb; i++) {
@@ -696,10 +689,8 @@ static int addr_event(struct notifier_block *this, unsigned long event,
696 } 689 }
697 690
698 work = kmalloc(sizeof(*work), GFP_ATOMIC); 691 work = kmalloc(sizeof(*work), GFP_ATOMIC);
699 if (!work) { 692 if (!work)
700 pr_warn("roce_gid_mgmt: Couldn't allocate work for addr_event\n");
701 return NOTIFY_DONE; 693 return NOTIFY_DONE;
702 }
703 694
704 INIT_WORK(&work->work, update_gid_event_work_handler); 695 INIT_WORK(&work->work, update_gid_event_work_handler);
705 696
diff --git a/drivers/infiniband/core/ucm.c b/drivers/infiniband/core/ucm.c
index 7713ef089c3c..579f9a7f6283 100644
--- a/drivers/infiniband/core/ucm.c
+++ b/drivers/infiniband/core/ucm.c
@@ -1104,8 +1104,11 @@ static ssize_t ib_ucm_write(struct file *filp, const char __user *buf,
1104 struct ib_ucm_cmd_hdr hdr; 1104 struct ib_ucm_cmd_hdr hdr;
1105 ssize_t result; 1105 ssize_t result;
1106 1106
1107 if (WARN_ON_ONCE(!ib_safe_file_access(filp))) 1107 if (!ib_safe_file_access(filp)) {
1108 pr_err_once("ucm_write: process %d (%s) changed security contexts after opening file descriptor, this is not allowed.\n",
1109 task_tgid_vnr(current), current->comm);
1108 return -EACCES; 1110 return -EACCES;
1111 }
1109 1112
1110 if (len < sizeof(hdr)) 1113 if (len < sizeof(hdr))
1111 return -EINVAL; 1114 return -EINVAL;
diff --git a/drivers/infiniband/core/ucma.c b/drivers/infiniband/core/ucma.c
index 9520154f1d7c..e12f8faf8c23 100644
--- a/drivers/infiniband/core/ucma.c
+++ b/drivers/infiniband/core/ucma.c
@@ -1584,8 +1584,11 @@ static ssize_t ucma_write(struct file *filp, const char __user *buf,
1584 struct rdma_ucm_cmd_hdr hdr; 1584 struct rdma_ucm_cmd_hdr hdr;
1585 ssize_t ret; 1585 ssize_t ret;
1586 1586
1587 if (WARN_ON_ONCE(!ib_safe_file_access(filp))) 1587 if (!ib_safe_file_access(filp)) {
1588 pr_err_once("ucma_write: process %d (%s) changed security contexts after opening file descriptor, this is not allowed.\n",
1589 task_tgid_vnr(current), current->comm);
1588 return -EACCES; 1590 return -EACCES;
1591 }
1589 1592
1590 if (len < sizeof(hdr)) 1593 if (len < sizeof(hdr))
1591 return -EINVAL; 1594 return -EINVAL;
diff --git a/drivers/infiniband/core/umem.c b/drivers/infiniband/core/umem.c
index 84b4eff90395..1e62a5f0cb28 100644
--- a/drivers/infiniband/core/umem.c
+++ b/drivers/infiniband/core/umem.c
@@ -51,7 +51,7 @@ static void __ib_umem_release(struct ib_device *dev, struct ib_umem *umem, int d
51 51
52 if (umem->nmap > 0) 52 if (umem->nmap > 0)
53 ib_dma_unmap_sg(dev, umem->sg_head.sgl, 53 ib_dma_unmap_sg(dev, umem->sg_head.sgl,
54 umem->nmap, 54 umem->npages,
55 DMA_BIDIRECTIONAL); 55 DMA_BIDIRECTIONAL);
56 56
57 for_each_sg(umem->sg_head.sgl, sg, umem->npages, i) { 57 for_each_sg(umem->sg_head.sgl, sg, umem->npages, i) {
diff --git a/drivers/infiniband/core/uverbs.h b/drivers/infiniband/core/uverbs.h
index df26a741cda6..455034ac994e 100644
--- a/drivers/infiniband/core/uverbs.h
+++ b/drivers/infiniband/core/uverbs.h
@@ -289,5 +289,6 @@ IB_UVERBS_DECLARE_EX_CMD(modify_wq);
289IB_UVERBS_DECLARE_EX_CMD(destroy_wq); 289IB_UVERBS_DECLARE_EX_CMD(destroy_wq);
290IB_UVERBS_DECLARE_EX_CMD(create_rwq_ind_table); 290IB_UVERBS_DECLARE_EX_CMD(create_rwq_ind_table);
291IB_UVERBS_DECLARE_EX_CMD(destroy_rwq_ind_table); 291IB_UVERBS_DECLARE_EX_CMD(destroy_rwq_ind_table);
292IB_UVERBS_DECLARE_EX_CMD(modify_qp);
292 293
293#endif /* UVERBS_H */ 294#endif /* UVERBS_H */
diff --git a/drivers/infiniband/core/uverbs_cmd.c b/drivers/infiniband/core/uverbs_cmd.c
index cb3f515a2285..09b649159e6c 100644
--- a/drivers/infiniband/core/uverbs_cmd.c
+++ b/drivers/infiniband/core/uverbs_cmd.c
@@ -2328,94 +2328,88 @@ static int modify_qp_mask(enum ib_qp_type qp_type, int mask)
2328 } 2328 }
2329} 2329}
2330 2330
2331ssize_t ib_uverbs_modify_qp(struct ib_uverbs_file *file, 2331static int modify_qp(struct ib_uverbs_file *file,
2332 struct ib_device *ib_dev, 2332 struct ib_uverbs_ex_modify_qp *cmd, struct ib_udata *udata)
2333 const char __user *buf, int in_len,
2334 int out_len)
2335{ 2333{
2336 struct ib_uverbs_modify_qp cmd; 2334 struct ib_qp_attr *attr;
2337 struct ib_udata udata; 2335 struct ib_qp *qp;
2338 struct ib_qp *qp; 2336 int ret;
2339 struct ib_qp_attr *attr;
2340 int ret;
2341
2342 if (copy_from_user(&cmd, buf, sizeof cmd))
2343 return -EFAULT;
2344
2345 INIT_UDATA(&udata, buf + sizeof cmd, NULL, in_len - sizeof cmd,
2346 out_len);
2347 2337
2348 attr = kmalloc(sizeof *attr, GFP_KERNEL); 2338 attr = kmalloc(sizeof *attr, GFP_KERNEL);
2349 if (!attr) 2339 if (!attr)
2350 return -ENOMEM; 2340 return -ENOMEM;
2351 2341
2352 qp = idr_read_qp(cmd.qp_handle, file->ucontext); 2342 qp = idr_read_qp(cmd->base.qp_handle, file->ucontext);
2353 if (!qp) { 2343 if (!qp) {
2354 ret = -EINVAL; 2344 ret = -EINVAL;
2355 goto out; 2345 goto out;
2356 } 2346 }
2357 2347
2358 attr->qp_state = cmd.qp_state; 2348 attr->qp_state = cmd->base.qp_state;
2359 attr->cur_qp_state = cmd.cur_qp_state; 2349 attr->cur_qp_state = cmd->base.cur_qp_state;
2360 attr->path_mtu = cmd.path_mtu; 2350 attr->path_mtu = cmd->base.path_mtu;
2361 attr->path_mig_state = cmd.path_mig_state; 2351 attr->path_mig_state = cmd->base.path_mig_state;
2362 attr->qkey = cmd.qkey; 2352 attr->qkey = cmd->base.qkey;
2363 attr->rq_psn = cmd.rq_psn; 2353 attr->rq_psn = cmd->base.rq_psn;
2364 attr->sq_psn = cmd.sq_psn; 2354 attr->sq_psn = cmd->base.sq_psn;
2365 attr->dest_qp_num = cmd.dest_qp_num; 2355 attr->dest_qp_num = cmd->base.dest_qp_num;
2366 attr->qp_access_flags = cmd.qp_access_flags; 2356 attr->qp_access_flags = cmd->base.qp_access_flags;
2367 attr->pkey_index = cmd.pkey_index; 2357 attr->pkey_index = cmd->base.pkey_index;
2368 attr->alt_pkey_index = cmd.alt_pkey_index; 2358 attr->alt_pkey_index = cmd->base.alt_pkey_index;
2369 attr->en_sqd_async_notify = cmd.en_sqd_async_notify; 2359 attr->en_sqd_async_notify = cmd->base.en_sqd_async_notify;
2370 attr->max_rd_atomic = cmd.max_rd_atomic; 2360 attr->max_rd_atomic = cmd->base.max_rd_atomic;
2371 attr->max_dest_rd_atomic = cmd.max_dest_rd_atomic; 2361 attr->max_dest_rd_atomic = cmd->base.max_dest_rd_atomic;
2372 attr->min_rnr_timer = cmd.min_rnr_timer; 2362 attr->min_rnr_timer = cmd->base.min_rnr_timer;
2373 attr->port_num = cmd.port_num; 2363 attr->port_num = cmd->base.port_num;
2374 attr->timeout = cmd.timeout; 2364 attr->timeout = cmd->base.timeout;
2375 attr->retry_cnt = cmd.retry_cnt; 2365 attr->retry_cnt = cmd->base.retry_cnt;
2376 attr->rnr_retry = cmd.rnr_retry; 2366 attr->rnr_retry = cmd->base.rnr_retry;
2377 attr->alt_port_num = cmd.alt_port_num; 2367 attr->alt_port_num = cmd->base.alt_port_num;
2378 attr->alt_timeout = cmd.alt_timeout; 2368 attr->alt_timeout = cmd->base.alt_timeout;
2379 2369 attr->rate_limit = cmd->rate_limit;
2380 memcpy(attr->ah_attr.grh.dgid.raw, cmd.dest.dgid, 16); 2370
2381 attr->ah_attr.grh.flow_label = cmd.dest.flow_label; 2371 memcpy(attr->ah_attr.grh.dgid.raw, cmd->base.dest.dgid, 16);
2382 attr->ah_attr.grh.sgid_index = cmd.dest.sgid_index; 2372 attr->ah_attr.grh.flow_label = cmd->base.dest.flow_label;
2383 attr->ah_attr.grh.hop_limit = cmd.dest.hop_limit; 2373 attr->ah_attr.grh.sgid_index = cmd->base.dest.sgid_index;
2384 attr->ah_attr.grh.traffic_class = cmd.dest.traffic_class; 2374 attr->ah_attr.grh.hop_limit = cmd->base.dest.hop_limit;
2385 attr->ah_attr.dlid = cmd.dest.dlid; 2375 attr->ah_attr.grh.traffic_class = cmd->base.dest.traffic_class;
2386 attr->ah_attr.sl = cmd.dest.sl; 2376 attr->ah_attr.dlid = cmd->base.dest.dlid;
2387 attr->ah_attr.src_path_bits = cmd.dest.src_path_bits; 2377 attr->ah_attr.sl = cmd->base.dest.sl;
2388 attr->ah_attr.static_rate = cmd.dest.static_rate; 2378 attr->ah_attr.src_path_bits = cmd->base.dest.src_path_bits;
2389 attr->ah_attr.ah_flags = cmd.dest.is_global ? IB_AH_GRH : 0; 2379 attr->ah_attr.static_rate = cmd->base.dest.static_rate;
2390 attr->ah_attr.port_num = cmd.dest.port_num; 2380 attr->ah_attr.ah_flags = cmd->base.dest.is_global ?
2391 2381 IB_AH_GRH : 0;
2392 memcpy(attr->alt_ah_attr.grh.dgid.raw, cmd.alt_dest.dgid, 16); 2382 attr->ah_attr.port_num = cmd->base.dest.port_num;
2393 attr->alt_ah_attr.grh.flow_label = cmd.alt_dest.flow_label; 2383
2394 attr->alt_ah_attr.grh.sgid_index = cmd.alt_dest.sgid_index; 2384 memcpy(attr->alt_ah_attr.grh.dgid.raw, cmd->base.alt_dest.dgid, 16);
2395 attr->alt_ah_attr.grh.hop_limit = cmd.alt_dest.hop_limit; 2385 attr->alt_ah_attr.grh.flow_label = cmd->base.alt_dest.flow_label;
2396 attr->alt_ah_attr.grh.traffic_class = cmd.alt_dest.traffic_class; 2386 attr->alt_ah_attr.grh.sgid_index = cmd->base.alt_dest.sgid_index;
2397 attr->alt_ah_attr.dlid = cmd.alt_dest.dlid; 2387 attr->alt_ah_attr.grh.hop_limit = cmd->base.alt_dest.hop_limit;
2398 attr->alt_ah_attr.sl = cmd.alt_dest.sl; 2388 attr->alt_ah_attr.grh.traffic_class = cmd->base.alt_dest.traffic_class;
2399 attr->alt_ah_attr.src_path_bits = cmd.alt_dest.src_path_bits; 2389 attr->alt_ah_attr.dlid = cmd->base.alt_dest.dlid;
2400 attr->alt_ah_attr.static_rate = cmd.alt_dest.static_rate; 2390 attr->alt_ah_attr.sl = cmd->base.alt_dest.sl;
2401 attr->alt_ah_attr.ah_flags = cmd.alt_dest.is_global ? IB_AH_GRH : 0; 2391 attr->alt_ah_attr.src_path_bits = cmd->base.alt_dest.src_path_bits;
2402 attr->alt_ah_attr.port_num = cmd.alt_dest.port_num; 2392 attr->alt_ah_attr.static_rate = cmd->base.alt_dest.static_rate;
2393 attr->alt_ah_attr.ah_flags = cmd->base.alt_dest.is_global ?
2394 IB_AH_GRH : 0;
2395 attr->alt_ah_attr.port_num = cmd->base.alt_dest.port_num;
2403 2396
2404 if (qp->real_qp == qp) { 2397 if (qp->real_qp == qp) {
2405 ret = ib_resolve_eth_dmac(qp, attr, &cmd.attr_mask); 2398 if (cmd->base.attr_mask & IB_QP_AV) {
2406 if (ret) 2399 ret = ib_resolve_eth_dmac(qp->device, &attr->ah_attr);
2407 goto release_qp; 2400 if (ret)
2401 goto release_qp;
2402 }
2408 ret = qp->device->modify_qp(qp, attr, 2403 ret = qp->device->modify_qp(qp, attr,
2409 modify_qp_mask(qp->qp_type, cmd.attr_mask), &udata); 2404 modify_qp_mask(qp->qp_type,
2405 cmd->base.attr_mask),
2406 udata);
2410 } else { 2407 } else {
2411 ret = ib_modify_qp(qp, attr, modify_qp_mask(qp->qp_type, cmd.attr_mask)); 2408 ret = ib_modify_qp(qp, attr,
2409 modify_qp_mask(qp->qp_type,
2410 cmd->base.attr_mask));
2412 } 2411 }
2413 2412
2414 if (ret)
2415 goto release_qp;
2416
2417 ret = in_len;
2418
2419release_qp: 2413release_qp:
2420 put_qp_read(qp); 2414 put_qp_read(qp);
2421 2415
@@ -2425,6 +2419,68 @@ out:
2425 return ret; 2419 return ret;
2426} 2420}
2427 2421
2422ssize_t ib_uverbs_modify_qp(struct ib_uverbs_file *file,
2423 struct ib_device *ib_dev,
2424 const char __user *buf, int in_len,
2425 int out_len)
2426{
2427 struct ib_uverbs_ex_modify_qp cmd = {};
2428 struct ib_udata udata;
2429 int ret;
2430
2431 if (copy_from_user(&cmd.base, buf, sizeof(cmd.base)))
2432 return -EFAULT;
2433
2434 if (cmd.base.attr_mask &
2435 ~((IB_USER_LEGACY_LAST_QP_ATTR_MASK << 1) - 1))
2436 return -EOPNOTSUPP;
2437
2438 INIT_UDATA(&udata, buf + sizeof(cmd.base), NULL,
2439 in_len - sizeof(cmd.base), out_len);
2440
2441 ret = modify_qp(file, &cmd, &udata);
2442 if (ret)
2443 return ret;
2444
2445 return in_len;
2446}
2447
2448int ib_uverbs_ex_modify_qp(struct ib_uverbs_file *file,
2449 struct ib_device *ib_dev,
2450 struct ib_udata *ucore,
2451 struct ib_udata *uhw)
2452{
2453 struct ib_uverbs_ex_modify_qp cmd = {};
2454 int ret;
2455
2456 /*
2457 * Last bit is reserved for extending the attr_mask by
2458 * using another field.
2459 */
2460 BUILD_BUG_ON(IB_USER_LAST_QP_ATTR_MASK == (1 << 31));
2461
2462 if (ucore->inlen < sizeof(cmd.base))
2463 return -EINVAL;
2464
2465 ret = ib_copy_from_udata(&cmd, ucore, min(sizeof(cmd), ucore->inlen));
2466 if (ret)
2467 return ret;
2468
2469 if (cmd.base.attr_mask &
2470 ~((IB_USER_LAST_QP_ATTR_MASK << 1) - 1))
2471 return -EOPNOTSUPP;
2472
2473 if (ucore->inlen > sizeof(cmd)) {
2474 if (ib_is_udata_cleared(ucore, sizeof(cmd),
2475 ucore->inlen - sizeof(cmd)))
2476 return -EOPNOTSUPP;
2477 }
2478
2479 ret = modify_qp(file, &cmd, uhw);
2480
2481 return ret;
2482}
2483
2428ssize_t ib_uverbs_destroy_qp(struct ib_uverbs_file *file, 2484ssize_t ib_uverbs_destroy_qp(struct ib_uverbs_file *file,
2429 struct ib_device *ib_dev, 2485 struct ib_device *ib_dev,
2430 const char __user *buf, int in_len, 2486 const char __user *buf, int in_len,
@@ -2875,6 +2931,7 @@ ssize_t ib_uverbs_create_ah(struct ib_uverbs_file *file,
2875 struct ib_ah *ah; 2931 struct ib_ah *ah;
2876 struct ib_ah_attr attr; 2932 struct ib_ah_attr attr;
2877 int ret; 2933 int ret;
2934 struct ib_udata udata;
2878 2935
2879 if (out_len < sizeof resp) 2936 if (out_len < sizeof resp)
2880 return -ENOSPC; 2937 return -ENOSPC;
@@ -2882,6 +2939,10 @@ ssize_t ib_uverbs_create_ah(struct ib_uverbs_file *file,
2882 if (copy_from_user(&cmd, buf, sizeof cmd)) 2939 if (copy_from_user(&cmd, buf, sizeof cmd))
2883 return -EFAULT; 2940 return -EFAULT;
2884 2941
2942 INIT_UDATA(&udata, buf + sizeof(cmd),
2943 (unsigned long)cmd.response + sizeof(resp),
2944 in_len - sizeof(cmd), out_len - sizeof(resp));
2945
2885 uobj = kmalloc(sizeof *uobj, GFP_KERNEL); 2946 uobj = kmalloc(sizeof *uobj, GFP_KERNEL);
2886 if (!uobj) 2947 if (!uobj)
2887 return -ENOMEM; 2948 return -ENOMEM;
@@ -2908,12 +2969,16 @@ ssize_t ib_uverbs_create_ah(struct ib_uverbs_file *file,
2908 memset(&attr.dmac, 0, sizeof(attr.dmac)); 2969 memset(&attr.dmac, 0, sizeof(attr.dmac));
2909 memcpy(attr.grh.dgid.raw, cmd.attr.grh.dgid, 16); 2970 memcpy(attr.grh.dgid.raw, cmd.attr.grh.dgid, 16);
2910 2971
2911 ah = ib_create_ah(pd, &attr); 2972 ah = pd->device->create_ah(pd, &attr, &udata);
2973
2912 if (IS_ERR(ah)) { 2974 if (IS_ERR(ah)) {
2913 ret = PTR_ERR(ah); 2975 ret = PTR_ERR(ah);
2914 goto err_put; 2976 goto err_put;
2915 } 2977 }
2916 2978
2979 ah->device = pd->device;
2980 ah->pd = pd;
2981 atomic_inc(&pd->usecnt);
2917 ah->uobject = uobj; 2982 ah->uobject = uobj;
2918 uobj->object = ah; 2983 uobj->object = ah;
2919 2984
@@ -3124,8 +3189,10 @@ static int kern_spec_to_ib_spec(struct ib_uverbs_flow_spec *kern_spec,
3124 kern_spec_val = (void *)kern_spec + 3189 kern_spec_val = (void *)kern_spec +
3125 sizeof(struct ib_uverbs_flow_spec_hdr); 3190 sizeof(struct ib_uverbs_flow_spec_hdr);
3126 kern_spec_mask = kern_spec_val + kern_filter_sz; 3191 kern_spec_mask = kern_spec_val + kern_filter_sz;
3192 if (ib_spec->type == (IB_FLOW_SPEC_INNER | IB_FLOW_SPEC_VXLAN_TUNNEL))
3193 return -EINVAL;
3127 3194
3128 switch (ib_spec->type) { 3195 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
3129 case IB_FLOW_SPEC_ETH: 3196 case IB_FLOW_SPEC_ETH:
3130 ib_filter_sz = offsetof(struct ib_flow_eth_filter, real_sz); 3197 ib_filter_sz = offsetof(struct ib_flow_eth_filter, real_sz);
3131 actual_filter_sz = spec_filter_size(kern_spec_mask, 3198 actual_filter_sz = spec_filter_size(kern_spec_mask,
@@ -3175,6 +3242,21 @@ static int kern_spec_to_ib_spec(struct ib_uverbs_flow_spec *kern_spec,
3175 memcpy(&ib_spec->tcp_udp.val, kern_spec_val, actual_filter_sz); 3242 memcpy(&ib_spec->tcp_udp.val, kern_spec_val, actual_filter_sz);
3176 memcpy(&ib_spec->tcp_udp.mask, kern_spec_mask, actual_filter_sz); 3243 memcpy(&ib_spec->tcp_udp.mask, kern_spec_mask, actual_filter_sz);
3177 break; 3244 break;
3245 case IB_FLOW_SPEC_VXLAN_TUNNEL:
3246 ib_filter_sz = offsetof(struct ib_flow_tunnel_filter, real_sz);
3247 actual_filter_sz = spec_filter_size(kern_spec_mask,
3248 kern_filter_sz,
3249 ib_filter_sz);
3250 if (actual_filter_sz <= 0)
3251 return -EINVAL;
3252 ib_spec->tunnel.size = sizeof(struct ib_flow_spec_tunnel);
3253 memcpy(&ib_spec->tunnel.val, kern_spec_val, actual_filter_sz);
3254 memcpy(&ib_spec->tunnel.mask, kern_spec_mask, actual_filter_sz);
3255
3256 if ((ntohl(ib_spec->tunnel.mask.tunnel_id)) >= BIT(24) ||
3257 (ntohl(ib_spec->tunnel.val.tunnel_id)) >= BIT(24))
3258 return -EINVAL;
3259 break;
3178 default: 3260 default:
3179 return -EINVAL; 3261 return -EINVAL;
3180 } 3262 }
@@ -3745,7 +3827,6 @@ int ib_uverbs_ex_create_flow(struct ib_uverbs_file *file,
3745 err = PTR_ERR(flow_id); 3827 err = PTR_ERR(flow_id);
3746 goto err_free; 3828 goto err_free;
3747 } 3829 }
3748 flow_id->qp = qp;
3749 flow_id->uobject = uobj; 3830 flow_id->uobject = uobj;
3750 uobj->object = flow_id; 3831 uobj->object = flow_id;
3751 3832
diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c
index 44b1104eb168..813593550c4b 100644
--- a/drivers/infiniband/core/uverbs_main.c
+++ b/drivers/infiniband/core/uverbs_main.c
@@ -137,6 +137,7 @@ static int (*uverbs_ex_cmd_table[])(struct ib_uverbs_file *file,
137 [IB_USER_VERBS_EX_CMD_DESTROY_WQ] = ib_uverbs_ex_destroy_wq, 137 [IB_USER_VERBS_EX_CMD_DESTROY_WQ] = ib_uverbs_ex_destroy_wq,
138 [IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL] = ib_uverbs_ex_create_rwq_ind_table, 138 [IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL] = ib_uverbs_ex_create_rwq_ind_table,
139 [IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL] = ib_uverbs_ex_destroy_rwq_ind_table, 139 [IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL] = ib_uverbs_ex_destroy_rwq_ind_table,
140 [IB_USER_VERBS_EX_CMD_MODIFY_QP] = ib_uverbs_ex_modify_qp,
140}; 141};
141 142
142static void ib_uverbs_add_one(struct ib_device *device); 143static void ib_uverbs_add_one(struct ib_device *device);
@@ -746,8 +747,11 @@ static ssize_t ib_uverbs_write(struct file *filp, const char __user *buf,
746 int srcu_key; 747 int srcu_key;
747 ssize_t ret; 748 ssize_t ret;
748 749
749 if (WARN_ON_ONCE(!ib_safe_file_access(filp))) 750 if (!ib_safe_file_access(filp)) {
751 pr_err_once("uverbs_write: process %d (%s) changed security contexts after opening file descriptor, this is not allowed.\n",
752 task_tgid_vnr(current), current->comm);
750 return -EACCES; 753 return -EACCES;
754 }
751 755
752 if (count < sizeof hdr) 756 if (count < sizeof hdr)
753 return -EINVAL; 757 return -EINVAL;
diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verbs.c
index 83687646da68..71580cc28c9e 100644
--- a/drivers/infiniband/core/verbs.c
+++ b/drivers/infiniband/core/verbs.c
@@ -315,7 +315,7 @@ struct ib_ah *ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr)
315{ 315{
316 struct ib_ah *ah; 316 struct ib_ah *ah;
317 317
318 ah = pd->device->create_ah(pd, ah_attr); 318 ah = pd->device->create_ah(pd, ah_attr, NULL);
319 319
320 if (!IS_ERR(ah)) { 320 if (!IS_ERR(ah)) {
321 ah->device = pd->device; 321 ah->device = pd->device;
@@ -328,7 +328,7 @@ struct ib_ah *ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr)
328} 328}
329EXPORT_SYMBOL(ib_create_ah); 329EXPORT_SYMBOL(ib_create_ah);
330 330
331static int ib_get_header_version(const union rdma_network_hdr *hdr) 331int ib_get_rdma_header_version(const union rdma_network_hdr *hdr)
332{ 332{
333 const struct iphdr *ip4h = (struct iphdr *)&hdr->roce4grh; 333 const struct iphdr *ip4h = (struct iphdr *)&hdr->roce4grh;
334 struct iphdr ip4h_checked; 334 struct iphdr ip4h_checked;
@@ -359,6 +359,7 @@ static int ib_get_header_version(const union rdma_network_hdr *hdr)
359 return 4; 359 return 4;
360 return 6; 360 return 6;
361} 361}
362EXPORT_SYMBOL(ib_get_rdma_header_version);
362 363
363static enum rdma_network_type ib_get_net_type_by_grh(struct ib_device *device, 364static enum rdma_network_type ib_get_net_type_by_grh(struct ib_device *device,
364 u8 port_num, 365 u8 port_num,
@@ -369,7 +370,7 @@ static enum rdma_network_type ib_get_net_type_by_grh(struct ib_device *device,
369 if (rdma_protocol_ib(device, port_num)) 370 if (rdma_protocol_ib(device, port_num))
370 return RDMA_NETWORK_IB; 371 return RDMA_NETWORK_IB;
371 372
372 grh_version = ib_get_header_version((union rdma_network_hdr *)grh); 373 grh_version = ib_get_rdma_header_version((union rdma_network_hdr *)grh);
373 374
374 if (grh_version == 4) 375 if (grh_version == 4)
375 return RDMA_NETWORK_IPV4; 376 return RDMA_NETWORK_IPV4;
@@ -415,9 +416,9 @@ static int get_sgid_index_from_eth(struct ib_device *device, u8 port_num,
415 &context, gid_index); 416 &context, gid_index);
416} 417}
417 418
418static int get_gids_from_rdma_hdr(union rdma_network_hdr *hdr, 419int ib_get_gids_from_rdma_hdr(const union rdma_network_hdr *hdr,
419 enum rdma_network_type net_type, 420 enum rdma_network_type net_type,
420 union ib_gid *sgid, union ib_gid *dgid) 421 union ib_gid *sgid, union ib_gid *dgid)
421{ 422{
422 struct sockaddr_in src_in; 423 struct sockaddr_in src_in;
423 struct sockaddr_in dst_in; 424 struct sockaddr_in dst_in;
@@ -447,6 +448,7 @@ static int get_gids_from_rdma_hdr(union rdma_network_hdr *hdr,
447 return -EINVAL; 448 return -EINVAL;
448 } 449 }
449} 450}
451EXPORT_SYMBOL(ib_get_gids_from_rdma_hdr);
450 452
451int ib_init_ah_from_wc(struct ib_device *device, u8 port_num, 453int ib_init_ah_from_wc(struct ib_device *device, u8 port_num,
452 const struct ib_wc *wc, const struct ib_grh *grh, 454 const struct ib_wc *wc, const struct ib_grh *grh,
@@ -469,8 +471,8 @@ int ib_init_ah_from_wc(struct ib_device *device, u8 port_num,
469 net_type = ib_get_net_type_by_grh(device, port_num, grh); 471 net_type = ib_get_net_type_by_grh(device, port_num, grh);
470 gid_type = ib_network_to_gid_type(net_type); 472 gid_type = ib_network_to_gid_type(net_type);
471 } 473 }
472 ret = get_gids_from_rdma_hdr((union rdma_network_hdr *)grh, net_type, 474 ret = ib_get_gids_from_rdma_hdr((union rdma_network_hdr *)grh, net_type,
473 &sgid, &dgid); 475 &sgid, &dgid);
474 if (ret) 476 if (ret)
475 return ret; 477 return ret;
476 478
@@ -1014,6 +1016,7 @@ static const struct {
1014 IB_QP_QKEY), 1016 IB_QP_QKEY),
1015 [IB_QPT_GSI] = (IB_QP_CUR_STATE | 1017 [IB_QPT_GSI] = (IB_QP_CUR_STATE |
1016 IB_QP_QKEY), 1018 IB_QP_QKEY),
1019 [IB_QPT_RAW_PACKET] = IB_QP_RATE_LIMIT,
1017 } 1020 }
1018 } 1021 }
1019 }, 1022 },
@@ -1047,6 +1050,7 @@ static const struct {
1047 IB_QP_QKEY), 1050 IB_QP_QKEY),
1048 [IB_QPT_GSI] = (IB_QP_CUR_STATE | 1051 [IB_QPT_GSI] = (IB_QP_CUR_STATE |
1049 IB_QP_QKEY), 1052 IB_QP_QKEY),
1053 [IB_QPT_RAW_PACKET] = IB_QP_RATE_LIMIT,
1050 } 1054 }
1051 }, 1055 },
1052 [IB_QPS_SQD] = { 1056 [IB_QPS_SQD] = {
@@ -1196,66 +1200,66 @@ int ib_modify_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state next_state,
1196} 1200}
1197EXPORT_SYMBOL(ib_modify_qp_is_ok); 1201EXPORT_SYMBOL(ib_modify_qp_is_ok);
1198 1202
1199int ib_resolve_eth_dmac(struct ib_qp *qp, 1203int ib_resolve_eth_dmac(struct ib_device *device,
1200 struct ib_qp_attr *qp_attr, int *qp_attr_mask) 1204 struct ib_ah_attr *ah_attr)
1201{ 1205{
1202 int ret = 0; 1206 int ret = 0;
1203 1207
1204 if (*qp_attr_mask & IB_QP_AV) { 1208 if (ah_attr->port_num < rdma_start_port(device) ||
1205 if (qp_attr->ah_attr.port_num < rdma_start_port(qp->device) || 1209 ah_attr->port_num > rdma_end_port(device))
1206 qp_attr->ah_attr.port_num > rdma_end_port(qp->device)) 1210 return -EINVAL;
1207 return -EINVAL;
1208
1209 if (!rdma_cap_eth_ah(qp->device, qp_attr->ah_attr.port_num))
1210 return 0;
1211
1212 if (rdma_link_local_addr((struct in6_addr *)qp_attr->ah_attr.grh.dgid.raw)) {
1213 rdma_get_ll_mac((struct in6_addr *)qp_attr->ah_attr.grh.dgid.raw,
1214 qp_attr->ah_attr.dmac);
1215 } else {
1216 union ib_gid sgid;
1217 struct ib_gid_attr sgid_attr;
1218 int ifindex;
1219 int hop_limit;
1220
1221 ret = ib_query_gid(qp->device,
1222 qp_attr->ah_attr.port_num,
1223 qp_attr->ah_attr.grh.sgid_index,
1224 &sgid, &sgid_attr);
1225
1226 if (ret || !sgid_attr.ndev) {
1227 if (!ret)
1228 ret = -ENXIO;
1229 goto out;
1230 }
1231 1211
1232 ifindex = sgid_attr.ndev->ifindex; 1212 if (!rdma_cap_eth_ah(device, ah_attr->port_num))
1213 return 0;
1233 1214
1234 ret = rdma_addr_find_l2_eth_by_grh(&sgid, 1215 if (rdma_link_local_addr((struct in6_addr *)ah_attr->grh.dgid.raw)) {
1235 &qp_attr->ah_attr.grh.dgid, 1216 rdma_get_ll_mac((struct in6_addr *)ah_attr->grh.dgid.raw,
1236 qp_attr->ah_attr.dmac, 1217 ah_attr->dmac);
1237 NULL, &ifindex, &hop_limit); 1218 } else {
1219 union ib_gid sgid;
1220 struct ib_gid_attr sgid_attr;
1221 int ifindex;
1222 int hop_limit;
1223
1224 ret = ib_query_gid(device,
1225 ah_attr->port_num,
1226 ah_attr->grh.sgid_index,
1227 &sgid, &sgid_attr);
1228
1229 if (ret || !sgid_attr.ndev) {
1230 if (!ret)
1231 ret = -ENXIO;
1232 goto out;
1233 }
1238 1234
1239 dev_put(sgid_attr.ndev); 1235 ifindex = sgid_attr.ndev->ifindex;
1240 1236
1241 qp_attr->ah_attr.grh.hop_limit = hop_limit; 1237 ret = rdma_addr_find_l2_eth_by_grh(&sgid,
1242 } 1238 &ah_attr->grh.dgid,
1239 ah_attr->dmac,
1240 NULL, &ifindex, &hop_limit);
1241
1242 dev_put(sgid_attr.ndev);
1243
1244 ah_attr->grh.hop_limit = hop_limit;
1243 } 1245 }
1244out: 1246out:
1245 return ret; 1247 return ret;
1246} 1248}
1247EXPORT_SYMBOL(ib_resolve_eth_dmac); 1249EXPORT_SYMBOL(ib_resolve_eth_dmac);
1248 1250
1249
1250int ib_modify_qp(struct ib_qp *qp, 1251int ib_modify_qp(struct ib_qp *qp,
1251 struct ib_qp_attr *qp_attr, 1252 struct ib_qp_attr *qp_attr,
1252 int qp_attr_mask) 1253 int qp_attr_mask)
1253{ 1254{
1254 int ret;
1255 1255
1256 ret = ib_resolve_eth_dmac(qp, qp_attr, &qp_attr_mask); 1256 if (qp_attr_mask & IB_QP_AV) {
1257 if (ret) 1257 int ret;
1258 return ret; 1258
1259 ret = ib_resolve_eth_dmac(qp->device, &qp_attr->ah_attr);
1260 if (ret)
1261 return ret;
1262 }
1259 1263
1260 return qp->device->modify_qp(qp->real_qp, qp_attr, qp_attr_mask, NULL); 1264 return qp->device->modify_qp(qp->real_qp, qp_attr, qp_attr_mask, NULL);
1261} 1265}
@@ -1734,8 +1738,10 @@ struct ib_flow *ib_create_flow(struct ib_qp *qp,
1734 return ERR_PTR(-ENOSYS); 1738 return ERR_PTR(-ENOSYS);
1735 1739
1736 flow_id = qp->device->create_flow(qp, flow_attr, domain); 1740 flow_id = qp->device->create_flow(qp, flow_attr, domain);
1737 if (!IS_ERR(flow_id)) 1741 if (!IS_ERR(flow_id)) {
1738 atomic_inc(&qp->usecnt); 1742 atomic_inc(&qp->usecnt);
1743 flow_id->qp = qp;
1744 }
1739 return flow_id; 1745 return flow_id;
1740} 1746}
1741EXPORT_SYMBOL(ib_create_flow); 1747EXPORT_SYMBOL(ib_create_flow);
diff --git a/drivers/infiniband/hw/Makefile b/drivers/infiniband/hw/Makefile
index e7a5ed9f6f3f..ed553de2ca12 100644
--- a/drivers/infiniband/hw/Makefile
+++ b/drivers/infiniband/hw/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_MLX4_INFINIBAND) += mlx4/
7obj-$(CONFIG_MLX5_INFINIBAND) += mlx5/ 7obj-$(CONFIG_MLX5_INFINIBAND) += mlx5/
8obj-$(CONFIG_INFINIBAND_NES) += nes/ 8obj-$(CONFIG_INFINIBAND_NES) += nes/
9obj-$(CONFIG_INFINIBAND_OCRDMA) += ocrdma/ 9obj-$(CONFIG_INFINIBAND_OCRDMA) += ocrdma/
10obj-$(CONFIG_INFINIBAND_VMWARE_PVRDMA) += vmw_pvrdma/
10obj-$(CONFIG_INFINIBAND_USNIC) += usnic/ 11obj-$(CONFIG_INFINIBAND_USNIC) += usnic/
11obj-$(CONFIG_INFINIBAND_HFI1) += hfi1/ 12obj-$(CONFIG_INFINIBAND_HFI1) += hfi1/
12obj-$(CONFIG_INFINIBAND_HNS) += hns/ 13obj-$(CONFIG_INFINIBAND_HNS) += hns/
diff --git a/drivers/infiniband/hw/cxgb3/cxio_dbg.c b/drivers/infiniband/hw/cxgb3/cxio_dbg.c
index 8bca6b4ec9af..445e89e5e7cf 100644
--- a/drivers/infiniband/hw/cxgb3/cxio_dbg.c
+++ b/drivers/infiniband/hw/cxgb3/cxio_dbg.c
@@ -45,10 +45,9 @@ void cxio_dump_tpt(struct cxio_rdev *rdev, u32 stag)
45 int size = 32; 45 int size = 32;
46 46
47 m = kmalloc(sizeof(*m) + size, GFP_ATOMIC); 47 m = kmalloc(sizeof(*m) + size, GFP_ATOMIC);
48 if (!m) { 48 if (!m)
49 PDBG("%s couldn't allocate memory.\n", __func__);
50 return; 49 return;
51 } 50
52 m->mem_id = MEM_PMRX; 51 m->mem_id = MEM_PMRX;
53 m->addr = (stag>>8) * 32 + rdev->rnic_info.tpt_base; 52 m->addr = (stag>>8) * 32 + rdev->rnic_info.tpt_base;
54 m->len = size; 53 m->len = size;
@@ -82,10 +81,9 @@ void cxio_dump_pbl(struct cxio_rdev *rdev, u32 pbl_addr, uint len, u8 shift)
82 size = npages * sizeof(u64); 81 size = npages * sizeof(u64);
83 82
84 m = kmalloc(sizeof(*m) + size, GFP_ATOMIC); 83 m = kmalloc(sizeof(*m) + size, GFP_ATOMIC);
85 if (!m) { 84 if (!m)
86 PDBG("%s couldn't allocate memory.\n", __func__);
87 return; 85 return;
88 } 86
89 m->mem_id = MEM_PMRX; 87 m->mem_id = MEM_PMRX;
90 m->addr = pbl_addr; 88 m->addr = pbl_addr;
91 m->len = size; 89 m->len = size;
@@ -144,10 +142,9 @@ void cxio_dump_rqt(struct cxio_rdev *rdev, u32 hwtid, int nents)
144 int rc; 142 int rc;
145 143
146 m = kmalloc(sizeof(*m) + size, GFP_ATOMIC); 144 m = kmalloc(sizeof(*m) + size, GFP_ATOMIC);
147 if (!m) { 145 if (!m)
148 PDBG("%s couldn't allocate memory.\n", __func__);
149 return; 146 return;
150 } 147
151 m->mem_id = MEM_PMRX; 148 m->mem_id = MEM_PMRX;
152 m->addr = ((hwtid)<<10) + rdev->rnic_info.rqt_base; 149 m->addr = ((hwtid)<<10) + rdev->rnic_info.rqt_base;
153 m->len = size; 150 m->len = size;
@@ -177,10 +174,9 @@ void cxio_dump_tcb(struct cxio_rdev *rdev, u32 hwtid)
177 int rc; 174 int rc;
178 175
179 m = kmalloc(sizeof(*m) + size, GFP_ATOMIC); 176 m = kmalloc(sizeof(*m) + size, GFP_ATOMIC);
180 if (!m) { 177 if (!m)
181 PDBG("%s couldn't allocate memory.\n", __func__);
182 return; 178 return;
183 } 179
184 m->mem_id = MEM_CM; 180 m->mem_id = MEM_CM;
185 m->addr = hwtid * size; 181 m->addr = hwtid * size;
186 m->len = size; 182 m->len = size;
diff --git a/drivers/infiniband/hw/cxgb3/iwch_provider.c b/drivers/infiniband/hw/cxgb3/iwch_provider.c
index cba57bb53dba..9d5fe1853da4 100644
--- a/drivers/infiniband/hw/cxgb3/iwch_provider.c
+++ b/drivers/infiniband/hw/cxgb3/iwch_provider.c
@@ -62,7 +62,8 @@
62#include "common.h" 62#include "common.h"
63 63
64static struct ib_ah *iwch_ah_create(struct ib_pd *pd, 64static struct ib_ah *iwch_ah_create(struct ib_pd *pd,
65 struct ib_ah_attr *ah_attr) 65 struct ib_ah_attr *ah_attr,
66 struct ib_udata *udata)
66{ 67{
67 return ERR_PTR(-ENOSYS); 68 return ERR_PTR(-ENOSYS);
68} 69}
diff --git a/drivers/infiniband/hw/cxgb4/device.c b/drivers/infiniband/hw/cxgb4/device.c
index 4e5baf4fe15e..516b0ae6dc3f 100644
--- a/drivers/infiniband/hw/cxgb4/device.c
+++ b/drivers/infiniband/hw/cxgb4/device.c
@@ -828,8 +828,10 @@ static int c4iw_rdev_open(struct c4iw_rdev *rdev)
828 } 828 }
829 rdev->status_page = (struct t4_dev_status_page *) 829 rdev->status_page = (struct t4_dev_status_page *)
830 __get_free_page(GFP_KERNEL); 830 __get_free_page(GFP_KERNEL);
831 if (!rdev->status_page) 831 if (!rdev->status_page) {
832 err = -ENOMEM;
832 goto destroy_ocqp_pool; 833 goto destroy_ocqp_pool;
834 }
833 rdev->status_page->qp_start = rdev->lldi.vr->qp.start; 835 rdev->status_page->qp_start = rdev->lldi.vr->qp.start;
834 rdev->status_page->qp_size = rdev->lldi.vr->qp.size; 836 rdev->status_page->qp_size = rdev->lldi.vr->qp.size;
835 rdev->status_page->cq_start = rdev->lldi.vr->cq.start; 837 rdev->status_page->cq_start = rdev->lldi.vr->cq.start;
@@ -841,8 +843,6 @@ static int c4iw_rdev_open(struct c4iw_rdev *rdev)
841 if (rdev->wr_log) { 843 if (rdev->wr_log) {
842 rdev->wr_log_size = 1 << c4iw_wr_log_size_order; 844 rdev->wr_log_size = 1 << c4iw_wr_log_size_order;
843 atomic_set(&rdev->wr_log_idx, 0); 845 atomic_set(&rdev->wr_log_idx, 0);
844 } else {
845 pr_err(MOD "error allocating wr_log. Logging disabled\n");
846 } 846 }
847 } 847 }
848 848
@@ -1424,8 +1424,6 @@ static void recover_queues(struct uld_ctx *ctx)
1424 1424
1425 qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC); 1425 qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC);
1426 if (!qp_list.qps) { 1426 if (!qp_list.qps) {
1427 printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n",
1428 pci_name(ctx->lldi.pdev));
1429 spin_unlock_irq(&ctx->dev->lock); 1427 spin_unlock_irq(&ctx->dev->lock);
1430 return; 1428 return;
1431 } 1429 }
diff --git a/drivers/infiniband/hw/cxgb4/provider.c b/drivers/infiniband/hw/cxgb4/provider.c
index 645e606a17c5..49b51b7e0fd7 100644
--- a/drivers/infiniband/hw/cxgb4/provider.c
+++ b/drivers/infiniband/hw/cxgb4/provider.c
@@ -59,7 +59,9 @@ module_param(fastreg_support, int, 0644);
59MODULE_PARM_DESC(fastreg_support, "Advertise fastreg support (default=1)"); 59MODULE_PARM_DESC(fastreg_support, "Advertise fastreg support (default=1)");
60 60
61static struct ib_ah *c4iw_ah_create(struct ib_pd *pd, 61static struct ib_ah *c4iw_ah_create(struct ib_pd *pd,
62 struct ib_ah_attr *ah_attr) 62 struct ib_ah_attr *ah_attr,
63 struct ib_udata *udata)
64
63{ 65{
64 return ERR_PTR(-ENOSYS); 66 return ERR_PTR(-ENOSYS);
65} 67}
diff --git a/drivers/infiniband/hw/hfi1/affinity.c b/drivers/infiniband/hw/hfi1/affinity.c
index 67ea85a56945..7a3d906b3671 100644
--- a/drivers/infiniband/hw/hfi1/affinity.c
+++ b/drivers/infiniband/hw/hfi1/affinity.c
@@ -125,6 +125,7 @@ int node_affinity_init(void)
125 cpumask_weight(topology_sibling_cpumask( 125 cpumask_weight(topology_sibling_cpumask(
126 cpumask_first(&node_affinity.proc.mask) 126 cpumask_first(&node_affinity.proc.mask)
127 )); 127 ));
128 node_affinity.num_possible_nodes = num_possible_nodes();
128 node_affinity.num_online_nodes = num_online_nodes(); 129 node_affinity.num_online_nodes = num_online_nodes();
129 node_affinity.num_online_cpus = num_online_cpus(); 130 node_affinity.num_online_cpus = num_online_cpus();
130 131
@@ -135,7 +136,7 @@ int node_affinity_init(void)
135 */ 136 */
136 init_real_cpu_mask(); 137 init_real_cpu_mask();
137 138
138 hfi1_per_node_cntr = kcalloc(num_possible_nodes(), 139 hfi1_per_node_cntr = kcalloc(node_affinity.num_possible_nodes,
139 sizeof(*hfi1_per_node_cntr), GFP_KERNEL); 140 sizeof(*hfi1_per_node_cntr), GFP_KERNEL);
140 if (!hfi1_per_node_cntr) 141 if (!hfi1_per_node_cntr)
141 return -ENOMEM; 142 return -ENOMEM;
diff --git a/drivers/infiniband/hw/hfi1/affinity.h b/drivers/infiniband/hw/hfi1/affinity.h
index 42e63316afd1..e78c7aa094e0 100644
--- a/drivers/infiniband/hw/hfi1/affinity.h
+++ b/drivers/infiniband/hw/hfi1/affinity.h
@@ -70,14 +70,6 @@ struct cpu_mask_set {
70 uint gen; 70 uint gen;
71}; 71};
72 72
73struct hfi1_affinity {
74 struct cpu_mask_set def_intr;
75 struct cpu_mask_set rcv_intr;
76 struct cpumask real_cpu_mask;
77 /* spin lock to protect affinity struct */
78 spinlock_t lock;
79};
80
81struct hfi1_msix_entry; 73struct hfi1_msix_entry;
82 74
83/* Initialize non-HT cpu cores mask */ 75/* Initialize non-HT cpu cores mask */
@@ -115,6 +107,7 @@ struct hfi1_affinity_node_list {
115 struct cpumask real_cpu_mask; 107 struct cpumask real_cpu_mask;
116 struct cpu_mask_set proc; 108 struct cpu_mask_set proc;
117 int num_core_siblings; 109 int num_core_siblings;
110 int num_possible_nodes;
118 int num_online_nodes; 111 int num_online_nodes;
119 int num_online_cpus; 112 int num_online_cpus;
120 struct mutex lock; /* protects affinity nodes */ 113 struct mutex lock; /* protects affinity nodes */
diff --git a/drivers/infiniband/hw/hfi1/chip.c b/drivers/infiniband/hw/hfi1/chip.c
index 24d0820873cf..ef72bc2a9e1d 100644
--- a/drivers/infiniband/hw/hfi1/chip.c
+++ b/drivers/infiniband/hw/hfi1/chip.c
@@ -8477,7 +8477,10 @@ static int do_8051_command(
8477 */ 8477 */
8478 if (type == HCMD_WRITE_LCB_CSR) { 8478 if (type == HCMD_WRITE_LCB_CSR) {
8479 in_data |= ((*out_data) & 0xffffffffffull) << 8; 8479 in_data |= ((*out_data) & 0xffffffffffull) << 8;
8480 reg = ((((*out_data) >> 40) & 0xff) << 8480 /* must preserve COMPLETED - it is tied to hardware */
8481 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0);
8482 reg &= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK;
8483 reg |= ((((*out_data) >> 40) & 0xff) <<
8481 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT) 8484 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT)
8482 | ((((*out_data) >> 48) & 0xffff) << 8485 | ((((*out_data) >> 48) & 0xffff) <<
8483 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT); 8486 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT);
@@ -9556,11 +9559,11 @@ int bringup_serdes(struct hfi1_pportdata *ppd)
9556 if (HFI1_CAP_IS_KSET(EXTENDED_PSN)) 9559 if (HFI1_CAP_IS_KSET(EXTENDED_PSN))
9557 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK); 9560 add_rcvctrl(dd, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK);
9558 9561
9559 guid = ppd->guid; 9562 guid = ppd->guids[HFI1_PORT_GUID_INDEX];
9560 if (!guid) { 9563 if (!guid) {
9561 if (dd->base_guid) 9564 if (dd->base_guid)
9562 guid = dd->base_guid + ppd->port - 1; 9565 guid = dd->base_guid + ppd->port - 1;
9563 ppd->guid = guid; 9566 ppd->guids[HFI1_PORT_GUID_INDEX] = guid;
9564 } 9567 }
9565 9568
9566 /* Set linkinit_reason on power up per OPA spec */ 9569 /* Set linkinit_reason on power up per OPA spec */
diff --git a/drivers/infiniband/hw/hfi1/chip_registers.h b/drivers/infiniband/hw/hfi1/chip_registers.h
index 5b9993899789..5bfa839d1c48 100644
--- a/drivers/infiniband/hw/hfi1/chip_registers.h
+++ b/drivers/infiniband/hw/hfi1/chip_registers.h
@@ -415,6 +415,9 @@
415#define ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT 32 415#define ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT 32
416#define ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT 0 416#define ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT 0
417#define ASIC_CFG_SCRATCH (ASIC + 0x000000000020) 417#define ASIC_CFG_SCRATCH (ASIC + 0x000000000020)
418#define ASIC_CFG_SCRATCH_1 (ASIC_CFG_SCRATCH + 0x08)
419#define ASIC_CFG_SCRATCH_2 (ASIC_CFG_SCRATCH + 0x10)
420#define ASIC_CFG_SCRATCH_3 (ASIC_CFG_SCRATCH + 0x18)
418#define ASIC_CFG_THERM_POLL_EN (ASIC + 0x000000000050) 421#define ASIC_CFG_THERM_POLL_EN (ASIC + 0x000000000050)
419#define ASIC_EEP_ADDR_CMD (ASIC + 0x000000000308) 422#define ASIC_EEP_ADDR_CMD (ASIC + 0x000000000308)
420#define ASIC_EEP_ADDR_CMD_EP_ADDR_MASK 0xFFFFFFull 423#define ASIC_EEP_ADDR_CMD_EP_ADDR_MASK 0xFFFFFFull
diff --git a/drivers/infiniband/hw/hfi1/debugfs.c b/drivers/infiniband/hw/hfi1/debugfs.c
index 632ba21759ab..8725f4c086cf 100644
--- a/drivers/infiniband/hw/hfi1/debugfs.c
+++ b/drivers/infiniband/hw/hfi1/debugfs.c
@@ -541,6 +541,114 @@ static ssize_t asic_flags_write(struct file *file, const char __user *buf,
541 return ret; 541 return ret;
542} 542}
543 543
544/* read the dc8051 memory */
545static ssize_t dc8051_memory_read(struct file *file, char __user *buf,
546 size_t count, loff_t *ppos)
547{
548 struct hfi1_pportdata *ppd = private2ppd(file);
549 ssize_t rval;
550 void *tmp;
551 loff_t start, end;
552
553 /* the checks below expect the position to be positive */
554 if (*ppos < 0)
555 return -EINVAL;
556
557 tmp = kzalloc(DC8051_DATA_MEM_SIZE, GFP_KERNEL);
558 if (!tmp)
559 return -ENOMEM;
560
561 /*
562 * Fill in the requested portion of the temporary buffer from the
563 * 8051 memory. The 8051 memory read is done in terms of 8 bytes.
564 * Adjust start and end to fit. Skip reading anything if out of
565 * range.
566 */
567 start = *ppos & ~0x7; /* round down */
568 if (start < DC8051_DATA_MEM_SIZE) {
569 end = (*ppos + count + 7) & ~0x7; /* round up */
570 if (end > DC8051_DATA_MEM_SIZE)
571 end = DC8051_DATA_MEM_SIZE;
572 rval = read_8051_data(ppd->dd, start, end - start,
573 (u64 *)(tmp + start));
574 if (rval)
575 goto done;
576 }
577
578 rval = simple_read_from_buffer(buf, count, ppos, tmp,
579 DC8051_DATA_MEM_SIZE);
580done:
581 kfree(tmp);
582 return rval;
583}
584
585static ssize_t debugfs_lcb_read(struct file *file, char __user *buf,
586 size_t count, loff_t *ppos)
587{
588 struct hfi1_pportdata *ppd = private2ppd(file);
589 struct hfi1_devdata *dd = ppd->dd;
590 unsigned long total, csr_off;
591 u64 data;
592
593 if (*ppos < 0)
594 return -EINVAL;
595 /* only read 8 byte quantities */
596 if ((count % 8) != 0)
597 return -EINVAL;
598 /* offset must be 8-byte aligned */
599 if ((*ppos % 8) != 0)
600 return -EINVAL;
601 /* do nothing if out of range or zero count */
602 if (*ppos >= (LCB_END - LCB_START) || !count)
603 return 0;
604 /* reduce count if needed */
605 if (*ppos + count > LCB_END - LCB_START)
606 count = (LCB_END - LCB_START) - *ppos;
607
608 csr_off = LCB_START + *ppos;
609 for (total = 0; total < count; total += 8, csr_off += 8) {
610 if (read_lcb_csr(dd, csr_off, (u64 *)&data))
611 break; /* failed */
612 if (put_user(data, (unsigned long __user *)(buf + total)))
613 break;
614 }
615 *ppos += total;
616 return total;
617}
618
619static ssize_t debugfs_lcb_write(struct file *file, const char __user *buf,
620 size_t count, loff_t *ppos)
621{
622 struct hfi1_pportdata *ppd = private2ppd(file);
623 struct hfi1_devdata *dd = ppd->dd;
624 unsigned long total, csr_off, data;
625
626 if (*ppos < 0)
627 return -EINVAL;
628 /* only write 8 byte quantities */
629 if ((count % 8) != 0)
630 return -EINVAL;
631 /* offset must be 8-byte aligned */
632 if ((*ppos % 8) != 0)
633 return -EINVAL;
634 /* do nothing if out of range or zero count */
635 if (*ppos >= (LCB_END - LCB_START) || !count)
636 return 0;
637 /* reduce count if needed */
638 if (*ppos + count > LCB_END - LCB_START)
639 count = (LCB_END - LCB_START) - *ppos;
640
641 csr_off = LCB_START + *ppos;
642 for (total = 0; total < count; total += 8, csr_off += 8) {
643 if (get_user(data, (unsigned long __user *)(buf + total)))
644 break;
645 if (write_lcb_csr(dd, csr_off, data))
646 break; /* failed */
647 }
648 *ppos += total;
649 return total;
650}
651
544/* 652/*
545 * read the per-port QSFP data for ppd 653 * read the per-port QSFP data for ppd
546 */ 654 */
@@ -931,6 +1039,8 @@ static const struct counter_info port_cntr_ops[] = {
931 DEBUGFS_XOPS("qsfp2", qsfp2_debugfs_read, qsfp2_debugfs_write, 1039 DEBUGFS_XOPS("qsfp2", qsfp2_debugfs_read, qsfp2_debugfs_write,
932 qsfp2_debugfs_open, qsfp2_debugfs_release), 1040 qsfp2_debugfs_open, qsfp2_debugfs_release),
933 DEBUGFS_OPS("asic_flags", asic_flags_read, asic_flags_write), 1041 DEBUGFS_OPS("asic_flags", asic_flags_read, asic_flags_write),
1042 DEBUGFS_OPS("dc8051_memory", dc8051_memory_read, NULL),
1043 DEBUGFS_OPS("lcb", debugfs_lcb_read, debugfs_lcb_write),
934}; 1044};
935 1045
936static void *_sdma_cpu_list_seq_start(struct seq_file *s, loff_t *pos) 1046static void *_sdma_cpu_list_seq_start(struct seq_file *s, loff_t *pos)
diff --git a/drivers/infiniband/hw/hfi1/driver.c b/drivers/infiniband/hw/hfi1/driver.c
index c5efff29c147..4fbaee68012b 100644
--- a/drivers/infiniband/hw/hfi1/driver.c
+++ b/drivers/infiniband/hw/hfi1/driver.c
@@ -795,8 +795,7 @@ static inline void process_rcv_qp_work(struct hfi1_packet *packet)
795 hfi1_schedule_send(qp); 795 hfi1_schedule_send(qp);
796 spin_unlock_irqrestore(&qp->s_lock, flags); 796 spin_unlock_irqrestore(&qp->s_lock, flags);
797 } 797 }
798 if (atomic_dec_and_test(&qp->refcount)) 798 rvt_put_qp(qp);
799 wake_up(&qp->wait);
800 } 799 }
801} 800}
802 801
diff --git a/drivers/infiniband/hw/hfi1/eprom.c b/drivers/infiniband/hw/hfi1/eprom.c
index e70c223801b4..26da124c88e2 100644
--- a/drivers/infiniband/hw/hfi1/eprom.c
+++ b/drivers/infiniband/hw/hfi1/eprom.c
@@ -207,6 +207,40 @@ done_asic:
207/* magic character sequence that trails an image */ 207/* magic character sequence that trails an image */
208#define IMAGE_TRAIL_MAGIC "egamiAPO" 208#define IMAGE_TRAIL_MAGIC "egamiAPO"
209 209
210/* EPROM file types */
211#define HFI1_EFT_PLATFORM_CONFIG 2
212
213/* segment size - 128 KiB */
214#define SEG_SIZE (128 * 1024)
215
216struct hfi1_eprom_footer {
217 u32 oprom_size; /* size of the oprom, in bytes */
218 u16 num_table_entries;
219 u16 version; /* version of this footer */
220 u32 magic; /* must be last */
221};
222
223struct hfi1_eprom_table_entry {
224 u32 type; /* file type */
225 u32 offset; /* file offset from start of EPROM */
226 u32 size; /* file size, in bytes */
227};
228
229/*
230 * Calculate the max number of table entries that will fit within a directory
231 * buffer of size 'dir_size'.
232 */
233#define MAX_TABLE_ENTRIES(dir_size) \
234 (((dir_size) - sizeof(struct hfi1_eprom_footer)) / \
235 sizeof(struct hfi1_eprom_table_entry))
236
237#define DIRECTORY_SIZE(n) (sizeof(struct hfi1_eprom_footer) + \
238 (sizeof(struct hfi1_eprom_table_entry) * (n)))
239
240#define MAGIC4(a, b, c, d) ((d) << 24 | (c) << 16 | (b) << 8 | (a))
241#define FOOTER_MAGIC MAGIC4('e', 'p', 'r', 'm')
242#define FOOTER_VERSION 1
243
210/* 244/*
211 * Read all of partition 1. The actual file is at the front. Adjust 245 * Read all of partition 1. The actual file is at the front. Adjust
212 * the returned size if a trailing image magic is found. 246 * the returned size if a trailing image magic is found.
@@ -242,6 +276,167 @@ static int read_partition_platform_config(struct hfi1_devdata *dd, void **data,
242} 276}
243 277
244/* 278/*
279 * The segment magic has been checked. There is a footer and table of
280 * contents present.
281 *
282 * directory is a u32 aligned buffer of size EP_PAGE_SIZE.
283 */
284static int read_segment_platform_config(struct hfi1_devdata *dd,
285 void *directory, void **data, u32 *size)
286{
287 struct hfi1_eprom_footer *footer;
288 struct hfi1_eprom_table_entry *table;
289 struct hfi1_eprom_table_entry *entry;
290 void *buffer = NULL;
291 void *table_buffer = NULL;
292 int ret, i;
293 u32 directory_size;
294 u32 seg_base, seg_offset;
295 u32 bytes_available, ncopied, to_copy;
296
297 /* the footer is at the end of the directory */
298 footer = (struct hfi1_eprom_footer *)
299 (directory + EP_PAGE_SIZE - sizeof(*footer));
300
301 /* make sure the structure version is supported */
302 if (footer->version != FOOTER_VERSION)
303 return -EINVAL;
304
305 /* oprom size cannot be larger than a segment */
306 if (footer->oprom_size >= SEG_SIZE)
307 return -EINVAL;
308
309 /* the file table must fit in a segment with the oprom */
310 if (footer->num_table_entries >
311 MAX_TABLE_ENTRIES(SEG_SIZE - footer->oprom_size))
312 return -EINVAL;
313
314 /* find the file table start, which precedes the footer */
315 directory_size = DIRECTORY_SIZE(footer->num_table_entries);
316 if (directory_size <= EP_PAGE_SIZE) {
317 /* the file table fits into the directory buffer handed in */
318 table = (struct hfi1_eprom_table_entry *)
319 (directory + EP_PAGE_SIZE - directory_size);
320 } else {
321 /* need to allocate and read more */
322 table_buffer = kmalloc(directory_size, GFP_KERNEL);
323 if (!table_buffer)
324 return -ENOMEM;
325 ret = read_length(dd, SEG_SIZE - directory_size,
326 directory_size, table_buffer);
327 if (ret)
328 goto done;
329 table = table_buffer;
330 }
331
332 /* look for the platform configuration file in the table */
333 for (entry = NULL, i = 0; i < footer->num_table_entries; i++) {
334 if (table[i].type == HFI1_EFT_PLATFORM_CONFIG) {
335 entry = &table[i];
336 break;
337 }
338 }
339 if (!entry) {
340 ret = -ENOENT;
341 goto done;
342 }
343
344 /*
345 * Sanity check on the configuration file size - it should never
346 * be larger than 4 KiB.
347 */
348 if (entry->size > (4 * 1024)) {
349 dd_dev_err(dd, "Bad configuration file size 0x%x\n",
350 entry->size);
351 ret = -EINVAL;
352 goto done;
353 }
354
355 /* check for bogus offset and size that wrap when added together */
356 if (entry->offset + entry->size < entry->offset) {
357 dd_dev_err(dd,
358 "Bad configuration file start + size 0x%x+0x%x\n",
359 entry->offset, entry->size);
360 ret = -EINVAL;
361 goto done;
362 }
363
364 /* allocate the buffer to return */
365 buffer = kmalloc(entry->size, GFP_KERNEL);
366 if (!buffer) {
367 ret = -ENOMEM;
368 goto done;
369 }
370
371 /*
372 * Extract the file by looping over segments until it is fully read.
373 */
374 seg_offset = entry->offset % SEG_SIZE;
375 seg_base = entry->offset - seg_offset;
376 ncopied = 0;
377 while (ncopied < entry->size) {
378 /* calculate data bytes available in this segment */
379
380 /* start with the bytes from the current offset to the end */
381 bytes_available = SEG_SIZE - seg_offset;
382 /* subtract off footer and table from segment 0 */
383 if (seg_base == 0) {
384 /*
385 * Sanity check: should not have a starting point
386 * at or within the directory.
387 */
388 if (bytes_available <= directory_size) {
389 dd_dev_err(dd,
390 "Bad configuration file - offset 0x%x within footer+table\n",
391 entry->offset);
392 ret = -EINVAL;
393 goto done;
394 }
395 bytes_available -= directory_size;
396 }
397
398 /* calculate bytes wanted */
399 to_copy = entry->size - ncopied;
400
401 /* max out at the available bytes in this segment */
402 if (to_copy > bytes_available)
403 to_copy = bytes_available;
404
405 /*
406 * Read from the EPROM.
407 *
408 * The sanity check for entry->offset is done in read_length().
409 * The EPROM offset is validated against what the hardware
410 * addressing supports. In addition, if the offset is larger
411 * than the actual EPROM, it silently wraps. It will work
412 * fine, though the reader may not get what they expected
413 * from the EPROM.
414 */
415 ret = read_length(dd, seg_base + seg_offset, to_copy,
416 buffer + ncopied);
417 if (ret)
418 goto done;
419
420 ncopied += to_copy;
421
422 /* set up for next segment */
423 seg_offset = footer->oprom_size;
424 seg_base += SEG_SIZE;
425 }
426
427 /* success */
428 ret = 0;
429 *data = buffer;
430 *size = entry->size;
431
432done:
433 kfree(table_buffer);
434 if (ret)
435 kfree(buffer);
436 return ret;
437}
438
439/*
245 * Read the platform configuration file from the EPROM. 440 * Read the platform configuration file from the EPROM.
246 * 441 *
247 * On success, an allocated buffer containing the data and its size are 442 * On success, an allocated buffer containing the data and its size are
@@ -253,6 +448,7 @@ static int read_partition_platform_config(struct hfi1_devdata *dd, void **data,
253 * -EBUSY - not able to acquire access to the EPROM 448 * -EBUSY - not able to acquire access to the EPROM
254 * -ENOENT - no recognizable file written 449 * -ENOENT - no recognizable file written
255 * -ENOMEM - buffer could not be allocated 450 * -ENOMEM - buffer could not be allocated
451 * -EINVAL - invalid EPROM contentents found
256 */ 452 */
257int eprom_read_platform_config(struct hfi1_devdata *dd, void **data, u32 *size) 453int eprom_read_platform_config(struct hfi1_devdata *dd, void **data, u32 *size)
258{ 454{
@@ -266,21 +462,20 @@ int eprom_read_platform_config(struct hfi1_devdata *dd, void **data, u32 *size)
266 if (ret) 462 if (ret)
267 return -EBUSY; 463 return -EBUSY;
268 464
269 /* read the last page of P0 for the EPROM format magic */ 465 /* read the last page of the segment for the EPROM format magic */
270 ret = read_length(dd, P1_START - EP_PAGE_SIZE, EP_PAGE_SIZE, directory); 466 ret = read_length(dd, SEG_SIZE - EP_PAGE_SIZE, EP_PAGE_SIZE, directory);
271 if (ret) 467 if (ret)
272 goto done; 468 goto done;
273 469
274 /* last dword of P0 contains a magic indicator */ 470 /* last dword of the segment contains a magic value */
275 if (directory[EP_PAGE_DWORDS - 1] == 0) { 471 if (directory[EP_PAGE_DWORDS - 1] == FOOTER_MAGIC) {
472 /* segment format */
473 ret = read_segment_platform_config(dd, directory, data, size);
474 } else {
276 /* partition format */ 475 /* partition format */
277 ret = read_partition_platform_config(dd, data, size); 476 ret = read_partition_platform_config(dd, data, size);
278 goto done;
279 } 477 }
280 478
281 /* nothing recognized */
282 ret = -ENOENT;
283
284done: 479done:
285 release_chip_resource(dd, CR_EPROM); 480 release_chip_resource(dd, CR_EPROM);
286 return ret; 481 return ret;
diff --git a/drivers/infiniband/hw/hfi1/firmware.c b/drivers/infiniband/hw/hfi1/firmware.c
index 13db8eb4f4ec..0dd50cdb039a 100644
--- a/drivers/infiniband/hw/hfi1/firmware.c
+++ b/drivers/infiniband/hw/hfi1/firmware.c
@@ -239,6 +239,16 @@ static const u8 all_fabric_serdes_broadcast = 0xe1;
239const u8 pcie_serdes_broadcast[2] = { 0xe2, 0xe3 }; 239const u8 pcie_serdes_broadcast[2] = { 0xe2, 0xe3 };
240static const u8 all_pcie_serdes_broadcast = 0xe0; 240static const u8 all_pcie_serdes_broadcast = 0xe0;
241 241
242static const u32 platform_config_table_limits[PLATFORM_CONFIG_TABLE_MAX] = {
243 0,
244 SYSTEM_TABLE_MAX,
245 PORT_TABLE_MAX,
246 RX_PRESET_TABLE_MAX,
247 TX_PRESET_TABLE_MAX,
248 QSFP_ATTEN_TABLE_MAX,
249 VARIABLE_SETTINGS_TABLE_MAX
250};
251
242/* forwards */ 252/* forwards */
243static void dispose_one_firmware(struct firmware_details *fdet); 253static void dispose_one_firmware(struct firmware_details *fdet);
244static int load_fabric_serdes_firmware(struct hfi1_devdata *dd, 254static int load_fabric_serdes_firmware(struct hfi1_devdata *dd,
@@ -263,11 +273,13 @@ static int __read_8051_data(struct hfi1_devdata *dd, u32 addr, u64 *result)
263 u64 reg; 273 u64 reg;
264 int count; 274 int count;
265 275
266 /* start the read at the given address */ 276 /* step 1: set the address, clear enable */
267 reg = ((addr & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK) 277 reg = (addr & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK)
268 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT) 278 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT;
269 | DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK;
270 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); 279 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
280 /* step 2: enable */
281 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL,
282 reg | DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK);
271 283
272 /* wait until ACCESS_COMPLETED is set */ 284 /* wait until ACCESS_COMPLETED is set */
273 count = 0; 285 count = 0;
@@ -707,6 +719,9 @@ static int obtain_firmware(struct hfi1_devdata *dd)
707 &dd->pcidev->dev); 719 &dd->pcidev->dev);
708 if (err) { 720 if (err) {
709 platform_config = NULL; 721 platform_config = NULL;
722 dd_dev_err(dd,
723 "%s: No default platform config file found\n",
724 __func__);
710 goto done; 725 goto done;
711 } 726 }
712 dd->platform_config.data = platform_config->data; 727 dd->platform_config.data = platform_config->data;
@@ -1761,8 +1776,17 @@ int parse_platform_config(struct hfi1_devdata *dd)
1761 u32 record_idx = 0, table_type = 0, table_length_dwords = 0; 1776 u32 record_idx = 0, table_type = 0, table_length_dwords = 0;
1762 int ret = -EINVAL; /* assume failure */ 1777 int ret = -EINVAL; /* assume failure */
1763 1778
1779 /*
1780 * For integrated devices that did not fall back to the default file,
1781 * the SI tuning information for active channels is acquired from the
1782 * scratch register bitmap, thus there is no platform config to parse.
1783 * Skip parsing in these situations.
1784 */
1785 if (is_integrated(dd) && !platform_config_load)
1786 return 0;
1787
1764 if (!dd->platform_config.data) { 1788 if (!dd->platform_config.data) {
1765 dd_dev_info(dd, "%s: Missing config file\n", __func__); 1789 dd_dev_err(dd, "%s: Missing config file\n", __func__);
1766 goto bail; 1790 goto bail;
1767 } 1791 }
1768 ptr = (u32 *)dd->platform_config.data; 1792 ptr = (u32 *)dd->platform_config.data;
@@ -1770,7 +1794,7 @@ int parse_platform_config(struct hfi1_devdata *dd)
1770 magic_num = *ptr; 1794 magic_num = *ptr;
1771 ptr++; 1795 ptr++;
1772 if (magic_num != PLATFORM_CONFIG_MAGIC_NUM) { 1796 if (magic_num != PLATFORM_CONFIG_MAGIC_NUM) {
1773 dd_dev_info(dd, "%s: Bad config file\n", __func__); 1797 dd_dev_err(dd, "%s: Bad config file\n", __func__);
1774 goto bail; 1798 goto bail;
1775 } 1799 }
1776 1800
@@ -1797,9 +1821,9 @@ int parse_platform_config(struct hfi1_devdata *dd)
1797 header1 = *ptr; 1821 header1 = *ptr;
1798 header2 = *(ptr + 1); 1822 header2 = *(ptr + 1);
1799 if (header1 != ~header2) { 1823 if (header1 != ~header2) {
1800 dd_dev_info(dd, "%s: Failed validation at offset %ld\n", 1824 dd_dev_err(dd, "%s: Failed validation at offset %ld\n",
1801 __func__, (ptr - (u32 *) 1825 __func__, (ptr - (u32 *)
1802 dd->platform_config.data)); 1826 dd->platform_config.data));
1803 goto bail; 1827 goto bail;
1804 } 1828 }
1805 1829
@@ -1841,11 +1865,11 @@ int parse_platform_config(struct hfi1_devdata *dd)
1841 table_length_dwords; 1865 table_length_dwords;
1842 break; 1866 break;
1843 default: 1867 default:
1844 dd_dev_info(dd, 1868 dd_dev_err(dd,
1845 "%s: Unknown data table %d, offset %ld\n", 1869 "%s: Unknown data table %d, offset %ld\n",
1846 __func__, table_type, 1870 __func__, table_type,
1847 (ptr - (u32 *) 1871 (ptr - (u32 *)
1848 dd->platform_config.data)); 1872 dd->platform_config.data));
1849 goto bail; /* We don't trust this file now */ 1873 goto bail; /* We don't trust this file now */
1850 } 1874 }
1851 pcfgcache->config_tables[table_type].table = ptr; 1875 pcfgcache->config_tables[table_type].table = ptr;
@@ -1865,11 +1889,11 @@ int parse_platform_config(struct hfi1_devdata *dd)
1865 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE: 1889 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1866 break; 1890 break;
1867 default: 1891 default:
1868 dd_dev_info(dd, 1892 dd_dev_err(dd,
1869 "%s: Unknown meta table %d, offset %ld\n", 1893 "%s: Unknown meta table %d, offset %ld\n",
1870 __func__, table_type, 1894 __func__, table_type,
1871 (ptr - 1895 (ptr -
1872 (u32 *)dd->platform_config.data)); 1896 (u32 *)dd->platform_config.data));
1873 goto bail; /* We don't trust this file now */ 1897 goto bail; /* We don't trust this file now */
1874 } 1898 }
1875 pcfgcache->config_tables[table_type].table_metadata = 1899 pcfgcache->config_tables[table_type].table_metadata =
@@ -1884,10 +1908,9 @@ int parse_platform_config(struct hfi1_devdata *dd)
1884 /* Jump the table */ 1908 /* Jump the table */
1885 ptr += table_length_dwords; 1909 ptr += table_length_dwords;
1886 if (crc != *ptr) { 1910 if (crc != *ptr) {
1887 dd_dev_info(dd, "%s: Failed CRC check at offset %ld\n", 1911 dd_dev_err(dd, "%s: Failed CRC check at offset %ld\n",
1888 __func__, (ptr - 1912 __func__, (ptr -
1889 (u32 *) 1913 (u32 *)dd->platform_config.data));
1890 dd->platform_config.data));
1891 goto bail; 1914 goto bail;
1892 } 1915 }
1893 /* Jump the CRC DWORD */ 1916 /* Jump the CRC DWORD */
@@ -1901,6 +1924,84 @@ bail:
1901 return ret; 1924 return ret;
1902} 1925}
1903 1926
1927static void get_integrated_platform_config_field(
1928 struct hfi1_devdata *dd,
1929 enum platform_config_table_type_encoding table_type,
1930 int field_index, u32 *data)
1931{
1932 struct hfi1_pportdata *ppd = dd->pport;
1933 u8 *cache = ppd->qsfp_info.cache;
1934 u32 tx_preset = 0;
1935
1936 switch (table_type) {
1937 case PLATFORM_CONFIG_SYSTEM_TABLE:
1938 if (field_index == SYSTEM_TABLE_QSFP_POWER_CLASS_MAX)
1939 *data = ppd->max_power_class;
1940 else if (field_index == SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G)
1941 *data = ppd->default_atten;
1942 break;
1943 case PLATFORM_CONFIG_PORT_TABLE:
1944 if (field_index == PORT_TABLE_PORT_TYPE)
1945 *data = ppd->port_type;
1946 else if (field_index == PORT_TABLE_LOCAL_ATTEN_25G)
1947 *data = ppd->local_atten;
1948 else if (field_index == PORT_TABLE_REMOTE_ATTEN_25G)
1949 *data = ppd->remote_atten;
1950 break;
1951 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1952 if (field_index == RX_PRESET_TABLE_QSFP_RX_CDR_APPLY)
1953 *data = (ppd->rx_preset & QSFP_RX_CDR_APPLY_SMASK) >>
1954 QSFP_RX_CDR_APPLY_SHIFT;
1955 else if (field_index == RX_PRESET_TABLE_QSFP_RX_EMP_APPLY)
1956 *data = (ppd->rx_preset & QSFP_RX_EMP_APPLY_SMASK) >>
1957 QSFP_RX_EMP_APPLY_SHIFT;
1958 else if (field_index == RX_PRESET_TABLE_QSFP_RX_AMP_APPLY)
1959 *data = (ppd->rx_preset & QSFP_RX_AMP_APPLY_SMASK) >>
1960 QSFP_RX_AMP_APPLY_SHIFT;
1961 else if (field_index == RX_PRESET_TABLE_QSFP_RX_CDR)
1962 *data = (ppd->rx_preset & QSFP_RX_CDR_SMASK) >>
1963 QSFP_RX_CDR_SHIFT;
1964 else if (field_index == RX_PRESET_TABLE_QSFP_RX_EMP)
1965 *data = (ppd->rx_preset & QSFP_RX_EMP_SMASK) >>
1966 QSFP_RX_EMP_SHIFT;
1967 else if (field_index == RX_PRESET_TABLE_QSFP_RX_AMP)
1968 *data = (ppd->rx_preset & QSFP_RX_AMP_SMASK) >>
1969 QSFP_RX_AMP_SHIFT;
1970 break;
1971 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1972 if (cache[QSFP_EQ_INFO_OFFS] & 0x4)
1973 tx_preset = ppd->tx_preset_eq;
1974 else
1975 tx_preset = ppd->tx_preset_noeq;
1976 if (field_index == TX_PRESET_TABLE_PRECUR)
1977 *data = (tx_preset & TX_PRECUR_SMASK) >>
1978 TX_PRECUR_SHIFT;
1979 else if (field_index == TX_PRESET_TABLE_ATTN)
1980 *data = (tx_preset & TX_ATTN_SMASK) >>
1981 TX_ATTN_SHIFT;
1982 else if (field_index == TX_PRESET_TABLE_POSTCUR)
1983 *data = (tx_preset & TX_POSTCUR_SMASK) >>
1984 TX_POSTCUR_SHIFT;
1985 else if (field_index == TX_PRESET_TABLE_QSFP_TX_CDR_APPLY)
1986 *data = (tx_preset & QSFP_TX_CDR_APPLY_SMASK) >>
1987 QSFP_TX_CDR_APPLY_SHIFT;
1988 else if (field_index == TX_PRESET_TABLE_QSFP_TX_EQ_APPLY)
1989 *data = (tx_preset & QSFP_TX_EQ_APPLY_SMASK) >>
1990 QSFP_TX_EQ_APPLY_SHIFT;
1991 else if (field_index == TX_PRESET_TABLE_QSFP_TX_CDR)
1992 *data = (tx_preset & QSFP_TX_CDR_SMASK) >>
1993 QSFP_TX_CDR_SHIFT;
1994 else if (field_index == TX_PRESET_TABLE_QSFP_TX_EQ)
1995 *data = (tx_preset & QSFP_TX_EQ_SMASK) >>
1996 QSFP_TX_EQ_SHIFT;
1997 break;
1998 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1999 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
2000 default:
2001 break;
2002 }
2003}
2004
1904static int get_platform_fw_field_metadata(struct hfi1_devdata *dd, int table, 2005static int get_platform_fw_field_metadata(struct hfi1_devdata *dd, int table,
1905 int field, u32 *field_len_bits, 2006 int field, u32 *field_len_bits,
1906 u32 *field_start_bits) 2007 u32 *field_start_bits)
@@ -1976,6 +2077,15 @@ int get_platform_config_field(struct hfi1_devdata *dd,
1976 else 2077 else
1977 return -EINVAL; 2078 return -EINVAL;
1978 2079
2080 if (is_integrated(dd) && !platform_config_load) {
2081 /*
2082 * Use saved configuration from ppd for integrated platforms
2083 */
2084 get_integrated_platform_config_field(dd, table_type,
2085 field_index, data);
2086 return 0;
2087 }
2088
1979 ret = get_platform_fw_field_metadata(dd, table_type, field_index, 2089 ret = get_platform_fw_field_metadata(dd, table_type, field_index,
1980 &field_len_bits, 2090 &field_len_bits,
1981 &field_start_bits); 2091 &field_start_bits);
diff --git a/drivers/infiniband/hw/hfi1/hfi.h b/drivers/infiniband/hw/hfi1/hfi.h
index cc87fd4e534b..751a0fb29fa5 100644
--- a/drivers/infiniband/hw/hfi1/hfi.h
+++ b/drivers/infiniband/hw/hfi1/hfi.h
@@ -492,6 +492,9 @@ struct rvt_sge_state;
492#define HFI1_MIN_VLS_SUPPORTED 1 492#define HFI1_MIN_VLS_SUPPORTED 1
493#define HFI1_MAX_VLS_SUPPORTED 8 493#define HFI1_MAX_VLS_SUPPORTED 8
494 494
495#define HFI1_GUIDS_PER_PORT 5
496#define HFI1_PORT_GUID_INDEX 0
497
495static inline void incr_cntr64(u64 *cntr) 498static inline void incr_cntr64(u64 *cntr)
496{ 499{
497 if (*cntr < (u64)-1LL) 500 if (*cntr < (u64)-1LL)
@@ -559,11 +562,20 @@ struct hfi1_pportdata {
559 struct kobject vl2mtu_kobj; 562 struct kobject vl2mtu_kobj;
560 563
561 /* PHY support */ 564 /* PHY support */
562 u32 port_type;
563 struct qsfp_data qsfp_info; 565 struct qsfp_data qsfp_info;
566 /* Values for SI tuning of SerDes */
567 u32 port_type;
568 u32 tx_preset_eq;
569 u32 tx_preset_noeq;
570 u32 rx_preset;
571 u8 local_atten;
572 u8 remote_atten;
573 u8 default_atten;
574 u8 max_power_class;
575
576 /* GUIDs for this interface, in host order, guids[0] is a port guid */
577 u64 guids[HFI1_GUIDS_PER_PORT];
564 578
565 /* GUID for this interface, in host order */
566 u64 guid;
567 /* GUID for peer interface, in host order */ 579 /* GUID for peer interface, in host order */
568 u64 neighbor_guid; 580 u64 neighbor_guid;
569 581
@@ -826,32 +838,29 @@ struct hfi1_devdata {
826 u8 __iomem *kregend; 838 u8 __iomem *kregend;
827 /* physical address of chip for io_remap, etc. */ 839 /* physical address of chip for io_remap, etc. */
828 resource_size_t physaddr; 840 resource_size_t physaddr;
829 /* receive context data */ 841 /* Per VL data. Enough for all VLs but not all elements are set/used. */
830 struct hfi1_ctxtdata **rcd; 842 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
831 /* send context data */ 843 /* send context data */
832 struct send_context_info *send_contexts; 844 struct send_context_info *send_contexts;
833 /* map hardware send contexts to software index */ 845 /* map hardware send contexts to software index */
834 u8 *hw_to_sw; 846 u8 *hw_to_sw;
835 /* spinlock for allocating and releasing send context resources */ 847 /* spinlock for allocating and releasing send context resources */
836 spinlock_t sc_lock; 848 spinlock_t sc_lock;
837 /* Per VL data. Enough for all VLs but not all elements are set/used. */
838 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
839 /* lock for pio_map */ 849 /* lock for pio_map */
840 spinlock_t pio_map_lock; 850 spinlock_t pio_map_lock;
851 /* Send Context initialization lock. */
852 spinlock_t sc_init_lock;
853 /* lock for sdma_map */
854 spinlock_t sde_map_lock;
841 /* array of kernel send contexts */ 855 /* array of kernel send contexts */
842 struct send_context **kernel_send_context; 856 struct send_context **kernel_send_context;
843 /* array of vl maps */ 857 /* array of vl maps */
844 struct pio_vl_map __rcu *pio_map; 858 struct pio_vl_map __rcu *pio_map;
845 /* seqlock for sc2vl */ 859 /* default flags to last descriptor */
846 seqlock_t sc2vl_lock; 860 u64 default_desc1;
847 u64 sc2vl[4];
848 /* Send Context initialization lock. */
849 spinlock_t sc_init_lock;
850 861
851 /* fields common to all SDMA engines */ 862 /* fields common to all SDMA engines */
852 863
853 /* default flags to last descriptor */
854 u64 default_desc1;
855 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */ 864 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */
856 dma_addr_t sdma_heads_phys; 865 dma_addr_t sdma_heads_phys;
857 void *sdma_pad_dma; /* DMA'ed by chip */ 866 void *sdma_pad_dma; /* DMA'ed by chip */
@@ -862,8 +871,6 @@ struct hfi1_devdata {
862 u32 chip_sdma_engines; 871 u32 chip_sdma_engines;
863 /* num used */ 872 /* num used */
864 u32 num_sdma; 873 u32 num_sdma;
865 /* lock for sdma_map */
866 spinlock_t sde_map_lock;
867 /* array of engines sized by num_sdma */ 874 /* array of engines sized by num_sdma */
868 struct sdma_engine *per_sdma; 875 struct sdma_engine *per_sdma;
869 /* array of vl maps */ 876 /* array of vl maps */
@@ -872,14 +879,11 @@ struct hfi1_devdata {
872 wait_queue_head_t sdma_unfreeze_wq; 879 wait_queue_head_t sdma_unfreeze_wq;
873 atomic_t sdma_unfreeze_count; 880 atomic_t sdma_unfreeze_count;
874 881
882 u32 lcb_access_count; /* count of LCB users */
883
875 /* common data between shared ASIC HFIs in this OS */ 884 /* common data between shared ASIC HFIs in this OS */
876 struct hfi1_asic_data *asic_data; 885 struct hfi1_asic_data *asic_data;
877 886
878 /* hfi1_pportdata, points to array of (physical) port-specific
879 * data structs, indexed by pidx (0..n-1)
880 */
881 struct hfi1_pportdata *pport;
882
883 /* mem-mapped pointer to base of PIO buffers */ 887 /* mem-mapped pointer to base of PIO buffers */
884 void __iomem *piobase; 888 void __iomem *piobase;
885 /* 889 /*
@@ -896,20 +900,13 @@ struct hfi1_devdata {
896 /* send context numbers and sizes for each type */ 900 /* send context numbers and sizes for each type */
897 struct sc_config_sizes sc_sizes[SC_MAX]; 901 struct sc_config_sizes sc_sizes[SC_MAX];
898 902
899 u32 lcb_access_count; /* count of LCB users */
900
901 char *boardname; /* human readable board info */ 903 char *boardname; /* human readable board info */
902 904
903 /* device (not port) flags, basically device capabilities */
904 u32 flags;
905
906 /* reset value */ 905 /* reset value */
907 u64 z_int_counter; 906 u64 z_int_counter;
908 u64 z_rcv_limit; 907 u64 z_rcv_limit;
909 u64 z_send_schedule; 908 u64 z_send_schedule;
910 /* percpu int_counter */ 909
911 u64 __percpu *int_counter;
912 u64 __percpu *rcv_limit;
913 u64 __percpu *send_schedule; 910 u64 __percpu *send_schedule;
914 /* number of receive contexts in use by the driver */ 911 /* number of receive contexts in use by the driver */
915 u32 num_rcv_contexts; 912 u32 num_rcv_contexts;
@@ -924,6 +921,7 @@ struct hfi1_devdata {
924 /* base receive interrupt timeout, in CSR units */ 921 /* base receive interrupt timeout, in CSR units */
925 u32 rcv_intr_timeout_csr; 922 u32 rcv_intr_timeout_csr;
926 923
924 u32 freezelen; /* max length of freezemsg */
927 u64 __iomem *egrtidbase; 925 u64 __iomem *egrtidbase;
928 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */ 926 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
929 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */ 927 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
@@ -945,7 +943,6 @@ struct hfi1_devdata {
945 * IB link status cheaply 943 * IB link status cheaply
946 */ 944 */
947 struct hfi1_status *status; 945 struct hfi1_status *status;
948 u32 freezelen; /* max length of freezemsg */
949 946
950 /* revision register shadow */ 947 /* revision register shadow */
951 u64 revision; 948 u64 revision;
@@ -973,6 +970,8 @@ struct hfi1_devdata {
973 u16 rcvegrbufsize_shift; 970 u16 rcvegrbufsize_shift;
974 /* both sides of the PCIe link are gen3 capable */ 971 /* both sides of the PCIe link are gen3 capable */
975 u8 link_gen3_capable; 972 u8 link_gen3_capable;
973 /* default link down value (poll/sleep) */
974 u8 link_default;
976 /* localbus width (1, 2,4,8,16,32) from config space */ 975 /* localbus width (1, 2,4,8,16,32) from config space */
977 u32 lbus_width; 976 u32 lbus_width;
978 /* localbus speed in MHz */ 977 /* localbus speed in MHz */
@@ -1008,8 +1007,6 @@ struct hfi1_devdata {
1008 u8 hfi1_id; 1007 u8 hfi1_id;
1009 /* implementation code */ 1008 /* implementation code */
1010 u8 icode; 1009 u8 icode;
1011 /* default link down value (poll/sleep) */
1012 u8 link_default;
1013 /* vAU of this device */ 1010 /* vAU of this device */
1014 u8 vau; 1011 u8 vau;
1015 /* vCU of this device */ 1012 /* vCU of this device */
@@ -1020,27 +1017,17 @@ struct hfi1_devdata {
1020 u16 vl15_init; 1017 u16 vl15_init;
1021 1018
1022 /* Misc small ints */ 1019 /* Misc small ints */
1023 /* Number of physical ports available */
1024 u8 num_pports;
1025 /* Lowest context number which can be used by user processes */
1026 u8 first_user_ctxt;
1027 u8 n_krcv_queues; 1020 u8 n_krcv_queues;
1028 u8 qos_shift; 1021 u8 qos_shift;
1029 u8 qpn_mask;
1030 1022
1031 u16 rhf_offset; /* offset of RHF within receive header entry */
1032 u16 irev; /* implementation revision */ 1023 u16 irev; /* implementation revision */
1033 u16 dc8051_ver; /* 8051 firmware version */ 1024 u16 dc8051_ver; /* 8051 firmware version */
1034 1025
1026 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1035 struct platform_config platform_config; 1027 struct platform_config platform_config;
1036 struct platform_config_cache pcfg_cache; 1028 struct platform_config_cache pcfg_cache;
1037 1029
1038 struct diag_client *diag_client; 1030 struct diag_client *diag_client;
1039 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1040
1041 u8 psxmitwait_supported;
1042 /* cycle length of PS* counters in HW (in picoseconds) */
1043 u16 psxmitwait_check_rate;
1044 1031
1045 /* MSI-X information */ 1032 /* MSI-X information */
1046 struct hfi1_msix_entry *msix_entries; 1033 struct hfi1_msix_entry *msix_entries;
@@ -1055,6 +1042,9 @@ struct hfi1_devdata {
1055 1042
1056 struct rcv_array_data rcv_entries; 1043 struct rcv_array_data rcv_entries;
1057 1044
1045 /* cycle length of PS* counters in HW (in picoseconds) */
1046 u16 psxmitwait_check_rate;
1047
1058 /* 1048 /*
1059 * 64 bit synthetic counters 1049 * 64 bit synthetic counters
1060 */ 1050 */
@@ -1085,11 +1075,11 @@ struct hfi1_devdata {
1085 struct err_info_rcvport err_info_rcvport; 1075 struct err_info_rcvport err_info_rcvport;
1086 struct err_info_constraint err_info_rcv_constraint; 1076 struct err_info_constraint err_info_rcv_constraint;
1087 struct err_info_constraint err_info_xmit_constraint; 1077 struct err_info_constraint err_info_xmit_constraint;
1088 u8 err_info_uncorrectable;
1089 u8 err_info_fmconfig;
1090 1078
1091 atomic_t drop_packet; 1079 atomic_t drop_packet;
1092 u8 do_drop; 1080 u8 do_drop;
1081 u8 err_info_uncorrectable;
1082 u8 err_info_fmconfig;
1093 1083
1094 /* 1084 /*
1095 * Software counters for the status bits defined by the 1085 * Software counters for the status bits defined by the
@@ -1112,40 +1102,60 @@ struct hfi1_devdata {
1112 u64 sw_cce_err_status_aggregate; 1102 u64 sw_cce_err_status_aggregate;
1113 /* Software counter that aggregates all bypass packet rcv errors */ 1103 /* Software counter that aggregates all bypass packet rcv errors */
1114 u64 sw_rcv_bypass_packet_errors; 1104 u64 sw_rcv_bypass_packet_errors;
1115 /* receive interrupt functions */ 1105 /* receive interrupt function */
1116 rhf_rcv_function_ptr *rhf_rcv_function_map;
1117 rhf_rcv_function_ptr normal_rhf_rcv_functions[8]; 1106 rhf_rcv_function_ptr normal_rhf_rcv_functions[8];
1118 1107
1108 /* Save the enabled LCB error bits */
1109 u64 lcb_err_en;
1110
1119 /* 1111 /*
1120 * Capability to have different send engines simply by changing a 1112 * Capability to have different send engines simply by changing a
1121 * pointer value. 1113 * pointer value.
1122 */ 1114 */
1123 send_routine process_pio_send; 1115 send_routine process_pio_send ____cacheline_aligned_in_smp;
1124 send_routine process_dma_send; 1116 send_routine process_dma_send;
1125 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf, 1117 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1126 u64 pbc, const void *from, size_t count); 1118 u64 pbc, const void *from, size_t count);
1119 /* hfi1_pportdata, points to array of (physical) port-specific
1120 * data structs, indexed by pidx (0..n-1)
1121 */
1122 struct hfi1_pportdata *pport;
1123 /* receive context data */
1124 struct hfi1_ctxtdata **rcd;
1125 u64 __percpu *int_counter;
1126 /* device (not port) flags, basically device capabilities */
1127 u16 flags;
1128 /* Number of physical ports available */
1129 u8 num_pports;
1130 /* Lowest context number which can be used by user processes */
1131 u8 first_user_ctxt;
1132 /* adding a new field here would make it part of this cacheline */
1133
1134 /* seqlock for sc2vl */
1135 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp;
1136 u64 sc2vl[4];
1137 /* receive interrupt functions */
1138 rhf_rcv_function_ptr *rhf_rcv_function_map;
1139 u64 __percpu *rcv_limit;
1140 u16 rhf_offset; /* offset of RHF within receive header entry */
1141 /* adding a new field here would make it part of this cacheline */
1127 1142
1128 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */ 1143 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1129 u8 oui1; 1144 u8 oui1;
1130 u8 oui2; 1145 u8 oui2;
1131 u8 oui3; 1146 u8 oui3;
1147 u8 dc_shutdown;
1148
1132 /* Timer and counter used to detect RcvBufOvflCnt changes */ 1149 /* Timer and counter used to detect RcvBufOvflCnt changes */
1133 struct timer_list rcverr_timer; 1150 struct timer_list rcverr_timer;
1134 u32 rcv_ovfl_cnt;
1135 1151
1136 wait_queue_head_t event_queue; 1152 wait_queue_head_t event_queue;
1137 1153
1138 /* Save the enabled LCB error bits */
1139 u64 lcb_err_en;
1140 u8 dc_shutdown;
1141
1142 /* receive context tail dummy address */ 1154 /* receive context tail dummy address */
1143 __le64 *rcvhdrtail_dummy_kvaddr; 1155 __le64 *rcvhdrtail_dummy_kvaddr;
1144 dma_addr_t rcvhdrtail_dummy_dma; 1156 dma_addr_t rcvhdrtail_dummy_dma;
1145 1157
1146 bool eprom_available; /* true if EPROM is available for this device */ 1158 u32 rcv_ovfl_cnt;
1147 bool aspm_supported; /* Does HW support ASPM */
1148 bool aspm_enabled; /* ASPM state: enabled/disabled */
1149 /* Serialize ASPM enable/disable between multiple verbs contexts */ 1159 /* Serialize ASPM enable/disable between multiple verbs contexts */
1150 spinlock_t aspm_lock; 1160 spinlock_t aspm_lock;
1151 /* Number of verbs contexts which have disabled ASPM */ 1161 /* Number of verbs contexts which have disabled ASPM */
@@ -1155,8 +1165,11 @@ struct hfi1_devdata {
1155 /* Used to wait for outstanding user space clients before dev removal */ 1165 /* Used to wait for outstanding user space clients before dev removal */
1156 struct completion user_comp; 1166 struct completion user_comp;
1157 1167
1158 struct hfi1_affinity *affinity; 1168 bool eprom_available; /* true if EPROM is available for this device */
1169 bool aspm_supported; /* Does HW support ASPM */
1170 bool aspm_enabled; /* ASPM state: enabled/disabled */
1159 struct rhashtable sdma_rht; 1171 struct rhashtable sdma_rht;
1172
1160 struct kobject kobj; 1173 struct kobject kobj;
1161}; 1174};
1162 1175
@@ -1604,6 +1617,17 @@ static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1604} 1617}
1605 1618
1606/* 1619/*
1620 * Return the indexed GUID from the port GUIDs table.
1621 */
1622static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index)
1623{
1624 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1625
1626 WARN_ON(index >= HFI1_GUIDS_PER_PORT);
1627 return cpu_to_be64(ppd->guids[index]);
1628}
1629
1630/*
1607 * Called by readers of cc_state only, must call under rcu_read_lock(). 1631 * Called by readers of cc_state only, must call under rcu_read_lock().
1608 */ 1632 */
1609static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd) 1633static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
@@ -1982,6 +2006,12 @@ static inline u32 qsfp_resource(struct hfi1_devdata *dd)
1982 return i2c_target(dd->hfi1_id); 2006 return i2c_target(dd->hfi1_id);
1983} 2007}
1984 2008
2009/* Is this device integrated or discrete? */
2010static inline bool is_integrated(struct hfi1_devdata *dd)
2011{
2012 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1;
2013}
2014
1985int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp); 2015int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
1986 2016
1987#define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev)) 2017#define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
diff --git a/drivers/infiniband/hw/hfi1/iowait.h b/drivers/infiniband/hw/hfi1/iowait.h
index 2ec6ef38d389..d9740ddea6f1 100644
--- a/drivers/infiniband/hw/hfi1/iowait.h
+++ b/drivers/infiniband/hw/hfi1/iowait.h
@@ -64,6 +64,7 @@ struct sdma_engine;
64/** 64/**
65 * struct iowait - linkage for delayed progress/waiting 65 * struct iowait - linkage for delayed progress/waiting
66 * @list: used to add/insert into QP/PQ wait lists 66 * @list: used to add/insert into QP/PQ wait lists
67 * @lock: uses to record the list head lock
67 * @tx_head: overflow list of sdma_txreq's 68 * @tx_head: overflow list of sdma_txreq's
68 * @sleep: no space callback 69 * @sleep: no space callback
69 * @wakeup: space callback wakeup 70 * @wakeup: space callback wakeup
@@ -91,6 +92,11 @@ struct sdma_engine;
91 * so sleeping is not allowed. 92 * so sleeping is not allowed.
92 * 93 *
93 * The wait_dma member along with the iow 94 * The wait_dma member along with the iow
95 *
96 * The lock field is used by waiters to record
97 * the seqlock_t that guards the list head.
98 * Waiters explicity know that, but the destroy
99 * code that unwaits QPs does not.
94 */ 100 */
95 101
96struct iowait { 102struct iowait {
@@ -103,6 +109,7 @@ struct iowait {
103 unsigned seq); 109 unsigned seq);
104 void (*wakeup)(struct iowait *wait, int reason); 110 void (*wakeup)(struct iowait *wait, int reason);
105 void (*sdma_drained)(struct iowait *wait); 111 void (*sdma_drained)(struct iowait *wait);
112 seqlock_t *lock;
106 struct work_struct iowork; 113 struct work_struct iowork;
107 wait_queue_head_t wait_dma; 114 wait_queue_head_t wait_dma;
108 wait_queue_head_t wait_pio; 115 wait_queue_head_t wait_pio;
@@ -141,6 +148,7 @@ static inline void iowait_init(
141 void (*sdma_drained)(struct iowait *wait)) 148 void (*sdma_drained)(struct iowait *wait))
142{ 149{
143 wait->count = 0; 150 wait->count = 0;
151 wait->lock = NULL;
144 INIT_LIST_HEAD(&wait->list); 152 INIT_LIST_HEAD(&wait->list);
145 INIT_LIST_HEAD(&wait->tx_head); 153 INIT_LIST_HEAD(&wait->tx_head);
146 INIT_WORK(&wait->iowork, func); 154 INIT_WORK(&wait->iowork, func);
diff --git a/drivers/infiniband/hw/hfi1/mad.c b/drivers/infiniband/hw/hfi1/mad.c
index 9487c9bb8920..6e595afca24c 100644
--- a/drivers/infiniband/hw/hfi1/mad.c
+++ b/drivers/infiniband/hw/hfi1/mad.c
@@ -128,7 +128,7 @@ static void send_trap(struct hfi1_ibport *ibp, void *data, unsigned len)
128 smp = send_buf->mad; 128 smp = send_buf->mad;
129 smp->base_version = OPA_MGMT_BASE_VERSION; 129 smp->base_version = OPA_MGMT_BASE_VERSION;
130 smp->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 130 smp->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
131 smp->class_version = OPA_SMI_CLASS_VERSION; 131 smp->class_version = OPA_SM_CLASS_VERSION;
132 smp->method = IB_MGMT_METHOD_TRAP; 132 smp->method = IB_MGMT_METHOD_TRAP;
133 ibp->rvp.tid++; 133 ibp->rvp.tid++;
134 smp->tid = cpu_to_be64(ibp->rvp.tid); 134 smp->tid = cpu_to_be64(ibp->rvp.tid);
@@ -336,20 +336,20 @@ static int __subn_get_opa_nodeinfo(struct opa_smp *smp, u32 am, u8 *data,
336 ni = (struct opa_node_info *)data; 336 ni = (struct opa_node_info *)data;
337 337
338 /* GUID 0 is illegal */ 338 /* GUID 0 is illegal */
339 if (am || pidx >= dd->num_pports || dd->pport[pidx].guid == 0) { 339 if (am || pidx >= dd->num_pports || ibdev->node_guid == 0 ||
340 get_sguid(to_iport(ibdev, port), HFI1_PORT_GUID_INDEX) == 0) {
340 smp->status |= IB_SMP_INVALID_FIELD; 341 smp->status |= IB_SMP_INVALID_FIELD;
341 return reply((struct ib_mad_hdr *)smp); 342 return reply((struct ib_mad_hdr *)smp);
342 } 343 }
343 344
344 ni->port_guid = cpu_to_be64(dd->pport[pidx].guid); 345 ni->port_guid = get_sguid(to_iport(ibdev, port), HFI1_PORT_GUID_INDEX);
345 ni->base_version = OPA_MGMT_BASE_VERSION; 346 ni->base_version = OPA_MGMT_BASE_VERSION;
346 ni->class_version = OPA_SMI_CLASS_VERSION; 347 ni->class_version = OPA_SM_CLASS_VERSION;
347 ni->node_type = 1; /* channel adapter */ 348 ni->node_type = 1; /* channel adapter */
348 ni->num_ports = ibdev->phys_port_cnt; 349 ni->num_ports = ibdev->phys_port_cnt;
349 /* This is already in network order */ 350 /* This is already in network order */
350 ni->system_image_guid = ib_hfi1_sys_image_guid; 351 ni->system_image_guid = ib_hfi1_sys_image_guid;
351 /* Use first-port GUID as node */ 352 ni->node_guid = ibdev->node_guid;
352 ni->node_guid = cpu_to_be64(dd->pport->guid);
353 ni->partition_cap = cpu_to_be16(hfi1_get_npkeys(dd)); 353 ni->partition_cap = cpu_to_be16(hfi1_get_npkeys(dd));
354 ni->device_id = cpu_to_be16(dd->pcidev->device); 354 ni->device_id = cpu_to_be16(dd->pcidev->device);
355 ni->revision = cpu_to_be32(dd->minrev); 355 ni->revision = cpu_to_be32(dd->minrev);
@@ -373,19 +373,20 @@ static int subn_get_nodeinfo(struct ib_smp *smp, struct ib_device *ibdev,
373 373
374 /* GUID 0 is illegal */ 374 /* GUID 0 is illegal */
375 if (smp->attr_mod || pidx >= dd->num_pports || 375 if (smp->attr_mod || pidx >= dd->num_pports ||
376 dd->pport[pidx].guid == 0) 376 ibdev->node_guid == 0 ||
377 get_sguid(to_iport(ibdev, port), HFI1_PORT_GUID_INDEX) == 0) {
377 smp->status |= IB_SMP_INVALID_FIELD; 378 smp->status |= IB_SMP_INVALID_FIELD;
378 else 379 return reply((struct ib_mad_hdr *)smp);
379 nip->port_guid = cpu_to_be64(dd->pport[pidx].guid); 380 }
380 381
382 nip->port_guid = get_sguid(to_iport(ibdev, port), HFI1_PORT_GUID_INDEX);
381 nip->base_version = OPA_MGMT_BASE_VERSION; 383 nip->base_version = OPA_MGMT_BASE_VERSION;
382 nip->class_version = OPA_SMI_CLASS_VERSION; 384 nip->class_version = OPA_SM_CLASS_VERSION;
383 nip->node_type = 1; /* channel adapter */ 385 nip->node_type = 1; /* channel adapter */
384 nip->num_ports = ibdev->phys_port_cnt; 386 nip->num_ports = ibdev->phys_port_cnt;
385 /* This is already in network order */ 387 /* This is already in network order */
386 nip->sys_guid = ib_hfi1_sys_image_guid; 388 nip->sys_guid = ib_hfi1_sys_image_guid;
387 /* Use first-port GUID as node */ 389 nip->node_guid = ibdev->node_guid;
388 nip->node_guid = cpu_to_be64(dd->pport->guid);
389 nip->partition_cap = cpu_to_be16(hfi1_get_npkeys(dd)); 390 nip->partition_cap = cpu_to_be16(hfi1_get_npkeys(dd));
390 nip->device_id = cpu_to_be16(dd->pcidev->device); 391 nip->device_id = cpu_to_be16(dd->pcidev->device);
391 nip->revision = cpu_to_be32(dd->minrev); 392 nip->revision = cpu_to_be32(dd->minrev);
@@ -2302,7 +2303,7 @@ static int pma_get_opa_classportinfo(struct opa_pma_mad *pmp,
2302 pmp->mad_hdr.status |= IB_SMP_INVALID_FIELD; 2303 pmp->mad_hdr.status |= IB_SMP_INVALID_FIELD;
2303 2304
2304 p->base_version = OPA_MGMT_BASE_VERSION; 2305 p->base_version = OPA_MGMT_BASE_VERSION;
2305 p->class_version = OPA_SMI_CLASS_VERSION; 2306 p->class_version = OPA_SM_CLASS_VERSION;
2306 /* 2307 /*
2307 * Expected response time is 4.096 usec. * 2^18 == 1.073741824 sec. 2308 * Expected response time is 4.096 usec. * 2^18 == 1.073741824 sec.
2308 */ 2309 */
@@ -4022,7 +4023,7 @@ static int process_subn_opa(struct ib_device *ibdev, int mad_flags,
4022 4023
4023 am = be32_to_cpu(smp->attr_mod); 4024 am = be32_to_cpu(smp->attr_mod);
4024 attr_id = smp->attr_id; 4025 attr_id = smp->attr_id;
4025 if (smp->class_version != OPA_SMI_CLASS_VERSION) { 4026 if (smp->class_version != OPA_SM_CLASS_VERSION) {
4026 smp->status |= IB_SMP_UNSUP_VERSION; 4027 smp->status |= IB_SMP_UNSUP_VERSION;
4027 ret = reply((struct ib_mad_hdr *)smp); 4028 ret = reply((struct ib_mad_hdr *)smp);
4028 return ret; 4029 return ret;
@@ -4232,7 +4233,7 @@ static int process_perf_opa(struct ib_device *ibdev, u8 port,
4232 4233
4233 *out_mad = *in_mad; 4234 *out_mad = *in_mad;
4234 4235
4235 if (pmp->mad_hdr.class_version != OPA_SMI_CLASS_VERSION) { 4236 if (pmp->mad_hdr.class_version != OPA_SM_CLASS_VERSION) {
4236 pmp->mad_hdr.status |= IB_SMP_UNSUP_VERSION; 4237 pmp->mad_hdr.status |= IB_SMP_UNSUP_VERSION;
4237 return reply((struct ib_mad_hdr *)pmp); 4238 return reply((struct ib_mad_hdr *)pmp);
4238 } 4239 }
diff --git a/drivers/infiniband/hw/hfi1/mmu_rb.c b/drivers/infiniband/hw/hfi1/mmu_rb.c
index 7ad30898fc19..ccbf52c8ff6f 100644
--- a/drivers/infiniband/hw/hfi1/mmu_rb.c
+++ b/drivers/infiniband/hw/hfi1/mmu_rb.c
@@ -81,7 +81,7 @@ static void do_remove(struct mmu_rb_handler *handler,
81 struct list_head *del_list); 81 struct list_head *del_list);
82static void handle_remove(struct work_struct *work); 82static void handle_remove(struct work_struct *work);
83 83
84static struct mmu_notifier_ops mn_opts = { 84static const struct mmu_notifier_ops mn_opts = {
85 .invalidate_page = mmu_notifier_page, 85 .invalidate_page = mmu_notifier_page,
86 .invalidate_range_start = mmu_notifier_range_start, 86 .invalidate_range_start = mmu_notifier_range_start,
87}; 87};
diff --git a/drivers/infiniband/hw/hfi1/pio.c b/drivers/infiniband/hw/hfi1/pio.c
index d89b8745d4c1..615be68e40b3 100644
--- a/drivers/infiniband/hw/hfi1/pio.c
+++ b/drivers/infiniband/hw/hfi1/pio.c
@@ -758,6 +758,7 @@ struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
758 sc->hw_context = hw_context; 758 sc->hw_context = hw_context;
759 cr_group_addresses(sc, &dma); 759 cr_group_addresses(sc, &dma);
760 sc->credits = sci->credits; 760 sc->credits = sci->credits;
761 sc->size = sc->credits * PIO_BLOCK_SIZE;
761 762
762/* PIO Send Memory Address details */ 763/* PIO Send Memory Address details */
763#define PIO_ADDR_CONTEXT_MASK 0xfful 764#define PIO_ADDR_CONTEXT_MASK 0xfful
@@ -1242,6 +1243,7 @@ int sc_enable(struct send_context *sc)
1242 sc->free = 0; 1243 sc->free = 0;
1243 sc->alloc_free = 0; 1244 sc->alloc_free = 0;
1244 sc->fill = 0; 1245 sc->fill = 0;
1246 sc->fill_wrap = 0;
1245 sc->sr_head = 0; 1247 sc->sr_head = 0;
1246 sc->sr_tail = 0; 1248 sc->sr_tail = 0;
1247 sc->flags = 0; 1249 sc->flags = 0;
@@ -1385,7 +1387,7 @@ struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
1385 unsigned long flags; 1387 unsigned long flags;
1386 unsigned long avail; 1388 unsigned long avail;
1387 unsigned long blocks = dwords_to_blocks(dw_len); 1389 unsigned long blocks = dwords_to_blocks(dw_len);
1388 unsigned long start_fill; 1390 u32 fill_wrap;
1389 int trycount = 0; 1391 int trycount = 0;
1390 u32 head, next; 1392 u32 head, next;
1391 1393
@@ -1410,9 +1412,7 @@ retry:
1410 (sc->fill - sc->alloc_free); 1412 (sc->fill - sc->alloc_free);
1411 if (blocks > avail) { 1413 if (blocks > avail) {
1412 /* still no room, actively update */ 1414 /* still no room, actively update */
1413 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1414 sc_release_update(sc); 1415 sc_release_update(sc);
1415 spin_lock_irqsave(&sc->alloc_lock, flags);
1416 sc->alloc_free = ACCESS_ONCE(sc->free); 1416 sc->alloc_free = ACCESS_ONCE(sc->free);
1417 trycount++; 1417 trycount++;
1418 goto retry; 1418 goto retry;
@@ -1428,8 +1428,11 @@ retry:
1428 head = sc->sr_head; 1428 head = sc->sr_head;
1429 1429
1430 /* "allocate" the buffer */ 1430 /* "allocate" the buffer */
1431 start_fill = sc->fill;
1432 sc->fill += blocks; 1431 sc->fill += blocks;
1432 fill_wrap = sc->fill_wrap;
1433 sc->fill_wrap += blocks;
1434 if (sc->fill_wrap >= sc->credits)
1435 sc->fill_wrap = sc->fill_wrap - sc->credits;
1433 1436
1434 /* 1437 /*
1435 * Fill the parts that the releaser looks at before moving the head. 1438 * Fill the parts that the releaser looks at before moving the head.
@@ -1458,11 +1461,8 @@ retry:
1458 spin_unlock_irqrestore(&sc->alloc_lock, flags); 1461 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1459 1462
1460 /* finish filling in the buffer outside the lock */ 1463 /* finish filling in the buffer outside the lock */
1461 pbuf->start = sc->base_addr + ((start_fill % sc->credits) 1464 pbuf->start = sc->base_addr + fill_wrap * PIO_BLOCK_SIZE;
1462 * PIO_BLOCK_SIZE); 1465 pbuf->end = sc->base_addr + sc->size;
1463 pbuf->size = sc->credits * PIO_BLOCK_SIZE;
1464 pbuf->end = sc->base_addr + pbuf->size;
1465 pbuf->block_count = blocks;
1466 pbuf->qw_written = 0; 1466 pbuf->qw_written = 0;
1467 pbuf->carry_bytes = 0; 1467 pbuf->carry_bytes = 0;
1468 pbuf->carry.val64 = 0; 1468 pbuf->carry.val64 = 0;
@@ -1573,6 +1573,7 @@ static void sc_piobufavail(struct send_context *sc)
1573 qp = iowait_to_qp(wait); 1573 qp = iowait_to_qp(wait);
1574 priv = qp->priv; 1574 priv = qp->priv;
1575 list_del_init(&priv->s_iowait.list); 1575 list_del_init(&priv->s_iowait.list);
1576 priv->s_iowait.lock = NULL;
1576 /* refcount held until actual wake up */ 1577 /* refcount held until actual wake up */
1577 qps[n++] = qp; 1578 qps[n++] = qp;
1578 } 1579 }
@@ -2028,29 +2029,17 @@ freesc15:
2028int init_credit_return(struct hfi1_devdata *dd) 2029int init_credit_return(struct hfi1_devdata *dd)
2029{ 2030{
2030 int ret; 2031 int ret;
2031 int num_numa;
2032 int i; 2032 int i;
2033 2033
2034 num_numa = num_online_nodes();
2035 /* enforce the expectation that the numas are compact */
2036 for (i = 0; i < num_numa; i++) {
2037 if (!node_online(i)) {
2038 dd_dev_err(dd, "NUMA nodes are not compact\n");
2039 ret = -EINVAL;
2040 goto done;
2041 }
2042 }
2043
2044 dd->cr_base = kcalloc( 2034 dd->cr_base = kcalloc(
2045 num_numa, 2035 node_affinity.num_possible_nodes,
2046 sizeof(struct credit_return_base), 2036 sizeof(struct credit_return_base),
2047 GFP_KERNEL); 2037 GFP_KERNEL);
2048 if (!dd->cr_base) { 2038 if (!dd->cr_base) {
2049 dd_dev_err(dd, "Unable to allocate credit return base\n");
2050 ret = -ENOMEM; 2039 ret = -ENOMEM;
2051 goto done; 2040 goto done;
2052 } 2041 }
2053 for (i = 0; i < num_numa; i++) { 2042 for_each_node_with_cpus(i) {
2054 int bytes = TXE_NUM_CONTEXTS * sizeof(struct credit_return); 2043 int bytes = TXE_NUM_CONTEXTS * sizeof(struct credit_return);
2055 2044
2056 set_dev_node(&dd->pcidev->dev, i); 2045 set_dev_node(&dd->pcidev->dev, i);
@@ -2077,14 +2066,11 @@ done:
2077 2066
2078void free_credit_return(struct hfi1_devdata *dd) 2067void free_credit_return(struct hfi1_devdata *dd)
2079{ 2068{
2080 int num_numa;
2081 int i; 2069 int i;
2082 2070
2083 if (!dd->cr_base) 2071 if (!dd->cr_base)
2084 return; 2072 return;
2085 2073 for (i = 0; i < node_affinity.num_possible_nodes; i++) {
2086 num_numa = num_online_nodes();
2087 for (i = 0; i < num_numa; i++) {
2088 if (dd->cr_base[i].va) { 2074 if (dd->cr_base[i].va) {
2089 dma_free_coherent(&dd->pcidev->dev, 2075 dma_free_coherent(&dd->pcidev->dev,
2090 TXE_NUM_CONTEXTS * 2076 TXE_NUM_CONTEXTS *
diff --git a/drivers/infiniband/hw/hfi1/pio.h b/drivers/infiniband/hw/hfi1/pio.h
index e709eaf743b5..867e5ffc3595 100644
--- a/drivers/infiniband/hw/hfi1/pio.h
+++ b/drivers/infiniband/hw/hfi1/pio.h
@@ -83,53 +83,55 @@ struct pio_buf {
83 void *arg; /* argument for cb */ 83 void *arg; /* argument for cb */
84 void __iomem *start; /* buffer start address */ 84 void __iomem *start; /* buffer start address */
85 void __iomem *end; /* context end address */ 85 void __iomem *end; /* context end address */
86 unsigned long size; /* context size, in bytes */
87 unsigned long sent_at; /* buffer is sent when <= free */ 86 unsigned long sent_at; /* buffer is sent when <= free */
88 u32 block_count; /* size of buffer, in blocks */
89 u32 qw_written; /* QW written so far */
90 u32 carry_bytes; /* number of valid bytes in carry */
91 union mix carry; /* pending unwritten bytes */ 87 union mix carry; /* pending unwritten bytes */
88 u16 qw_written; /* QW written so far */
89 u8 carry_bytes; /* number of valid bytes in carry */
92}; 90};
93 91
94/* cache line aligned pio buffer array */ 92/* cache line aligned pio buffer array */
95union pio_shadow_ring { 93union pio_shadow_ring {
96 struct pio_buf pbuf; 94 struct pio_buf pbuf;
97 u64 unused[16]; /* cache line spacer */
98} ____cacheline_aligned; 95} ____cacheline_aligned;
99 96
100/* per-NUMA send context */ 97/* per-NUMA send context */
101struct send_context { 98struct send_context {
102 /* read-only after init */ 99 /* read-only after init */
103 struct hfi1_devdata *dd; /* device */ 100 struct hfi1_devdata *dd; /* device */
104 void __iomem *base_addr; /* start of PIO memory */
105 union pio_shadow_ring *sr; /* shadow ring */ 101 union pio_shadow_ring *sr; /* shadow ring */
102 void __iomem *base_addr; /* start of PIO memory */
103 u32 __percpu *buffers_allocated;/* count of buffers allocated */
104 u32 size; /* context size, in bytes */
106 105
107 volatile __le64 *hw_free; /* HW free counter */
108 struct work_struct halt_work; /* halted context work queue entry */
109 unsigned long flags; /* flags */
110 int node; /* context home node */ 106 int node; /* context home node */
111 int type; /* context type */
112 u32 sw_index; /* software index number */
113 u32 hw_context; /* hardware context number */
114 u32 credits; /* number of blocks in context */
115 u32 sr_size; /* size of the shadow ring */ 107 u32 sr_size; /* size of the shadow ring */
116 u32 group; /* credit return group */ 108 u16 flags; /* flags */
109 u8 type; /* context type */
110 u8 sw_index; /* software index number */
111 u8 hw_context; /* hardware context number */
112 u8 group; /* credit return group */
113
117 /* allocator fields */ 114 /* allocator fields */
118 spinlock_t alloc_lock ____cacheline_aligned_in_smp; 115 spinlock_t alloc_lock ____cacheline_aligned_in_smp;
116 u32 sr_head; /* shadow ring head */
119 unsigned long fill; /* official alloc count */ 117 unsigned long fill; /* official alloc count */
120 unsigned long alloc_free; /* copy of free (less cache thrash) */ 118 unsigned long alloc_free; /* copy of free (less cache thrash) */
121 u32 sr_head; /* shadow ring head */ 119 u32 fill_wrap; /* tracks fill within ring */
120 u32 credits; /* number of blocks in context */
121 /* adding a new field here would make it part of this cacheline */
122
122 /* releaser fields */ 123 /* releaser fields */
123 spinlock_t release_lock ____cacheline_aligned_in_smp; 124 spinlock_t release_lock ____cacheline_aligned_in_smp;
124 unsigned long free; /* official free count */
125 u32 sr_tail; /* shadow ring tail */ 125 u32 sr_tail; /* shadow ring tail */
126 unsigned long free; /* official free count */
127 volatile __le64 *hw_free; /* HW free counter */
126 /* list for PIO waiters */ 128 /* list for PIO waiters */
127 struct list_head piowait ____cacheline_aligned_in_smp; 129 struct list_head piowait ____cacheline_aligned_in_smp;
128 spinlock_t credit_ctrl_lock ____cacheline_aligned_in_smp; 130 spinlock_t credit_ctrl_lock ____cacheline_aligned_in_smp;
129 u64 credit_ctrl; /* cache for credit control */
130 u32 credit_intr_count; /* count of credit intr users */ 131 u32 credit_intr_count; /* count of credit intr users */
131 u32 __percpu *buffers_allocated;/* count of buffers allocated */ 132 u64 credit_ctrl; /* cache for credit control */
132 wait_queue_head_t halt_wait; /* wait until kernel sees interrupt */ 133 wait_queue_head_t halt_wait; /* wait until kernel sees interrupt */
134 struct work_struct halt_work; /* halted context work queue entry */
133}; 135};
134 136
135/* send context flags */ 137/* send context flags */
diff --git a/drivers/infiniband/hw/hfi1/pio_copy.c b/drivers/infiniband/hw/hfi1/pio_copy.c
index aa7773643107..03024cec78dd 100644
--- a/drivers/infiniband/hw/hfi1/pio_copy.c
+++ b/drivers/infiniband/hw/hfi1/pio_copy.c
@@ -129,8 +129,8 @@ void pio_copy(struct hfi1_devdata *dd, struct pio_buf *pbuf, u64 pbc,
129 dest += sizeof(u64); 129 dest += sizeof(u64);
130 } 130 }
131 131
132 dest -= pbuf->size; 132 dest -= pbuf->sc->size;
133 dend -= pbuf->size; 133 dend -= pbuf->sc->size;
134 } 134 }
135 135
136 /* write 8-byte non-SOP, non-wrap chunk data */ 136 /* write 8-byte non-SOP, non-wrap chunk data */
@@ -361,8 +361,8 @@ void seg_pio_copy_start(struct pio_buf *pbuf, u64 pbc,
361 dest += sizeof(u64); 361 dest += sizeof(u64);
362 } 362 }
363 363
364 dest -= pbuf->size; 364 dest -= pbuf->sc->size;
365 dend -= pbuf->size; 365 dend -= pbuf->sc->size;
366 } 366 }
367 367
368 /* write 8-byte non-SOP, non-wrap chunk data */ 368 /* write 8-byte non-SOP, non-wrap chunk data */
@@ -458,8 +458,8 @@ static void mid_copy_mix(struct pio_buf *pbuf, const void *from, size_t nbytes)
458 dest += sizeof(u64); 458 dest += sizeof(u64);
459 } 459 }
460 460
461 dest -= pbuf->size; 461 dest -= pbuf->sc->size;
462 dend -= pbuf->size; 462 dend -= pbuf->sc->size;
463 } 463 }
464 464
465 /* write 8-byte non-SOP, non-wrap chunk data */ 465 /* write 8-byte non-SOP, non-wrap chunk data */
@@ -492,7 +492,7 @@ static void mid_copy_mix(struct pio_buf *pbuf, const void *from, size_t nbytes)
492 */ 492 */
493 /* adjust if we have wrapped */ 493 /* adjust if we have wrapped */
494 if (dest >= pbuf->end) 494 if (dest >= pbuf->end)
495 dest -= pbuf->size; 495 dest -= pbuf->sc->size;
496 /* jump to the SOP range if within the first block */ 496 /* jump to the SOP range if within the first block */
497 else if (pbuf->qw_written < PIO_BLOCK_QWS) 497 else if (pbuf->qw_written < PIO_BLOCK_QWS)
498 dest += SOP_DISTANCE; 498 dest += SOP_DISTANCE;
@@ -584,8 +584,8 @@ static void mid_copy_straight(struct pio_buf *pbuf,
584 dest += sizeof(u64); 584 dest += sizeof(u64);
585 } 585 }
586 586
587 dest -= pbuf->size; 587 dest -= pbuf->sc->size;
588 dend -= pbuf->size; 588 dend -= pbuf->sc->size;
589 } 589 }
590 590
591 /* write 8-byte non-SOP, non-wrap chunk data */ 591 /* write 8-byte non-SOP, non-wrap chunk data */
@@ -666,7 +666,7 @@ void seg_pio_copy_mid(struct pio_buf *pbuf, const void *from, size_t nbytes)
666 */ 666 */
667 /* adjust if we've wrapped */ 667 /* adjust if we've wrapped */
668 if (dest >= pbuf->end) 668 if (dest >= pbuf->end)
669 dest -= pbuf->size; 669 dest -= pbuf->sc->size;
670 /* jump to SOP range if within the first block */ 670 /* jump to SOP range if within the first block */
671 else if (pbuf->qw_written < PIO_BLOCK_QWS) 671 else if (pbuf->qw_written < PIO_BLOCK_QWS)
672 dest += SOP_DISTANCE; 672 dest += SOP_DISTANCE;
@@ -719,7 +719,7 @@ void seg_pio_copy_end(struct pio_buf *pbuf)
719 */ 719 */
720 /* adjust if we have wrapped */ 720 /* adjust if we have wrapped */
721 if (dest >= pbuf->end) 721 if (dest >= pbuf->end)
722 dest -= pbuf->size; 722 dest -= pbuf->sc->size;
723 /* jump to the SOP range if within the first block */ 723 /* jump to the SOP range if within the first block */
724 else if (pbuf->qw_written < PIO_BLOCK_QWS) 724 else if (pbuf->qw_written < PIO_BLOCK_QWS)
725 dest += SOP_DISTANCE; 725 dest += SOP_DISTANCE;
diff --git a/drivers/infiniband/hw/hfi1/platform.c b/drivers/infiniband/hw/hfi1/platform.c
index 202433178864..838fe84e285a 100644
--- a/drivers/infiniband/hw/hfi1/platform.c
+++ b/drivers/infiniband/hw/hfi1/platform.c
@@ -49,6 +49,90 @@
49#include "efivar.h" 49#include "efivar.h"
50#include "eprom.h" 50#include "eprom.h"
51 51
52static int validate_scratch_checksum(struct hfi1_devdata *dd)
53{
54 u64 checksum = 0, temp_scratch = 0;
55 int i, j, version;
56
57 temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH);
58 version = (temp_scratch & BITMAP_VERSION_SMASK) >> BITMAP_VERSION_SHIFT;
59
60 /* Prevent power on default of all zeroes from passing checksum */
61 if (!version)
62 return 0;
63
64 /*
65 * ASIC scratch 0 only contains the checksum and bitmap version as
66 * fields of interest, both of which are handled separately from the
67 * loop below, so skip it
68 */
69 checksum += version;
70 for (i = 1; i < ASIC_NUM_SCRATCH; i++) {
71 temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH + (8 * i));
72 for (j = sizeof(u64); j != 0; j -= 2) {
73 checksum += (temp_scratch & 0xFFFF);
74 temp_scratch >>= 16;
75 }
76 }
77
78 while (checksum >> 16)
79 checksum = (checksum & CHECKSUM_MASK) + (checksum >> 16);
80
81 temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH);
82 temp_scratch &= CHECKSUM_SMASK;
83 temp_scratch >>= CHECKSUM_SHIFT;
84
85 if (checksum + temp_scratch == 0xFFFF)
86 return 1;
87 return 0;
88}
89
90static void save_platform_config_fields(struct hfi1_devdata *dd)
91{
92 struct hfi1_pportdata *ppd = dd->pport;
93 u64 temp_scratch = 0, temp_dest = 0;
94
95 temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH_1);
96
97 temp_dest = temp_scratch &
98 (dd->hfi1_id ? PORT1_PORT_TYPE_SMASK :
99 PORT0_PORT_TYPE_SMASK);
100 ppd->port_type = temp_dest >>
101 (dd->hfi1_id ? PORT1_PORT_TYPE_SHIFT :
102 PORT0_PORT_TYPE_SHIFT);
103
104 temp_dest = temp_scratch &
105 (dd->hfi1_id ? PORT1_LOCAL_ATTEN_SMASK :
106 PORT0_LOCAL_ATTEN_SMASK);
107 ppd->local_atten = temp_dest >>
108 (dd->hfi1_id ? PORT1_LOCAL_ATTEN_SHIFT :
109 PORT0_LOCAL_ATTEN_SHIFT);
110
111 temp_dest = temp_scratch &
112 (dd->hfi1_id ? PORT1_REMOTE_ATTEN_SMASK :
113 PORT0_REMOTE_ATTEN_SMASK);
114 ppd->remote_atten = temp_dest >>
115 (dd->hfi1_id ? PORT1_REMOTE_ATTEN_SHIFT :
116 PORT0_REMOTE_ATTEN_SHIFT);
117
118 temp_dest = temp_scratch &
119 (dd->hfi1_id ? PORT1_DEFAULT_ATTEN_SMASK :
120 PORT0_DEFAULT_ATTEN_SMASK);
121 ppd->default_atten = temp_dest >>
122 (dd->hfi1_id ? PORT1_DEFAULT_ATTEN_SHIFT :
123 PORT0_DEFAULT_ATTEN_SHIFT);
124
125 temp_scratch = read_csr(dd, dd->hfi1_id ? ASIC_CFG_SCRATCH_3 :
126 ASIC_CFG_SCRATCH_2);
127
128 ppd->tx_preset_eq = (temp_scratch & TX_EQ_SMASK) >> TX_EQ_SHIFT;
129 ppd->tx_preset_noeq = (temp_scratch & TX_NO_EQ_SMASK) >> TX_NO_EQ_SHIFT;
130 ppd->rx_preset = (temp_scratch & RX_SMASK) >> RX_SHIFT;
131
132 ppd->max_power_class = (temp_scratch & QSFP_MAX_POWER_SMASK) >>
133 QSFP_MAX_POWER_SHIFT;
134}
135
52void get_platform_config(struct hfi1_devdata *dd) 136void get_platform_config(struct hfi1_devdata *dd)
53{ 137{
54 int ret = 0; 138 int ret = 0;
@@ -56,38 +140,49 @@ void get_platform_config(struct hfi1_devdata *dd)
56 u8 *temp_platform_config = NULL; 140 u8 *temp_platform_config = NULL;
57 u32 esize; 141 u32 esize;
58 142
59 ret = eprom_read_platform_config(dd, (void **)&temp_platform_config, 143 if (is_integrated(dd)) {
60 &esize); 144 if (validate_scratch_checksum(dd)) {
61 if (!ret) { 145 save_platform_config_fields(dd);
62 /* success */ 146 return;
63 size = esize; 147 }
64 goto success; 148 dd_dev_err(dd, "%s: Config bitmap corrupted/uninitialized\n",
149 __func__);
150 dd_dev_err(dd,
151 "%s: Please update your BIOS to support active channels\n",
152 __func__);
153 } else {
154 ret = eprom_read_platform_config(dd,
155 (void **)&temp_platform_config,
156 &esize);
157 if (!ret) {
158 /* success */
159 dd->platform_config.data = temp_platform_config;
160 dd->platform_config.size = esize;
161 return;
162 }
163 /* fail, try EFI variable */
164
165 ret = read_hfi1_efi_var(dd, "configuration", &size,
166 (void **)&temp_platform_config);
167 if (!ret) {
168 dd->platform_config.data = temp_platform_config;
169 dd->platform_config.size = size;
170 return;
171 }
65 } 172 }
66 /* fail, try EFI variable */ 173 dd_dev_err(dd,
67 174 "%s: Failed to get platform config, falling back to sub-optimal default file\n",
68 ret = read_hfi1_efi_var(dd, "configuration", &size, 175 __func__);
69 (void **)&temp_platform_config);
70 if (!ret)
71 goto success;
72
73 dd_dev_info(dd,
74 "%s: Failed to get platform config from UEFI, falling back to request firmware\n",
75 __func__);
76 /* fall back to request firmware */ 176 /* fall back to request firmware */
77 platform_config_load = 1; 177 platform_config_load = 1;
78 return;
79
80success:
81 dd->platform_config.data = temp_platform_config;
82 dd->platform_config.size = size;
83} 178}
84 179
85void free_platform_config(struct hfi1_devdata *dd) 180void free_platform_config(struct hfi1_devdata *dd)
86{ 181{
87 if (!platform_config_load) { 182 if (!platform_config_load) {
88 /* 183 /*
89 * was loaded from EFI, release memory 184 * was loaded from EFI or the EPROM, release memory
90 * allocated by read_efi_var 185 * allocated by read_efi_var/eprom_read_platform_config
91 */ 186 */
92 kfree(dd->platform_config.data); 187 kfree(dd->platform_config.data);
93 } 188 }
@@ -100,12 +195,16 @@ void free_platform_config(struct hfi1_devdata *dd)
100void get_port_type(struct hfi1_pportdata *ppd) 195void get_port_type(struct hfi1_pportdata *ppd)
101{ 196{
102 int ret; 197 int ret;
198 u32 temp;
103 199
104 ret = get_platform_config_field(ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0, 200 ret = get_platform_config_field(ppd->dd, PLATFORM_CONFIG_PORT_TABLE, 0,
105 PORT_TABLE_PORT_TYPE, &ppd->port_type, 201 PORT_TABLE_PORT_TYPE, &temp,
106 4); 202 4);
107 if (ret) 203 if (ret) {
108 ppd->port_type = PORT_TYPE_UNKNOWN; 204 ppd->port_type = PORT_TYPE_UNKNOWN;
205 return;
206 }
207 ppd->port_type = temp;
109} 208}
110 209
111int set_qsfp_tx(struct hfi1_pportdata *ppd, int on) 210int set_qsfp_tx(struct hfi1_pportdata *ppd, int on)
@@ -538,6 +637,38 @@ static void apply_tx_lanes(struct hfi1_pportdata *ppd, u8 field_id,
538 } 637 }
539} 638}
540 639
640/*
641 * Return a special SerDes setting for low power AOC cables. The power class
642 * threshold and setting being used were all found by empirical testing.
643 *
644 * Summary of the logic:
645 *
646 * if (QSFP and QSFP_TYPE == AOC and QSFP_POWER_CLASS < 4)
647 * return 0xe
648 * return 0; // leave at default
649 */
650static u8 aoc_low_power_setting(struct hfi1_pportdata *ppd)
651{
652 u8 *cache = ppd->qsfp_info.cache;
653 int power_class;
654
655 /* QSFP only */
656 if (ppd->port_type != PORT_TYPE_QSFP)
657 return 0; /* leave at default */
658
659 /* active optical cables only */
660 switch ((cache[QSFP_MOD_TECH_OFFS] & 0xF0) >> 4) {
661 case 0x0 ... 0x9: /* fallthrough */
662 case 0xC: /* fallthrough */
663 case 0xE:
664 /* active AOC */
665 power_class = get_qsfp_power_class(cache[QSFP_MOD_PWR_OFFS]);
666 if (power_class < QSFP_POWER_CLASS_4)
667 return 0xe;
668 }
669 return 0; /* leave at default */
670}
671
541static void apply_tunings( 672static void apply_tunings(
542 struct hfi1_pportdata *ppd, u32 tx_preset_index, 673 struct hfi1_pportdata *ppd, u32 tx_preset_index,
543 u8 tuning_method, u32 total_atten, u8 limiting_active) 674 u8 tuning_method, u32 total_atten, u8 limiting_active)
@@ -606,7 +737,17 @@ static void apply_tunings(
606 tx_preset_index, TX_PRESET_TABLE_POSTCUR, &tx_preset, 4); 737 tx_preset_index, TX_PRESET_TABLE_POSTCUR, &tx_preset, 4);
607 postcur = tx_preset; 738 postcur = tx_preset;
608 739
609 config_data = precur | (attn << 8) | (postcur << 16); 740 /*
741 * NOTES:
742 * o The aoc_low_power_setting is applied to all lanes even
743 * though only lane 0's value is examined by the firmware.
744 * o A lingering low power setting after a cable swap does
745 * not occur. On cable unplug the 8051 is reset and
746 * restarted on cable insert. This resets all settings to
747 * their default, erasing any previous low power setting.
748 */
749 config_data = precur | (attn << 8) | (postcur << 16) |
750 (aoc_low_power_setting(ppd) << 24);
610 751
611 apply_tx_lanes(ppd, TX_EQ_SETTINGS, config_data, 752 apply_tx_lanes(ppd, TX_EQ_SETTINGS, config_data,
612 "Applying TX settings"); 753 "Applying TX settings");
diff --git a/drivers/infiniband/hw/hfi1/platform.h b/drivers/infiniband/hw/hfi1/platform.h
index e2c21613c326..eed0aa9124fa 100644
--- a/drivers/infiniband/hw/hfi1/platform.h
+++ b/drivers/infiniband/hw/hfi1/platform.h
@@ -168,16 +168,6 @@ struct platform_config_cache {
168 struct platform_config_data config_tables[PLATFORM_CONFIG_TABLE_MAX]; 168 struct platform_config_data config_tables[PLATFORM_CONFIG_TABLE_MAX];
169}; 169};
170 170
171static const u32 platform_config_table_limits[PLATFORM_CONFIG_TABLE_MAX] = {
172 0,
173 SYSTEM_TABLE_MAX,
174 PORT_TABLE_MAX,
175 RX_PRESET_TABLE_MAX,
176 TX_PRESET_TABLE_MAX,
177 QSFP_ATTEN_TABLE_MAX,
178 VARIABLE_SETTINGS_TABLE_MAX
179};
180
181/* This section defines default values and encodings for the 171/* This section defines default values and encodings for the
182 * fields defined for each table above 172 * fields defined for each table above
183 */ 173 */
@@ -295,6 +285,123 @@ enum link_tuning_encoding {
295 OPA_UNKNOWN_TUNING 285 OPA_UNKNOWN_TUNING
296}; 286};
297 287
288/*
289 * Shifts and masks for the link SI tuning values stuffed into the ASIC scratch
290 * registers for integrated platforms
291 */
292#define PORT0_PORT_TYPE_SHIFT 0
293#define PORT0_LOCAL_ATTEN_SHIFT 4
294#define PORT0_REMOTE_ATTEN_SHIFT 10
295#define PORT0_DEFAULT_ATTEN_SHIFT 32
296
297#define PORT1_PORT_TYPE_SHIFT 16
298#define PORT1_LOCAL_ATTEN_SHIFT 20
299#define PORT1_REMOTE_ATTEN_SHIFT 26
300#define PORT1_DEFAULT_ATTEN_SHIFT 40
301
302#define PORT0_PORT_TYPE_MASK 0xFUL
303#define PORT0_LOCAL_ATTEN_MASK 0x3FUL
304#define PORT0_REMOTE_ATTEN_MASK 0x3FUL
305#define PORT0_DEFAULT_ATTEN_MASK 0xFFUL
306
307#define PORT1_PORT_TYPE_MASK 0xFUL
308#define PORT1_LOCAL_ATTEN_MASK 0x3FUL
309#define PORT1_REMOTE_ATTEN_MASK 0x3FUL
310#define PORT1_DEFAULT_ATTEN_MASK 0xFFUL
311
312#define PORT0_PORT_TYPE_SMASK (PORT0_PORT_TYPE_MASK << \
313 PORT0_PORT_TYPE_SHIFT)
314#define PORT0_LOCAL_ATTEN_SMASK (PORT0_LOCAL_ATTEN_MASK << \
315 PORT0_LOCAL_ATTEN_SHIFT)
316#define PORT0_REMOTE_ATTEN_SMASK (PORT0_REMOTE_ATTEN_MASK << \
317 PORT0_REMOTE_ATTEN_SHIFT)
318#define PORT0_DEFAULT_ATTEN_SMASK (PORT0_DEFAULT_ATTEN_MASK << \
319 PORT0_DEFAULT_ATTEN_SHIFT)
320
321#define PORT1_PORT_TYPE_SMASK (PORT1_PORT_TYPE_MASK << \
322 PORT1_PORT_TYPE_SHIFT)
323#define PORT1_LOCAL_ATTEN_SMASK (PORT1_LOCAL_ATTEN_MASK << \
324 PORT1_LOCAL_ATTEN_SHIFT)
325#define PORT1_REMOTE_ATTEN_SMASK (PORT1_REMOTE_ATTEN_MASK << \
326 PORT1_REMOTE_ATTEN_SHIFT)
327#define PORT1_DEFAULT_ATTEN_SMASK (PORT1_DEFAULT_ATTEN_MASK << \
328 PORT1_DEFAULT_ATTEN_SHIFT)
329
330#define QSFP_MAX_POWER_SHIFT 0
331#define TX_NO_EQ_SHIFT 4
332#define TX_EQ_SHIFT 25
333#define RX_SHIFT 46
334
335#define QSFP_MAX_POWER_MASK 0xFUL
336#define TX_NO_EQ_MASK 0x1FFFFFUL
337#define TX_EQ_MASK 0x1FFFFFUL
338#define RX_MASK 0xFFFFUL
339
340#define QSFP_MAX_POWER_SMASK (QSFP_MAX_POWER_MASK << \
341 QSFP_MAX_POWER_SHIFT)
342#define TX_NO_EQ_SMASK (TX_NO_EQ_MASK << TX_NO_EQ_SHIFT)
343#define TX_EQ_SMASK (TX_EQ_MASK << TX_EQ_SHIFT)
344#define RX_SMASK (RX_MASK << RX_SHIFT)
345
346#define TX_PRECUR_SHIFT 0
347#define TX_ATTN_SHIFT 4
348#define QSFP_TX_CDR_APPLY_SHIFT 9
349#define QSFP_TX_EQ_APPLY_SHIFT 10
350#define QSFP_TX_CDR_SHIFT 11
351#define QSFP_TX_EQ_SHIFT 12
352#define TX_POSTCUR_SHIFT 16
353
354#define TX_PRECUR_MASK 0xFUL
355#define TX_ATTN_MASK 0x1FUL
356#define QSFP_TX_CDR_APPLY_MASK 0x1UL
357#define QSFP_TX_EQ_APPLY_MASK 0x1UL
358#define QSFP_TX_CDR_MASK 0x1UL
359#define QSFP_TX_EQ_MASK 0xFUL
360#define TX_POSTCUR_MASK 0x1FUL
361
362#define TX_PRECUR_SMASK (TX_PRECUR_MASK << TX_PRECUR_SHIFT)
363#define TX_ATTN_SMASK (TX_ATTN_MASK << TX_ATTN_SHIFT)
364#define QSFP_TX_CDR_APPLY_SMASK (QSFP_TX_CDR_APPLY_MASK << \
365 QSFP_TX_CDR_APPLY_SHIFT)
366#define QSFP_TX_EQ_APPLY_SMASK (QSFP_TX_EQ_APPLY_MASK << \
367 QSFP_TX_EQ_APPLY_SHIFT)
368#define QSFP_TX_CDR_SMASK (QSFP_TX_CDR_MASK << QSFP_TX_CDR_SHIFT)
369#define QSFP_TX_EQ_SMASK (QSFP_TX_EQ_MASK << QSFP_TX_EQ_SHIFT)
370#define TX_POSTCUR_SMASK (TX_POSTCUR_MASK << TX_POSTCUR_SHIFT)
371
372#define QSFP_RX_CDR_APPLY_SHIFT 0
373#define QSFP_RX_EMP_APPLY_SHIFT 1
374#define QSFP_RX_AMP_APPLY_SHIFT 2
375#define QSFP_RX_CDR_SHIFT 3
376#define QSFP_RX_EMP_SHIFT 4
377#define QSFP_RX_AMP_SHIFT 8
378
379#define QSFP_RX_CDR_APPLY_MASK 0x1UL
380#define QSFP_RX_EMP_APPLY_MASK 0x1UL
381#define QSFP_RX_AMP_APPLY_MASK 0x1UL
382#define QSFP_RX_CDR_MASK 0x1UL
383#define QSFP_RX_EMP_MASK 0xFUL
384#define QSFP_RX_AMP_MASK 0x3UL
385
386#define QSFP_RX_CDR_APPLY_SMASK (QSFP_RX_CDR_APPLY_MASK << \
387 QSFP_RX_CDR_APPLY_SHIFT)
388#define QSFP_RX_EMP_APPLY_SMASK (QSFP_RX_EMP_APPLY_MASK << \
389 QSFP_RX_EMP_APPLY_SHIFT)
390#define QSFP_RX_AMP_APPLY_SMASK (QSFP_RX_AMP_APPLY_MASK << \
391 QSFP_RX_AMP_APPLY_SHIFT)
392#define QSFP_RX_CDR_SMASK (QSFP_RX_CDR_MASK << QSFP_RX_CDR_SHIFT)
393#define QSFP_RX_EMP_SMASK (QSFP_RX_EMP_MASK << QSFP_RX_EMP_SHIFT)
394#define QSFP_RX_AMP_SMASK (QSFP_RX_AMP_MASK << QSFP_RX_AMP_SHIFT)
395
396#define BITMAP_VERSION 1
397#define BITMAP_VERSION_SHIFT 44
398#define BITMAP_VERSION_MASK 0xFUL
399#define BITMAP_VERSION_SMASK (BITMAP_VERSION_MASK << \
400 BITMAP_VERSION_SHIFT)
401#define CHECKSUM_SHIFT 48
402#define CHECKSUM_MASK 0xFFFFUL
403#define CHECKSUM_SMASK (CHECKSUM_MASK << CHECKSUM_SHIFT)
404
298/* platform.c */ 405/* platform.c */
299void get_platform_config(struct hfi1_devdata *dd); 406void get_platform_config(struct hfi1_devdata *dd);
300void free_platform_config(struct hfi1_devdata *dd); 407void free_platform_config(struct hfi1_devdata *dd);
diff --git a/drivers/infiniband/hw/hfi1/qp.c b/drivers/infiniband/hw/hfi1/qp.c
index 9fc75e7e8781..d752d6768a49 100644
--- a/drivers/infiniband/hw/hfi1/qp.c
+++ b/drivers/infiniband/hw/hfi1/qp.c
@@ -196,15 +196,18 @@ static void flush_tx_list(struct rvt_qp *qp)
196static void flush_iowait(struct rvt_qp *qp) 196static void flush_iowait(struct rvt_qp *qp)
197{ 197{
198 struct hfi1_qp_priv *priv = qp->priv; 198 struct hfi1_qp_priv *priv = qp->priv;
199 struct hfi1_ibdev *dev = to_idev(qp->ibqp.device);
200 unsigned long flags; 199 unsigned long flags;
200 seqlock_t *lock = priv->s_iowait.lock;
201 201
202 write_seqlock_irqsave(&dev->iowait_lock, flags); 202 if (!lock)
203 return;
204 write_seqlock_irqsave(lock, flags);
203 if (!list_empty(&priv->s_iowait.list)) { 205 if (!list_empty(&priv->s_iowait.list)) {
204 list_del_init(&priv->s_iowait.list); 206 list_del_init(&priv->s_iowait.list);
207 priv->s_iowait.lock = NULL;
205 rvt_put_qp(qp); 208 rvt_put_qp(qp);
206 } 209 }
207 write_sequnlock_irqrestore(&dev->iowait_lock, flags); 210 write_sequnlock_irqrestore(lock, flags);
208} 211}
209 212
210static inline int opa_mtu_enum_to_int(int mtu) 213static inline int opa_mtu_enum_to_int(int mtu)
@@ -543,6 +546,7 @@ static int iowait_sleep(
543 ibp->rvp.n_dmawait++; 546 ibp->rvp.n_dmawait++;
544 qp->s_flags |= RVT_S_WAIT_DMA_DESC; 547 qp->s_flags |= RVT_S_WAIT_DMA_DESC;
545 list_add_tail(&priv->s_iowait.list, &sde->dmawait); 548 list_add_tail(&priv->s_iowait.list, &sde->dmawait);
549 priv->s_iowait.lock = &dev->iowait_lock;
546 trace_hfi1_qpsleep(qp, RVT_S_WAIT_DMA_DESC); 550 trace_hfi1_qpsleep(qp, RVT_S_WAIT_DMA_DESC);
547 rvt_get_qp(qp); 551 rvt_get_qp(qp);
548 } 552 }
@@ -964,6 +968,7 @@ void notify_error_qp(struct rvt_qp *qp)
964 if (!list_empty(&priv->s_iowait.list) && !(qp->s_flags & RVT_S_BUSY)) { 968 if (!list_empty(&priv->s_iowait.list) && !(qp->s_flags & RVT_S_BUSY)) {
965 qp->s_flags &= ~RVT_S_ANY_WAIT_IO; 969 qp->s_flags &= ~RVT_S_ANY_WAIT_IO;
966 list_del_init(&priv->s_iowait.list); 970 list_del_init(&priv->s_iowait.list);
971 priv->s_iowait.lock = NULL;
967 rvt_put_qp(qp); 972 rvt_put_qp(qp);
968 } 973 }
969 write_sequnlock(&dev->iowait_lock); 974 write_sequnlock(&dev->iowait_lock);
diff --git a/drivers/infiniband/hw/hfi1/rc.c b/drivers/infiniband/hw/hfi1/rc.c
index 83198a8a8797..809b26eb6d3c 100644
--- a/drivers/infiniband/hw/hfi1/rc.c
+++ b/drivers/infiniband/hw/hfi1/rc.c
@@ -276,7 +276,7 @@ static int make_rc_ack(struct hfi1_ibdev *dev, struct rvt_qp *qp,
276 rvt_get_mr(ps->s_txreq->mr); 276 rvt_get_mr(ps->s_txreq->mr);
277 qp->s_ack_rdma_sge.sge = e->rdma_sge; 277 qp->s_ack_rdma_sge.sge = e->rdma_sge;
278 qp->s_ack_rdma_sge.num_sge = 1; 278 qp->s_ack_rdma_sge.num_sge = 1;
279 qp->s_cur_sge = &qp->s_ack_rdma_sge; 279 ps->s_txreq->ss = &qp->s_ack_rdma_sge;
280 if (len > pmtu) { 280 if (len > pmtu) {
281 len = pmtu; 281 len = pmtu;
282 qp->s_ack_state = OP(RDMA_READ_RESPONSE_FIRST); 282 qp->s_ack_state = OP(RDMA_READ_RESPONSE_FIRST);
@@ -290,7 +290,7 @@ static int make_rc_ack(struct hfi1_ibdev *dev, struct rvt_qp *qp,
290 bth2 = mask_psn(qp->s_ack_rdma_psn++); 290 bth2 = mask_psn(qp->s_ack_rdma_psn++);
291 } else { 291 } else {
292 /* COMPARE_SWAP or FETCH_ADD */ 292 /* COMPARE_SWAP or FETCH_ADD */
293 qp->s_cur_sge = NULL; 293 ps->s_txreq->ss = NULL;
294 len = 0; 294 len = 0;
295 qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE); 295 qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE);
296 ohdr->u.at.aeth = hfi1_compute_aeth(qp); 296 ohdr->u.at.aeth = hfi1_compute_aeth(qp);
@@ -306,7 +306,7 @@ static int make_rc_ack(struct hfi1_ibdev *dev, struct rvt_qp *qp,
306 qp->s_ack_state = OP(RDMA_READ_RESPONSE_MIDDLE); 306 qp->s_ack_state = OP(RDMA_READ_RESPONSE_MIDDLE);
307 /* FALLTHROUGH */ 307 /* FALLTHROUGH */
308 case OP(RDMA_READ_RESPONSE_MIDDLE): 308 case OP(RDMA_READ_RESPONSE_MIDDLE):
309 qp->s_cur_sge = &qp->s_ack_rdma_sge; 309 ps->s_txreq->ss = &qp->s_ack_rdma_sge;
310 ps->s_txreq->mr = qp->s_ack_rdma_sge.sge.mr; 310 ps->s_txreq->mr = qp->s_ack_rdma_sge.sge.mr;
311 if (ps->s_txreq->mr) 311 if (ps->s_txreq->mr)
312 rvt_get_mr(ps->s_txreq->mr); 312 rvt_get_mr(ps->s_txreq->mr);
@@ -335,7 +335,7 @@ normal:
335 */ 335 */
336 qp->s_ack_state = OP(SEND_ONLY); 336 qp->s_ack_state = OP(SEND_ONLY);
337 qp->s_flags &= ~RVT_S_ACK_PENDING; 337 qp->s_flags &= ~RVT_S_ACK_PENDING;
338 qp->s_cur_sge = NULL; 338 ps->s_txreq->ss = NULL;
339 if (qp->s_nak_state) 339 if (qp->s_nak_state)
340 ohdr->u.aeth = 340 ohdr->u.aeth =
341 cpu_to_be32((qp->r_msn & HFI1_MSN_MASK) | 341 cpu_to_be32((qp->r_msn & HFI1_MSN_MASK) |
@@ -351,7 +351,7 @@ normal:
351 qp->s_rdma_ack_cnt++; 351 qp->s_rdma_ack_cnt++;
352 qp->s_hdrwords = hwords; 352 qp->s_hdrwords = hwords;
353 ps->s_txreq->sde = priv->s_sde; 353 ps->s_txreq->sde = priv->s_sde;
354 qp->s_cur_size = len; 354 ps->s_txreq->s_cur_size = len;
355 hfi1_make_ruc_header(qp, ohdr, bth0, bth2, middle, ps); 355 hfi1_make_ruc_header(qp, ohdr, bth0, bth2, middle, ps);
356 /* pbc */ 356 /* pbc */
357 ps->s_txreq->hdr_dwords = qp->s_hdrwords + 2; 357 ps->s_txreq->hdr_dwords = qp->s_hdrwords + 2;
@@ -801,8 +801,8 @@ int hfi1_make_rc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
801 qp->s_len -= len; 801 qp->s_len -= len;
802 qp->s_hdrwords = hwords; 802 qp->s_hdrwords = hwords;
803 ps->s_txreq->sde = priv->s_sde; 803 ps->s_txreq->sde = priv->s_sde;
804 qp->s_cur_sge = ss; 804 ps->s_txreq->ss = ss;
805 qp->s_cur_size = len; 805 ps->s_txreq->s_cur_size = len;
806 hfi1_make_ruc_header( 806 hfi1_make_ruc_header(
807 qp, 807 qp,
808 ohdr, 808 ohdr,
@@ -1146,8 +1146,6 @@ void hfi1_rc_send_complete(struct rvt_qp *qp, struct ib_header *hdr)
1146{ 1146{
1147 struct ib_other_headers *ohdr; 1147 struct ib_other_headers *ohdr;
1148 struct rvt_swqe *wqe; 1148 struct rvt_swqe *wqe;
1149 struct ib_wc wc;
1150 unsigned i;
1151 u32 opcode; 1149 u32 opcode;
1152 u32 psn; 1150 u32 psn;
1153 1151
@@ -1195,22 +1193,8 @@ void hfi1_rc_send_complete(struct rvt_qp *qp, struct ib_header *hdr)
1195 qp->s_last = s_last; 1193 qp->s_last = s_last;
1196 /* see post_send() */ 1194 /* see post_send() */
1197 barrier(); 1195 barrier();
1198 for (i = 0; i < wqe->wr.num_sge; i++) { 1196 rvt_put_swqe(wqe);
1199 struct rvt_sge *sge = &wqe->sg_list[i]; 1197 rvt_qp_swqe_complete(qp, wqe, IB_WC_SUCCESS);
1200
1201 rvt_put_mr(sge->mr);
1202 }
1203 /* Post a send completion queue entry if requested. */
1204 if (!(qp->s_flags & RVT_S_SIGNAL_REQ_WR) ||
1205 (wqe->wr.send_flags & IB_SEND_SIGNALED)) {
1206 memset(&wc, 0, sizeof(wc));
1207 wc.wr_id = wqe->wr.wr_id;
1208 wc.status = IB_WC_SUCCESS;
1209 wc.opcode = ib_hfi1_wc_opcode[wqe->wr.opcode];
1210 wc.byte_len = wqe->length;
1211 wc.qp = &qp->ibqp;
1212 rvt_cq_enter(ibcq_to_rvtcq(qp->ibqp.send_cq), &wc, 0);
1213 }
1214 } 1198 }
1215 /* 1199 /*
1216 * If we were waiting for sends to complete before re-sending, 1200 * If we were waiting for sends to complete before re-sending,
@@ -1240,9 +1224,6 @@ static struct rvt_swqe *do_rc_completion(struct rvt_qp *qp,
1240 struct rvt_swqe *wqe, 1224 struct rvt_swqe *wqe,
1241 struct hfi1_ibport *ibp) 1225 struct hfi1_ibport *ibp)
1242{ 1226{
1243 struct ib_wc wc;
1244 unsigned i;
1245
1246 lockdep_assert_held(&qp->s_lock); 1227 lockdep_assert_held(&qp->s_lock);
1247 /* 1228 /*
1248 * Don't decrement refcount and don't generate a 1229 * Don't decrement refcount and don't generate a
@@ -1253,28 +1234,14 @@ static struct rvt_swqe *do_rc_completion(struct rvt_qp *qp,
1253 cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) > 0) { 1234 cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) > 0) {
1254 u32 s_last; 1235 u32 s_last;
1255 1236
1256 for (i = 0; i < wqe->wr.num_sge; i++) { 1237 rvt_put_swqe(wqe);
1257 struct rvt_sge *sge = &wqe->sg_list[i];
1258
1259 rvt_put_mr(sge->mr);
1260 }
1261 s_last = qp->s_last; 1238 s_last = qp->s_last;
1262 if (++s_last >= qp->s_size) 1239 if (++s_last >= qp->s_size)
1263 s_last = 0; 1240 s_last = 0;
1264 qp->s_last = s_last; 1241 qp->s_last = s_last;
1265 /* see post_send() */ 1242 /* see post_send() */
1266 barrier(); 1243 barrier();
1267 /* Post a send completion queue entry if requested. */ 1244 rvt_qp_swqe_complete(qp, wqe, IB_WC_SUCCESS);
1268 if (!(qp->s_flags & RVT_S_SIGNAL_REQ_WR) ||
1269 (wqe->wr.send_flags & IB_SEND_SIGNALED)) {
1270 memset(&wc, 0, sizeof(wc));
1271 wc.wr_id = wqe->wr.wr_id;
1272 wc.status = IB_WC_SUCCESS;
1273 wc.opcode = ib_hfi1_wc_opcode[wqe->wr.opcode];
1274 wc.byte_len = wqe->length;
1275 wc.qp = &qp->ibqp;
1276 rvt_cq_enter(ibcq_to_rvtcq(qp->ibqp.send_cq), &wc, 0);
1277 }
1278 } else { 1245 } else {
1279 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp); 1246 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1280 1247
@@ -2295,7 +2262,7 @@ send_last:
2295 hfi1_copy_sge(&qp->r_sge, data, tlen, 1, copy_last); 2262 hfi1_copy_sge(&qp->r_sge, data, tlen, 1, copy_last);
2296 rvt_put_ss(&qp->r_sge); 2263 rvt_put_ss(&qp->r_sge);
2297 qp->r_msn++; 2264 qp->r_msn++;
2298 if (!test_and_clear_bit(RVT_R_WRID_VALID, &qp->r_aflags)) 2265 if (!__test_and_clear_bit(RVT_R_WRID_VALID, &qp->r_aflags))
2299 break; 2266 break;
2300 wc.wr_id = qp->r_wr_id; 2267 wc.wr_id = qp->r_wr_id;
2301 wc.status = IB_WC_SUCCESS; 2268 wc.status = IB_WC_SUCCESS;
@@ -2410,8 +2377,7 @@ send_last:
2410 * Update the next expected PSN. We add 1 later 2377 * Update the next expected PSN. We add 1 later
2411 * below, so only add the remainder here. 2378 * below, so only add the remainder here.
2412 */ 2379 */
2413 if (len > pmtu) 2380 qp->r_psn += rvt_div_mtu(qp, len - 1);
2414 qp->r_psn += (len - 1) / pmtu;
2415 } else { 2381 } else {
2416 e->rdma_sge.mr = NULL; 2382 e->rdma_sge.mr = NULL;
2417 e->rdma_sge.vaddr = NULL; 2383 e->rdma_sge.vaddr = NULL;
diff --git a/drivers/infiniband/hw/hfi1/ruc.c b/drivers/infiniband/hw/hfi1/ruc.c
index a1576aea4756..717ed4b159d3 100644
--- a/drivers/infiniband/hw/hfi1/ruc.c
+++ b/drivers/infiniband/hw/hfi1/ruc.c
@@ -239,16 +239,6 @@ bail:
239 return ret; 239 return ret;
240} 240}
241 241
242static __be64 get_sguid(struct hfi1_ibport *ibp, unsigned index)
243{
244 if (!index) {
245 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
246
247 return cpu_to_be64(ppd->guid);
248 }
249 return ibp->guids[index - 1];
250}
251
252static int gid_ok(union ib_gid *gid, __be64 gid_prefix, __be64 id) 242static int gid_ok(union ib_gid *gid, __be64 gid_prefix, __be64 id)
253{ 243{
254 return (gid->global.interface_id == id && 244 return (gid->global.interface_id == id &&
@@ -699,9 +689,9 @@ u32 hfi1_make_grh(struct hfi1_ibport *ibp, struct ib_grh *hdr,
699 /* The SGID is 32-bit aligned. */ 689 /* The SGID is 32-bit aligned. */
700 hdr->sgid.global.subnet_prefix = ibp->rvp.gid_prefix; 690 hdr->sgid.global.subnet_prefix = ibp->rvp.gid_prefix;
701 hdr->sgid.global.interface_id = 691 hdr->sgid.global.interface_id =
702 grh->sgid_index && grh->sgid_index < ARRAY_SIZE(ibp->guids) ? 692 grh->sgid_index < HFI1_GUIDS_PER_PORT ?
703 ibp->guids[grh->sgid_index - 1] : 693 get_sguid(ibp, grh->sgid_index) :
704 cpu_to_be64(ppd_from_ibp(ibp)->guid); 694 get_sguid(ibp, HFI1_PORT_GUID_INDEX);
705 hdr->dgid = grh->dgid; 695 hdr->dgid = grh->dgid;
706 696
707 /* GRH header size in 32-bit words. */ 697 /* GRH header size in 32-bit words. */
@@ -777,8 +767,8 @@ void hfi1_make_ruc_header(struct rvt_qp *qp, struct ib_other_headers *ohdr,
777 u32 bth1; 767 u32 bth1;
778 768
779 /* Construct the header. */ 769 /* Construct the header. */
780 extra_bytes = -qp->s_cur_size & 3; 770 extra_bytes = -ps->s_txreq->s_cur_size & 3;
781 nwords = (qp->s_cur_size + extra_bytes) >> 2; 771 nwords = (ps->s_txreq->s_cur_size + extra_bytes) >> 2;
782 lrh0 = HFI1_LRH_BTH; 772 lrh0 = HFI1_LRH_BTH;
783 if (unlikely(qp->remote_ah_attr.ah_flags & IB_AH_GRH)) { 773 if (unlikely(qp->remote_ah_attr.ah_flags & IB_AH_GRH)) {
784 qp->s_hdrwords += hfi1_make_grh(ibp, 774 qp->s_hdrwords += hfi1_make_grh(ibp,
@@ -952,7 +942,6 @@ void hfi1_send_complete(struct rvt_qp *qp, struct rvt_swqe *wqe,
952 enum ib_wc_status status) 942 enum ib_wc_status status)
953{ 943{
954 u32 old_last, last; 944 u32 old_last, last;
955 unsigned i;
956 945
957 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_OR_FLUSH_SEND)) 946 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_OR_FLUSH_SEND))
958 return; 947 return;
@@ -964,32 +953,13 @@ void hfi1_send_complete(struct rvt_qp *qp, struct rvt_swqe *wqe,
964 qp->s_last = last; 953 qp->s_last = last;
965 /* See post_send() */ 954 /* See post_send() */
966 barrier(); 955 barrier();
967 for (i = 0; i < wqe->wr.num_sge; i++) { 956 rvt_put_swqe(wqe);
968 struct rvt_sge *sge = &wqe->sg_list[i];
969
970 rvt_put_mr(sge->mr);
971 }
972 if (qp->ibqp.qp_type == IB_QPT_UD || 957 if (qp->ibqp.qp_type == IB_QPT_UD ||
973 qp->ibqp.qp_type == IB_QPT_SMI || 958 qp->ibqp.qp_type == IB_QPT_SMI ||
974 qp->ibqp.qp_type == IB_QPT_GSI) 959 qp->ibqp.qp_type == IB_QPT_GSI)
975 atomic_dec(&ibah_to_rvtah(wqe->ud_wr.ah)->refcount); 960 atomic_dec(&ibah_to_rvtah(wqe->ud_wr.ah)->refcount);
976 961
977 /* See ch. 11.2.4.1 and 10.7.3.1 */ 962 rvt_qp_swqe_complete(qp, wqe, status);
978 if (!(qp->s_flags & RVT_S_SIGNAL_REQ_WR) ||
979 (wqe->wr.send_flags & IB_SEND_SIGNALED) ||
980 status != IB_WC_SUCCESS) {
981 struct ib_wc wc;
982
983 memset(&wc, 0, sizeof(wc));
984 wc.wr_id = wqe->wr.wr_id;
985 wc.status = status;
986 wc.opcode = ib_hfi1_wc_opcode[wqe->wr.opcode];
987 wc.qp = &qp->ibqp;
988 if (status == IB_WC_SUCCESS)
989 wc.byte_len = wqe->length;
990 rvt_cq_enter(ibcq_to_rvtcq(qp->ibqp.send_cq), &wc,
991 status != IB_WC_SUCCESS);
992 }
993 963
994 if (qp->s_acked == old_last) 964 if (qp->s_acked == old_last)
995 qp->s_acked = last; 965 qp->s_acked = last;
diff --git a/drivers/infiniband/hw/hfi1/sdma.c b/drivers/infiniband/hw/hfi1/sdma.c
index 9cbe52d21077..1d81cac1fa6c 100644
--- a/drivers/infiniband/hw/hfi1/sdma.c
+++ b/drivers/infiniband/hw/hfi1/sdma.c
@@ -375,7 +375,7 @@ static inline void complete_tx(struct sdma_engine *sde,
375 sde->head_sn, tx->sn); 375 sde->head_sn, tx->sn);
376 sde->head_sn++; 376 sde->head_sn++;
377#endif 377#endif
378 sdma_txclean(sde->dd, tx); 378 __sdma_txclean(sde->dd, tx);
379 if (complete) 379 if (complete)
380 (*complete)(tx, res); 380 (*complete)(tx, res);
381 if (wait && iowait_sdma_dec(wait)) 381 if (wait && iowait_sdma_dec(wait))
@@ -1643,7 +1643,7 @@ static inline u8 ahg_mode(struct sdma_txreq *tx)
1643} 1643}
1644 1644
1645/** 1645/**
1646 * sdma_txclean() - clean tx of mappings, descp *kmalloc's 1646 * __sdma_txclean() - clean tx of mappings, descp *kmalloc's
1647 * @dd: hfi1_devdata for unmapping 1647 * @dd: hfi1_devdata for unmapping
1648 * @tx: tx request to clean 1648 * @tx: tx request to clean
1649 * 1649 *
@@ -1653,7 +1653,7 @@ static inline u8 ahg_mode(struct sdma_txreq *tx)
1653 * The code can be called multiple times without issue. 1653 * The code can be called multiple times without issue.
1654 * 1654 *
1655 */ 1655 */
1656void sdma_txclean( 1656void __sdma_txclean(
1657 struct hfi1_devdata *dd, 1657 struct hfi1_devdata *dd,
1658 struct sdma_txreq *tx) 1658 struct sdma_txreq *tx)
1659{ 1659{
@@ -3065,7 +3065,7 @@ static int _extend_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
3065 tx->descp[i] = tx->descs[i]; 3065 tx->descp[i] = tx->descs[i];
3066 return 0; 3066 return 0;
3067enomem: 3067enomem:
3068 sdma_txclean(dd, tx); 3068 __sdma_txclean(dd, tx);
3069 return -ENOMEM; 3069 return -ENOMEM;
3070} 3070}
3071 3071
@@ -3094,14 +3094,14 @@ int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
3094 3094
3095 rval = _extend_sdma_tx_descs(dd, tx); 3095 rval = _extend_sdma_tx_descs(dd, tx);
3096 if (rval) { 3096 if (rval) {
3097 sdma_txclean(dd, tx); 3097 __sdma_txclean(dd, tx);
3098 return rval; 3098 return rval;
3099 } 3099 }
3100 3100
3101 /* If coalesce buffer is allocated, copy data into it */ 3101 /* If coalesce buffer is allocated, copy data into it */
3102 if (tx->coalesce_buf) { 3102 if (tx->coalesce_buf) {
3103 if (type == SDMA_MAP_NONE) { 3103 if (type == SDMA_MAP_NONE) {
3104 sdma_txclean(dd, tx); 3104 __sdma_txclean(dd, tx);
3105 return -EINVAL; 3105 return -EINVAL;
3106 } 3106 }
3107 3107
@@ -3109,7 +3109,7 @@ int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
3109 kvaddr = kmap(page); 3109 kvaddr = kmap(page);
3110 kvaddr += offset; 3110 kvaddr += offset;
3111 } else if (WARN_ON(!kvaddr)) { 3111 } else if (WARN_ON(!kvaddr)) {
3112 sdma_txclean(dd, tx); 3112 __sdma_txclean(dd, tx);
3113 return -EINVAL; 3113 return -EINVAL;
3114 } 3114 }
3115 3115
@@ -3139,7 +3139,7 @@ int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
3139 DMA_TO_DEVICE); 3139 DMA_TO_DEVICE);
3140 3140
3141 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) { 3141 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
3142 sdma_txclean(dd, tx); 3142 __sdma_txclean(dd, tx);
3143 return -ENOSPC; 3143 return -ENOSPC;
3144 } 3144 }
3145 3145
@@ -3181,7 +3181,7 @@ int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx)
3181 if ((unlikely(tx->num_desc == tx->desc_limit))) { 3181 if ((unlikely(tx->num_desc == tx->desc_limit))) {
3182 rval = _extend_sdma_tx_descs(dd, tx); 3182 rval = _extend_sdma_tx_descs(dd, tx);
3183 if (rval) { 3183 if (rval) {
3184 sdma_txclean(dd, tx); 3184 __sdma_txclean(dd, tx);
3185 return rval; 3185 return rval;
3186 } 3186 }
3187 } 3187 }
diff --git a/drivers/infiniband/hw/hfi1/sdma.h b/drivers/infiniband/hw/hfi1/sdma.h
index 56257ea3598f..21f1e2834f37 100644
--- a/drivers/infiniband/hw/hfi1/sdma.h
+++ b/drivers/infiniband/hw/hfi1/sdma.h
@@ -667,7 +667,13 @@ int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
667 int type, void *kvaddr, struct page *page, 667 int type, void *kvaddr, struct page *page,
668 unsigned long offset, u16 len); 668 unsigned long offset, u16 len);
669int _pad_sdma_tx_descs(struct hfi1_devdata *, struct sdma_txreq *); 669int _pad_sdma_tx_descs(struct hfi1_devdata *, struct sdma_txreq *);
670void sdma_txclean(struct hfi1_devdata *, struct sdma_txreq *); 670void __sdma_txclean(struct hfi1_devdata *, struct sdma_txreq *);
671
672static inline void sdma_txclean(struct hfi1_devdata *dd, struct sdma_txreq *tx)
673{
674 if (tx->num_desc)
675 __sdma_txclean(dd, tx);
676}
671 677
672/* helpers used by public routines */ 678/* helpers used by public routines */
673static inline void _sdma_close_tx(struct hfi1_devdata *dd, 679static inline void _sdma_close_tx(struct hfi1_devdata *dd,
@@ -753,7 +759,7 @@ static inline int sdma_txadd_page(
753 DMA_TO_DEVICE); 759 DMA_TO_DEVICE);
754 760
755 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) { 761 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
756 sdma_txclean(dd, tx); 762 __sdma_txclean(dd, tx);
757 return -ENOSPC; 763 return -ENOSPC;
758 } 764 }
759 765
@@ -834,7 +840,7 @@ static inline int sdma_txadd_kvaddr(
834 DMA_TO_DEVICE); 840 DMA_TO_DEVICE);
835 841
836 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) { 842 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
837 sdma_txclean(dd, tx); 843 __sdma_txclean(dd, tx);
838 return -ENOSPC; 844 return -ENOSPC;
839 } 845 }
840 846
diff --git a/drivers/infiniband/hw/hfi1/uc.c b/drivers/infiniband/hw/hfi1/uc.c
index 5e6d1bac4914..b141a78ae38b 100644
--- a/drivers/infiniband/hw/hfi1/uc.c
+++ b/drivers/infiniband/hw/hfi1/uc.c
@@ -258,8 +258,8 @@ int hfi1_make_uc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
258 qp->s_len -= len; 258 qp->s_len -= len;
259 qp->s_hdrwords = hwords; 259 qp->s_hdrwords = hwords;
260 ps->s_txreq->sde = priv->s_sde; 260 ps->s_txreq->sde = priv->s_sde;
261 qp->s_cur_sge = &qp->s_sge; 261 ps->s_txreq->ss = &qp->s_sge;
262 qp->s_cur_size = len; 262 ps->s_txreq->s_cur_size = len;
263 hfi1_make_ruc_header(qp, ohdr, bth0 | (qp->s_state << 24), 263 hfi1_make_ruc_header(qp, ohdr, bth0 | (qp->s_state << 24),
264 mask_psn(qp->s_psn++), middle, ps); 264 mask_psn(qp->s_psn++), middle, ps);
265 /* pbc */ 265 /* pbc */
diff --git a/drivers/infiniband/hw/hfi1/ud.c b/drivers/infiniband/hw/hfi1/ud.c
index 97ae24b6314c..c071955c0272 100644
--- a/drivers/infiniband/hw/hfi1/ud.c
+++ b/drivers/infiniband/hw/hfi1/ud.c
@@ -354,8 +354,8 @@ int hfi1_make_ud_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
354 354
355 /* header size in 32-bit words LRH+BTH+DETH = (8+12+8)/4. */ 355 /* header size in 32-bit words LRH+BTH+DETH = (8+12+8)/4. */
356 qp->s_hdrwords = 7; 356 qp->s_hdrwords = 7;
357 qp->s_cur_size = wqe->length; 357 ps->s_txreq->s_cur_size = wqe->length;
358 qp->s_cur_sge = &qp->s_sge; 358 ps->s_txreq->ss = &qp->s_sge;
359 qp->s_srate = ah_attr->static_rate; 359 qp->s_srate = ah_attr->static_rate;
360 qp->srate_mbps = ib_rate_to_mbps(qp->s_srate); 360 qp->srate_mbps = ib_rate_to_mbps(qp->s_srate);
361 qp->s_wqe = wqe; 361 qp->s_wqe = wqe;
diff --git a/drivers/infiniband/hw/hfi1/user_sdma.c b/drivers/infiniband/hw/hfi1/user_sdma.c
index 77697d690f3e..7d22f8ee98ef 100644
--- a/drivers/infiniband/hw/hfi1/user_sdma.c
+++ b/drivers/infiniband/hw/hfi1/user_sdma.c
@@ -115,6 +115,7 @@ MODULE_PARM_DESC(sdma_comp_size, "Size of User SDMA completion ring. Default: 12
115#define KDETH_HCRC_LOWER_MASK 0xff 115#define KDETH_HCRC_LOWER_MASK 0xff
116 116
117#define AHG_KDETH_INTR_SHIFT 12 117#define AHG_KDETH_INTR_SHIFT 12
118#define AHG_KDETH_SH_SHIFT 13
118 119
119#define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4) 120#define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4)
120#define LRH2PBC(x) ((((x) >> 2) + 1) & 0xfff) 121#define LRH2PBC(x) ((((x) >> 2) + 1) & 0xfff)
@@ -144,8 +145,9 @@ MODULE_PARM_DESC(sdma_comp_size, "Size of User SDMA completion ring. Default: 12
144#define KDETH_OM_LARGE 64 145#define KDETH_OM_LARGE 64
145#define KDETH_OM_MAX_SIZE (1 << ((KDETH_OM_LARGE / KDETH_OM_SMALL) + 1)) 146#define KDETH_OM_MAX_SIZE (1 << ((KDETH_OM_LARGE / KDETH_OM_SMALL) + 1))
146 147
147/* Last packet in the request */ 148/* Tx request flag bits */
148#define TXREQ_FLAGS_REQ_LAST_PKT BIT(0) 149#define TXREQ_FLAGS_REQ_ACK BIT(0) /* Set the ACK bit in the header */
150#define TXREQ_FLAGS_REQ_DISABLE_SH BIT(1) /* Disable header suppression */
149 151
150/* SDMA request flag bits */ 152/* SDMA request flag bits */
151#define SDMA_REQ_FOR_THREAD 1 153#define SDMA_REQ_FOR_THREAD 1
@@ -943,8 +945,13 @@ static int user_sdma_send_pkts(struct user_sdma_request *req, unsigned maxpkts)
943 tx->busycount = 0; 945 tx->busycount = 0;
944 INIT_LIST_HEAD(&tx->list); 946 INIT_LIST_HEAD(&tx->list);
945 947
948 /*
949 * For the last packet set the ACK request
950 * and disable header suppression.
951 */
946 if (req->seqnum == req->info.npkts - 1) 952 if (req->seqnum == req->info.npkts - 1)
947 tx->flags |= TXREQ_FLAGS_REQ_LAST_PKT; 953 tx->flags |= (TXREQ_FLAGS_REQ_ACK |
954 TXREQ_FLAGS_REQ_DISABLE_SH);
948 955
949 /* 956 /*
950 * Calculate the payload size - this is min of the fragment 957 * Calculate the payload size - this is min of the fragment
@@ -963,11 +970,22 @@ static int user_sdma_send_pkts(struct user_sdma_request *req, unsigned maxpkts)
963 } 970 }
964 971
965 datalen = compute_data_length(req, tx); 972 datalen = compute_data_length(req, tx);
973
974 /*
975 * Disable header suppression for the payload <= 8DWS.
976 * If there is an uncorrectable error in the receive
977 * data FIFO when the received payload size is less than
978 * or equal to 8DWS then the RxDmaDataFifoRdUncErr is
979 * not reported.There is set RHF.EccErr if the header
980 * is not suppressed.
981 */
966 if (!datalen) { 982 if (!datalen) {
967 SDMA_DBG(req, 983 SDMA_DBG(req,
968 "Request has data but pkt len is 0"); 984 "Request has data but pkt len is 0");
969 ret = -EFAULT; 985 ret = -EFAULT;
970 goto free_tx; 986 goto free_tx;
987 } else if (datalen <= 32) {
988 tx->flags |= TXREQ_FLAGS_REQ_DISABLE_SH;
971 } 989 }
972 } 990 }
973 991
@@ -990,6 +1008,10 @@ static int user_sdma_send_pkts(struct user_sdma_request *req, unsigned maxpkts)
990 LRH2PBC(lrhlen); 1008 LRH2PBC(lrhlen);
991 tx->hdr.pbc[0] = cpu_to_le16(pbclen); 1009 tx->hdr.pbc[0] = cpu_to_le16(pbclen);
992 } 1010 }
1011 ret = check_header_template(req, &tx->hdr,
1012 lrhlen, datalen);
1013 if (ret)
1014 goto free_tx;
993 ret = sdma_txinit_ahg(&tx->txreq, 1015 ret = sdma_txinit_ahg(&tx->txreq,
994 SDMA_TXREQ_F_AHG_COPY, 1016 SDMA_TXREQ_F_AHG_COPY,
995 sizeof(tx->hdr) + datalen, 1017 sizeof(tx->hdr) + datalen,
@@ -1351,7 +1373,7 @@ static int set_txreq_header(struct user_sdma_request *req,
1351 req->seqnum)); 1373 req->seqnum));
1352 1374
1353 /* Set ACK request on last packet */ 1375 /* Set ACK request on last packet */
1354 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) 1376 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_ACK))
1355 hdr->bth[2] |= cpu_to_be32(1UL << 31); 1377 hdr->bth[2] |= cpu_to_be32(1UL << 31);
1356 1378
1357 /* Set the new offset */ 1379 /* Set the new offset */
@@ -1384,8 +1406,8 @@ static int set_txreq_header(struct user_sdma_request *req,
1384 /* Set KDETH.TID based on value for this TID */ 1406 /* Set KDETH.TID based on value for this TID */
1385 KDETH_SET(hdr->kdeth.ver_tid_offset, TID, 1407 KDETH_SET(hdr->kdeth.ver_tid_offset, TID,
1386 EXP_TID_GET(tidval, IDX)); 1408 EXP_TID_GET(tidval, IDX));
1387 /* Clear KDETH.SH only on the last packet */ 1409 /* Clear KDETH.SH when DISABLE_SH flag is set */
1388 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) 1410 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_DISABLE_SH))
1389 KDETH_SET(hdr->kdeth.ver_tid_offset, SH, 0); 1411 KDETH_SET(hdr->kdeth.ver_tid_offset, SH, 0);
1390 /* 1412 /*
1391 * Set the KDETH.OFFSET and KDETH.OM based on size of 1413 * Set the KDETH.OFFSET and KDETH.OM based on size of
@@ -1429,7 +1451,7 @@ static int set_txreq_header_ahg(struct user_sdma_request *req,
1429 /* BTH.PSN and BTH.A */ 1451 /* BTH.PSN and BTH.A */
1430 val32 = (be32_to_cpu(hdr->bth[2]) + req->seqnum) & 1452 val32 = (be32_to_cpu(hdr->bth[2]) + req->seqnum) &
1431 (HFI1_CAP_IS_KSET(EXTENDED_PSN) ? 0x7fffffff : 0xffffff); 1453 (HFI1_CAP_IS_KSET(EXTENDED_PSN) ? 0x7fffffff : 0xffffff);
1432 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) 1454 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_ACK))
1433 val32 |= 1UL << 31; 1455 val32 |= 1UL << 31;
1434 AHG_HEADER_SET(req->ahg, diff, 6, 0, 16, cpu_to_be16(val32 >> 16)); 1456 AHG_HEADER_SET(req->ahg, diff, 6, 0, 16, cpu_to_be16(val32 >> 16));
1435 AHG_HEADER_SET(req->ahg, diff, 6, 16, 16, cpu_to_be16(val32 & 0xffff)); 1457 AHG_HEADER_SET(req->ahg, diff, 6, 16, 16, cpu_to_be16(val32 & 0xffff));
@@ -1468,19 +1490,23 @@ static int set_txreq_header_ahg(struct user_sdma_request *req,
1468 AHG_HEADER_SET(req->ahg, diff, 7, 0, 16, 1490 AHG_HEADER_SET(req->ahg, diff, 7, 0, 16,
1469 ((!!(req->omfactor - KDETH_OM_SMALL)) << 15 | 1491 ((!!(req->omfactor - KDETH_OM_SMALL)) << 15 |
1470 ((req->tidoffset / req->omfactor) & 0x7fff))); 1492 ((req->tidoffset / req->omfactor) & 0x7fff)));
1471 /* KDETH.TIDCtrl, KDETH.TID */ 1493 /* KDETH.TIDCtrl, KDETH.TID, KDETH.Intr, KDETH.SH */
1472 val = cpu_to_le16(((EXP_TID_GET(tidval, CTRL) & 0x3) << 10) | 1494 val = cpu_to_le16(((EXP_TID_GET(tidval, CTRL) & 0x3) << 10) |
1473 (EXP_TID_GET(tidval, IDX) & 0x3ff)); 1495 (EXP_TID_GET(tidval, IDX) & 0x3ff));
1474 /* Clear KDETH.SH on last packet */ 1496
1475 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_LAST_PKT)) { 1497 if (unlikely(tx->flags & TXREQ_FLAGS_REQ_DISABLE_SH)) {
1476 val |= cpu_to_le16(KDETH_GET(hdr->kdeth.ver_tid_offset, 1498 val |= cpu_to_le16((KDETH_GET(hdr->kdeth.ver_tid_offset,
1477 INTR) << 1499 INTR) <<
1478 AHG_KDETH_INTR_SHIFT); 1500 AHG_KDETH_INTR_SHIFT));
1479 val &= cpu_to_le16(~(1U << 13));
1480 AHG_HEADER_SET(req->ahg, diff, 7, 16, 14, val);
1481 } else { 1501 } else {
1482 AHG_HEADER_SET(req->ahg, diff, 7, 16, 12, val); 1502 val |= KDETH_GET(hdr->kdeth.ver_tid_offset, SH) ?
1503 cpu_to_le16(0x1 << AHG_KDETH_SH_SHIFT) :
1504 cpu_to_le16((KDETH_GET(hdr->kdeth.ver_tid_offset,
1505 INTR) <<
1506 AHG_KDETH_INTR_SHIFT));
1483 } 1507 }
1508
1509 AHG_HEADER_SET(req->ahg, diff, 7, 16, 14, val);
1484 } 1510 }
1485 1511
1486 trace_hfi1_sdma_user_header_ahg(pq->dd, pq->ctxt, pq->subctxt, 1512 trace_hfi1_sdma_user_header_ahg(pq->dd, pq->ctxt, pq->subctxt,
diff --git a/drivers/infiniband/hw/hfi1/verbs.c b/drivers/infiniband/hw/hfi1/verbs.c
index 4b7a16ceb362..95ed4d6da510 100644
--- a/drivers/infiniband/hw/hfi1/verbs.c
+++ b/drivers/infiniband/hw/hfi1/verbs.c
@@ -297,22 +297,6 @@ static inline int wss_exceeds_threshold(void)
297} 297}
298 298
299/* 299/*
300 * Translate ib_wr_opcode into ib_wc_opcode.
301 */
302const enum ib_wc_opcode ib_hfi1_wc_opcode[] = {
303 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
304 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
305 [IB_WR_SEND] = IB_WC_SEND,
306 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
307 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
308 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
309 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD,
310 [IB_WR_SEND_WITH_INV] = IB_WC_SEND,
311 [IB_WR_LOCAL_INV] = IB_WC_LOCAL_INV,
312 [IB_WR_REG_MR] = IB_WC_REG_MR
313};
314
315/*
316 * Length of header by opcode, 0 --> not supported 300 * Length of header by opcode, 0 --> not supported
317 */ 301 */
318const u8 hdr_len_by_opcode[256] = { 302const u8 hdr_len_by_opcode[256] = {
@@ -694,6 +678,7 @@ static void mem_timer(unsigned long data)
694 qp = iowait_to_qp(wait); 678 qp = iowait_to_qp(wait);
695 priv = qp->priv; 679 priv = qp->priv;
696 list_del_init(&priv->s_iowait.list); 680 list_del_init(&priv->s_iowait.list);
681 priv->s_iowait.lock = NULL;
697 /* refcount held until actual wake up */ 682 /* refcount held until actual wake up */
698 if (!list_empty(list)) 683 if (!list_empty(list))
699 mod_timer(&dev->mem_timer, jiffies + 1); 684 mod_timer(&dev->mem_timer, jiffies + 1);
@@ -769,6 +754,7 @@ static int wait_kmem(struct hfi1_ibdev *dev,
769 mod_timer(&dev->mem_timer, jiffies + 1); 754 mod_timer(&dev->mem_timer, jiffies + 1);
770 qp->s_flags |= RVT_S_WAIT_KMEM; 755 qp->s_flags |= RVT_S_WAIT_KMEM;
771 list_add_tail(&priv->s_iowait.list, &dev->memwait); 756 list_add_tail(&priv->s_iowait.list, &dev->memwait);
757 priv->s_iowait.lock = &dev->iowait_lock;
772 trace_hfi1_qpsleep(qp, RVT_S_WAIT_KMEM); 758 trace_hfi1_qpsleep(qp, RVT_S_WAIT_KMEM);
773 rvt_get_qp(qp); 759 rvt_get_qp(qp);
774 } 760 }
@@ -788,10 +774,10 @@ static int wait_kmem(struct hfi1_ibdev *dev,
788 */ 774 */
789static noinline int build_verbs_ulp_payload( 775static noinline int build_verbs_ulp_payload(
790 struct sdma_engine *sde, 776 struct sdma_engine *sde,
791 struct rvt_sge_state *ss,
792 u32 length, 777 u32 length,
793 struct verbs_txreq *tx) 778 struct verbs_txreq *tx)
794{ 779{
780 struct rvt_sge_state *ss = tx->ss;
795 struct rvt_sge *sg_list = ss->sg_list; 781 struct rvt_sge *sg_list = ss->sg_list;
796 struct rvt_sge sge = ss->sge; 782 struct rvt_sge sge = ss->sge;
797 u8 num_sge = ss->num_sge; 783 u8 num_sge = ss->num_sge;
@@ -835,7 +821,6 @@ bail_txadd:
835/* New API */ 821/* New API */
836static int build_verbs_tx_desc( 822static int build_verbs_tx_desc(
837 struct sdma_engine *sde, 823 struct sdma_engine *sde,
838 struct rvt_sge_state *ss,
839 u32 length, 824 u32 length,
840 struct verbs_txreq *tx, 825 struct verbs_txreq *tx,
841 struct hfi1_ahg_info *ahg_info, 826 struct hfi1_ahg_info *ahg_info,
@@ -879,9 +864,9 @@ static int build_verbs_tx_desc(
879 goto bail_txadd; 864 goto bail_txadd;
880 } 865 }
881 866
882 /* add the ulp payload - if any. ss can be NULL for acks */ 867 /* add the ulp payload - if any. tx->ss can be NULL for acks */
883 if (ss) 868 if (tx->ss)
884 ret = build_verbs_ulp_payload(sde, ss, length, tx); 869 ret = build_verbs_ulp_payload(sde, length, tx);
885bail_txadd: 870bail_txadd:
886 return ret; 871 return ret;
887} 872}
@@ -892,8 +877,7 @@ int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
892 struct hfi1_qp_priv *priv = qp->priv; 877 struct hfi1_qp_priv *priv = qp->priv;
893 struct hfi1_ahg_info *ahg_info = priv->s_ahg; 878 struct hfi1_ahg_info *ahg_info = priv->s_ahg;
894 u32 hdrwords = qp->s_hdrwords; 879 u32 hdrwords = qp->s_hdrwords;
895 struct rvt_sge_state *ss = qp->s_cur_sge; 880 u32 len = ps->s_txreq->s_cur_size;
896 u32 len = qp->s_cur_size;
897 u32 plen = hdrwords + ((len + 3) >> 2) + 2; /* includes pbc */ 881 u32 plen = hdrwords + ((len + 3) >> 2) + 2; /* includes pbc */
898 struct hfi1_ibdev *dev = ps->dev; 882 struct hfi1_ibdev *dev = ps->dev;
899 struct hfi1_pportdata *ppd = ps->ppd; 883 struct hfi1_pportdata *ppd = ps->ppd;
@@ -918,7 +902,7 @@ int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
918 plen); 902 plen);
919 } 903 }
920 tx->wqe = qp->s_wqe; 904 tx->wqe = qp->s_wqe;
921 ret = build_verbs_tx_desc(tx->sde, ss, len, tx, ahg_info, pbc); 905 ret = build_verbs_tx_desc(tx->sde, len, tx, ahg_info, pbc);
922 if (unlikely(ret)) 906 if (unlikely(ret))
923 goto bail_build; 907 goto bail_build;
924 } 908 }
@@ -980,6 +964,7 @@ static int pio_wait(struct rvt_qp *qp,
980 qp->s_flags |= flag; 964 qp->s_flags |= flag;
981 was_empty = list_empty(&sc->piowait); 965 was_empty = list_empty(&sc->piowait);
982 list_add_tail(&priv->s_iowait.list, &sc->piowait); 966 list_add_tail(&priv->s_iowait.list, &sc->piowait);
967 priv->s_iowait.lock = &dev->iowait_lock;
983 trace_hfi1_qpsleep(qp, RVT_S_WAIT_PIO); 968 trace_hfi1_qpsleep(qp, RVT_S_WAIT_PIO);
984 rvt_get_qp(qp); 969 rvt_get_qp(qp);
985 /* counting: only call wantpiobuf_intr if first user */ 970 /* counting: only call wantpiobuf_intr if first user */
@@ -1008,8 +993,8 @@ int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
1008{ 993{
1009 struct hfi1_qp_priv *priv = qp->priv; 994 struct hfi1_qp_priv *priv = qp->priv;
1010 u32 hdrwords = qp->s_hdrwords; 995 u32 hdrwords = qp->s_hdrwords;
1011 struct rvt_sge_state *ss = qp->s_cur_sge; 996 struct rvt_sge_state *ss = ps->s_txreq->ss;
1012 u32 len = qp->s_cur_size; 997 u32 len = ps->s_txreq->s_cur_size;
1013 u32 dwords = (len + 3) >> 2; 998 u32 dwords = (len + 3) >> 2;
1014 u32 plen = hdrwords + dwords + 2; /* includes pbc */ 999 u32 plen = hdrwords + dwords + 2; /* includes pbc */
1015 struct hfi1_pportdata *ppd = ps->ppd; 1000 struct hfi1_pportdata *ppd = ps->ppd;
@@ -1237,7 +1222,7 @@ static inline send_routine get_send_routine(struct rvt_qp *qp,
1237 u8 op = get_opcode(h); 1222 u8 op = get_opcode(h);
1238 1223
1239 if (piothreshold && 1224 if (piothreshold &&
1240 qp->s_cur_size <= min(piothreshold, qp->pmtu) && 1225 tx->s_cur_size <= min(piothreshold, qp->pmtu) &&
1241 (BIT(op & OPMASK) & pio_opmask[op >> 5]) && 1226 (BIT(op & OPMASK) & pio_opmask[op >> 5]) &&
1242 iowait_sdma_pending(&priv->s_iowait) == 0 && 1227 iowait_sdma_pending(&priv->s_iowait) == 0 &&
1243 !sdma_txreq_built(&tx->txreq)) 1228 !sdma_txreq_built(&tx->txreq))
@@ -1483,15 +1468,11 @@ static int hfi1_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp,
1483 int guid_index, __be64 *guid) 1468 int guid_index, __be64 *guid)
1484{ 1469{
1485 struct hfi1_ibport *ibp = container_of(rvp, struct hfi1_ibport, rvp); 1470 struct hfi1_ibport *ibp = container_of(rvp, struct hfi1_ibport, rvp);
1486 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1487 1471
1488 if (guid_index == 0) 1472 if (guid_index >= HFI1_GUIDS_PER_PORT)
1489 *guid = cpu_to_be64(ppd->guid);
1490 else if (guid_index < HFI1_GUIDS_PER_PORT)
1491 *guid = ibp->guids[guid_index - 1];
1492 else
1493 return -EINVAL; 1473 return -EINVAL;
1494 1474
1475 *guid = get_sguid(ibp, guid_index);
1495 return 0; 1476 return 0;
1496} 1477}
1497 1478
@@ -1610,6 +1591,154 @@ static void hfi1_get_dev_fw_str(struct ib_device *ibdev, char *str,
1610 dc8051_ver_min(ver)); 1591 dc8051_ver_min(ver));
1611} 1592}
1612 1593
1594static const char * const driver_cntr_names[] = {
1595 /* must be element 0*/
1596 "DRIVER_KernIntr",
1597 "DRIVER_ErrorIntr",
1598 "DRIVER_Tx_Errs",
1599 "DRIVER_Rcv_Errs",
1600 "DRIVER_HW_Errs",
1601 "DRIVER_NoPIOBufs",
1602 "DRIVER_CtxtsOpen",
1603 "DRIVER_RcvLen_Errs",
1604 "DRIVER_EgrBufFull",
1605 "DRIVER_EgrHdrFull"
1606};
1607
1608static const char **dev_cntr_names;
1609static const char **port_cntr_names;
1610static int num_driver_cntrs = ARRAY_SIZE(driver_cntr_names);
1611static int num_dev_cntrs;
1612static int num_port_cntrs;
1613static int cntr_names_initialized;
1614
1615/*
1616 * Convert a list of names separated by '\n' into an array of NULL terminated
1617 * strings. Optionally some entries can be reserved in the array to hold extra
1618 * external strings.
1619 */
1620static int init_cntr_names(const char *names_in,
1621 const int names_len,
1622 int num_extra_names,
1623 int *num_cntrs,
1624 const char ***cntr_names)
1625{
1626 char *names_out, *p, **q;
1627 int i, n;
1628
1629 n = 0;
1630 for (i = 0; i < names_len; i++)
1631 if (names_in[i] == '\n')
1632 n++;
1633
1634 names_out = kmalloc((n + num_extra_names) * sizeof(char *) + names_len,
1635 GFP_KERNEL);
1636 if (!names_out) {
1637 *num_cntrs = 0;
1638 *cntr_names = NULL;
1639 return -ENOMEM;
1640 }
1641
1642 p = names_out + (n + num_extra_names) * sizeof(char *);
1643 memcpy(p, names_in, names_len);
1644
1645 q = (char **)names_out;
1646 for (i = 0; i < n; i++) {
1647 q[i] = p;
1648 p = strchr(p, '\n');
1649 *p++ = '\0';
1650 }
1651
1652 *num_cntrs = n;
1653 *cntr_names = (const char **)names_out;
1654 return 0;
1655}
1656
1657static struct rdma_hw_stats *alloc_hw_stats(struct ib_device *ibdev,
1658 u8 port_num)
1659{
1660 int i, err;
1661
1662 if (!cntr_names_initialized) {
1663 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1664
1665 err = init_cntr_names(dd->cntrnames,
1666 dd->cntrnameslen,
1667 num_driver_cntrs,
1668 &num_dev_cntrs,
1669 &dev_cntr_names);
1670 if (err)
1671 return NULL;
1672
1673 for (i = 0; i < num_driver_cntrs; i++)
1674 dev_cntr_names[num_dev_cntrs + i] =
1675 driver_cntr_names[i];
1676
1677 err = init_cntr_names(dd->portcntrnames,
1678 dd->portcntrnameslen,
1679 0,
1680 &num_port_cntrs,
1681 &port_cntr_names);
1682 if (err) {
1683 kfree(dev_cntr_names);
1684 dev_cntr_names = NULL;
1685 return NULL;
1686 }
1687 cntr_names_initialized = 1;
1688 }
1689
1690 if (!port_num)
1691 return rdma_alloc_hw_stats_struct(
1692 dev_cntr_names,
1693 num_dev_cntrs + num_driver_cntrs,
1694 RDMA_HW_STATS_DEFAULT_LIFESPAN);
1695 else
1696 return rdma_alloc_hw_stats_struct(
1697 port_cntr_names,
1698 num_port_cntrs,
1699 RDMA_HW_STATS_DEFAULT_LIFESPAN);
1700}
1701
1702static u64 hfi1_sps_ints(void)
1703{
1704 unsigned long flags;
1705 struct hfi1_devdata *dd;
1706 u64 sps_ints = 0;
1707
1708 spin_lock_irqsave(&hfi1_devs_lock, flags);
1709 list_for_each_entry(dd, &hfi1_dev_list, list) {
1710 sps_ints += get_all_cpu_total(dd->int_counter);
1711 }
1712 spin_unlock_irqrestore(&hfi1_devs_lock, flags);
1713 return sps_ints;
1714}
1715
1716static int get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats,
1717 u8 port, int index)
1718{
1719 u64 *values;
1720 int count;
1721
1722 if (!port) {
1723 u64 *stats = (u64 *)&hfi1_stats;
1724 int i;
1725
1726 hfi1_read_cntrs(dd_from_ibdev(ibdev), NULL, &values);
1727 values[num_dev_cntrs] = hfi1_sps_ints();
1728 for (i = 1; i < num_driver_cntrs; i++)
1729 values[num_dev_cntrs + i] = stats[i];
1730 count = num_dev_cntrs + num_driver_cntrs;
1731 } else {
1732 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1733
1734 hfi1_read_portcntrs(ppd_from_ibp(ibp), NULL, &values);
1735 count = num_port_cntrs;
1736 }
1737
1738 memcpy(stats->value, values, count * sizeof(u64));
1739 return count;
1740}
1741
1613/** 1742/**
1614 * hfi1_register_ib_device - register our device with the infiniband core 1743 * hfi1_register_ib_device - register our device with the infiniband core
1615 * @dd: the device data structure 1744 * @dd: the device data structure
@@ -1620,6 +1749,7 @@ int hfi1_register_ib_device(struct hfi1_devdata *dd)
1620 struct hfi1_ibdev *dev = &dd->verbs_dev; 1749 struct hfi1_ibdev *dev = &dd->verbs_dev;
1621 struct ib_device *ibdev = &dev->rdi.ibdev; 1750 struct ib_device *ibdev = &dev->rdi.ibdev;
1622 struct hfi1_pportdata *ppd = dd->pport; 1751 struct hfi1_pportdata *ppd = dd->pport;
1752 struct hfi1_ibport *ibp = &ppd->ibport_data;
1623 unsigned i; 1753 unsigned i;
1624 int ret; 1754 int ret;
1625 size_t lcpysz = IB_DEVICE_NAME_MAX; 1755 size_t lcpysz = IB_DEVICE_NAME_MAX;
@@ -1632,6 +1762,7 @@ int hfi1_register_ib_device(struct hfi1_devdata *dd)
1632 setup_timer(&dev->mem_timer, mem_timer, (unsigned long)dev); 1762 setup_timer(&dev->mem_timer, mem_timer, (unsigned long)dev);
1633 1763
1634 seqlock_init(&dev->iowait_lock); 1764 seqlock_init(&dev->iowait_lock);
1765 seqlock_init(&dev->txwait_lock);
1635 INIT_LIST_HEAD(&dev->txwait); 1766 INIT_LIST_HEAD(&dev->txwait);
1636 INIT_LIST_HEAD(&dev->memwait); 1767 INIT_LIST_HEAD(&dev->memwait);
1637 1768
@@ -1639,20 +1770,24 @@ int hfi1_register_ib_device(struct hfi1_devdata *dd)
1639 if (ret) 1770 if (ret)
1640 goto err_verbs_txreq; 1771 goto err_verbs_txreq;
1641 1772
1773 /* Use first-port GUID as node guid */
1774 ibdev->node_guid = get_sguid(ibp, HFI1_PORT_GUID_INDEX);
1775
1642 /* 1776 /*
1643 * The system image GUID is supposed to be the same for all 1777 * The system image GUID is supposed to be the same for all
1644 * HFIs in a single system but since there can be other 1778 * HFIs in a single system but since there can be other
1645 * device types in the system, we can't be sure this is unique. 1779 * device types in the system, we can't be sure this is unique.
1646 */ 1780 */
1647 if (!ib_hfi1_sys_image_guid) 1781 if (!ib_hfi1_sys_image_guid)
1648 ib_hfi1_sys_image_guid = cpu_to_be64(ppd->guid); 1782 ib_hfi1_sys_image_guid = ibdev->node_guid;
1649 lcpysz = strlcpy(ibdev->name, class_name(), lcpysz); 1783 lcpysz = strlcpy(ibdev->name, class_name(), lcpysz);
1650 strlcpy(ibdev->name + lcpysz, "_%d", IB_DEVICE_NAME_MAX - lcpysz); 1784 strlcpy(ibdev->name + lcpysz, "_%d", IB_DEVICE_NAME_MAX - lcpysz);
1651 ibdev->owner = THIS_MODULE; 1785 ibdev->owner = THIS_MODULE;
1652 ibdev->node_guid = cpu_to_be64(ppd->guid);
1653 ibdev->phys_port_cnt = dd->num_pports; 1786 ibdev->phys_port_cnt = dd->num_pports;
1654 ibdev->dma_device = &dd->pcidev->dev; 1787 ibdev->dma_device = &dd->pcidev->dev;
1655 ibdev->modify_device = modify_device; 1788 ibdev->modify_device = modify_device;
1789 ibdev->alloc_hw_stats = alloc_hw_stats;
1790 ibdev->get_hw_stats = get_hw_stats;
1656 1791
1657 /* keep process mad in the driver */ 1792 /* keep process mad in the driver */
1658 ibdev->process_mad = hfi1_process_mad; 1793 ibdev->process_mad = hfi1_process_mad;
@@ -1767,6 +1902,10 @@ void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
1767 1902
1768 del_timer_sync(&dev->mem_timer); 1903 del_timer_sync(&dev->mem_timer);
1769 verbs_txreq_exit(dev); 1904 verbs_txreq_exit(dev);
1905
1906 kfree(dev_cntr_names);
1907 kfree(port_cntr_names);
1908 cntr_names_initialized = 0;
1770} 1909}
1771 1910
1772void hfi1_cnp_rcv(struct hfi1_packet *packet) 1911void hfi1_cnp_rcv(struct hfi1_packet *packet)
diff --git a/drivers/infiniband/hw/hfi1/verbs.h b/drivers/infiniband/hw/hfi1/verbs.h
index 1c3815d89eb7..e6b893010e6d 100644
--- a/drivers/infiniband/hw/hfi1/verbs.h
+++ b/drivers/infiniband/hw/hfi1/verbs.h
@@ -73,7 +73,6 @@ struct hfi1_packet;
73#include "iowait.h" 73#include "iowait.h"
74 74
75#define HFI1_MAX_RDMA_ATOMIC 16 75#define HFI1_MAX_RDMA_ATOMIC 16
76#define HFI1_GUIDS_PER_PORT 5
77 76
78/* 77/*
79 * Increment this value if any changes that break userspace ABI 78 * Increment this value if any changes that break userspace ABI
@@ -169,8 +168,6 @@ struct hfi1_ibport {
169 struct rvt_qp __rcu *qp[2]; 168 struct rvt_qp __rcu *qp[2];
170 struct rvt_ibport rvp; 169 struct rvt_ibport rvp;
171 170
172 __be64 guids[HFI1_GUIDS_PER_PORT - 1]; /* writable GUIDs */
173
174 /* the first 16 entries are sl_to_vl for !OPA */ 171 /* the first 16 entries are sl_to_vl for !OPA */
175 u8 sl_to_sc[32]; 172 u8 sl_to_sc[32];
176 u8 sc_to_sl[32]; 173 u8 sc_to_sl[32];
@@ -180,18 +177,19 @@ struct hfi1_ibdev {
180 struct rvt_dev_info rdi; /* Must be first */ 177 struct rvt_dev_info rdi; /* Must be first */
181 178
182 /* QP numbers are shared by all IB ports */ 179 /* QP numbers are shared by all IB ports */
183 /* protect wait lists */ 180 /* protect txwait list */
184 seqlock_t iowait_lock; 181 seqlock_t txwait_lock ____cacheline_aligned_in_smp;
185 struct list_head txwait; /* list for wait verbs_txreq */ 182 struct list_head txwait; /* list for wait verbs_txreq */
186 struct list_head memwait; /* list for wait kernel memory */ 183 struct list_head memwait; /* list for wait kernel memory */
187 struct list_head txreq_free;
188 struct kmem_cache *verbs_txreq_cache; 184 struct kmem_cache *verbs_txreq_cache;
189 struct timer_list mem_timer; 185 u64 n_txwait;
186 u64 n_kmem_wait;
190 187
188 /* protect iowait lists */
189 seqlock_t iowait_lock ____cacheline_aligned_in_smp;
191 u64 n_piowait; 190 u64 n_piowait;
192 u64 n_piodrain; 191 u64 n_piodrain;
193 u64 n_txwait; 192 struct timer_list mem_timer;
194 u64 n_kmem_wait;
195 193
196#ifdef CONFIG_DEBUG_FS 194#ifdef CONFIG_DEBUG_FS
197 /* per HFI debugfs */ 195 /* per HFI debugfs */
diff --git a/drivers/infiniband/hw/hfi1/verbs_txreq.c b/drivers/infiniband/hw/hfi1/verbs_txreq.c
index 094ab829ec42..5d23172c470f 100644
--- a/drivers/infiniband/hw/hfi1/verbs_txreq.c
+++ b/drivers/infiniband/hw/hfi1/verbs_txreq.c
@@ -72,22 +72,22 @@ void hfi1_put_txreq(struct verbs_txreq *tx)
72 kmem_cache_free(dev->verbs_txreq_cache, tx); 72 kmem_cache_free(dev->verbs_txreq_cache, tx);
73 73
74 do { 74 do {
75 seq = read_seqbegin(&dev->iowait_lock); 75 seq = read_seqbegin(&dev->txwait_lock);
76 if (!list_empty(&dev->txwait)) { 76 if (!list_empty(&dev->txwait)) {
77 struct iowait *wait; 77 struct iowait *wait;
78 78
79 write_seqlock_irqsave(&dev->iowait_lock, flags); 79 write_seqlock_irqsave(&dev->txwait_lock, flags);
80 wait = list_first_entry(&dev->txwait, struct iowait, 80 wait = list_first_entry(&dev->txwait, struct iowait,
81 list); 81 list);
82 qp = iowait_to_qp(wait); 82 qp = iowait_to_qp(wait);
83 priv = qp->priv; 83 priv = qp->priv;
84 list_del_init(&priv->s_iowait.list); 84 list_del_init(&priv->s_iowait.list);
85 /* refcount held until actual wake up */ 85 /* refcount held until actual wake up */
86 write_sequnlock_irqrestore(&dev->iowait_lock, flags); 86 write_sequnlock_irqrestore(&dev->txwait_lock, flags);
87 hfi1_qp_wakeup(qp, RVT_S_WAIT_TX); 87 hfi1_qp_wakeup(qp, RVT_S_WAIT_TX);
88 break; 88 break;
89 } 89 }
90 } while (read_seqretry(&dev->iowait_lock, seq)); 90 } while (read_seqretry(&dev->txwait_lock, seq));
91} 91}
92 92
93struct verbs_txreq *__get_txreq(struct hfi1_ibdev *dev, 93struct verbs_txreq *__get_txreq(struct hfi1_ibdev *dev,
@@ -96,7 +96,7 @@ struct verbs_txreq *__get_txreq(struct hfi1_ibdev *dev,
96{ 96{
97 struct verbs_txreq *tx = ERR_PTR(-EBUSY); 97 struct verbs_txreq *tx = ERR_PTR(-EBUSY);
98 98
99 write_seqlock(&dev->iowait_lock); 99 write_seqlock(&dev->txwait_lock);
100 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) { 100 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
101 struct hfi1_qp_priv *priv; 101 struct hfi1_qp_priv *priv;
102 102
@@ -108,13 +108,14 @@ struct verbs_txreq *__get_txreq(struct hfi1_ibdev *dev,
108 dev->n_txwait++; 108 dev->n_txwait++;
109 qp->s_flags |= RVT_S_WAIT_TX; 109 qp->s_flags |= RVT_S_WAIT_TX;
110 list_add_tail(&priv->s_iowait.list, &dev->txwait); 110 list_add_tail(&priv->s_iowait.list, &dev->txwait);
111 priv->s_iowait.lock = &dev->txwait_lock;
111 trace_hfi1_qpsleep(qp, RVT_S_WAIT_TX); 112 trace_hfi1_qpsleep(qp, RVT_S_WAIT_TX);
112 rvt_get_qp(qp); 113 rvt_get_qp(qp);
113 } 114 }
114 qp->s_flags &= ~RVT_S_BUSY; 115 qp->s_flags &= ~RVT_S_BUSY;
115 } 116 }
116out: 117out:
117 write_sequnlock(&dev->iowait_lock); 118 write_sequnlock(&dev->txwait_lock);
118 return tx; 119 return tx;
119} 120}
120 121
diff --git a/drivers/infiniband/hw/hfi1/verbs_txreq.h b/drivers/infiniband/hw/hfi1/verbs_txreq.h
index 5660897593ba..76216f2ef35a 100644
--- a/drivers/infiniband/hw/hfi1/verbs_txreq.h
+++ b/drivers/infiniband/hw/hfi1/verbs_txreq.h
@@ -65,6 +65,7 @@ struct verbs_txreq {
65 struct sdma_engine *sde; 65 struct sdma_engine *sde;
66 struct send_context *psc; 66 struct send_context *psc;
67 u16 hdr_dwords; 67 u16 hdr_dwords;
68 u16 s_cur_size;
68}; 69};
69 70
70struct hfi1_ibdev; 71struct hfi1_ibdev;
diff --git a/drivers/infiniband/hw/hns/hns_roce_ah.c b/drivers/infiniband/hw/hns/hns_roce_ah.c
index 24f79ee39fdf..0ac294db3b29 100644
--- a/drivers/infiniband/hw/hns/hns_roce_ah.c
+++ b/drivers/infiniband/hw/hns/hns_roce_ah.c
@@ -39,7 +39,8 @@
39#define HNS_ROCE_VLAN_SL_BIT_MASK 7 39#define HNS_ROCE_VLAN_SL_BIT_MASK 7
40#define HNS_ROCE_VLAN_SL_SHIFT 13 40#define HNS_ROCE_VLAN_SL_SHIFT 13
41 41
42struct ib_ah *hns_roce_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *ah_attr) 42struct ib_ah *hns_roce_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *ah_attr,
43 struct ib_udata *udata)
43{ 44{
44 struct hns_roce_dev *hr_dev = to_hr_dev(ibpd->device); 45 struct hns_roce_dev *hr_dev = to_hr_dev(ibpd->device);
45 struct device *dev = &hr_dev->pdev->dev; 46 struct device *dev = &hr_dev->pdev->dev;
diff --git a/drivers/infiniband/hw/hns/hns_roce_alloc.c b/drivers/infiniband/hw/hns/hns_roce_alloc.c
index 863a17a2de40..605962f2828c 100644
--- a/drivers/infiniband/hw/hns/hns_roce_alloc.c
+++ b/drivers/infiniband/hw/hns/hns_roce_alloc.c
@@ -61,9 +61,10 @@ int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj)
61 return ret; 61 return ret;
62} 62}
63 63
64void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj) 64void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
65 int rr)
65{ 66{
66 hns_roce_bitmap_free_range(bitmap, obj, 1); 67 hns_roce_bitmap_free_range(bitmap, obj, 1, rr);
67} 68}
68 69
69int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, 70int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
@@ -106,7 +107,8 @@ int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
106} 107}
107 108
108void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, 109void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
109 unsigned long obj, int cnt) 110 unsigned long obj, int cnt,
111 int rr)
110{ 112{
111 int i; 113 int i;
112 114
@@ -116,7 +118,8 @@ void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
116 for (i = 0; i < cnt; i++) 118 for (i = 0; i < cnt; i++)
117 clear_bit(obj + i, bitmap->table); 119 clear_bit(obj + i, bitmap->table);
118 120
119 bitmap->last = min(bitmap->last, obj); 121 if (!rr)
122 bitmap->last = min(bitmap->last, obj);
120 bitmap->top = (bitmap->top + bitmap->max + bitmap->reserved_top) 123 bitmap->top = (bitmap->top + bitmap->max + bitmap->reserved_top)
121 & bitmap->mask; 124 & bitmap->mask;
122 spin_unlock(&bitmap->lock); 125 spin_unlock(&bitmap->lock);
diff --git a/drivers/infiniband/hw/hns/hns_roce_cmd.c b/drivers/infiniband/hw/hns/hns_roce_cmd.c
index 2a0b6c05da5f..8c1f7a6f84d2 100644
--- a/drivers/infiniband/hw/hns/hns_roce_cmd.c
+++ b/drivers/infiniband/hw/hns/hns_roce_cmd.c
@@ -216,10 +216,10 @@ static int __hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,
216 goto out; 216 goto out;
217 217
218 /* 218 /*
219 * It is timeout when wait_for_completion_timeout return 0 219 * It is timeout when wait_for_completion_timeout return 0
220 * The return value is the time limit set in advance 220 * The return value is the time limit set in advance
221 * how many seconds showing 221 * how many seconds showing
222 */ 222 */
223 if (!wait_for_completion_timeout(&context->done, 223 if (!wait_for_completion_timeout(&context->done,
224 msecs_to_jiffies(timeout))) { 224 msecs_to_jiffies(timeout))) {
225 dev_err(dev, "[cmd]wait_for_completion_timeout timeout\n"); 225 dev_err(dev, "[cmd]wait_for_completion_timeout timeout\n");
diff --git a/drivers/infiniband/hw/hns/hns_roce_cmd.h b/drivers/infiniband/hw/hns/hns_roce_cmd.h
index e3997d312c55..f5a9ee2fc53d 100644
--- a/drivers/infiniband/hw/hns/hns_roce_cmd.h
+++ b/drivers/infiniband/hw/hns/hns_roce_cmd.h
@@ -34,6 +34,7 @@
34#define _HNS_ROCE_CMD_H 34#define _HNS_ROCE_CMD_H
35 35
36#define HNS_ROCE_MAILBOX_SIZE 4096 36#define HNS_ROCE_MAILBOX_SIZE 4096
37#define HNS_ROCE_CMD_TIMEOUT_MSECS 10000
37 38
38enum { 39enum {
39 /* TPT commands */ 40 /* TPT commands */
@@ -57,17 +58,6 @@ enum {
57 HNS_ROCE_CMD_QUERY_QP = 0x22, 58 HNS_ROCE_CMD_QUERY_QP = 0x22,
58}; 59};
59 60
60enum {
61 HNS_ROCE_CMD_TIME_CLASS_A = 10000,
62 HNS_ROCE_CMD_TIME_CLASS_B = 10000,
63 HNS_ROCE_CMD_TIME_CLASS_C = 10000,
64};
65
66struct hns_roce_cmd_mailbox {
67 void *buf;
68 dma_addr_t dma;
69};
70
71int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param, 61int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
72 unsigned long in_modifier, u8 op_modifier, u16 op, 62 unsigned long in_modifier, u8 op_modifier, u16 op,
73 unsigned long timeout); 63 unsigned long timeout);
diff --git a/drivers/infiniband/hw/hns/hns_roce_common.h b/drivers/infiniband/hw/hns/hns_roce_common.h
index 297016103aa7..4af403e1348c 100644
--- a/drivers/infiniband/hw/hns/hns_roce_common.h
+++ b/drivers/infiniband/hw/hns/hns_roce_common.h
@@ -57,6 +57,32 @@
57#define roce_set_bit(origin, shift, val) \ 57#define roce_set_bit(origin, shift, val) \
58 roce_set_field((origin), (1ul << (shift)), (shift), (val)) 58 roce_set_field((origin), (1ul << (shift)), (shift), (val))
59 59
60/*
61 * roce_hw_index_cmp_lt - Compare two hardware index values in hisilicon
62 * SOC, check if a is less than b.
63 * @a: hardware index value
64 * @b: hardware index value
65 * @bits: the number of bits of a and b, range: 0~31.
66 *
67 * Hardware index increases continuously till max value, and then restart
68 * from zero, again and again. Because the bits of reg field is often
69 * limited, the reg field can only hold the low bits of the hardware index
70 * in hisilicon SOC.
71 * In some scenes we need to compare two values(a,b) getted from two reg
72 * fields in this driver, for example:
73 * If a equals 0xfffe, b equals 0x1 and bits equals 16, we think b has
74 * incresed from 0xffff to 0x1 and a is less than b.
75 * If a equals 0xfffe, b equals 0x0xf001 and bits equals 16, we think a
76 * is bigger than b.
77 *
78 * Return true on a less than b, otherwise false.
79 */
80#define roce_hw_index_mask(bits) ((1ul << (bits)) - 1)
81#define roce_hw_index_shift(bits) (32 - (bits))
82#define roce_hw_index_cmp_lt(a, b, bits) \
83 ((int)((((a) - (b)) & roce_hw_index_mask(bits)) << \
84 roce_hw_index_shift(bits)) < 0)
85
60#define ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S 3 86#define ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S 3
61#define ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S 4 87#define ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S 4
62 88
@@ -245,16 +271,26 @@
245#define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M \ 271#define ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M \
246 (((1UL << 28) - 1) << ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) 272 (((1UL << 28) - 1) << ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)
247 273
274#define ROCEE_SDB_PTR_CMP_BITS 28
275
248#define ROCEE_SDB_INV_CNT_SDB_INV_CNT_S 0 276#define ROCEE_SDB_INV_CNT_SDB_INV_CNT_S 0
249#define ROCEE_SDB_INV_CNT_SDB_INV_CNT_M \ 277#define ROCEE_SDB_INV_CNT_SDB_INV_CNT_M \
250 (((1UL << 16) - 1) << ROCEE_SDB_INV_CNT_SDB_INV_CNT_S) 278 (((1UL << 16) - 1) << ROCEE_SDB_INV_CNT_SDB_INV_CNT_S)
251 279
280#define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S 0
281#define ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M \
282 (((1UL << 16) - 1) << ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S)
283
284#define ROCEE_SDB_CNT_CMP_BITS 16
285
286#define ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S 20
287
288#define ROCEE_CNT_CLR_CE_CNT_CLR_CE_S 0
289
252/*************ROCEE_REG DEFINITION****************/ 290/*************ROCEE_REG DEFINITION****************/
253#define ROCEE_VENDOR_ID_REG 0x0 291#define ROCEE_VENDOR_ID_REG 0x0
254#define ROCEE_VENDOR_PART_ID_REG 0x4 292#define ROCEE_VENDOR_PART_ID_REG 0x4
255 293
256#define ROCEE_HW_VERSION_REG 0x8
257
258#define ROCEE_SYS_IMAGE_GUID_L_REG 0xC 294#define ROCEE_SYS_IMAGE_GUID_L_REG 0xC
259#define ROCEE_SYS_IMAGE_GUID_H_REG 0x10 295#define ROCEE_SYS_IMAGE_GUID_H_REG 0x10
260 296
@@ -318,7 +354,11 @@
318 354
319#define ROCEE_SDB_ISSUE_PTR_REG 0x758 355#define ROCEE_SDB_ISSUE_PTR_REG 0x758
320#define ROCEE_SDB_SEND_PTR_REG 0x75C 356#define ROCEE_SDB_SEND_PTR_REG 0x75C
357#define ROCEE_CAEP_CQE_WCMD_EMPTY 0x850
358#define ROCEE_SCAEP_WR_CQE_CNT 0x8D0
321#define ROCEE_SDB_INV_CNT_REG 0x9A4 359#define ROCEE_SDB_INV_CNT_REG 0x9A4
360#define ROCEE_SDB_RETRY_CNT_REG 0x9AC
361#define ROCEE_TSP_BP_ST_REG 0x9EC
322#define ROCEE_ECC_UCERR_ALM0_REG 0xB34 362#define ROCEE_ECC_UCERR_ALM0_REG 0xB34
323#define ROCEE_ECC_CERR_ALM0_REG 0xB40 363#define ROCEE_ECC_CERR_ALM0_REG 0xB40
324 364
diff --git a/drivers/infiniband/hw/hns/hns_roce_cq.c b/drivers/infiniband/hw/hns/hns_roce_cq.c
index 097365932b09..589496c8fb9e 100644
--- a/drivers/infiniband/hw/hns/hns_roce_cq.c
+++ b/drivers/infiniband/hw/hns/hns_roce_cq.c
@@ -35,7 +35,7 @@
35#include "hns_roce_device.h" 35#include "hns_roce_device.h"
36#include "hns_roce_cmd.h" 36#include "hns_roce_cmd.h"
37#include "hns_roce_hem.h" 37#include "hns_roce_hem.h"
38#include "hns_roce_user.h" 38#include <rdma/hns-abi.h>
39#include "hns_roce_common.h" 39#include "hns_roce_common.h"
40 40
41static void hns_roce_ib_cq_comp(struct hns_roce_cq *hr_cq) 41static void hns_roce_ib_cq_comp(struct hns_roce_cq *hr_cq)
@@ -77,7 +77,7 @@ static int hns_roce_sw2hw_cq(struct hns_roce_dev *dev,
77 unsigned long cq_num) 77 unsigned long cq_num)
78{ 78{
79 return hns_roce_cmd_mbox(dev, mailbox->dma, 0, cq_num, 0, 79 return hns_roce_cmd_mbox(dev, mailbox->dma, 0, cq_num, 0,
80 HNS_ROCE_CMD_SW2HW_CQ, HNS_ROCE_CMD_TIME_CLASS_A); 80 HNS_ROCE_CMD_SW2HW_CQ, HNS_ROCE_CMD_TIMEOUT_MSECS);
81} 81}
82 82
83static int hns_roce_cq_alloc(struct hns_roce_dev *hr_dev, int nent, 83static int hns_roce_cq_alloc(struct hns_roce_dev *hr_dev, int nent,
@@ -166,7 +166,7 @@ err_put:
166 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn); 166 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
167 167
168err_out: 168err_out:
169 hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn); 169 hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
170 return ret; 170 return ret;
171} 171}
172 172
@@ -176,11 +176,10 @@ static int hns_roce_hw2sw_cq(struct hns_roce_dev *dev,
176{ 176{
177 return hns_roce_cmd_mbox(dev, 0, mailbox ? mailbox->dma : 0, cq_num, 177 return hns_roce_cmd_mbox(dev, 0, mailbox ? mailbox->dma : 0, cq_num,
178 mailbox ? 0 : 1, HNS_ROCE_CMD_HW2SW_CQ, 178 mailbox ? 0 : 1, HNS_ROCE_CMD_HW2SW_CQ,
179 HNS_ROCE_CMD_TIME_CLASS_A); 179 HNS_ROCE_CMD_TIMEOUT_MSECS);
180} 180}
181 181
182static void hns_roce_free_cq(struct hns_roce_dev *hr_dev, 182void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
183 struct hns_roce_cq *hr_cq)
184{ 183{
185 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table; 184 struct hns_roce_cq_table *cq_table = &hr_dev->cq_table;
186 struct device *dev = &hr_dev->pdev->dev; 185 struct device *dev = &hr_dev->pdev->dev;
@@ -204,7 +203,7 @@ static void hns_roce_free_cq(struct hns_roce_dev *hr_dev,
204 spin_unlock_irq(&cq_table->lock); 203 spin_unlock_irq(&cq_table->lock);
205 204
206 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn); 205 hns_roce_table_put(hr_dev, &cq_table->table, hr_cq->cqn);
207 hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn); 206 hns_roce_bitmap_free(&cq_table->bitmap, hr_cq->cqn, BITMAP_NO_RR);
208} 207}
209 208
210static int hns_roce_ib_get_cq_umem(struct hns_roce_dev *hr_dev, 209static int hns_roce_ib_get_cq_umem(struct hns_roce_dev *hr_dev,
@@ -349,6 +348,15 @@ struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
349 goto err_mtt; 348 goto err_mtt;
350 } 349 }
351 350
351 /*
352 * For the QP created by kernel space, tptr value should be initialized
353 * to zero; For the QP created by user space, it will cause synchronous
354 * problems if tptr is set to zero here, so we initialze it in user
355 * space.
356 */
357 if (!context)
358 *hr_cq->tptr_addr = 0;
359
352 /* Get created cq handler and carry out event */ 360 /* Get created cq handler and carry out event */
353 hr_cq->comp = hns_roce_ib_cq_comp; 361 hr_cq->comp = hns_roce_ib_cq_comp;
354 hr_cq->event = hns_roce_ib_cq_event; 362 hr_cq->event = hns_roce_ib_cq_event;
@@ -383,19 +391,25 @@ int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq)
383{ 391{
384 struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device); 392 struct hns_roce_dev *hr_dev = to_hr_dev(ib_cq->device);
385 struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq); 393 struct hns_roce_cq *hr_cq = to_hr_cq(ib_cq);
394 int ret = 0;
386 395
387 hns_roce_free_cq(hr_dev, hr_cq); 396 if (hr_dev->hw->destroy_cq) {
388 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt); 397 ret = hr_dev->hw->destroy_cq(ib_cq);
398 } else {
399 hns_roce_free_cq(hr_dev, hr_cq);
400 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
389 401
390 if (ib_cq->uobject) 402 if (ib_cq->uobject)
391 ib_umem_release(hr_cq->umem); 403 ib_umem_release(hr_cq->umem);
392 else 404 else
393 /* Free the buff of stored cq */ 405 /* Free the buff of stored cq */
394 hns_roce_ib_free_cq_buf(hr_dev, &hr_cq->hr_buf, ib_cq->cqe); 406 hns_roce_ib_free_cq_buf(hr_dev, &hr_cq->hr_buf,
407 ib_cq->cqe);
395 408
396 kfree(hr_cq); 409 kfree(hr_cq);
410 }
397 411
398 return 0; 412 return ret;
399} 413}
400 414
401void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn) 415void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn)
diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
index 341731553a60..1a6cb5d7a0dd 100644
--- a/drivers/infiniband/hw/hns/hns_roce_device.h
+++ b/drivers/infiniband/hw/hns/hns_roce_device.h
@@ -37,6 +37,8 @@
37 37
38#define DRV_NAME "hns_roce" 38#define DRV_NAME "hns_roce"
39 39
40#define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
41
40#define MAC_ADDR_OCTET_NUM 6 42#define MAC_ADDR_OCTET_NUM 6
41#define HNS_ROCE_MAX_MSG_LEN 0x80000000 43#define HNS_ROCE_MAX_MSG_LEN 0x80000000
42 44
@@ -54,6 +56,12 @@
54#define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7 56#define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7
55#define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000 57#define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000
56 58
59#define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20
60#define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \
61 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
62#define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2
63#define HNS_ROCE_MIN_CQE_CNT 16
64
57#define HNS_ROCE_MAX_IRQ_NUM 34 65#define HNS_ROCE_MAX_IRQ_NUM 34
58 66
59#define HNS_ROCE_COMP_VEC_NUM 32 67#define HNS_ROCE_COMP_VEC_NUM 32
@@ -70,6 +78,9 @@
70#define HNS_ROCE_MAX_GID_NUM 16 78#define HNS_ROCE_MAX_GID_NUM 16
71#define HNS_ROCE_GID_SIZE 16 79#define HNS_ROCE_GID_SIZE 16
72 80
81#define BITMAP_NO_RR 0
82#define BITMAP_RR 1
83
73#define MR_TYPE_MR 0x00 84#define MR_TYPE_MR 0x00
74#define MR_TYPE_DMA 0x03 85#define MR_TYPE_DMA 0x03
75 86
@@ -196,9 +207,9 @@ struct hns_roce_bitmap {
196/* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */ 207/* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */
197/* Every bit repesent to a partner free/used status in bitmap */ 208/* Every bit repesent to a partner free/used status in bitmap */
198/* 209/*
199* Initial, bits of other bitmap are all 0 except that a bit of max_order is 1 210 * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1
200* Bit = 1 represent to idle and available; bit = 0: not available 211 * Bit = 1 represent to idle and available; bit = 0: not available
201*/ 212 */
202struct hns_roce_buddy { 213struct hns_roce_buddy {
203 /* Members point to every order level bitmap */ 214 /* Members point to every order level bitmap */
204 unsigned long **bits; 215 unsigned long **bits;
@@ -296,7 +307,7 @@ struct hns_roce_cq {
296 u32 cq_depth; 307 u32 cq_depth;
297 u32 cons_index; 308 u32 cons_index;
298 void __iomem *cq_db_l; 309 void __iomem *cq_db_l;
299 void __iomem *tptr_addr; 310 u16 *tptr_addr;
300 unsigned long cqn; 311 unsigned long cqn;
301 u32 vector; 312 u32 vector;
302 atomic_t refcount; 313 atomic_t refcount;
@@ -360,29 +371,34 @@ struct hns_roce_cmdq {
360 struct mutex hcr_mutex; 371 struct mutex hcr_mutex;
361 struct semaphore poll_sem; 372 struct semaphore poll_sem;
362 /* 373 /*
363 * Event mode: cmd register mutex protection, 374 * Event mode: cmd register mutex protection,
364 * ensure to not exceed max_cmds and user use limit region 375 * ensure to not exceed max_cmds and user use limit region
365 */ 376 */
366 struct semaphore event_sem; 377 struct semaphore event_sem;
367 int max_cmds; 378 int max_cmds;
368 spinlock_t context_lock; 379 spinlock_t context_lock;
369 int free_head; 380 int free_head;
370 struct hns_roce_cmd_context *context; 381 struct hns_roce_cmd_context *context;
371 /* 382 /*
372 * Result of get integer part 383 * Result of get integer part
373 * which max_comds compute according a power of 2 384 * which max_comds compute according a power of 2
374 */ 385 */
375 u16 token_mask; 386 u16 token_mask;
376 /* 387 /*
377 * Process whether use event mode, init default non-zero 388 * Process whether use event mode, init default non-zero
378 * After the event queue of cmd event ready, 389 * After the event queue of cmd event ready,
379 * can switch into event mode 390 * can switch into event mode
380 * close device, switch into poll mode(non event mode) 391 * close device, switch into poll mode(non event mode)
381 */ 392 */
382 u8 use_events; 393 u8 use_events;
383 u8 toggle; 394 u8 toggle;
384}; 395};
385 396
397struct hns_roce_cmd_mailbox {
398 void *buf;
399 dma_addr_t dma;
400};
401
386struct hns_roce_dev; 402struct hns_roce_dev;
387 403
388struct hns_roce_qp { 404struct hns_roce_qp {
@@ -424,8 +440,6 @@ struct hns_roce_ib_iboe {
424 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 440 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
425 struct notifier_block nb; 441 struct notifier_block nb;
426 struct notifier_block nb_inet; 442 struct notifier_block nb_inet;
427 /* 16 GID is shared by 6 port in v1 engine. */
428 union ib_gid gid_table[HNS_ROCE_MAX_GID_NUM];
429 u8 phy_port[HNS_ROCE_MAX_PORTS]; 443 u8 phy_port[HNS_ROCE_MAX_PORTS];
430}; 444};
431 445
@@ -519,6 +533,8 @@ struct hns_roce_hw {
519 struct ib_recv_wr **bad_recv_wr); 533 struct ib_recv_wr **bad_recv_wr);
520 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 534 int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
521 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 535 int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
536 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr);
537 int (*destroy_cq)(struct ib_cq *ibcq);
522 void *priv; 538 void *priv;
523}; 539};
524 540
@@ -553,6 +569,8 @@ struct hns_roce_dev {
553 569
554 int cmd_mod; 570 int cmd_mod;
555 int loop_idc; 571 int loop_idc;
572 dma_addr_t tptr_dma_addr; /*only for hw v1*/
573 u32 tptr_size; /*only for hw v1*/
556 struct hns_roce_hw *hw; 574 struct hns_roce_hw *hw;
557}; 575};
558 576
@@ -657,7 +675,8 @@ void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
657void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 675void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
658 676
659int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj); 677int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
660void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj); 678void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
679 int rr);
661int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask, 680int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
662 u32 reserved_bot, u32 resetrved_top); 681 u32 reserved_bot, u32 resetrved_top);
663void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap); 682void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
@@ -665,9 +684,11 @@ void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
665int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt, 684int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
666 int align, unsigned long *obj); 685 int align, unsigned long *obj);
667void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap, 686void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
668 unsigned long obj, int cnt); 687 unsigned long obj, int cnt,
688 int rr);
669 689
670struct ib_ah *hns_roce_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); 690struct ib_ah *hns_roce_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr,
691 struct ib_udata *udata);
671int hns_roce_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 692int hns_roce_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
672int hns_roce_destroy_ah(struct ib_ah *ah); 693int hns_roce_destroy_ah(struct ib_ah *ah);
673 694
@@ -681,6 +702,10 @@ struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
681 u64 virt_addr, int access_flags, 702 u64 virt_addr, int access_flags,
682 struct ib_udata *udata); 703 struct ib_udata *udata);
683int hns_roce_dereg_mr(struct ib_mr *ibmr); 704int hns_roce_dereg_mr(struct ib_mr *ibmr);
705int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
706 struct hns_roce_cmd_mailbox *mailbox,
707 unsigned long mpt_index);
708unsigned long key_to_hw_index(u32 key);
684 709
685void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size, 710void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size,
686 struct hns_roce_buf *buf); 711 struct hns_roce_buf *buf);
@@ -717,6 +742,7 @@ struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
717 struct ib_udata *udata); 742 struct ib_udata *udata);
718 743
719int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq); 744int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq);
745void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq);
720 746
721void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 747void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
722void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 748void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
diff --git a/drivers/infiniband/hw/hns/hns_roce_eq.c b/drivers/infiniband/hw/hns/hns_roce_eq.c
index 21e21b03cfb5..50f864935a0e 100644
--- a/drivers/infiniband/hw/hns/hns_roce_eq.c
+++ b/drivers/infiniband/hw/hns/hns_roce_eq.c
@@ -371,9 +371,9 @@ static int hns_roce_aeq_ovf_int(struct hns_roce_dev *hr_dev,
371 int i = 0; 371 int i = 0;
372 372
373 /** 373 /**
374 * AEQ overflow ECC mult bit err CEQ overflow alarm 374 * AEQ overflow ECC mult bit err CEQ overflow alarm
375 * must clear interrupt, mask irq, clear irq, cancel mask operation 375 * must clear interrupt, mask irq, clear irq, cancel mask operation
376 */ 376 */
377 aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG); 377 aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
378 378
379 if (roce_get_bit(aeshift_val, 379 if (roce_get_bit(aeshift_val,
diff --git a/drivers/infiniband/hw/hns/hns_roce_hem.c b/drivers/infiniband/hw/hns/hns_roce_hem.c
index 250d8f280390..c5104e0b2916 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hem.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hem.c
@@ -80,9 +80,9 @@ struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev, int npages,
80 --order; 80 --order;
81 81
82 /* 82 /*
83 * Alloc memory one time. If failed, don't alloc small block 83 * Alloc memory one time. If failed, don't alloc small block
84 * memory, directly return fail. 84 * memory, directly return fail.
85 */ 85 */
86 mem = &chunk->mem[chunk->npages]; 86 mem = &chunk->mem[chunk->npages];
87 buf = dma_alloc_coherent(&hr_dev->pdev->dev, PAGE_SIZE << order, 87 buf = dma_alloc_coherent(&hr_dev->pdev->dev, PAGE_SIZE << order,
88 &sg_dma_address(mem), gfp_mask); 88 &sg_dma_address(mem), gfp_mask);
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
index 71232e5fabf6..b8111b0c8877 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c
@@ -32,6 +32,7 @@
32 32
33#include <linux/platform_device.h> 33#include <linux/platform_device.h>
34#include <linux/acpi.h> 34#include <linux/acpi.h>
35#include <linux/etherdevice.h>
35#include <rdma/ib_umem.h> 36#include <rdma/ib_umem.h>
36#include "hns_roce_common.h" 37#include "hns_roce_common.h"
37#include "hns_roce_device.h" 38#include "hns_roce_device.h"
@@ -72,6 +73,8 @@ int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
72 int nreq = 0; 73 int nreq = 0;
73 u32 ind = 0; 74 u32 ind = 0;
74 int ret = 0; 75 int ret = 0;
76 u8 *smac;
77 int loopback;
75 78
76 if (unlikely(ibqp->qp_type != IB_QPT_GSI && 79 if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
77 ibqp->qp_type != IB_QPT_RC)) { 80 ibqp->qp_type != IB_QPT_RC)) {
@@ -129,6 +132,14 @@ int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
129 UD_SEND_WQE_U32_8_DMAC_5_M, 132 UD_SEND_WQE_U32_8_DMAC_5_M,
130 UD_SEND_WQE_U32_8_DMAC_5_S, 133 UD_SEND_WQE_U32_8_DMAC_5_S,
131 ah->av.mac[5]); 134 ah->av.mac[5]);
135
136 smac = (u8 *)hr_dev->dev_addr[qp->port];
137 loopback = ether_addr_equal_unaligned(ah->av.mac,
138 smac) ? 1 : 0;
139 roce_set_bit(ud_sq_wqe->u32_8,
140 UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
141 loopback);
142
132 roce_set_field(ud_sq_wqe->u32_8, 143 roce_set_field(ud_sq_wqe->u32_8,
133 UD_SEND_WQE_U32_8_OPERATION_TYPE_M, 144 UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
134 UD_SEND_WQE_U32_8_OPERATION_TYPE_S, 145 UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
@@ -284,6 +295,8 @@ out:
284 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M, 295 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
285 SQ_DOORBELL_U32_4_SQ_HEAD_S, 296 SQ_DOORBELL_U32_4_SQ_HEAD_S,
286 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1))); 297 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
298 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
299 SQ_DOORBELL_U32_4_SL_S, qp->sl);
287 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M, 300 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
288 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port); 301 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
289 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M, 302 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
@@ -611,6 +624,213 @@ ext_sdb_buf_fail_out:
611 return ret; 624 return ret;
612} 625}
613 626
627static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
628 struct ib_pd *pd)
629{
630 struct device *dev = &hr_dev->pdev->dev;
631 struct ib_qp_init_attr init_attr;
632 struct ib_qp *qp;
633
634 memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
635 init_attr.qp_type = IB_QPT_RC;
636 init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
637 init_attr.cap.max_recv_wr = HNS_ROCE_MIN_WQE_NUM;
638 init_attr.cap.max_send_wr = HNS_ROCE_MIN_WQE_NUM;
639
640 qp = hns_roce_create_qp(pd, &init_attr, NULL);
641 if (IS_ERR(qp)) {
642 dev_err(dev, "Create loop qp for mr free failed!");
643 return NULL;
644 }
645
646 return to_hr_qp(qp);
647}
648
649static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
650{
651 struct hns_roce_caps *caps = &hr_dev->caps;
652 struct device *dev = &hr_dev->pdev->dev;
653 struct ib_cq_init_attr cq_init_attr;
654 struct hns_roce_free_mr *free_mr;
655 struct ib_qp_attr attr = { 0 };
656 struct hns_roce_v1_priv *priv;
657 struct hns_roce_qp *hr_qp;
658 struct ib_cq *cq;
659 struct ib_pd *pd;
660 u64 subnet_prefix;
661 int attr_mask = 0;
662 int i;
663 int ret;
664 u8 phy_port;
665 u8 sl;
666
667 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
668 free_mr = &priv->free_mr;
669
670 /* Reserved cq for loop qp */
671 cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
672 cq_init_attr.comp_vector = 0;
673 cq = hns_roce_ib_create_cq(&hr_dev->ib_dev, &cq_init_attr, NULL, NULL);
674 if (IS_ERR(cq)) {
675 dev_err(dev, "Create cq for reseved loop qp failed!");
676 return -ENOMEM;
677 }
678 free_mr->mr_free_cq = to_hr_cq(cq);
679 free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
680 free_mr->mr_free_cq->ib_cq.uobject = NULL;
681 free_mr->mr_free_cq->ib_cq.comp_handler = NULL;
682 free_mr->mr_free_cq->ib_cq.event_handler = NULL;
683 free_mr->mr_free_cq->ib_cq.cq_context = NULL;
684 atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
685
686 pd = hns_roce_alloc_pd(&hr_dev->ib_dev, NULL, NULL);
687 if (IS_ERR(pd)) {
688 dev_err(dev, "Create pd for reseved loop qp failed!");
689 ret = -ENOMEM;
690 goto alloc_pd_failed;
691 }
692 free_mr->mr_free_pd = to_hr_pd(pd);
693 free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
694 free_mr->mr_free_pd->ibpd.uobject = NULL;
695 atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
696
697 attr.qp_access_flags = IB_ACCESS_REMOTE_WRITE;
698 attr.pkey_index = 0;
699 attr.min_rnr_timer = 0;
700 /* Disable read ability */
701 attr.max_dest_rd_atomic = 0;
702 attr.max_rd_atomic = 0;
703 /* Use arbitrary values as rq_psn and sq_psn */
704 attr.rq_psn = 0x0808;
705 attr.sq_psn = 0x0808;
706 attr.retry_cnt = 7;
707 attr.rnr_retry = 7;
708 attr.timeout = 0x12;
709 attr.path_mtu = IB_MTU_256;
710 attr.ah_attr.ah_flags = 1;
711 attr.ah_attr.static_rate = 3;
712 attr.ah_attr.grh.sgid_index = 0;
713 attr.ah_attr.grh.hop_limit = 1;
714 attr.ah_attr.grh.flow_label = 0;
715 attr.ah_attr.grh.traffic_class = 0;
716
717 subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
718 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
719 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
720 if (IS_ERR(free_mr->mr_free_qp[i])) {
721 dev_err(dev, "Create loop qp failed!\n");
722 goto create_lp_qp_failed;
723 }
724 hr_qp = free_mr->mr_free_qp[i];
725
726 sl = i / caps->num_ports;
727
728 if (caps->num_ports == HNS_ROCE_MAX_PORTS)
729 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
730 (i % caps->num_ports);
731 else
732 phy_port = i % caps->num_ports;
733
734 hr_qp->port = phy_port + 1;
735 hr_qp->phy_port = phy_port;
736 hr_qp->ibqp.qp_type = IB_QPT_RC;
737 hr_qp->ibqp.device = &hr_dev->ib_dev;
738 hr_qp->ibqp.uobject = NULL;
739 atomic_set(&hr_qp->ibqp.usecnt, 0);
740 hr_qp->ibqp.pd = pd;
741 hr_qp->ibqp.recv_cq = cq;
742 hr_qp->ibqp.send_cq = cq;
743
744 attr.ah_attr.port_num = phy_port + 1;
745 attr.ah_attr.sl = sl;
746 attr.port_num = phy_port + 1;
747
748 attr.dest_qp_num = hr_qp->qpn;
749 memcpy(attr.ah_attr.dmac, hr_dev->dev_addr[phy_port],
750 MAC_ADDR_OCTET_NUM);
751
752 memcpy(attr.ah_attr.grh.dgid.raw,
753 &subnet_prefix, sizeof(u64));
754 memcpy(&attr.ah_attr.grh.dgid.raw[8],
755 hr_dev->dev_addr[phy_port], 3);
756 memcpy(&attr.ah_attr.grh.dgid.raw[13],
757 hr_dev->dev_addr[phy_port] + 3, 3);
758 attr.ah_attr.grh.dgid.raw[11] = 0xff;
759 attr.ah_attr.grh.dgid.raw[12] = 0xfe;
760 attr.ah_attr.grh.dgid.raw[8] ^= 2;
761
762 attr_mask |= IB_QP_PORT;
763
764 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
765 IB_QPS_RESET, IB_QPS_INIT);
766 if (ret) {
767 dev_err(dev, "modify qp failed(%d)!\n", ret);
768 goto create_lp_qp_failed;
769 }
770
771 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
772 IB_QPS_INIT, IB_QPS_RTR);
773 if (ret) {
774 dev_err(dev, "modify qp failed(%d)!\n", ret);
775 goto create_lp_qp_failed;
776 }
777
778 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
779 IB_QPS_RTR, IB_QPS_RTS);
780 if (ret) {
781 dev_err(dev, "modify qp failed(%d)!\n", ret);
782 goto create_lp_qp_failed;
783 }
784 }
785
786 return 0;
787
788create_lp_qp_failed:
789 for (i -= 1; i >= 0; i--) {
790 hr_qp = free_mr->mr_free_qp[i];
791 if (hns_roce_v1_destroy_qp(&hr_qp->ibqp))
792 dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
793 }
794
795 if (hns_roce_dealloc_pd(pd))
796 dev_err(dev, "Destroy pd for create_lp_qp failed!\n");
797
798alloc_pd_failed:
799 if (hns_roce_ib_destroy_cq(cq))
800 dev_err(dev, "Destroy cq for create_lp_qp failed!\n");
801
802 return -EINVAL;
803}
804
805static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
806{
807 struct device *dev = &hr_dev->pdev->dev;
808 struct hns_roce_free_mr *free_mr;
809 struct hns_roce_v1_priv *priv;
810 struct hns_roce_qp *hr_qp;
811 int ret;
812 int i;
813
814 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
815 free_mr = &priv->free_mr;
816
817 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
818 hr_qp = free_mr->mr_free_qp[i];
819 ret = hns_roce_v1_destroy_qp(&hr_qp->ibqp);
820 if (ret)
821 dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
822 i, ret);
823 }
824
825 ret = hns_roce_ib_destroy_cq(&free_mr->mr_free_cq->ib_cq);
826 if (ret)
827 dev_err(dev, "Destroy cq for mr_free failed(%d)!\n", ret);
828
829 ret = hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd);
830 if (ret)
831 dev_err(dev, "Destroy pd for mr_free failed(%d)!\n", ret);
832}
833
614static int hns_roce_db_init(struct hns_roce_dev *hr_dev) 834static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
615{ 835{
616 struct device *dev = &hr_dev->pdev->dev; 836 struct device *dev = &hr_dev->pdev->dev;
@@ -648,6 +868,223 @@ static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
648 return 0; 868 return 0;
649} 869}
650 870
871void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
872{
873 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
874 struct hns_roce_dev *hr_dev;
875
876 lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
877 work);
878 hr_dev = to_hr_dev(lp_qp_work->ib_dev);
879
880 hns_roce_v1_release_lp_qp(hr_dev);
881
882 if (hns_roce_v1_rsv_lp_qp(hr_dev))
883 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
884
885 if (lp_qp_work->comp_flag)
886 complete(lp_qp_work->comp);
887
888 kfree(lp_qp_work);
889}
890
891static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
892{
893 struct device *dev = &hr_dev->pdev->dev;
894 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
895 struct hns_roce_free_mr *free_mr;
896 struct hns_roce_v1_priv *priv;
897 struct completion comp;
898 unsigned long end =
899 msecs_to_jiffies(HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS) + jiffies;
900
901 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
902 free_mr = &priv->free_mr;
903
904 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
905 GFP_KERNEL);
906
907 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
908
909 lp_qp_work->ib_dev = &(hr_dev->ib_dev);
910 lp_qp_work->comp = &comp;
911 lp_qp_work->comp_flag = 1;
912
913 init_completion(lp_qp_work->comp);
914
915 queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
916
917 while (time_before_eq(jiffies, end)) {
918 if (try_wait_for_completion(&comp))
919 return 0;
920 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
921 }
922
923 lp_qp_work->comp_flag = 0;
924 if (try_wait_for_completion(&comp))
925 return 0;
926
927 dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
928 return -ETIMEDOUT;
929}
930
931static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
932{
933 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
934 struct device *dev = &hr_dev->pdev->dev;
935 struct ib_send_wr send_wr, *bad_wr;
936 int ret;
937
938 memset(&send_wr, 0, sizeof(send_wr));
939 send_wr.next = NULL;
940 send_wr.num_sge = 0;
941 send_wr.send_flags = 0;
942 send_wr.sg_list = NULL;
943 send_wr.wr_id = (unsigned long long)&send_wr;
944 send_wr.opcode = IB_WR_RDMA_WRITE;
945
946 ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
947 if (ret) {
948 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
949 return ret;
950 }
951
952 return 0;
953}
954
955static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
956{
957 struct hns_roce_mr_free_work *mr_work;
958 struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
959 struct hns_roce_free_mr *free_mr;
960 struct hns_roce_cq *mr_free_cq;
961 struct hns_roce_v1_priv *priv;
962 struct hns_roce_dev *hr_dev;
963 struct hns_roce_mr *hr_mr;
964 struct hns_roce_qp *hr_qp;
965 struct device *dev;
966 unsigned long end =
967 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
968 int i;
969 int ret;
970 int ne;
971
972 mr_work = container_of(work, struct hns_roce_mr_free_work, work);
973 hr_mr = (struct hns_roce_mr *)mr_work->mr;
974 hr_dev = to_hr_dev(mr_work->ib_dev);
975 dev = &hr_dev->pdev->dev;
976
977 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
978 free_mr = &priv->free_mr;
979 mr_free_cq = free_mr->mr_free_cq;
980
981 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
982 hr_qp = free_mr->mr_free_qp[i];
983 ret = hns_roce_v1_send_lp_wqe(hr_qp);
984 if (ret) {
985 dev_err(dev,
986 "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
987 hr_qp->qpn, ret);
988 goto free_work;
989 }
990 }
991
992 ne = HNS_ROCE_V1_RESV_QP;
993 do {
994 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
995 if (ret < 0) {
996 dev_err(dev,
997 "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
998 hr_qp->qpn, ret, hr_mr->key, ne);
999 goto free_work;
1000 }
1001 ne -= ret;
1002 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1003 } while (ne && time_before_eq(jiffies, end));
1004
1005 if (ne != 0)
1006 dev_err(dev,
1007 "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1008 hr_mr->key, ne);
1009
1010free_work:
1011 if (mr_work->comp_flag)
1012 complete(mr_work->comp);
1013 kfree(mr_work);
1014}
1015
1016int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr)
1017{
1018 struct device *dev = &hr_dev->pdev->dev;
1019 struct hns_roce_mr_free_work *mr_work;
1020 struct hns_roce_free_mr *free_mr;
1021 struct hns_roce_v1_priv *priv;
1022 struct completion comp;
1023 unsigned long end =
1024 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1025 unsigned long start = jiffies;
1026 int npages;
1027 int ret = 0;
1028
1029 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1030 free_mr = &priv->free_mr;
1031
1032 if (mr->enabled) {
1033 if (hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
1034 & (hr_dev->caps.num_mtpts - 1)))
1035 dev_warn(dev, "HW2SW_MPT failed!\n");
1036 }
1037
1038 mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1039 if (!mr_work) {
1040 ret = -ENOMEM;
1041 goto free_mr;
1042 }
1043
1044 INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1045
1046 mr_work->ib_dev = &(hr_dev->ib_dev);
1047 mr_work->comp = &comp;
1048 mr_work->comp_flag = 1;
1049 mr_work->mr = (void *)mr;
1050 init_completion(mr_work->comp);
1051
1052 queue_work(free_mr->free_mr_wq, &(mr_work->work));
1053
1054 while (time_before_eq(jiffies, end)) {
1055 if (try_wait_for_completion(&comp))
1056 goto free_mr;
1057 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1058 }
1059
1060 mr_work->comp_flag = 0;
1061 if (try_wait_for_completion(&comp))
1062 goto free_mr;
1063
1064 dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1065 ret = -ETIMEDOUT;
1066
1067free_mr:
1068 dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1069 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1070
1071 if (mr->size != ~0ULL) {
1072 npages = ib_umem_page_count(mr->umem);
1073 dma_free_coherent(dev, npages * 8, mr->pbl_buf,
1074 mr->pbl_dma_addr);
1075 }
1076
1077 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
1078 key_to_hw_index(mr->key), 0);
1079
1080 if (mr->umem)
1081 ib_umem_release(mr->umem);
1082
1083 kfree(mr);
1084
1085 return ret;
1086}
1087
651static void hns_roce_db_free(struct hns_roce_dev *hr_dev) 1088static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
652{ 1089{
653 struct device *dev = &hr_dev->pdev->dev; 1090 struct device *dev = &hr_dev->pdev->dev;
@@ -849,6 +1286,85 @@ static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
849 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map); 1286 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
850} 1287}
851 1288
1289static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1290{
1291 struct device *dev = &hr_dev->pdev->dev;
1292 struct hns_roce_buf_list *tptr_buf;
1293 struct hns_roce_v1_priv *priv;
1294
1295 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1296 tptr_buf = &priv->tptr_table.tptr_buf;
1297
1298 /*
1299 * This buffer will be used for CQ's tptr(tail pointer), also
1300 * named ci(customer index). Every CQ will use 2 bytes to save
1301 * cqe ci in hip06. Hardware will read this area to get new ci
1302 * when the queue is almost full.
1303 */
1304 tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1305 &tptr_buf->map, GFP_KERNEL);
1306 if (!tptr_buf->buf)
1307 return -ENOMEM;
1308
1309 hr_dev->tptr_dma_addr = tptr_buf->map;
1310 hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1311
1312 return 0;
1313}
1314
1315static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1316{
1317 struct device *dev = &hr_dev->pdev->dev;
1318 struct hns_roce_buf_list *tptr_buf;
1319 struct hns_roce_v1_priv *priv;
1320
1321 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1322 tptr_buf = &priv->tptr_table.tptr_buf;
1323
1324 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1325 tptr_buf->buf, tptr_buf->map);
1326}
1327
1328static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1329{
1330 struct device *dev = &hr_dev->pdev->dev;
1331 struct hns_roce_free_mr *free_mr;
1332 struct hns_roce_v1_priv *priv;
1333 int ret = 0;
1334
1335 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1336 free_mr = &priv->free_mr;
1337
1338 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1339 if (!free_mr->free_mr_wq) {
1340 dev_err(dev, "Create free mr workqueue failed!\n");
1341 return -ENOMEM;
1342 }
1343
1344 ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1345 if (ret) {
1346 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1347 flush_workqueue(free_mr->free_mr_wq);
1348 destroy_workqueue(free_mr->free_mr_wq);
1349 }
1350
1351 return ret;
1352}
1353
1354static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1355{
1356 struct hns_roce_free_mr *free_mr;
1357 struct hns_roce_v1_priv *priv;
1358
1359 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1360 free_mr = &priv->free_mr;
1361
1362 flush_workqueue(free_mr->free_mr_wq);
1363 destroy_workqueue(free_mr->free_mr_wq);
1364
1365 hns_roce_v1_release_lp_qp(hr_dev);
1366}
1367
852/** 1368/**
853 * hns_roce_v1_reset - reset RoCE 1369 * hns_roce_v1_reset - reset RoCE
854 * @hr_dev: RoCE device struct pointer 1370 * @hr_dev: RoCE device struct pointer
@@ -898,6 +1414,38 @@ int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
898 return ret; 1414 return ret;
899} 1415}
900 1416
1417static int hns_roce_des_qp_init(struct hns_roce_dev *hr_dev)
1418{
1419 struct device *dev = &hr_dev->pdev->dev;
1420 struct hns_roce_v1_priv *priv;
1421 struct hns_roce_des_qp *des_qp;
1422
1423 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1424 des_qp = &priv->des_qp;
1425
1426 des_qp->requeue_flag = 1;
1427 des_qp->qp_wq = create_singlethread_workqueue("hns_roce_destroy_qp");
1428 if (!des_qp->qp_wq) {
1429 dev_err(dev, "Create destroy qp workqueue failed!\n");
1430 return -ENOMEM;
1431 }
1432
1433 return 0;
1434}
1435
1436static void hns_roce_des_qp_free(struct hns_roce_dev *hr_dev)
1437{
1438 struct hns_roce_v1_priv *priv;
1439 struct hns_roce_des_qp *des_qp;
1440
1441 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1442 des_qp = &priv->des_qp;
1443
1444 des_qp->requeue_flag = 0;
1445 flush_workqueue(des_qp->qp_wq);
1446 destroy_workqueue(des_qp->qp_wq);
1447}
1448
901void hns_roce_v1_profile(struct hns_roce_dev *hr_dev) 1449void hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
902{ 1450{
903 int i = 0; 1451 int i = 0;
@@ -906,12 +1454,11 @@ void hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
906 hr_dev->vendor_id = le32_to_cpu(roce_read(hr_dev, ROCEE_VENDOR_ID_REG)); 1454 hr_dev->vendor_id = le32_to_cpu(roce_read(hr_dev, ROCEE_VENDOR_ID_REG));
907 hr_dev->vendor_part_id = le32_to_cpu(roce_read(hr_dev, 1455 hr_dev->vendor_part_id = le32_to_cpu(roce_read(hr_dev,
908 ROCEE_VENDOR_PART_ID_REG)); 1456 ROCEE_VENDOR_PART_ID_REG));
909 hr_dev->hw_rev = le32_to_cpu(roce_read(hr_dev, ROCEE_HW_VERSION_REG));
910
911 hr_dev->sys_image_guid = le32_to_cpu(roce_read(hr_dev, 1457 hr_dev->sys_image_guid = le32_to_cpu(roce_read(hr_dev,
912 ROCEE_SYS_IMAGE_GUID_L_REG)) | 1458 ROCEE_SYS_IMAGE_GUID_L_REG)) |
913 ((u64)le32_to_cpu(roce_read(hr_dev, 1459 ((u64)le32_to_cpu(roce_read(hr_dev,
914 ROCEE_SYS_IMAGE_GUID_H_REG)) << 32); 1460 ROCEE_SYS_IMAGE_GUID_H_REG)) << 32);
1461 hr_dev->hw_rev = HNS_ROCE_HW_VER1;
915 1462
916 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM; 1463 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
917 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM; 1464 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
@@ -1001,18 +1548,44 @@ int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1001 goto error_failed_raq_init; 1548 goto error_failed_raq_init;
1002 } 1549 }
1003 1550
1004 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1005
1006 ret = hns_roce_bt_init(hr_dev); 1551 ret = hns_roce_bt_init(hr_dev);
1007 if (ret) { 1552 if (ret) {
1008 dev_err(dev, "bt init failed!\n"); 1553 dev_err(dev, "bt init failed!\n");
1009 goto error_failed_bt_init; 1554 goto error_failed_bt_init;
1010 } 1555 }
1011 1556
1557 ret = hns_roce_tptr_init(hr_dev);
1558 if (ret) {
1559 dev_err(dev, "tptr init failed!\n");
1560 goto error_failed_tptr_init;
1561 }
1562
1563 ret = hns_roce_des_qp_init(hr_dev);
1564 if (ret) {
1565 dev_err(dev, "des qp init failed!\n");
1566 goto error_failed_des_qp_init;
1567 }
1568
1569 ret = hns_roce_free_mr_init(hr_dev);
1570 if (ret) {
1571 dev_err(dev, "free mr init failed!\n");
1572 goto error_failed_free_mr_init;
1573 }
1574
1575 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1576
1012 return 0; 1577 return 0;
1013 1578
1579error_failed_free_mr_init:
1580 hns_roce_des_qp_free(hr_dev);
1581
1582error_failed_des_qp_init:
1583 hns_roce_tptr_free(hr_dev);
1584
1585error_failed_tptr_init:
1586 hns_roce_bt_free(hr_dev);
1587
1014error_failed_bt_init: 1588error_failed_bt_init:
1015 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1016 hns_roce_raq_free(hr_dev); 1589 hns_roce_raq_free(hr_dev);
1017 1590
1018error_failed_raq_init: 1591error_failed_raq_init:
@@ -1022,8 +1595,11 @@ error_failed_raq_init:
1022 1595
1023void hns_roce_v1_exit(struct hns_roce_dev *hr_dev) 1596void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1024{ 1597{
1025 hns_roce_bt_free(hr_dev);
1026 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN); 1598 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1599 hns_roce_free_mr_free(hr_dev);
1600 hns_roce_des_qp_free(hr_dev);
1601 hns_roce_tptr_free(hr_dev);
1602 hns_roce_bt_free(hr_dev);
1027 hns_roce_raq_free(hr_dev); 1603 hns_roce_raq_free(hr_dev);
1028 hns_roce_db_free(hr_dev); 1604 hns_roce_db_free(hr_dev);
1029} 1605}
@@ -1061,6 +1637,14 @@ void hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr)
1061 u32 *p; 1637 u32 *p;
1062 u32 val; 1638 u32 val;
1063 1639
1640 /*
1641 * When mac changed, loopback may fail
1642 * because of smac not equal to dmac.
1643 * We Need to release and create reserved qp again.
1644 */
1645 if (hr_dev->hw->dereg_mr && hns_roce_v1_recreate_lp_qp(hr_dev))
1646 dev_warn(&hr_dev->pdev->dev, "recreate lp qp timeout!\n");
1647
1064 p = (u32 *)(&addr[0]); 1648 p = (u32 *)(&addr[0]);
1065 reg_smac_l = *p; 1649 reg_smac_l = *p;
1066 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG + 1650 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
@@ -1293,9 +1877,9 @@ static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1293 } 1877 }
1294 1878
1295 /* 1879 /*
1296 * Now backwards through the CQ, removing CQ entries 1880 * Now backwards through the CQ, removing CQ entries
1297 * that match our QP by overwriting them with next entries. 1881 * that match our QP by overwriting them with next entries.
1298 */ 1882 */
1299 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { 1883 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
1300 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe); 1884 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
1301 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M, 1885 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
@@ -1317,9 +1901,9 @@ static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
1317 if (nfreed) { 1901 if (nfreed) {
1318 hr_cq->cons_index += nfreed; 1902 hr_cq->cons_index += nfreed;
1319 /* 1903 /*
1320 * Make sure update of buffer contents is done before 1904 * Make sure update of buffer contents is done before
1321 * updating consumer index. 1905 * updating consumer index.
1322 */ 1906 */
1323 wmb(); 1907 wmb();
1324 1908
1325 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index); 1909 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
@@ -1339,14 +1923,21 @@ void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1339 dma_addr_t dma_handle, int nent, u32 vector) 1923 dma_addr_t dma_handle, int nent, u32 vector)
1340{ 1924{
1341 struct hns_roce_cq_context *cq_context = NULL; 1925 struct hns_roce_cq_context *cq_context = NULL;
1342 void __iomem *tptr_addr; 1926 struct hns_roce_buf_list *tptr_buf;
1927 struct hns_roce_v1_priv *priv;
1928 dma_addr_t tptr_dma_addr;
1929 int offset;
1930
1931 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
1932 tptr_buf = &priv->tptr_table.tptr_buf;
1343 1933
1344 cq_context = mb_buf; 1934 cq_context = mb_buf;
1345 memset(cq_context, 0, sizeof(*cq_context)); 1935 memset(cq_context, 0, sizeof(*cq_context));
1346 1936
1347 tptr_addr = 0; 1937 /* Get the tptr for this CQ. */
1348 hr_dev->priv_addr = tptr_addr; 1938 offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
1349 hr_cq->tptr_addr = tptr_addr; 1939 tptr_dma_addr = tptr_buf->map + offset;
1940 hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
1350 1941
1351 /* Register cq_context members */ 1942 /* Register cq_context members */
1352 roce_set_field(cq_context->cqc_byte_4, 1943 roce_set_field(cq_context->cqc_byte_4,
@@ -1390,10 +1981,10 @@ void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1390 roce_set_field(cq_context->cqc_byte_20, 1981 roce_set_field(cq_context->cqc_byte_20,
1391 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M, 1982 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
1392 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S, 1983 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
1393 (u64)tptr_addr >> 44); 1984 tptr_dma_addr >> 44);
1394 cq_context->cqc_byte_20 = cpu_to_le32(cq_context->cqc_byte_20); 1985 cq_context->cqc_byte_20 = cpu_to_le32(cq_context->cqc_byte_20);
1395 1986
1396 cq_context->cqe_tptr_addr_l = (u32)((u64)tptr_addr >> 12); 1987 cq_context->cqe_tptr_addr_l = (u32)(tptr_dma_addr >> 12);
1397 1988
1398 roce_set_field(cq_context->cqc_byte_32, 1989 roce_set_field(cq_context->cqc_byte_32,
1399 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M, 1990 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
@@ -1407,7 +1998,7 @@ void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
1407 roce_set_bit(cq_context->cqc_byte_32, 1998 roce_set_bit(cq_context->cqc_byte_32,
1408 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S, 1999 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
1409 0); 2000 0);
1410 /*The initial value of cq's ci is 0 */ 2001 /* The initial value of cq's ci is 0 */
1411 roce_set_field(cq_context->cqc_byte_32, 2002 roce_set_field(cq_context->cqc_byte_32,
1412 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M, 2003 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
1413 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0); 2004 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
@@ -1424,9 +2015,9 @@ int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
1424 notification_flag = (flags & IB_CQ_SOLICITED_MASK) == 2015 notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
1425 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL; 2016 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
1426 /* 2017 /*
1427 * flags = 0; Notification Flag = 1, next 2018 * flags = 0; Notification Flag = 1, next
1428 * flags = 1; Notification Flag = 0, solocited 2019 * flags = 1; Notification Flag = 0, solocited
1429 */ 2020 */
1430 doorbell[0] = hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1); 2021 doorbell[0] = hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1);
1431 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1); 2022 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
1432 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M, 2023 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
@@ -1581,10 +2172,10 @@ static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
1581 wq = &(*cur_qp)->sq; 2172 wq = &(*cur_qp)->sq;
1582 if ((*cur_qp)->sq_signal_bits) { 2173 if ((*cur_qp)->sq_signal_bits) {
1583 /* 2174 /*
1584 * If sg_signal_bit is 1, 2175 * If sg_signal_bit is 1,
1585 * firstly tail pointer updated to wqe 2176 * firstly tail pointer updated to wqe
1586 * which current cqe correspond to 2177 * which current cqe correspond to
1587 */ 2178 */
1588 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4, 2179 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
1589 CQE_BYTE_4_WQE_INDEX_M, 2180 CQE_BYTE_4_WQE_INDEX_M,
1590 CQE_BYTE_4_WQE_INDEX_S); 2181 CQE_BYTE_4_WQE_INDEX_S);
@@ -1659,8 +2250,14 @@ int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
1659 break; 2250 break;
1660 } 2251 }
1661 2252
1662 if (npolled) 2253 if (npolled) {
2254 *hr_cq->tptr_addr = hr_cq->cons_index &
2255 ((hr_cq->cq_depth << 1) - 1);
2256
2257 /* Memroy barrier */
2258 wmb();
1663 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index); 2259 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2260 }
1664 2261
1665 spin_unlock_irqrestore(&hr_cq->lock, flags); 2262 spin_unlock_irqrestore(&hr_cq->lock, flags);
1666 2263
@@ -1799,12 +2396,12 @@ static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
1799 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP) 2396 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
1800 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2, 2397 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
1801 HNS_ROCE_CMD_2RST_QP, 2398 HNS_ROCE_CMD_2RST_QP,
1802 HNS_ROCE_CMD_TIME_CLASS_A); 2399 HNS_ROCE_CMD_TIMEOUT_MSECS);
1803 2400
1804 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP) 2401 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
1805 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2, 2402 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
1806 HNS_ROCE_CMD_2ERR_QP, 2403 HNS_ROCE_CMD_2ERR_QP,
1807 HNS_ROCE_CMD_TIME_CLASS_A); 2404 HNS_ROCE_CMD_TIMEOUT_MSECS);
1808 2405
1809 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 2406 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
1810 if (IS_ERR(mailbox)) 2407 if (IS_ERR(mailbox))
@@ -1814,7 +2411,7 @@ static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
1814 2411
1815 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 2412 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
1816 op[cur_state][new_state], 2413 op[cur_state][new_state],
1817 HNS_ROCE_CMD_TIME_CLASS_C); 2414 HNS_ROCE_CMD_TIMEOUT_MSECS);
1818 2415
1819 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 2416 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
1820 return ret; 2417 return ret;
@@ -2000,11 +2597,11 @@ static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2000 } 2597 }
2001 2598
2002 /* 2599 /*
2003 *Reset to init 2600 * Reset to init
2004 * Mandatory param: 2601 * Mandatory param:
2005 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS 2602 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2006 * Optional param: NA 2603 * Optional param: NA
2007 */ 2604 */
2008 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2605 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2009 roce_set_field(context->qpc_bytes_4, 2606 roce_set_field(context->qpc_bytes_4,
2010 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M, 2607 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
@@ -2172,24 +2769,14 @@ static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2172 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S, 2769 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2173 hr_qp->sq_signal_bits); 2770 hr_qp->sq_signal_bits);
2174 2771
2175 for (port = 0; port < hr_dev->caps.num_ports; port++) { 2772 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2176 smac = (u8 *)hr_dev->dev_addr[port]; 2773 hr_qp->port;
2177 dev_dbg(dev, "smac: %2x: %2x: %2x: %2x: %2x: %2x\n", 2774 smac = (u8 *)hr_dev->dev_addr[port];
2178 smac[0], smac[1], smac[2], smac[3], smac[4], 2775 /* when dmac equals smac or loop_idc is 1, it should loopback */
2179 smac[5]); 2776 if (ether_addr_equal_unaligned(dmac, smac) ||
2180 if ((dmac[0] == smac[0]) && (dmac[1] == smac[1]) && 2777 hr_dev->loop_idc == 0x1)
2181 (dmac[2] == smac[2]) && (dmac[3] == smac[3]) &&
2182 (dmac[4] == smac[4]) && (dmac[5] == smac[5])) {
2183 roce_set_bit(context->qpc_bytes_32,
2184 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S,
2185 1);
2186 break;
2187 }
2188 }
2189
2190 if (hr_dev->loop_idc == 0x1)
2191 roce_set_bit(context->qpc_bytes_32, 2778 roce_set_bit(context->qpc_bytes_32,
2192 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1); 2779 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2193 2780
2194 roce_set_bit(context->qpc_bytes_32, 2781 roce_set_bit(context->qpc_bytes_32,
2195 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S, 2782 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
@@ -2509,7 +3096,7 @@ static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2509 /* Every status migrate must change state */ 3096 /* Every status migrate must change state */
2510 roce_set_field(context->qpc_bytes_144, 3097 roce_set_field(context->qpc_bytes_144,
2511 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M, 3098 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
2512 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, attr->qp_state); 3099 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
2513 3100
2514 /* SW pass context to HW */ 3101 /* SW pass context to HW */
2515 ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt, 3102 ret = hns_roce_v1_qp_modify(hr_dev, &hr_qp->mtt,
@@ -2522,9 +3109,9 @@ static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2522 } 3109 }
2523 3110
2524 /* 3111 /*
2525 * Use rst2init to instead of init2init with drv, 3112 * Use rst2init to instead of init2init with drv,
2526 * need to hw to flash RQ HEAD by DB again 3113 * need to hw to flash RQ HEAD by DB again
2527 */ 3114 */
2528 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { 3115 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2529 /* Memory barrier */ 3116 /* Memory barrier */
2530 wmb(); 3117 wmb();
@@ -2619,7 +3206,7 @@ static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
2619 3206
2620 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0, 3207 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
2621 HNS_ROCE_CMD_QUERY_QP, 3208 HNS_ROCE_CMD_QUERY_QP,
2622 HNS_ROCE_CMD_TIME_CLASS_A); 3209 HNS_ROCE_CMD_TIMEOUT_MSECS);
2623 if (!ret) 3210 if (!ret)
2624 memcpy(hr_context, mailbox->buf, sizeof(*hr_context)); 3211 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
2625 else 3212 else
@@ -2630,8 +3217,78 @@ static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
2630 return ret; 3217 return ret;
2631} 3218}
2632 3219
2633int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, 3220static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
2634 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 3221 int qp_attr_mask,
3222 struct ib_qp_init_attr *qp_init_attr)
3223{
3224 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3225 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3226 struct hns_roce_sqp_context context;
3227 u32 addr;
3228
3229 mutex_lock(&hr_qp->mutex);
3230
3231 if (hr_qp->state == IB_QPS_RESET) {
3232 qp_attr->qp_state = IB_QPS_RESET;
3233 goto done;
3234 }
3235
3236 addr = ROCEE_QP1C_CFG0_0_REG +
3237 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3238 context.qp1c_bytes_4 = roce_read(hr_dev, addr);
3239 context.sq_rq_bt_l = roce_read(hr_dev, addr + 1);
3240 context.qp1c_bytes_12 = roce_read(hr_dev, addr + 2);
3241 context.qp1c_bytes_16 = roce_read(hr_dev, addr + 3);
3242 context.qp1c_bytes_20 = roce_read(hr_dev, addr + 4);
3243 context.cur_rq_wqe_ba_l = roce_read(hr_dev, addr + 5);
3244 context.qp1c_bytes_28 = roce_read(hr_dev, addr + 6);
3245 context.qp1c_bytes_32 = roce_read(hr_dev, addr + 7);
3246 context.cur_sq_wqe_ba_l = roce_read(hr_dev, addr + 8);
3247 context.qp1c_bytes_40 = roce_read(hr_dev, addr + 9);
3248
3249 hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3250 QP1C_BYTES_4_QP_STATE_M,
3251 QP1C_BYTES_4_QP_STATE_S);
3252 qp_attr->qp_state = hr_qp->state;
3253 qp_attr->path_mtu = IB_MTU_256;
3254 qp_attr->path_mig_state = IB_MIG_ARMED;
3255 qp_attr->qkey = QKEY_VAL;
3256 qp_attr->rq_psn = 0;
3257 qp_attr->sq_psn = 0;
3258 qp_attr->dest_qp_num = 1;
3259 qp_attr->qp_access_flags = 6;
3260
3261 qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3262 QP1C_BYTES_20_PKEY_IDX_M,
3263 QP1C_BYTES_20_PKEY_IDX_S);
3264 qp_attr->port_num = hr_qp->port + 1;
3265 qp_attr->sq_draining = 0;
3266 qp_attr->max_rd_atomic = 0;
3267 qp_attr->max_dest_rd_atomic = 0;
3268 qp_attr->min_rnr_timer = 0;
3269 qp_attr->timeout = 0;
3270 qp_attr->retry_cnt = 0;
3271 qp_attr->rnr_retry = 0;
3272 qp_attr->alt_timeout = 0;
3273
3274done:
3275 qp_attr->cur_qp_state = qp_attr->qp_state;
3276 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3277 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3278 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3279 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3280 qp_attr->cap.max_inline_data = 0;
3281 qp_init_attr->cap = qp_attr->cap;
3282 qp_init_attr->create_flags = 0;
3283
3284 mutex_unlock(&hr_qp->mutex);
3285
3286 return 0;
3287}
3288
3289static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3290 int qp_attr_mask,
3291 struct ib_qp_init_attr *qp_init_attr)
2635{ 3292{
2636 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3293 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2637 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3294 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
@@ -2725,9 +3382,7 @@ int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
2725 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12, 3382 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
2726 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M, 3383 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2727 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S); 3384 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
2728 qp_attr->port_num = (u8)roce_get_field(context->qpc_bytes_156, 3385 qp_attr->port_num = hr_qp->port + 1;
2729 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
2730 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S) + 1;
2731 qp_attr->sq_draining = 0; 3386 qp_attr->sq_draining = 0;
2732 qp_attr->max_rd_atomic = roce_get_field(context->qpc_bytes_156, 3387 qp_attr->max_rd_atomic = roce_get_field(context->qpc_bytes_156,
2733 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M, 3388 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
@@ -2767,134 +3422,397 @@ out:
2767 return ret; 3422 return ret;
2768} 3423}
2769 3424
2770static void hns_roce_v1_destroy_qp_common(struct hns_roce_dev *hr_dev, 3425int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
2771 struct hns_roce_qp *hr_qp, 3426 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
2772 int is_user) 3427{
3428 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3429
3430 return hr_qp->doorbell_qpn <= 1 ?
3431 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3432 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3433}
3434
3435static int check_qp_db_process_status(struct hns_roce_dev *hr_dev,
3436 struct hns_roce_qp *hr_qp,
3437 u32 sdb_issue_ptr,
3438 u32 *sdb_inv_cnt,
3439 u32 *wait_stage)
2773{ 3440{
2774 u32 sdbinvcnt;
2775 unsigned long end = 0;
2776 u32 sdbinvcnt_val;
2777 u32 sdbsendptr_val;
2778 u32 sdbisusepr_val;
2779 struct hns_roce_cq *send_cq, *recv_cq;
2780 struct device *dev = &hr_dev->pdev->dev; 3441 struct device *dev = &hr_dev->pdev->dev;
3442 u32 sdb_retry_cnt, old_retry;
3443 u32 sdb_send_ptr, old_send;
3444 u32 success_flags = 0;
3445 u32 cur_cnt, old_cnt;
3446 unsigned long end;
3447 u32 send_ptr;
3448 u32 inv_cnt;
3449 u32 tsp_st;
3450
3451 if (*wait_stage > HNS_ROCE_V1_DB_STAGE2 ||
3452 *wait_stage < HNS_ROCE_V1_DB_STAGE1) {
3453 dev_err(dev, "QP(0x%lx) db status wait stage(%d) error!\n",
3454 hr_qp->qpn, *wait_stage);
3455 return -EINVAL;
3456 }
2781 3457
2782 if (hr_qp->ibqp.qp_type == IB_QPT_RC) { 3458 /* Calculate the total timeout for the entire verification process */
2783 if (hr_qp->state != IB_QPS_RESET) { 3459 end = msecs_to_jiffies(HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS) + jiffies;
2784 /* 3460
2785 * Set qp to ERR, 3461 if (*wait_stage == HNS_ROCE_V1_DB_STAGE1) {
2786 * waiting for hw complete processing all dbs 3462 /* Query db process status, until hw process completely */
2787 */ 3463 sdb_send_ptr = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
2788 if (hns_roce_v1_qp_modify(hr_dev, NULL, 3464 while (roce_hw_index_cmp_lt(sdb_send_ptr, sdb_issue_ptr,
2789 to_hns_roce_state( 3465 ROCEE_SDB_PTR_CMP_BITS)) {
2790 (enum ib_qp_state)hr_qp->state), 3466 if (!time_before(jiffies, end)) {
2791 HNS_ROCE_QP_STATE_ERR, NULL, 3467 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout. issue 0x%x send 0x%x.\n",
2792 hr_qp)) 3468 hr_qp->qpn, sdb_issue_ptr,
2793 dev_err(dev, "modify QP %06lx to ERR failed.\n", 3469 sdb_send_ptr);
2794 hr_qp->qpn); 3470 return 0;
2795 3471 }
2796 /* Record issued doorbell */ 3472
2797 sdbisusepr_val = roce_read(hr_dev, 3473 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
2798 ROCEE_SDB_ISSUE_PTR_REG); 3474 sdb_send_ptr = roce_read(hr_dev,
2799 /*
2800 * Query db process status,
2801 * until hw process completely
2802 */
2803 end = msecs_to_jiffies(
2804 HNS_ROCE_QP_DESTROY_TIMEOUT_MSECS) + jiffies;
2805 do {
2806 sdbsendptr_val = roce_read(hr_dev,
2807 ROCEE_SDB_SEND_PTR_REG); 3475 ROCEE_SDB_SEND_PTR_REG);
2808 if (!time_before(jiffies, end)) { 3476 }
2809 dev_err(dev, "destroy qp(0x%lx) timeout!!!",
2810 hr_qp->qpn);
2811 break;
2812 }
2813 } while ((short)(roce_get_field(sdbsendptr_val,
2814 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
2815 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) -
2816 roce_get_field(sdbisusepr_val,
2817 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
2818 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S)
2819 ) < 0);
2820 3477
2821 /* Get list pointer */ 3478 if (roce_get_field(sdb_issue_ptr,
2822 sdbinvcnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG); 3479 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M,
3480 ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S) ==
3481 roce_get_field(sdb_send_ptr,
3482 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3483 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S)) {
3484 old_send = roce_read(hr_dev, ROCEE_SDB_SEND_PTR_REG);
3485 old_retry = roce_read(hr_dev, ROCEE_SDB_RETRY_CNT_REG);
2823 3486
2824 /* Query db's list status, until hw reversal */
2825 do { 3487 do {
2826 sdbinvcnt_val = roce_read(hr_dev, 3488 tsp_st = roce_read(hr_dev, ROCEE_TSP_BP_ST_REG);
2827 ROCEE_SDB_INV_CNT_REG); 3489 if (roce_get_bit(tsp_st,
3490 ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S) == 1) {
3491 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3492 return 0;
3493 }
3494
2828 if (!time_before(jiffies, end)) { 3495 if (!time_before(jiffies, end)) {
2829 dev_err(dev, "destroy qp(0x%lx) timeout!!!", 3496 dev_dbg(dev, "QP(0x%lx) db process stage1 timeout when send ptr equals issue ptr.\n"
2830 hr_qp->qpn); 3497 "issue 0x%x send 0x%x.\n",
2831 dev_err(dev, "SdbInvCnt = 0x%x\n", 3498 hr_qp->qpn, sdb_issue_ptr,
2832 sdbinvcnt_val); 3499 sdb_send_ptr);
2833 break; 3500 return 0;
3501 }
3502
3503 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3504
3505 sdb_send_ptr = roce_read(hr_dev,
3506 ROCEE_SDB_SEND_PTR_REG);
3507 sdb_retry_cnt = roce_read(hr_dev,
3508 ROCEE_SDB_RETRY_CNT_REG);
3509 cur_cnt = roce_get_field(sdb_send_ptr,
3510 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3511 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3512 roce_get_field(sdb_retry_cnt,
3513 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3514 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3515 if (!roce_get_bit(tsp_st,
3516 ROCEE_CNT_CLR_CE_CNT_CLR_CE_S)) {
3517 old_cnt = roce_get_field(old_send,
3518 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3519 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3520 roce_get_field(old_retry,
3521 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3522 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3523 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3524 success_flags = 1;
3525 } else {
3526 old_cnt = roce_get_field(old_send,
3527 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3528 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S);
3529 if (cur_cnt - old_cnt > SDB_ST_CMP_VAL)
3530 success_flags = 1;
3531 else {
3532 send_ptr = roce_get_field(old_send,
3533 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3534 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S) +
3535 roce_get_field(sdb_retry_cnt,
3536 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M,
3537 ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S);
3538 roce_set_field(old_send,
3539 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M,
3540 ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S,
3541 send_ptr);
3542 }
2834 } 3543 }
2835 } while ((short)(roce_get_field(sdbinvcnt_val, 3544 } while (!success_flags);
2836 ROCEE_SDB_INV_CNT_SDB_INV_CNT_M,
2837 ROCEE_SDB_INV_CNT_SDB_INV_CNT_S) -
2838 (sdbinvcnt + SDB_INV_CNT_OFFSET)) < 0);
2839
2840 /* Modify qp to reset before destroying qp */
2841 if (hns_roce_v1_qp_modify(hr_dev, NULL,
2842 to_hns_roce_state(
2843 (enum ib_qp_state)hr_qp->state),
2844 HNS_ROCE_QP_STATE_RST, NULL, hr_qp))
2845 dev_err(dev, "modify QP %06lx to RESET failed.\n",
2846 hr_qp->qpn);
2847 } 3545 }
3546
3547 *wait_stage = HNS_ROCE_V1_DB_STAGE2;
3548
3549 /* Get list pointer */
3550 *sdb_inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3551 dev_dbg(dev, "QP(0x%lx) db process stage2. inv cnt = 0x%x.\n",
3552 hr_qp->qpn, *sdb_inv_cnt);
3553 }
3554
3555 if (*wait_stage == HNS_ROCE_V1_DB_STAGE2) {
3556 /* Query db's list status, until hw reversal */
3557 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3558 while (roce_hw_index_cmp_lt(inv_cnt,
3559 *sdb_inv_cnt + SDB_INV_CNT_OFFSET,
3560 ROCEE_SDB_CNT_CMP_BITS)) {
3561 if (!time_before(jiffies, end)) {
3562 dev_dbg(dev, "QP(0x%lx) db process stage2 timeout. inv cnt 0x%x.\n",
3563 hr_qp->qpn, inv_cnt);
3564 return 0;
3565 }
3566
3567 msleep(HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS);
3568 inv_cnt = roce_read(hr_dev, ROCEE_SDB_INV_CNT_REG);
3569 }
3570
3571 *wait_stage = HNS_ROCE_V1_DB_WAIT_OK;
3572 }
3573
3574 return 0;
3575}
3576
3577static int check_qp_reset_state(struct hns_roce_dev *hr_dev,
3578 struct hns_roce_qp *hr_qp,
3579 struct hns_roce_qp_work *qp_work_entry,
3580 int *is_timeout)
3581{
3582 struct device *dev = &hr_dev->pdev->dev;
3583 u32 sdb_issue_ptr;
3584 int ret;
3585
3586 if (hr_qp->state != IB_QPS_RESET) {
3587 /* Set qp to ERR, waiting for hw complete processing all dbs */
3588 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3589 IB_QPS_ERR);
3590 if (ret) {
3591 dev_err(dev, "Modify QP(0x%lx) to ERR failed!\n",
3592 hr_qp->qpn);
3593 return ret;
3594 }
3595
3596 /* Record issued doorbell */
3597 sdb_issue_ptr = roce_read(hr_dev, ROCEE_SDB_ISSUE_PTR_REG);
3598 qp_work_entry->sdb_issue_ptr = sdb_issue_ptr;
3599 qp_work_entry->db_wait_stage = HNS_ROCE_V1_DB_STAGE1;
3600
3601 /* Query db process status, until hw process completely */
3602 ret = check_qp_db_process_status(hr_dev, hr_qp, sdb_issue_ptr,
3603 &qp_work_entry->sdb_inv_cnt,
3604 &qp_work_entry->db_wait_stage);
3605 if (ret) {
3606 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3607 hr_qp->qpn);
3608 return ret;
3609 }
3610
3611 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK) {
3612 qp_work_entry->sche_cnt = 0;
3613 *is_timeout = 1;
3614 return 0;
3615 }
3616
3617 /* Modify qp to reset before destroying qp */
3618 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3619 IB_QPS_RESET);
3620 if (ret) {
3621 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n",
3622 hr_qp->qpn);
3623 return ret;
3624 }
3625 }
3626
3627 return 0;
3628}
3629
3630static void hns_roce_v1_destroy_qp_work_fn(struct work_struct *work)
3631{
3632 struct hns_roce_qp_work *qp_work_entry;
3633 struct hns_roce_v1_priv *priv;
3634 struct hns_roce_dev *hr_dev;
3635 struct hns_roce_qp *hr_qp;
3636 struct device *dev;
3637 int ret;
3638
3639 qp_work_entry = container_of(work, struct hns_roce_qp_work, work);
3640 hr_dev = to_hr_dev(qp_work_entry->ib_dev);
3641 dev = &hr_dev->pdev->dev;
3642 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
3643 hr_qp = qp_work_entry->qp;
3644
3645 dev_dbg(dev, "Schedule destroy QP(0x%lx) work.\n", hr_qp->qpn);
3646
3647 qp_work_entry->sche_cnt++;
3648
3649 /* Query db process status, until hw process completely */
3650 ret = check_qp_db_process_status(hr_dev, hr_qp,
3651 qp_work_entry->sdb_issue_ptr,
3652 &qp_work_entry->sdb_inv_cnt,
3653 &qp_work_entry->db_wait_stage);
3654 if (ret) {
3655 dev_err(dev, "Check QP(0x%lx) db process status failed!\n",
3656 hr_qp->qpn);
3657 return;
3658 }
3659
3660 if (qp_work_entry->db_wait_stage != HNS_ROCE_V1_DB_WAIT_OK &&
3661 priv->des_qp.requeue_flag) {
3662 queue_work(priv->des_qp.qp_wq, work);
3663 return;
3664 }
3665
3666 /* Modify qp to reset before destroying qp */
3667 ret = hns_roce_v1_modify_qp(&hr_qp->ibqp, NULL, 0, hr_qp->state,
3668 IB_QPS_RESET);
3669 if (ret) {
3670 dev_err(dev, "Modify QP(0x%lx) to RST failed!\n", hr_qp->qpn);
3671 return;
3672 }
3673
3674 hns_roce_qp_remove(hr_dev, hr_qp);
3675 hns_roce_qp_free(hr_dev, hr_qp);
3676
3677 if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3678 /* RC QP, release QPN */
3679 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
3680 kfree(hr_qp);
3681 } else
3682 kfree(hr_to_hr_sqp(hr_qp));
3683
3684 kfree(qp_work_entry);
3685
3686 dev_dbg(dev, "Accomplished destroy QP(0x%lx) work.\n", hr_qp->qpn);
3687}
3688
3689int hns_roce_v1_destroy_qp(struct ib_qp *ibqp)
3690{
3691 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3692 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3693 struct device *dev = &hr_dev->pdev->dev;
3694 struct hns_roce_qp_work qp_work_entry;
3695 struct hns_roce_qp_work *qp_work;
3696 struct hns_roce_v1_priv *priv;
3697 struct hns_roce_cq *send_cq, *recv_cq;
3698 int is_user = !!ibqp->pd->uobject;
3699 int is_timeout = 0;
3700 int ret;
3701
3702 ret = check_qp_reset_state(hr_dev, hr_qp, &qp_work_entry, &is_timeout);
3703 if (ret) {
3704 dev_err(dev, "QP reset state check failed(%d)!\n", ret);
3705 return ret;
2848 } 3706 }
2849 3707
2850 send_cq = to_hr_cq(hr_qp->ibqp.send_cq); 3708 send_cq = to_hr_cq(hr_qp->ibqp.send_cq);
2851 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq); 3709 recv_cq = to_hr_cq(hr_qp->ibqp.recv_cq);
2852 3710
2853 hns_roce_lock_cqs(send_cq, recv_cq); 3711 hns_roce_lock_cqs(send_cq, recv_cq);
2854
2855 if (!is_user) { 3712 if (!is_user) {
2856 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ? 3713 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn, hr_qp->ibqp.srq ?
2857 to_hr_srq(hr_qp->ibqp.srq) : NULL); 3714 to_hr_srq(hr_qp->ibqp.srq) : NULL);
2858 if (send_cq != recv_cq) 3715 if (send_cq != recv_cq)
2859 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL); 3716 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
2860 } 3717 }
2861
2862 hns_roce_qp_remove(hr_dev, hr_qp);
2863
2864 hns_roce_unlock_cqs(send_cq, recv_cq); 3718 hns_roce_unlock_cqs(send_cq, recv_cq);
2865 3719
2866 hns_roce_qp_free(hr_dev, hr_qp); 3720 if (!is_timeout) {
3721 hns_roce_qp_remove(hr_dev, hr_qp);
3722 hns_roce_qp_free(hr_dev, hr_qp);
2867 3723
2868 /* Not special_QP, free their QPN */ 3724 /* RC QP, release QPN */
2869 if ((hr_qp->ibqp.qp_type == IB_QPT_RC) || 3725 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
2870 (hr_qp->ibqp.qp_type == IB_QPT_UC) || 3726 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
2871 (hr_qp->ibqp.qp_type == IB_QPT_UD)) 3727 }
2872 hns_roce_release_range_qp(hr_dev, hr_qp->qpn, 1);
2873 3728
2874 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt); 3729 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
2875 3730
2876 if (is_user) { 3731 if (is_user)
2877 ib_umem_release(hr_qp->umem); 3732 ib_umem_release(hr_qp->umem);
2878 } else { 3733 else {
2879 kfree(hr_qp->sq.wrid); 3734 kfree(hr_qp->sq.wrid);
2880 kfree(hr_qp->rq.wrid); 3735 kfree(hr_qp->rq.wrid);
3736
2881 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf); 3737 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
2882 } 3738 }
3739
3740 if (!is_timeout) {
3741 if (hr_qp->ibqp.qp_type == IB_QPT_RC)
3742 kfree(hr_qp);
3743 else
3744 kfree(hr_to_hr_sqp(hr_qp));
3745 } else {
3746 qp_work = kzalloc(sizeof(*qp_work), GFP_KERNEL);
3747 if (!qp_work)
3748 return -ENOMEM;
3749
3750 INIT_WORK(&qp_work->work, hns_roce_v1_destroy_qp_work_fn);
3751 qp_work->ib_dev = &hr_dev->ib_dev;
3752 qp_work->qp = hr_qp;
3753 qp_work->db_wait_stage = qp_work_entry.db_wait_stage;
3754 qp_work->sdb_issue_ptr = qp_work_entry.sdb_issue_ptr;
3755 qp_work->sdb_inv_cnt = qp_work_entry.sdb_inv_cnt;
3756 qp_work->sche_cnt = qp_work_entry.sche_cnt;
3757
3758 priv = (struct hns_roce_v1_priv *)hr_dev->hw->priv;
3759 queue_work(priv->des_qp.qp_wq, &qp_work->work);
3760 dev_dbg(dev, "Begin destroy QP(0x%lx) work.\n", hr_qp->qpn);
3761 }
3762
3763 return 0;
2883} 3764}
2884 3765
2885int hns_roce_v1_destroy_qp(struct ib_qp *ibqp) 3766int hns_roce_v1_destroy_cq(struct ib_cq *ibcq)
2886{ 3767{
2887 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 3768 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
2888 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 3769 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3770 struct device *dev = &hr_dev->pdev->dev;
3771 u32 cqe_cnt_ori;
3772 u32 cqe_cnt_cur;
3773 u32 cq_buf_size;
3774 int wait_time = 0;
3775 int ret = 0;
2889 3776
2890 hns_roce_v1_destroy_qp_common(hr_dev, hr_qp, !!ibqp->pd->uobject); 3777 hns_roce_free_cq(hr_dev, hr_cq);
2891 3778
2892 if (hr_qp->ibqp.qp_type == IB_QPT_GSI) 3779 /*
2893 kfree(hr_to_hr_sqp(hr_qp)); 3780 * Before freeing cq buffer, we need to ensure that the outstanding CQE
2894 else 3781 * have been written by checking the CQE counter.
2895 kfree(hr_qp); 3782 */
3783 cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3784 while (1) {
3785 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3786 HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3787 break;
2896 3788
2897 return 0; 3789 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3790 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3791 break;
3792
3793 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3794 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3795 dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3796 hr_cq->cqn);
3797 ret = -ETIMEDOUT;
3798 break;
3799 }
3800 wait_time++;
3801 }
3802
3803 hns_roce_mtt_cleanup(hr_dev, &hr_cq->hr_buf.hr_mtt);
3804
3805 if (ibcq->uobject)
3806 ib_umem_release(hr_cq->umem);
3807 else {
3808 /* Free the buff of stored cq */
3809 cq_buf_size = (ibcq->cqe + 1) * hr_dev->caps.cq_entry_sz;
3810 hns_roce_buf_free(hr_dev, cq_buf_size, &hr_cq->hr_buf.hr_buf);
3811 }
3812
3813 kfree(hr_cq);
3814
3815 return ret;
2898} 3816}
2899 3817
2900struct hns_roce_v1_priv hr_v1_priv; 3818struct hns_roce_v1_priv hr_v1_priv;
@@ -2917,5 +3835,7 @@ struct hns_roce_hw hns_roce_hw_v1 = {
2917 .post_recv = hns_roce_v1_post_recv, 3835 .post_recv = hns_roce_v1_post_recv,
2918 .req_notify_cq = hns_roce_v1_req_notify_cq, 3836 .req_notify_cq = hns_roce_v1_req_notify_cq,
2919 .poll_cq = hns_roce_v1_poll_cq, 3837 .poll_cq = hns_roce_v1_poll_cq,
3838 .dereg_mr = hns_roce_v1_dereg_mr,
3839 .destroy_cq = hns_roce_v1_destroy_cq,
2920 .priv = &hr_v1_priv, 3840 .priv = &hr_v1_priv,
2921}; 3841};
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.h b/drivers/infiniband/hw/hns/hns_roce_hw_v1.h
index 539b0a3b92b0..b213b5e6fef1 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.h
@@ -58,6 +58,7 @@
58#define HNS_ROCE_V1_PHY_UAR_NUM 8 58#define HNS_ROCE_V1_PHY_UAR_NUM 8
59 59
60#define HNS_ROCE_V1_GID_NUM 16 60#define HNS_ROCE_V1_GID_NUM 16
61#define HNS_ROCE_V1_RESV_QP 8
61 62
62#define HNS_ROCE_V1_NUM_COMP_EQE 0x8000 63#define HNS_ROCE_V1_NUM_COMP_EQE 0x8000
63#define HNS_ROCE_V1_NUM_ASYNC_EQE 0x400 64#define HNS_ROCE_V1_NUM_ASYNC_EQE 0x400
@@ -102,8 +103,22 @@
102#define HNS_ROCE_V1_EXT_ODB_ALFUL \ 103#define HNS_ROCE_V1_EXT_ODB_ALFUL \
103 (HNS_ROCE_V1_EXT_ODB_DEPTH - HNS_ROCE_V1_DB_RSVD) 104 (HNS_ROCE_V1_EXT_ODB_DEPTH - HNS_ROCE_V1_DB_RSVD)
104 105
106#define HNS_ROCE_V1_DB_WAIT_OK 0
107#define HNS_ROCE_V1_DB_STAGE1 1
108#define HNS_ROCE_V1_DB_STAGE2 2
109#define HNS_ROCE_V1_CHECK_DB_TIMEOUT_MSECS 10000
110#define HNS_ROCE_V1_CHECK_DB_SLEEP_MSECS 20
111#define HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS 50000
112#define HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS 10000
113#define HNS_ROCE_V1_FREE_MR_WAIT_VALUE 5
114#define HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE 20
115
105#define HNS_ROCE_BT_RSV_BUF_SIZE (1 << 17) 116#define HNS_ROCE_BT_RSV_BUF_SIZE (1 << 17)
106 117
118#define HNS_ROCE_V1_TPTR_ENTRY_SIZE 2
119#define HNS_ROCE_V1_TPTR_BUF_SIZE \
120 (HNS_ROCE_V1_TPTR_ENTRY_SIZE * HNS_ROCE_V1_MAX_CQ_NUM)
121
107#define HNS_ROCE_ODB_POLL_MODE 0 122#define HNS_ROCE_ODB_POLL_MODE 0
108 123
109#define HNS_ROCE_SDB_NORMAL_MODE 0 124#define HNS_ROCE_SDB_NORMAL_MODE 0
@@ -140,6 +155,7 @@
140#define SQ_PSN_SHIFT 8 155#define SQ_PSN_SHIFT 8
141#define QKEY_VAL 0x80010000 156#define QKEY_VAL 0x80010000
142#define SDB_INV_CNT_OFFSET 8 157#define SDB_INV_CNT_OFFSET 8
158#define SDB_ST_CMP_VAL 8
143 159
144struct hns_roce_cq_context { 160struct hns_roce_cq_context {
145 u32 cqc_byte_4; 161 u32 cqc_byte_4;
@@ -436,6 +452,8 @@ struct hns_roce_ud_send_wqe {
436#define UD_SEND_WQE_U32_8_DMAC_5_M \ 452#define UD_SEND_WQE_U32_8_DMAC_5_M \
437 (((1UL << 8) - 1) << UD_SEND_WQE_U32_8_DMAC_5_S) 453 (((1UL << 8) - 1) << UD_SEND_WQE_U32_8_DMAC_5_S)
438 454
455#define UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S 22
456
439#define UD_SEND_WQE_U32_8_OPERATION_TYPE_S 16 457#define UD_SEND_WQE_U32_8_OPERATION_TYPE_S 16
440#define UD_SEND_WQE_U32_8_OPERATION_TYPE_M \ 458#define UD_SEND_WQE_U32_8_OPERATION_TYPE_M \
441 (((1UL << 4) - 1) << UD_SEND_WQE_U32_8_OPERATION_TYPE_S) 459 (((1UL << 4) - 1) << UD_SEND_WQE_U32_8_OPERATION_TYPE_S)
@@ -480,13 +498,17 @@ struct hns_roce_sqp_context {
480 u32 qp1c_bytes_12; 498 u32 qp1c_bytes_12;
481 u32 qp1c_bytes_16; 499 u32 qp1c_bytes_16;
482 u32 qp1c_bytes_20; 500 u32 qp1c_bytes_20;
483 u32 qp1c_bytes_28;
484 u32 cur_rq_wqe_ba_l; 501 u32 cur_rq_wqe_ba_l;
502 u32 qp1c_bytes_28;
485 u32 qp1c_bytes_32; 503 u32 qp1c_bytes_32;
486 u32 cur_sq_wqe_ba_l; 504 u32 cur_sq_wqe_ba_l;
487 u32 qp1c_bytes_40; 505 u32 qp1c_bytes_40;
488}; 506};
489 507
508#define QP1C_BYTES_4_QP_STATE_S 0
509#define QP1C_BYTES_4_QP_STATE_M \
510 (((1UL << 3) - 1) << QP1C_BYTES_4_QP_STATE_S)
511
490#define QP1C_BYTES_4_SQ_WQE_SHIFT_S 8 512#define QP1C_BYTES_4_SQ_WQE_SHIFT_S 8
491#define QP1C_BYTES_4_SQ_WQE_SHIFT_M \ 513#define QP1C_BYTES_4_SQ_WQE_SHIFT_M \
492 (((1UL << 4) - 1) << QP1C_BYTES_4_SQ_WQE_SHIFT_S) 514 (((1UL << 4) - 1) << QP1C_BYTES_4_SQ_WQE_SHIFT_S)
@@ -952,6 +974,10 @@ struct hns_roce_sq_db {
952#define SQ_DOORBELL_U32_4_SQ_HEAD_M \ 974#define SQ_DOORBELL_U32_4_SQ_HEAD_M \
953 (((1UL << 15) - 1) << SQ_DOORBELL_U32_4_SQ_HEAD_S) 975 (((1UL << 15) - 1) << SQ_DOORBELL_U32_4_SQ_HEAD_S)
954 976
977#define SQ_DOORBELL_U32_4_SL_S 16
978#define SQ_DOORBELL_U32_4_SL_M \
979 (((1UL << 2) - 1) << SQ_DOORBELL_U32_4_SL_S)
980
955#define SQ_DOORBELL_U32_4_PORT_S 18 981#define SQ_DOORBELL_U32_4_PORT_S 18
956#define SQ_DOORBELL_U32_4_PORT_M (((1UL << 3) - 1) << SQ_DOORBELL_U32_4_PORT_S) 982#define SQ_DOORBELL_U32_4_PORT_M (((1UL << 3) - 1) << SQ_DOORBELL_U32_4_PORT_S)
957 983
@@ -979,12 +1005,58 @@ struct hns_roce_bt_table {
979 struct hns_roce_buf_list cqc_buf; 1005 struct hns_roce_buf_list cqc_buf;
980}; 1006};
981 1007
1008struct hns_roce_tptr_table {
1009 struct hns_roce_buf_list tptr_buf;
1010};
1011
1012struct hns_roce_qp_work {
1013 struct work_struct work;
1014 struct ib_device *ib_dev;
1015 struct hns_roce_qp *qp;
1016 u32 db_wait_stage;
1017 u32 sdb_issue_ptr;
1018 u32 sdb_inv_cnt;
1019 u32 sche_cnt;
1020};
1021
1022struct hns_roce_des_qp {
1023 struct workqueue_struct *qp_wq;
1024 int requeue_flag;
1025};
1026
1027struct hns_roce_mr_free_work {
1028 struct work_struct work;
1029 struct ib_device *ib_dev;
1030 struct completion *comp;
1031 int comp_flag;
1032 void *mr;
1033};
1034
1035struct hns_roce_recreate_lp_qp_work {
1036 struct work_struct work;
1037 struct ib_device *ib_dev;
1038 struct completion *comp;
1039 int comp_flag;
1040};
1041
1042struct hns_roce_free_mr {
1043 struct workqueue_struct *free_mr_wq;
1044 struct hns_roce_qp *mr_free_qp[HNS_ROCE_V1_RESV_QP];
1045 struct hns_roce_cq *mr_free_cq;
1046 struct hns_roce_pd *mr_free_pd;
1047};
1048
982struct hns_roce_v1_priv { 1049struct hns_roce_v1_priv {
983 struct hns_roce_db_table db_table; 1050 struct hns_roce_db_table db_table;
984 struct hns_roce_raq_table raq_table; 1051 struct hns_roce_raq_table raq_table;
985 struct hns_roce_bt_table bt_table; 1052 struct hns_roce_bt_table bt_table;
1053 struct hns_roce_tptr_table tptr_table;
1054 struct hns_roce_des_qp des_qp;
1055 struct hns_roce_free_mr free_mr;
986}; 1056};
987 1057
988int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset); 1058int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset);
1059int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1060int hns_roce_v1_destroy_qp(struct ib_qp *ibqp);
989 1061
990#endif 1062#endif
diff --git a/drivers/infiniband/hw/hns/hns_roce_main.c b/drivers/infiniband/hw/hns/hns_roce_main.c
index 764e35a54457..4953d9cb83a7 100644
--- a/drivers/infiniband/hw/hns/hns_roce_main.c
+++ b/drivers/infiniband/hw/hns/hns_roce_main.c
@@ -35,52 +35,13 @@
35#include <rdma/ib_addr.h> 35#include <rdma/ib_addr.h>
36#include <rdma/ib_smi.h> 36#include <rdma/ib_smi.h>
37#include <rdma/ib_user_verbs.h> 37#include <rdma/ib_user_verbs.h>
38#include <rdma/ib_cache.h>
38#include "hns_roce_common.h" 39#include "hns_roce_common.h"
39#include "hns_roce_device.h" 40#include "hns_roce_device.h"
40#include "hns_roce_user.h" 41#include <rdma/hns-abi.h>
41#include "hns_roce_hem.h" 42#include "hns_roce_hem.h"
42 43
43/** 44/**
44 * hns_roce_addrconf_ifid_eui48 - Get default gid.
45 * @eui: eui.
46 * @vlan_id: gid
47 * @dev: net device
48 * Description:
49 * MAC convert to GID
50 * gid[0..7] = fe80 0000 0000 0000
51 * gid[8] = mac[0] ^ 2
52 * gid[9] = mac[1]
53 * gid[10] = mac[2]
54 * gid[11] = ff (VLAN ID high byte (4 MS bits))
55 * gid[12] = fe (VLAN ID low byte)
56 * gid[13] = mac[3]
57 * gid[14] = mac[4]
58 * gid[15] = mac[5]
59 */
60static void hns_roce_addrconf_ifid_eui48(u8 *eui, u16 vlan_id,
61 struct net_device *dev)
62{
63 memcpy(eui, dev->dev_addr, 3);
64 memcpy(eui + 5, dev->dev_addr + 3, 3);
65 if (vlan_id < 0x1000) {
66 eui[3] = vlan_id >> 8;
67 eui[4] = vlan_id & 0xff;
68 } else {
69 eui[3] = 0xff;
70 eui[4] = 0xfe;
71 }
72 eui[0] ^= 2;
73}
74
75static void hns_roce_make_default_gid(struct net_device *dev, union ib_gid *gid)
76{
77 memset(gid, 0, sizeof(*gid));
78 gid->raw[0] = 0xFE;
79 gid->raw[1] = 0x80;
80 hns_roce_addrconf_ifid_eui48(&gid->raw[8], 0xffff, dev);
81}
82
83/**
84 * hns_get_gid_index - Get gid index. 45 * hns_get_gid_index - Get gid index.
85 * @hr_dev: pointer to structure hns_roce_dev. 46 * @hr_dev: pointer to structure hns_roce_dev.
86 * @port: port, value range: 0 ~ MAX 47 * @port: port, value range: 0 ~ MAX
@@ -96,30 +57,6 @@ int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
96 return gid_index * hr_dev->caps.num_ports + port; 57 return gid_index * hr_dev->caps.num_ports + port;
97} 58}
98 59
99static int hns_roce_set_gid(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
100 union ib_gid *gid)
101{
102 struct device *dev = &hr_dev->pdev->dev;
103 u8 gid_idx = 0;
104
105 if (gid_index >= hr_dev->caps.gid_table_len[port]) {
106 dev_err(dev, "gid_index %d illegal, port %d gid range: 0~%d\n",
107 gid_index, port, hr_dev->caps.gid_table_len[port] - 1);
108 return -EINVAL;
109 }
110
111 gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
112
113 if (!memcmp(gid, &hr_dev->iboe.gid_table[gid_idx], sizeof(*gid)))
114 return -EINVAL;
115
116 memcpy(&hr_dev->iboe.gid_table[gid_idx], gid, sizeof(*gid));
117
118 hr_dev->hw->set_gid(hr_dev, port, gid_index, gid);
119
120 return 0;
121}
122
123static void hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr) 60static void hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
124{ 61{
125 u8 phy_port; 62 u8 phy_port;
@@ -135,27 +72,44 @@ static void hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
135 hr_dev->hw->set_mac(hr_dev, phy_port, addr); 72 hr_dev->hw->set_mac(hr_dev, phy_port, addr);
136} 73}
137 74
138static void hns_roce_set_mtu(struct hns_roce_dev *hr_dev, u8 port, int mtu) 75static int hns_roce_add_gid(struct ib_device *device, u8 port_num,
76 unsigned int index, const union ib_gid *gid,
77 const struct ib_gid_attr *attr, void **context)
139{ 78{
140 u8 phy_port = hr_dev->iboe.phy_port[port]; 79 struct hns_roce_dev *hr_dev = to_hr_dev(device);
141 enum ib_mtu tmp; 80 u8 port = port_num - 1;
81 unsigned long flags;
82
83 if (port >= hr_dev->caps.num_ports)
84 return -EINVAL;
85
86 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
142 87
143 tmp = iboe_get_mtu(mtu); 88 hr_dev->hw->set_gid(hr_dev, port, index, (union ib_gid *)gid);
144 if (!tmp)
145 tmp = IB_MTU_256;
146 89
147 hr_dev->hw->set_mtu(hr_dev, phy_port, tmp); 90 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
91
92 return 0;
148} 93}
149 94
150static void hns_roce_update_gids(struct hns_roce_dev *hr_dev, int port) 95static int hns_roce_del_gid(struct ib_device *device, u8 port_num,
96 unsigned int index, void **context)
151{ 97{
152 struct ib_event event; 98 struct hns_roce_dev *hr_dev = to_hr_dev(device);
99 union ib_gid zgid = { {0} };
100 u8 port = port_num - 1;
101 unsigned long flags;
102
103 if (port >= hr_dev->caps.num_ports)
104 return -EINVAL;
105
106 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
153 107
154 /* Refresh gid in ib_cache */ 108 hr_dev->hw->set_gid(hr_dev, port, index, &zgid);
155 event.device = &hr_dev->ib_dev; 109
156 event.element.port_num = port + 1; 110 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
157 event.event = IB_EVENT_GID_CHANGE; 111
158 ib_dispatch_event(&event); 112 return 0;
159} 113}
160 114
161static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port, 115static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
@@ -163,9 +117,6 @@ static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
163{ 117{
164 struct device *dev = &hr_dev->pdev->dev; 118 struct device *dev = &hr_dev->pdev->dev;
165 struct net_device *netdev; 119 struct net_device *netdev;
166 unsigned long flags;
167 union ib_gid gid;
168 int ret = 0;
169 120
170 netdev = hr_dev->iboe.netdevs[port]; 121 netdev = hr_dev->iboe.netdevs[port];
171 if (!netdev) { 122 if (!netdev) {
@@ -173,7 +124,7 @@ static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
173 return -ENODEV; 124 return -ENODEV;
174 } 125 }
175 126
176 spin_lock_irqsave(&hr_dev->iboe.lock, flags); 127 spin_lock_bh(&hr_dev->iboe.lock);
177 128
178 switch (event) { 129 switch (event) {
179 case NETDEV_UP: 130 case NETDEV_UP:
@@ -181,23 +132,19 @@ static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
181 case NETDEV_REGISTER: 132 case NETDEV_REGISTER:
182 case NETDEV_CHANGEADDR: 133 case NETDEV_CHANGEADDR:
183 hns_roce_set_mac(hr_dev, port, netdev->dev_addr); 134 hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
184 hns_roce_make_default_gid(netdev, &gid);
185 ret = hns_roce_set_gid(hr_dev, port, 0, &gid);
186 if (!ret)
187 hns_roce_update_gids(hr_dev, port);
188 break; 135 break;
189 case NETDEV_DOWN: 136 case NETDEV_DOWN:
190 /* 137 /*
191 * In v1 engine, only support all ports closed together. 138 * In v1 engine, only support all ports closed together.
192 */ 139 */
193 break; 140 break;
194 default: 141 default:
195 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); 142 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
196 break; 143 break;
197 } 144 }
198 145
199 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags); 146 spin_unlock_bh(&hr_dev->iboe.lock);
200 return ret; 147 return 0;
201} 148}
202 149
203static int hns_roce_netdev_event(struct notifier_block *self, 150static int hns_roce_netdev_event(struct notifier_block *self,
@@ -224,118 +171,17 @@ static int hns_roce_netdev_event(struct notifier_block *self,
224 return NOTIFY_DONE; 171 return NOTIFY_DONE;
225} 172}
226 173
227static void hns_roce_addr_event(int event, struct net_device *event_netdev, 174static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
228 struct hns_roce_dev *hr_dev, union ib_gid *gid)
229{ 175{
230 struct hns_roce_ib_iboe *iboe = NULL; 176 u8 i;
231 int gid_table_len = 0;
232 unsigned long flags;
233 union ib_gid zgid;
234 u8 gid_idx = 0;
235 u8 port = 0;
236 int i = 0;
237 int free;
238 struct net_device *real_dev = rdma_vlan_dev_real_dev(event_netdev) ?
239 rdma_vlan_dev_real_dev(event_netdev) :
240 event_netdev;
241
242 if (event != NETDEV_UP && event != NETDEV_DOWN)
243 return;
244
245 iboe = &hr_dev->iboe;
246 while (port < hr_dev->caps.num_ports) {
247 if (real_dev == iboe->netdevs[port])
248 break;
249 port++;
250 }
251
252 if (port >= hr_dev->caps.num_ports) {
253 dev_dbg(&hr_dev->pdev->dev, "can't find netdev\n");
254 return;
255 }
256
257 memset(zgid.raw, 0, sizeof(zgid.raw));
258 free = -1;
259 gid_table_len = hr_dev->caps.gid_table_len[port];
260
261 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
262
263 for (i = 0; i < gid_table_len; i++) {
264 gid_idx = hns_get_gid_index(hr_dev, port, i);
265 if (!memcmp(gid->raw, iboe->gid_table[gid_idx].raw,
266 sizeof(gid->raw)))
267 break;
268 if (free < 0 && !memcmp(zgid.raw,
269 iboe->gid_table[gid_idx].raw, sizeof(zgid.raw)))
270 free = i;
271 }
272
273 if (i >= gid_table_len) {
274 if (free < 0) {
275 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
276 dev_dbg(&hr_dev->pdev->dev,
277 "gid_index overflow, port(%d)\n", port);
278 return;
279 }
280 if (!hns_roce_set_gid(hr_dev, port, free, gid))
281 hns_roce_update_gids(hr_dev, port);
282 } else if (event == NETDEV_DOWN) {
283 if (!hns_roce_set_gid(hr_dev, port, i, &zgid))
284 hns_roce_update_gids(hr_dev, port);
285 }
286
287 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
288}
289
290static int hns_roce_inet_event(struct notifier_block *self, unsigned long event,
291 void *ptr)
292{
293 struct in_ifaddr *ifa = ptr;
294 struct hns_roce_dev *hr_dev;
295 struct net_device *dev = ifa->ifa_dev->dev;
296 union ib_gid gid;
297
298 ipv6_addr_set_v4mapped(ifa->ifa_address, (struct in6_addr *)&gid);
299
300 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb_inet);
301
302 hns_roce_addr_event(event, dev, hr_dev, &gid);
303
304 return NOTIFY_DONE;
305}
306
307static int hns_roce_setup_mtu_gids(struct hns_roce_dev *hr_dev)
308{
309 struct in_ifaddr *ifa_list = NULL;
310 union ib_gid gid = {{0} };
311 u32 ipaddr = 0;
312 int index = 0;
313 int ret = 0;
314 u8 i = 0;
315 177
316 for (i = 0; i < hr_dev->caps.num_ports; i++) { 178 for (i = 0; i < hr_dev->caps.num_ports; i++) {
317 hns_roce_set_mtu(hr_dev, i, 179 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
318 ib_mtu_enum_to_int(hr_dev->caps.max_mtu)); 180 hr_dev->caps.max_mtu);
319 hns_roce_set_mac(hr_dev, i, hr_dev->iboe.netdevs[i]->dev_addr); 181 hns_roce_set_mac(hr_dev, i, hr_dev->iboe.netdevs[i]->dev_addr);
320
321 if (hr_dev->iboe.netdevs[i]->ip_ptr) {
322 ifa_list = hr_dev->iboe.netdevs[i]->ip_ptr->ifa_list;
323 index = 1;
324 while (ifa_list) {
325 ipaddr = ifa_list->ifa_address;
326 ipv6_addr_set_v4mapped(ipaddr,
327 (struct in6_addr *)&gid);
328 ret = hns_roce_set_gid(hr_dev, i, index, &gid);
329 if (ret)
330 break;
331 index++;
332 ifa_list = ifa_list->ifa_next;
333 }
334 hns_roce_update_gids(hr_dev, i);
335 }
336 } 182 }
337 183
338 return ret; 184 return 0;
339} 185}
340 186
341static int hns_roce_query_device(struct ib_device *ib_dev, 187static int hns_roce_query_device(struct ib_device *ib_dev,
@@ -444,31 +290,6 @@ static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
444static int hns_roce_query_gid(struct ib_device *ib_dev, u8 port_num, int index, 290static int hns_roce_query_gid(struct ib_device *ib_dev, u8 port_num, int index,
445 union ib_gid *gid) 291 union ib_gid *gid)
446{ 292{
447 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
448 struct device *dev = &hr_dev->pdev->dev;
449 u8 gid_idx = 0;
450 u8 port;
451
452 if (port_num < 1 || port_num > hr_dev->caps.num_ports ||
453 index >= hr_dev->caps.gid_table_len[port_num - 1]) {
454 dev_err(dev,
455 "port_num %d index %d illegal! correct range: port_num 1~%d index 0~%d!\n",
456 port_num, index, hr_dev->caps.num_ports,
457 hr_dev->caps.gid_table_len[port_num - 1] - 1);
458 return -EINVAL;
459 }
460
461 port = port_num - 1;
462 gid_idx = hns_get_gid_index(hr_dev, port, index);
463 if (gid_idx >= HNS_ROCE_MAX_GID_NUM) {
464 dev_err(dev, "port_num %d index %d illegal! total gid num %d!\n",
465 port_num, index, HNS_ROCE_MAX_GID_NUM);
466 return -EINVAL;
467 }
468
469 memcpy(gid->raw, hr_dev->iboe.gid_table[gid_idx].raw,
470 HNS_ROCE_GID_SIZE);
471
472 return 0; 293 return 0;
473} 294}
474 295
@@ -549,6 +370,8 @@ static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
549static int hns_roce_mmap(struct ib_ucontext *context, 370static int hns_roce_mmap(struct ib_ucontext *context,
550 struct vm_area_struct *vma) 371 struct vm_area_struct *vma)
551{ 372{
373 struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
374
552 if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0) 375 if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0)
553 return -EINVAL; 376 return -EINVAL;
554 377
@@ -558,10 +381,15 @@ static int hns_roce_mmap(struct ib_ucontext *context,
558 to_hr_ucontext(context)->uar.pfn, 381 to_hr_ucontext(context)->uar.pfn,
559 PAGE_SIZE, vma->vm_page_prot)) 382 PAGE_SIZE, vma->vm_page_prot))
560 return -EAGAIN; 383 return -EAGAIN;
561 384 } else if (vma->vm_pgoff == 1 && hr_dev->hw_rev == HNS_ROCE_HW_VER1) {
562 } else { 385 /* vm_pgoff: 1 -- TPTR */
386 if (io_remap_pfn_range(vma, vma->vm_start,
387 hr_dev->tptr_dma_addr >> PAGE_SHIFT,
388 hr_dev->tptr_size,
389 vma->vm_page_prot))
390 return -EAGAIN;
391 } else
563 return -EINVAL; 392 return -EINVAL;
564 }
565 393
566 return 0; 394 return 0;
567} 395}
@@ -605,7 +433,7 @@ static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
605 spin_lock_init(&iboe->lock); 433 spin_lock_init(&iboe->lock);
606 434
607 ib_dev = &hr_dev->ib_dev; 435 ib_dev = &hr_dev->ib_dev;
608 strlcpy(ib_dev->name, "hisi_%d", IB_DEVICE_NAME_MAX); 436 strlcpy(ib_dev->name, "hns_%d", IB_DEVICE_NAME_MAX);
609 437
610 ib_dev->owner = THIS_MODULE; 438 ib_dev->owner = THIS_MODULE;
611 ib_dev->node_type = RDMA_NODE_IB_CA; 439 ib_dev->node_type = RDMA_NODE_IB_CA;
@@ -639,6 +467,8 @@ static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
639 ib_dev->get_link_layer = hns_roce_get_link_layer; 467 ib_dev->get_link_layer = hns_roce_get_link_layer;
640 ib_dev->get_netdev = hns_roce_get_netdev; 468 ib_dev->get_netdev = hns_roce_get_netdev;
641 ib_dev->query_gid = hns_roce_query_gid; 469 ib_dev->query_gid = hns_roce_query_gid;
470 ib_dev->add_gid = hns_roce_add_gid;
471 ib_dev->del_gid = hns_roce_del_gid;
642 ib_dev->query_pkey = hns_roce_query_pkey; 472 ib_dev->query_pkey = hns_roce_query_pkey;
643 ib_dev->alloc_ucontext = hns_roce_alloc_ucontext; 473 ib_dev->alloc_ucontext = hns_roce_alloc_ucontext;
644 ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext; 474 ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext;
@@ -681,32 +511,22 @@ static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
681 return ret; 511 return ret;
682 } 512 }
683 513
684 ret = hns_roce_setup_mtu_gids(hr_dev); 514 ret = hns_roce_setup_mtu_mac(hr_dev);
685 if (ret) { 515 if (ret) {
686 dev_err(dev, "roce_setup_mtu_gids failed!\n"); 516 dev_err(dev, "setup_mtu_mac failed!\n");
687 goto error_failed_setup_mtu_gids; 517 goto error_failed_setup_mtu_mac;
688 } 518 }
689 519
690 iboe->nb.notifier_call = hns_roce_netdev_event; 520 iboe->nb.notifier_call = hns_roce_netdev_event;
691 ret = register_netdevice_notifier(&iboe->nb); 521 ret = register_netdevice_notifier(&iboe->nb);
692 if (ret) { 522 if (ret) {
693 dev_err(dev, "register_netdevice_notifier failed!\n"); 523 dev_err(dev, "register_netdevice_notifier failed!\n");
694 goto error_failed_setup_mtu_gids; 524 goto error_failed_setup_mtu_mac;
695 }
696
697 iboe->nb_inet.notifier_call = hns_roce_inet_event;
698 ret = register_inetaddr_notifier(&iboe->nb_inet);
699 if (ret) {
700 dev_err(dev, "register inet addr notifier failed!\n");
701 goto error_failed_register_inetaddr_notifier;
702 } 525 }
703 526
704 return 0; 527 return 0;
705 528
706error_failed_register_inetaddr_notifier: 529error_failed_setup_mtu_mac:
707 unregister_netdevice_notifier(&iboe->nb);
708
709error_failed_setup_mtu_gids:
710 ib_unregister_device(ib_dev); 530 ib_unregister_device(ib_dev);
711 531
712 return ret; 532 return ret;
@@ -940,10 +760,10 @@ err_unmap_mtt:
940} 760}
941 761
942/** 762/**
943* hns_roce_setup_hca - setup host channel adapter 763 * hns_roce_setup_hca - setup host channel adapter
944* @hr_dev: pointer to hns roce device 764 * @hr_dev: pointer to hns roce device
945* Return : int 765 * Return : int
946*/ 766 */
947static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) 767static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
948{ 768{
949 int ret; 769 int ret;
@@ -1008,11 +828,11 @@ err_uar_table_free:
1008} 828}
1009 829
1010/** 830/**
1011* hns_roce_probe - RoCE driver entrance 831 * hns_roce_probe - RoCE driver entrance
1012* @pdev: pointer to platform device 832 * @pdev: pointer to platform device
1013* Return : int 833 * Return : int
1014* 834 *
1015*/ 835 */
1016static int hns_roce_probe(struct platform_device *pdev) 836static int hns_roce_probe(struct platform_device *pdev)
1017{ 837{
1018 int ret; 838 int ret;
@@ -1023,9 +843,6 @@ static int hns_roce_probe(struct platform_device *pdev)
1023 if (!hr_dev) 843 if (!hr_dev)
1024 return -ENOMEM; 844 return -ENOMEM;
1025 845
1026 memset((u8 *)hr_dev + sizeof(struct ib_device), 0,
1027 sizeof(struct hns_roce_dev) - sizeof(struct ib_device));
1028
1029 hr_dev->pdev = pdev; 846 hr_dev->pdev = pdev;
1030 platform_set_drvdata(pdev, hr_dev); 847 platform_set_drvdata(pdev, hr_dev);
1031 848
@@ -1125,9 +942,9 @@ error_failed_get_cfg:
1125} 942}
1126 943
1127/** 944/**
1128* hns_roce_remove - remove RoCE device 945 * hns_roce_remove - remove RoCE device
1129* @pdev: pointer to platform device 946 * @pdev: pointer to platform device
1130*/ 947 */
1131static int hns_roce_remove(struct platform_device *pdev) 948static int hns_roce_remove(struct platform_device *pdev)
1132{ 949{
1133 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev); 950 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
diff --git a/drivers/infiniband/hw/hns/hns_roce_mr.c b/drivers/infiniband/hw/hns/hns_roce_mr.c
index fb87883ead34..4139abee3b54 100644
--- a/drivers/infiniband/hw/hns/hns_roce_mr.c
+++ b/drivers/infiniband/hw/hns/hns_roce_mr.c
@@ -42,7 +42,7 @@ static u32 hw_index_to_key(unsigned long ind)
42 return (u32)(ind >> 24) | (ind << 8); 42 return (u32)(ind >> 24) | (ind << 8);
43} 43}
44 44
45static unsigned long key_to_hw_index(u32 key) 45unsigned long key_to_hw_index(u32 key)
46{ 46{
47 return (key << 24) | (key >> 8); 47 return (key << 24) | (key >> 8);
48} 48}
@@ -53,16 +53,16 @@ static int hns_roce_sw2hw_mpt(struct hns_roce_dev *hr_dev,
53{ 53{
54 return hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, mpt_index, 0, 54 return hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, mpt_index, 0,
55 HNS_ROCE_CMD_SW2HW_MPT, 55 HNS_ROCE_CMD_SW2HW_MPT,
56 HNS_ROCE_CMD_TIME_CLASS_B); 56 HNS_ROCE_CMD_TIMEOUT_MSECS);
57} 57}
58 58
59static int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev, 59int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
60 struct hns_roce_cmd_mailbox *mailbox, 60 struct hns_roce_cmd_mailbox *mailbox,
61 unsigned long mpt_index) 61 unsigned long mpt_index)
62{ 62{
63 return hns_roce_cmd_mbox(hr_dev, 0, mailbox ? mailbox->dma : 0, 63 return hns_roce_cmd_mbox(hr_dev, 0, mailbox ? mailbox->dma : 0,
64 mpt_index, !mailbox, HNS_ROCE_CMD_HW2SW_MPT, 64 mpt_index, !mailbox, HNS_ROCE_CMD_HW2SW_MPT,
65 HNS_ROCE_CMD_TIME_CLASS_B); 65 HNS_ROCE_CMD_TIMEOUT_MSECS);
66} 66}
67 67
68static int hns_roce_buddy_alloc(struct hns_roce_buddy *buddy, int order, 68static int hns_roce_buddy_alloc(struct hns_roce_buddy *buddy, int order,
@@ -137,11 +137,13 @@ static int hns_roce_buddy_init(struct hns_roce_buddy *buddy, int max_order)
137 137
138 for (i = 0; i <= buddy->max_order; ++i) { 138 for (i = 0; i <= buddy->max_order; ++i) {
139 s = BITS_TO_LONGS(1 << (buddy->max_order - i)); 139 s = BITS_TO_LONGS(1 << (buddy->max_order - i));
140 buddy->bits[i] = kmalloc_array(s, sizeof(long), GFP_KERNEL); 140 buddy->bits[i] = kcalloc(s, sizeof(long), GFP_KERNEL |
141 if (!buddy->bits[i]) 141 __GFP_NOWARN);
142 goto err_out_free; 142 if (!buddy->bits[i]) {
143 143 buddy->bits[i] = vzalloc(s * sizeof(long));
144 bitmap_zero(buddy->bits[i], 1 << (buddy->max_order - i)); 144 if (!buddy->bits[i])
145 goto err_out_free;
146 }
145 } 147 }
146 148
147 set_bit(0, buddy->bits[buddy->max_order]); 149 set_bit(0, buddy->bits[buddy->max_order]);
@@ -151,7 +153,7 @@ static int hns_roce_buddy_init(struct hns_roce_buddy *buddy, int max_order)
151 153
152err_out_free: 154err_out_free:
153 for (i = 0; i <= buddy->max_order; ++i) 155 for (i = 0; i <= buddy->max_order; ++i)
154 kfree(buddy->bits[i]); 156 kvfree(buddy->bits[i]);
155 157
156err_out: 158err_out:
157 kfree(buddy->bits); 159 kfree(buddy->bits);
@@ -164,7 +166,7 @@ static void hns_roce_buddy_cleanup(struct hns_roce_buddy *buddy)
164 int i; 166 int i;
165 167
166 for (i = 0; i <= buddy->max_order; ++i) 168 for (i = 0; i <= buddy->max_order; ++i)
167 kfree(buddy->bits[i]); 169 kvfree(buddy->bits[i]);
168 170
169 kfree(buddy->bits); 171 kfree(buddy->bits);
170 kfree(buddy->num_free); 172 kfree(buddy->num_free);
@@ -287,7 +289,7 @@ static void hns_roce_mr_free(struct hns_roce_dev *hr_dev,
287 } 289 }
288 290
289 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap, 291 hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
290 key_to_hw_index(mr->key)); 292 key_to_hw_index(mr->key), BITMAP_NO_RR);
291} 293}
292 294
293static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev, 295static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev,
@@ -605,13 +607,20 @@ err_free:
605 607
606int hns_roce_dereg_mr(struct ib_mr *ibmr) 608int hns_roce_dereg_mr(struct ib_mr *ibmr)
607{ 609{
610 struct hns_roce_dev *hr_dev = to_hr_dev(ibmr->device);
608 struct hns_roce_mr *mr = to_hr_mr(ibmr); 611 struct hns_roce_mr *mr = to_hr_mr(ibmr);
612 int ret = 0;
609 613
610 hns_roce_mr_free(to_hr_dev(ibmr->device), mr); 614 if (hr_dev->hw->dereg_mr) {
611 if (mr->umem) 615 ret = hr_dev->hw->dereg_mr(hr_dev, mr);
612 ib_umem_release(mr->umem); 616 } else {
617 hns_roce_mr_free(hr_dev, mr);
613 618
614 kfree(mr); 619 if (mr->umem)
620 ib_umem_release(mr->umem);
615 621
616 return 0; 622 kfree(mr);
623 }
624
625 return ret;
617} 626}
diff --git a/drivers/infiniband/hw/hns/hns_roce_pd.c b/drivers/infiniband/hw/hns/hns_roce_pd.c
index 05db7d59812a..a64500fa1145 100644
--- a/drivers/infiniband/hw/hns/hns_roce_pd.c
+++ b/drivers/infiniband/hw/hns/hns_roce_pd.c
@@ -40,7 +40,7 @@ static int hns_roce_pd_alloc(struct hns_roce_dev *hr_dev, unsigned long *pdn)
40 40
41static void hns_roce_pd_free(struct hns_roce_dev *hr_dev, unsigned long pdn) 41static void hns_roce_pd_free(struct hns_roce_dev *hr_dev, unsigned long pdn)
42{ 42{
43 hns_roce_bitmap_free(&hr_dev->pd_bitmap, pdn); 43 hns_roce_bitmap_free(&hr_dev->pd_bitmap, pdn, BITMAP_NO_RR);
44} 44}
45 45
46int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev) 46int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev)
@@ -121,7 +121,8 @@ int hns_roce_uar_alloc(struct hns_roce_dev *hr_dev, struct hns_roce_uar *uar)
121 121
122void hns_roce_uar_free(struct hns_roce_dev *hr_dev, struct hns_roce_uar *uar) 122void hns_roce_uar_free(struct hns_roce_dev *hr_dev, struct hns_roce_uar *uar)
123{ 123{
124 hns_roce_bitmap_free(&hr_dev->uar_table.bitmap, uar->index); 124 hns_roce_bitmap_free(&hr_dev->uar_table.bitmap, uar->index,
125 BITMAP_NO_RR);
125} 126}
126 127
127int hns_roce_init_uar_table(struct hns_roce_dev *hr_dev) 128int hns_roce_init_uar_table(struct hns_roce_dev *hr_dev)
diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c
index e86dd8d06777..f036f32f15d3 100644
--- a/drivers/infiniband/hw/hns/hns_roce_qp.c
+++ b/drivers/infiniband/hw/hns/hns_roce_qp.c
@@ -37,7 +37,7 @@
37#include "hns_roce_common.h" 37#include "hns_roce_common.h"
38#include "hns_roce_device.h" 38#include "hns_roce_device.h"
39#include "hns_roce_hem.h" 39#include "hns_roce_hem.h"
40#include "hns_roce_user.h" 40#include <rdma/hns-abi.h>
41 41
42#define SQP_NUM (2 * HNS_ROCE_MAX_PORTS) 42#define SQP_NUM (2 * HNS_ROCE_MAX_PORTS)
43 43
@@ -250,7 +250,7 @@ void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
250 if (base_qpn < SQP_NUM) 250 if (base_qpn < SQP_NUM)
251 return; 251 return;
252 252
253 hns_roce_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt); 253 hns_roce_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt, BITMAP_RR);
254} 254}
255 255
256static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev, 256static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev,
diff --git a/drivers/infiniband/hw/hns/hns_roce_user.h b/drivers/infiniband/hw/hns/hns_roce_user.h
deleted file mode 100644
index a28f761a9f65..000000000000
--- a/drivers/infiniband/hw/hns/hns_roce_user.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef _HNS_ROCE_USER_H
34#define _HNS_ROCE_USER_H
35
36struct hns_roce_ib_create_cq {
37 __u64 buf_addr;
38};
39
40struct hns_roce_ib_create_qp {
41 __u64 buf_addr;
42 __u64 db_addr;
43 __u8 log_sq_bb_count;
44 __u8 log_sq_stride;
45 __u8 sq_no_prefetch;
46 __u8 reserved[5];
47};
48
49struct hns_roce_ib_alloc_ucontext_resp {
50 __u32 qp_tab_size;
51};
52
53#endif /*_HNS_ROCE_USER_H */
diff --git a/drivers/infiniband/hw/i40iw/i40iw.h b/drivers/infiniband/hw/i40iw/i40iw.h
index 8ec09e470f84..da2eb5a281fa 100644
--- a/drivers/infiniband/hw/i40iw/i40iw.h
+++ b/drivers/infiniband/hw/i40iw/i40iw.h
@@ -112,9 +112,12 @@
112#define I40IW_DRV_OPT_MCAST_LOGPORT_MAP 0x00000800 112#define I40IW_DRV_OPT_MCAST_LOGPORT_MAP 0x00000800
113 113
114#define IW_HMC_OBJ_TYPE_NUM ARRAY_SIZE(iw_hmc_obj_types) 114#define IW_HMC_OBJ_TYPE_NUM ARRAY_SIZE(iw_hmc_obj_types)
115#define IW_CFG_FPM_QP_COUNT 32768 115#define IW_CFG_FPM_QP_COUNT 32768
116#define I40IW_MAX_PAGES_PER_FMR 512 116#define I40IW_MAX_PAGES_PER_FMR 512
117#define I40IW_MIN_PAGES_PER_FMR 1 117#define I40IW_MIN_PAGES_PER_FMR 1
118#define I40IW_CQP_COMPL_RQ_WQE_FLUSHED 2
119#define I40IW_CQP_COMPL_SQ_WQE_FLUSHED 3
120#define I40IW_CQP_COMPL_RQ_SQ_WQE_FLUSHED 4
118 121
119#define I40IW_MTU_TO_MSS 40 122#define I40IW_MTU_TO_MSS 40
120#define I40IW_DEFAULT_MSS 1460 123#define I40IW_DEFAULT_MSS 1460
@@ -210,6 +213,12 @@ struct i40iw_msix_vector {
210 u32 ceq_id; 213 u32 ceq_id;
211}; 214};
212 215
216struct l2params_work {
217 struct work_struct work;
218 struct i40iw_device *iwdev;
219 struct i40iw_l2params l2params;
220};
221
213#define I40IW_MSIX_TABLE_SIZE 65 222#define I40IW_MSIX_TABLE_SIZE 65
214 223
215struct virtchnl_work { 224struct virtchnl_work {
@@ -227,6 +236,7 @@ struct i40iw_device {
227 struct net_device *netdev; 236 struct net_device *netdev;
228 wait_queue_head_t vchnl_waitq; 237 wait_queue_head_t vchnl_waitq;
229 struct i40iw_sc_dev sc_dev; 238 struct i40iw_sc_dev sc_dev;
239 struct i40iw_sc_vsi vsi;
230 struct i40iw_handler *hdl; 240 struct i40iw_handler *hdl;
231 struct i40e_info *ldev; 241 struct i40e_info *ldev;
232 struct i40e_client *client; 242 struct i40e_client *client;
@@ -280,7 +290,6 @@ struct i40iw_device {
280 u32 sd_type; 290 u32 sd_type;
281 struct workqueue_struct *param_wq; 291 struct workqueue_struct *param_wq;
282 atomic_t params_busy; 292 atomic_t params_busy;
283 u32 mss;
284 enum init_completion_state init_state; 293 enum init_completion_state init_state;
285 u16 mac_ip_table_idx; 294 u16 mac_ip_table_idx;
286 atomic_t vchnl_msgs; 295 atomic_t vchnl_msgs;
@@ -297,6 +306,14 @@ struct i40iw_device {
297 u32 mr_stagmask; 306 u32 mr_stagmask;
298 u32 mpa_version; 307 u32 mpa_version;
299 bool dcb; 308 bool dcb;
309 bool closing;
310 bool reset;
311 u32 used_pds;
312 u32 used_cqs;
313 u32 used_mrs;
314 u32 used_qps;
315 wait_queue_head_t close_wq;
316 atomic64_t use_count;
300}; 317};
301 318
302struct i40iw_ib_device { 319struct i40iw_ib_device {
@@ -498,7 +515,7 @@ u32 i40iw_initialize_hw_resources(struct i40iw_device *iwdev);
498 515
499int i40iw_register_rdma_device(struct i40iw_device *iwdev); 516int i40iw_register_rdma_device(struct i40iw_device *iwdev);
500void i40iw_port_ibevent(struct i40iw_device *iwdev); 517void i40iw_port_ibevent(struct i40iw_device *iwdev);
501int i40iw_cm_disconn(struct i40iw_qp *); 518void i40iw_cm_disconn(struct i40iw_qp *iwqp);
502void i40iw_cm_disconn_worker(void *); 519void i40iw_cm_disconn_worker(void *);
503int mini_cm_recv_pkt(struct i40iw_cm_core *, struct i40iw_device *, 520int mini_cm_recv_pkt(struct i40iw_cm_core *, struct i40iw_device *,
504 struct sk_buff *); 521 struct sk_buff *);
@@ -508,20 +525,26 @@ enum i40iw_status_code i40iw_handle_cqp_op(struct i40iw_device *iwdev,
508enum i40iw_status_code i40iw_add_mac_addr(struct i40iw_device *iwdev, 525enum i40iw_status_code i40iw_add_mac_addr(struct i40iw_device *iwdev,
509 u8 *mac_addr, u8 *mac_index); 526 u8 *mac_addr, u8 *mac_index);
510int i40iw_modify_qp(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *); 527int i40iw_modify_qp(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);
528void i40iw_cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq);
511 529
512void i40iw_rem_pdusecount(struct i40iw_pd *iwpd, struct i40iw_device *iwdev); 530void i40iw_rem_pdusecount(struct i40iw_pd *iwpd, struct i40iw_device *iwdev);
513void i40iw_add_pdusecount(struct i40iw_pd *iwpd); 531void i40iw_add_pdusecount(struct i40iw_pd *iwpd);
532void i40iw_rem_devusecount(struct i40iw_device *iwdev);
533void i40iw_add_devusecount(struct i40iw_device *iwdev);
514void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp, 534void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp,
515 struct i40iw_modify_qp_info *info, bool wait); 535 struct i40iw_modify_qp_info *info, bool wait);
516 536
537void i40iw_qp_suspend_resume(struct i40iw_sc_dev *dev,
538 struct i40iw_sc_qp *qp,
539 bool suspend);
517enum i40iw_status_code i40iw_manage_qhash(struct i40iw_device *iwdev, 540enum i40iw_status_code i40iw_manage_qhash(struct i40iw_device *iwdev,
518 struct i40iw_cm_info *cminfo, 541 struct i40iw_cm_info *cminfo,
519 enum i40iw_quad_entry_type etype, 542 enum i40iw_quad_entry_type etype,
520 enum i40iw_quad_hash_manage_type mtype, 543 enum i40iw_quad_hash_manage_type mtype,
521 void *cmnode, 544 void *cmnode,
522 bool wait); 545 bool wait);
523void i40iw_receive_ilq(struct i40iw_sc_dev *dev, struct i40iw_puda_buf *rbuf); 546void i40iw_receive_ilq(struct i40iw_sc_vsi *vsi, struct i40iw_puda_buf *rbuf);
524void i40iw_free_sqbuf(struct i40iw_sc_dev *dev, void *bufp); 547void i40iw_free_sqbuf(struct i40iw_sc_vsi *vsi, void *bufp);
525void i40iw_free_qp_resources(struct i40iw_device *iwdev, 548void i40iw_free_qp_resources(struct i40iw_device *iwdev,
526 struct i40iw_qp *iwqp, 549 struct i40iw_qp *iwqp,
527 u32 qp_num); 550 u32 qp_num);
diff --git a/drivers/infiniband/hw/i40iw/i40iw_cm.c b/drivers/infiniband/hw/i40iw/i40iw_cm.c
index 85637696f6e9..95a0586a4da8 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_cm.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_cm.c
@@ -68,13 +68,13 @@ static void i40iw_disconnect_worker(struct work_struct *work);
68 68
69/** 69/**
70 * i40iw_free_sqbuf - put back puda buffer if refcount = 0 70 * i40iw_free_sqbuf - put back puda buffer if refcount = 0
71 * @dev: FPK device 71 * @vsi: pointer to vsi structure
72 * @buf: puda buffer to free 72 * @buf: puda buffer to free
73 */ 73 */
74void i40iw_free_sqbuf(struct i40iw_sc_dev *dev, void *bufp) 74void i40iw_free_sqbuf(struct i40iw_sc_vsi *vsi, void *bufp)
75{ 75{
76 struct i40iw_puda_buf *buf = (struct i40iw_puda_buf *)bufp; 76 struct i40iw_puda_buf *buf = (struct i40iw_puda_buf *)bufp;
77 struct i40iw_puda_rsrc *ilq = dev->ilq; 77 struct i40iw_puda_rsrc *ilq = vsi->ilq;
78 78
79 if (!atomic_dec_return(&buf->refcount)) 79 if (!atomic_dec_return(&buf->refcount))
80 i40iw_puda_ret_bufpool(ilq, buf); 80 i40iw_puda_ret_bufpool(ilq, buf);
@@ -221,6 +221,7 @@ static void i40iw_get_addr_info(struct i40iw_cm_node *cm_node,
221 memcpy(cm_info->rem_addr, cm_node->rem_addr, sizeof(cm_info->rem_addr)); 221 memcpy(cm_info->rem_addr, cm_node->rem_addr, sizeof(cm_info->rem_addr));
222 cm_info->loc_port = cm_node->loc_port; 222 cm_info->loc_port = cm_node->loc_port;
223 cm_info->rem_port = cm_node->rem_port; 223 cm_info->rem_port = cm_node->rem_port;
224 cm_info->user_pri = cm_node->user_pri;
224} 225}
225 226
226/** 227/**
@@ -271,6 +272,7 @@ static int i40iw_send_cm_event(struct i40iw_cm_node *cm_node,
271 event.provider_data = (void *)cm_node; 272 event.provider_data = (void *)cm_node;
272 event.private_data = (void *)cm_node->pdata_buf; 273 event.private_data = (void *)cm_node->pdata_buf;
273 event.private_data_len = (u8)cm_node->pdata.size; 274 event.private_data_len = (u8)cm_node->pdata.size;
275 event.ird = cm_node->ird_size;
274 break; 276 break;
275 case IW_CM_EVENT_CONNECT_REPLY: 277 case IW_CM_EVENT_CONNECT_REPLY:
276 i40iw_get_cmevent_info(cm_node, cm_id, &event); 278 i40iw_get_cmevent_info(cm_node, cm_id, &event);
@@ -335,13 +337,13 @@ static struct i40iw_cm_event *i40iw_create_event(struct i40iw_cm_node *cm_node,
335 */ 337 */
336static void i40iw_free_retrans_entry(struct i40iw_cm_node *cm_node) 338static void i40iw_free_retrans_entry(struct i40iw_cm_node *cm_node)
337{ 339{
338 struct i40iw_sc_dev *dev = cm_node->dev; 340 struct i40iw_device *iwdev = cm_node->iwdev;
339 struct i40iw_timer_entry *send_entry; 341 struct i40iw_timer_entry *send_entry;
340 342
341 send_entry = cm_node->send_entry; 343 send_entry = cm_node->send_entry;
342 if (send_entry) { 344 if (send_entry) {
343 cm_node->send_entry = NULL; 345 cm_node->send_entry = NULL;
344 i40iw_free_sqbuf(dev, (void *)send_entry->sqbuf); 346 i40iw_free_sqbuf(&iwdev->vsi, (void *)send_entry->sqbuf);
345 kfree(send_entry); 347 kfree(send_entry);
346 atomic_dec(&cm_node->ref_count); 348 atomic_dec(&cm_node->ref_count);
347 } 349 }
@@ -360,15 +362,6 @@ static void i40iw_cleanup_retrans_entry(struct i40iw_cm_node *cm_node)
360 spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags); 362 spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags);
361} 363}
362 364
363static bool is_remote_ne020_or_chelsio(struct i40iw_cm_node *cm_node)
364{
365 if ((cm_node->rem_mac[0] == 0x0) &&
366 (((cm_node->rem_mac[1] == 0x12) && (cm_node->rem_mac[2] == 0x55)) ||
367 ((cm_node->rem_mac[1] == 0x07 && (cm_node->rem_mac[2] == 0x43)))))
368 return true;
369 return false;
370}
371
372/** 365/**
373 * i40iw_form_cm_frame - get a free packet and build frame 366 * i40iw_form_cm_frame - get a free packet and build frame
374 * @cm_node: connection's node ionfo to use in frame 367 * @cm_node: connection's node ionfo to use in frame
@@ -384,7 +377,7 @@ static struct i40iw_puda_buf *i40iw_form_cm_frame(struct i40iw_cm_node *cm_node,
384 u8 flags) 377 u8 flags)
385{ 378{
386 struct i40iw_puda_buf *sqbuf; 379 struct i40iw_puda_buf *sqbuf;
387 struct i40iw_sc_dev *dev = cm_node->dev; 380 struct i40iw_sc_vsi *vsi = &cm_node->iwdev->vsi;
388 u8 *buf; 381 u8 *buf;
389 382
390 struct tcphdr *tcph; 383 struct tcphdr *tcph;
@@ -396,8 +389,9 @@ static struct i40iw_puda_buf *i40iw_form_cm_frame(struct i40iw_cm_node *cm_node,
396 u32 opts_len = 0; 389 u32 opts_len = 0;
397 u32 pd_len = 0; 390 u32 pd_len = 0;
398 u32 hdr_len = 0; 391 u32 hdr_len = 0;
392 u16 vtag;
399 393
400 sqbuf = i40iw_puda_get_bufpool(dev->ilq); 394 sqbuf = i40iw_puda_get_bufpool(vsi->ilq);
401 if (!sqbuf) 395 if (!sqbuf)
402 return NULL; 396 return NULL;
403 buf = sqbuf->mem.va; 397 buf = sqbuf->mem.va;
@@ -408,11 +402,8 @@ static struct i40iw_puda_buf *i40iw_form_cm_frame(struct i40iw_cm_node *cm_node,
408 if (hdr) 402 if (hdr)
409 hdr_len = hdr->size; 403 hdr_len = hdr->size;
410 404
411 if (pdata) { 405 if (pdata)
412 pd_len = pdata->size; 406 pd_len = pdata->size;
413 if (!is_remote_ne020_or_chelsio(cm_node))
414 pd_len += MPA_ZERO_PAD_LEN;
415 }
416 407
417 if (cm_node->vlan_id < VLAN_TAG_PRESENT) 408 if (cm_node->vlan_id < VLAN_TAG_PRESENT)
418 eth_hlen += 4; 409 eth_hlen += 4;
@@ -445,7 +436,8 @@ static struct i40iw_puda_buf *i40iw_form_cm_frame(struct i40iw_cm_node *cm_node,
445 ether_addr_copy(ethh->h_source, cm_node->loc_mac); 436 ether_addr_copy(ethh->h_source, cm_node->loc_mac);
446 if (cm_node->vlan_id < VLAN_TAG_PRESENT) { 437 if (cm_node->vlan_id < VLAN_TAG_PRESENT) {
447 ((struct vlan_ethhdr *)ethh)->h_vlan_proto = htons(ETH_P_8021Q); 438 ((struct vlan_ethhdr *)ethh)->h_vlan_proto = htons(ETH_P_8021Q);
448 ((struct vlan_ethhdr *)ethh)->h_vlan_TCI = htons(cm_node->vlan_id); 439 vtag = (cm_node->user_pri << VLAN_PRIO_SHIFT) | cm_node->vlan_id;
440 ((struct vlan_ethhdr *)ethh)->h_vlan_TCI = htons(vtag);
449 441
450 ((struct vlan_ethhdr *)ethh)->h_vlan_encapsulated_proto = htons(ETH_P_IP); 442 ((struct vlan_ethhdr *)ethh)->h_vlan_encapsulated_proto = htons(ETH_P_IP);
451 } else { 443 } else {
@@ -454,7 +446,7 @@ static struct i40iw_puda_buf *i40iw_form_cm_frame(struct i40iw_cm_node *cm_node,
454 446
455 iph->version = IPVERSION; 447 iph->version = IPVERSION;
456 iph->ihl = 5; /* 5 * 4Byte words, IP headr len */ 448 iph->ihl = 5; /* 5 * 4Byte words, IP headr len */
457 iph->tos = 0; 449 iph->tos = cm_node->tos;
458 iph->tot_len = htons(packetsize); 450 iph->tot_len = htons(packetsize);
459 iph->id = htons(++cm_node->tcp_cntxt.loc_id); 451 iph->id = htons(++cm_node->tcp_cntxt.loc_id);
460 452
@@ -474,13 +466,15 @@ static struct i40iw_puda_buf *i40iw_form_cm_frame(struct i40iw_cm_node *cm_node,
474 ether_addr_copy(ethh->h_source, cm_node->loc_mac); 466 ether_addr_copy(ethh->h_source, cm_node->loc_mac);
475 if (cm_node->vlan_id < VLAN_TAG_PRESENT) { 467 if (cm_node->vlan_id < VLAN_TAG_PRESENT) {
476 ((struct vlan_ethhdr *)ethh)->h_vlan_proto = htons(ETH_P_8021Q); 468 ((struct vlan_ethhdr *)ethh)->h_vlan_proto = htons(ETH_P_8021Q);
477 ((struct vlan_ethhdr *)ethh)->h_vlan_TCI = htons(cm_node->vlan_id); 469 vtag = (cm_node->user_pri << VLAN_PRIO_SHIFT) | cm_node->vlan_id;
470 ((struct vlan_ethhdr *)ethh)->h_vlan_TCI = htons(vtag);
478 ((struct vlan_ethhdr *)ethh)->h_vlan_encapsulated_proto = htons(ETH_P_IPV6); 471 ((struct vlan_ethhdr *)ethh)->h_vlan_encapsulated_proto = htons(ETH_P_IPV6);
479 } else { 472 } else {
480 ethh->h_proto = htons(ETH_P_IPV6); 473 ethh->h_proto = htons(ETH_P_IPV6);
481 } 474 }
482 ip6h->version = 6; 475 ip6h->version = 6;
483 ip6h->flow_lbl[0] = 0; 476 ip6h->priority = cm_node->tos >> 4;
477 ip6h->flow_lbl[0] = cm_node->tos << 4;
484 ip6h->flow_lbl[1] = 0; 478 ip6h->flow_lbl[1] = 0;
485 ip6h->flow_lbl[2] = 0; 479 ip6h->flow_lbl[2] = 0;
486 ip6h->payload_len = htons(packetsize - sizeof(*ip6h)); 480 ip6h->payload_len = htons(packetsize - sizeof(*ip6h));
@@ -1065,7 +1059,7 @@ int i40iw_schedule_cm_timer(struct i40iw_cm_node *cm_node,
1065 int send_retrans, 1059 int send_retrans,
1066 int close_when_complete) 1060 int close_when_complete)
1067{ 1061{
1068 struct i40iw_sc_dev *dev = cm_node->dev; 1062 struct i40iw_sc_vsi *vsi = &cm_node->iwdev->vsi;
1069 struct i40iw_cm_core *cm_core = cm_node->cm_core; 1063 struct i40iw_cm_core *cm_core = cm_node->cm_core;
1070 struct i40iw_timer_entry *new_send; 1064 struct i40iw_timer_entry *new_send;
1071 int ret = 0; 1065 int ret = 0;
@@ -1074,7 +1068,7 @@ int i40iw_schedule_cm_timer(struct i40iw_cm_node *cm_node,
1074 1068
1075 new_send = kzalloc(sizeof(*new_send), GFP_ATOMIC); 1069 new_send = kzalloc(sizeof(*new_send), GFP_ATOMIC);
1076 if (!new_send) { 1070 if (!new_send) {
1077 i40iw_free_sqbuf(cm_node->dev, (void *)sqbuf); 1071 i40iw_free_sqbuf(vsi, (void *)sqbuf);
1078 return -ENOMEM; 1072 return -ENOMEM;
1079 } 1073 }
1080 new_send->retrycount = I40IW_DEFAULT_RETRYS; 1074 new_send->retrycount = I40IW_DEFAULT_RETRYS;
@@ -1089,7 +1083,7 @@ int i40iw_schedule_cm_timer(struct i40iw_cm_node *cm_node,
1089 new_send->timetosend += (HZ / 10); 1083 new_send->timetosend += (HZ / 10);
1090 if (cm_node->close_entry) { 1084 if (cm_node->close_entry) {
1091 kfree(new_send); 1085 kfree(new_send);
1092 i40iw_free_sqbuf(cm_node->dev, (void *)sqbuf); 1086 i40iw_free_sqbuf(vsi, (void *)sqbuf);
1093 i40iw_pr_err("already close entry\n"); 1087 i40iw_pr_err("already close entry\n");
1094 return -EINVAL; 1088 return -EINVAL;
1095 } 1089 }
@@ -1104,7 +1098,7 @@ int i40iw_schedule_cm_timer(struct i40iw_cm_node *cm_node,
1104 new_send->timetosend = jiffies + I40IW_RETRY_TIMEOUT; 1098 new_send->timetosend = jiffies + I40IW_RETRY_TIMEOUT;
1105 1099
1106 atomic_inc(&sqbuf->refcount); 1100 atomic_inc(&sqbuf->refcount);
1107 i40iw_puda_send_buf(dev->ilq, sqbuf); 1101 i40iw_puda_send_buf(vsi->ilq, sqbuf);
1108 if (!send_retrans) { 1102 if (!send_retrans) {
1109 i40iw_cleanup_retrans_entry(cm_node); 1103 i40iw_cleanup_retrans_entry(cm_node);
1110 if (close_when_complete) 1104 if (close_when_complete)
@@ -1201,6 +1195,7 @@ static void i40iw_cm_timer_tick(unsigned long pass)
1201 struct i40iw_cm_node *cm_node; 1195 struct i40iw_cm_node *cm_node;
1202 struct i40iw_timer_entry *send_entry, *close_entry; 1196 struct i40iw_timer_entry *send_entry, *close_entry;
1203 struct list_head *list_core_temp; 1197 struct list_head *list_core_temp;
1198 struct i40iw_sc_vsi *vsi;
1204 struct list_head *list_node; 1199 struct list_head *list_node;
1205 struct i40iw_cm_core *cm_core = (struct i40iw_cm_core *)pass; 1200 struct i40iw_cm_core *cm_core = (struct i40iw_cm_core *)pass;
1206 u32 settimer = 0; 1201 u32 settimer = 0;
@@ -1276,9 +1271,10 @@ static void i40iw_cm_timer_tick(unsigned long pass)
1276 cm_node->cm_core->stats_pkt_retrans++; 1271 cm_node->cm_core->stats_pkt_retrans++;
1277 spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags); 1272 spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags);
1278 1273
1274 vsi = &cm_node->iwdev->vsi;
1279 dev = cm_node->dev; 1275 dev = cm_node->dev;
1280 atomic_inc(&send_entry->sqbuf->refcount); 1276 atomic_inc(&send_entry->sqbuf->refcount);
1281 i40iw_puda_send_buf(dev->ilq, send_entry->sqbuf); 1277 i40iw_puda_send_buf(vsi->ilq, send_entry->sqbuf);
1282 spin_lock_irqsave(&cm_node->retrans_list_lock, flags); 1278 spin_lock_irqsave(&cm_node->retrans_list_lock, flags);
1283 if (send_entry->send_retrans) { 1279 if (send_entry->send_retrans) {
1284 send_entry->retranscount--; 1280 send_entry->retranscount--;
@@ -1379,10 +1375,11 @@ int i40iw_send_syn(struct i40iw_cm_node *cm_node, u32 sendack)
1379static void i40iw_send_ack(struct i40iw_cm_node *cm_node) 1375static void i40iw_send_ack(struct i40iw_cm_node *cm_node)
1380{ 1376{
1381 struct i40iw_puda_buf *sqbuf; 1377 struct i40iw_puda_buf *sqbuf;
1378 struct i40iw_sc_vsi *vsi = &cm_node->iwdev->vsi;
1382 1379
1383 sqbuf = i40iw_form_cm_frame(cm_node, NULL, NULL, NULL, SET_ACK); 1380 sqbuf = i40iw_form_cm_frame(cm_node, NULL, NULL, NULL, SET_ACK);
1384 if (sqbuf) 1381 if (sqbuf)
1385 i40iw_puda_send_buf(cm_node->dev->ilq, sqbuf); 1382 i40iw_puda_send_buf(vsi->ilq, sqbuf);
1386 else 1383 else
1387 i40iw_pr_err("no sqbuf\n"); 1384 i40iw_pr_err("no sqbuf\n");
1388} 1385}
@@ -1564,9 +1561,15 @@ static enum i40iw_status_code i40iw_del_multiple_qhash(
1564 memcpy(cm_info->loc_addr, child_listen_node->loc_addr, 1561 memcpy(cm_info->loc_addr, child_listen_node->loc_addr,
1565 sizeof(cm_info->loc_addr)); 1562 sizeof(cm_info->loc_addr));
1566 cm_info->vlan_id = child_listen_node->vlan_id; 1563 cm_info->vlan_id = child_listen_node->vlan_id;
1567 ret = i40iw_manage_qhash(iwdev, cm_info, 1564 if (child_listen_node->qhash_set) {
1568 I40IW_QHASH_TYPE_TCP_SYN, 1565 ret = i40iw_manage_qhash(iwdev, cm_info,
1569 I40IW_QHASH_MANAGE_TYPE_DELETE, NULL, false); 1566 I40IW_QHASH_TYPE_TCP_SYN,
1567 I40IW_QHASH_MANAGE_TYPE_DELETE,
1568 NULL, false);
1569 child_listen_node->qhash_set = false;
1570 } else {
1571 ret = I40IW_SUCCESS;
1572 }
1570 i40iw_debug(&iwdev->sc_dev, 1573 i40iw_debug(&iwdev->sc_dev,
1571 I40IW_DEBUG_CM, 1574 I40IW_DEBUG_CM,
1572 "freed pointer = %p\n", 1575 "freed pointer = %p\n",
@@ -1591,9 +1594,10 @@ static enum i40iw_status_code i40iw_del_multiple_qhash(
1591static struct net_device *i40iw_netdev_vlan_ipv6(u32 *addr, u16 *vlan_id, u8 *mac) 1594static struct net_device *i40iw_netdev_vlan_ipv6(u32 *addr, u16 *vlan_id, u8 *mac)
1592{ 1595{
1593 struct net_device *ip_dev = NULL; 1596 struct net_device *ip_dev = NULL;
1594#if IS_ENABLED(CONFIG_IPV6)
1595 struct in6_addr laddr6; 1597 struct in6_addr laddr6;
1596 1598
1599 if (!IS_ENABLED(CONFIG_IPV6))
1600 return NULL;
1597 i40iw_copy_ip_htonl(laddr6.in6_u.u6_addr32, addr); 1601 i40iw_copy_ip_htonl(laddr6.in6_u.u6_addr32, addr);
1598 if (vlan_id) 1602 if (vlan_id)
1599 *vlan_id = I40IW_NO_VLAN; 1603 *vlan_id = I40IW_NO_VLAN;
@@ -1610,7 +1614,6 @@ static struct net_device *i40iw_netdev_vlan_ipv6(u32 *addr, u16 *vlan_id, u8 *ma
1610 } 1614 }
1611 } 1615 }
1612 rcu_read_unlock(); 1616 rcu_read_unlock();
1613#endif
1614 return ip_dev; 1617 return ip_dev;
1615} 1618}
1616 1619
@@ -1646,7 +1649,7 @@ static enum i40iw_status_code i40iw_add_mqh_6(struct i40iw_device *iwdev,
1646{ 1649{
1647 struct net_device *ip_dev; 1650 struct net_device *ip_dev;
1648 struct inet6_dev *idev; 1651 struct inet6_dev *idev;
1649 struct inet6_ifaddr *ifp; 1652 struct inet6_ifaddr *ifp, *tmp;
1650 enum i40iw_status_code ret = 0; 1653 enum i40iw_status_code ret = 0;
1651 struct i40iw_cm_listener *child_listen_node; 1654 struct i40iw_cm_listener *child_listen_node;
1652 unsigned long flags; 1655 unsigned long flags;
@@ -1661,7 +1664,7 @@ static enum i40iw_status_code i40iw_add_mqh_6(struct i40iw_device *iwdev,
1661 i40iw_pr_err("idev == NULL\n"); 1664 i40iw_pr_err("idev == NULL\n");
1662 break; 1665 break;
1663 } 1666 }
1664 list_for_each_entry(ifp, &idev->addr_list, if_list) { 1667 list_for_each_entry_safe(ifp, tmp, &idev->addr_list, if_list) {
1665 i40iw_debug(&iwdev->sc_dev, 1668 i40iw_debug(&iwdev->sc_dev,
1666 I40IW_DEBUG_CM, 1669 I40IW_DEBUG_CM,
1667 "IP=%pI6, vlan_id=%d, MAC=%pM\n", 1670 "IP=%pI6, vlan_id=%d, MAC=%pM\n",
@@ -1675,7 +1678,6 @@ static enum i40iw_status_code i40iw_add_mqh_6(struct i40iw_device *iwdev,
1675 "Allocating child listener %p\n", 1678 "Allocating child listener %p\n",
1676 child_listen_node); 1679 child_listen_node);
1677 if (!child_listen_node) { 1680 if (!child_listen_node) {
1678 i40iw_pr_err("listener memory allocation\n");
1679 ret = I40IW_ERR_NO_MEMORY; 1681 ret = I40IW_ERR_NO_MEMORY;
1680 goto exit; 1682 goto exit;
1681 } 1683 }
@@ -1695,6 +1697,7 @@ static enum i40iw_status_code i40iw_add_mqh_6(struct i40iw_device *iwdev,
1695 I40IW_QHASH_MANAGE_TYPE_ADD, 1697 I40IW_QHASH_MANAGE_TYPE_ADD,
1696 NULL, true); 1698 NULL, true);
1697 if (!ret) { 1699 if (!ret) {
1700 child_listen_node->qhash_set = true;
1698 spin_lock_irqsave(&iwdev->cm_core.listen_list_lock, flags); 1701 spin_lock_irqsave(&iwdev->cm_core.listen_list_lock, flags);
1699 list_add(&child_listen_node->child_listen_list, 1702 list_add(&child_listen_node->child_listen_list,
1700 &cm_parent_listen_node->child_listen_list); 1703 &cm_parent_listen_node->child_listen_list);
@@ -1751,7 +1754,6 @@ static enum i40iw_status_code i40iw_add_mqh_4(
1751 "Allocating child listener %p\n", 1754 "Allocating child listener %p\n",
1752 child_listen_node); 1755 child_listen_node);
1753 if (!child_listen_node) { 1756 if (!child_listen_node) {
1754 i40iw_pr_err("listener memory allocation\n");
1755 in_dev_put(idev); 1757 in_dev_put(idev);
1756 ret = I40IW_ERR_NO_MEMORY; 1758 ret = I40IW_ERR_NO_MEMORY;
1757 goto exit; 1759 goto exit;
@@ -1773,6 +1775,7 @@ static enum i40iw_status_code i40iw_add_mqh_4(
1773 NULL, 1775 NULL,
1774 true); 1776 true);
1775 if (!ret) { 1777 if (!ret) {
1778 child_listen_node->qhash_set = true;
1776 spin_lock_irqsave(&iwdev->cm_core.listen_list_lock, flags); 1779 spin_lock_irqsave(&iwdev->cm_core.listen_list_lock, flags);
1777 list_add(&child_listen_node->child_listen_list, 1780 list_add(&child_listen_node->child_listen_list,
1778 &cm_parent_listen_node->child_listen_list); 1781 &cm_parent_listen_node->child_listen_list);
@@ -1880,6 +1883,7 @@ static int i40iw_dec_refcnt_listen(struct i40iw_cm_core *cm_core,
1880 nfo.loc_port = listener->loc_port; 1883 nfo.loc_port = listener->loc_port;
1881 nfo.ipv4 = listener->ipv4; 1884 nfo.ipv4 = listener->ipv4;
1882 nfo.vlan_id = listener->vlan_id; 1885 nfo.vlan_id = listener->vlan_id;
1886 nfo.user_pri = listener->user_pri;
1883 1887
1884 if (!list_empty(&listener->child_listen_list)) { 1888 if (!list_empty(&listener->child_listen_list)) {
1885 i40iw_del_multiple_qhash(listener->iwdev, &nfo, listener); 1889 i40iw_del_multiple_qhash(listener->iwdev, &nfo, listener);
@@ -2138,6 +2142,20 @@ static struct i40iw_cm_node *i40iw_make_cm_node(
2138 /* set our node specific transport info */ 2142 /* set our node specific transport info */
2139 cm_node->ipv4 = cm_info->ipv4; 2143 cm_node->ipv4 = cm_info->ipv4;
2140 cm_node->vlan_id = cm_info->vlan_id; 2144 cm_node->vlan_id = cm_info->vlan_id;
2145 if ((cm_node->vlan_id == I40IW_NO_VLAN) && iwdev->dcb)
2146 cm_node->vlan_id = 0;
2147 cm_node->tos = cm_info->tos;
2148 cm_node->user_pri = cm_info->user_pri;
2149 if (listener) {
2150 if (listener->tos != cm_info->tos)
2151 i40iw_debug(&iwdev->sc_dev, I40IW_DEBUG_DCB,
2152 "application TOS[%d] and remote client TOS[%d] mismatch\n",
2153 listener->tos, cm_info->tos);
2154 cm_node->tos = max(listener->tos, cm_info->tos);
2155 cm_node->user_pri = rt_tos2priority(cm_node->tos);
2156 i40iw_debug(&iwdev->sc_dev, I40IW_DEBUG_DCB, "listener: TOS:[%d] UP:[%d]\n",
2157 cm_node->tos, cm_node->user_pri);
2158 }
2141 memcpy(cm_node->loc_addr, cm_info->loc_addr, sizeof(cm_node->loc_addr)); 2159 memcpy(cm_node->loc_addr, cm_info->loc_addr, sizeof(cm_node->loc_addr));
2142 memcpy(cm_node->rem_addr, cm_info->rem_addr, sizeof(cm_node->rem_addr)); 2160 memcpy(cm_node->rem_addr, cm_info->rem_addr, sizeof(cm_node->rem_addr));
2143 cm_node->loc_port = cm_info->loc_port; 2161 cm_node->loc_port = cm_info->loc_port;
@@ -2162,7 +2180,7 @@ static struct i40iw_cm_node *i40iw_make_cm_node(
2162 I40IW_CM_DEFAULT_RCV_WND_SCALED >> I40IW_CM_DEFAULT_RCV_WND_SCALE; 2180 I40IW_CM_DEFAULT_RCV_WND_SCALED >> I40IW_CM_DEFAULT_RCV_WND_SCALE;
2163 ts = current_kernel_time(); 2181 ts = current_kernel_time();
2164 cm_node->tcp_cntxt.loc_seq_num = ts.tv_nsec; 2182 cm_node->tcp_cntxt.loc_seq_num = ts.tv_nsec;
2165 cm_node->tcp_cntxt.mss = iwdev->mss; 2183 cm_node->tcp_cntxt.mss = iwdev->vsi.mss;
2166 2184
2167 cm_node->iwdev = iwdev; 2185 cm_node->iwdev = iwdev;
2168 cm_node->dev = &iwdev->sc_dev; 2186 cm_node->dev = &iwdev->sc_dev;
@@ -2236,7 +2254,7 @@ static void i40iw_rem_ref_cm_node(struct i40iw_cm_node *cm_node)
2236 i40iw_dec_refcnt_listen(cm_core, cm_node->listener, 0, true); 2254 i40iw_dec_refcnt_listen(cm_core, cm_node->listener, 0, true);
2237 } else { 2255 } else {
2238 if (!i40iw_listen_port_in_use(cm_core, cm_node->loc_port) && 2256 if (!i40iw_listen_port_in_use(cm_core, cm_node->loc_port) &&
2239 cm_node->apbvt_set && cm_node->iwdev) { 2257 cm_node->apbvt_set) {
2240 i40iw_manage_apbvt(cm_node->iwdev, 2258 i40iw_manage_apbvt(cm_node->iwdev,
2241 cm_node->loc_port, 2259 cm_node->loc_port,
2242 I40IW_MANAGE_APBVT_DEL); 2260 I40IW_MANAGE_APBVT_DEL);
@@ -2861,7 +2879,7 @@ static struct i40iw_cm_node *i40iw_create_cm_node(
2861 /* create a CM connection node */ 2879 /* create a CM connection node */
2862 cm_node = i40iw_make_cm_node(cm_core, iwdev, cm_info, NULL); 2880 cm_node = i40iw_make_cm_node(cm_core, iwdev, cm_info, NULL);
2863 if (!cm_node) 2881 if (!cm_node)
2864 return NULL; 2882 return ERR_PTR(-ENOMEM);
2865 /* set our node side to client (active) side */ 2883 /* set our node side to client (active) side */
2866 cm_node->tcp_cntxt.client = 1; 2884 cm_node->tcp_cntxt.client = 1;
2867 cm_node->tcp_cntxt.rcv_wscale = I40IW_CM_DEFAULT_RCV_WND_SCALE; 2885 cm_node->tcp_cntxt.rcv_wscale = I40IW_CM_DEFAULT_RCV_WND_SCALE;
@@ -2874,7 +2892,8 @@ static struct i40iw_cm_node *i40iw_create_cm_node(
2874 cm_node->vlan_id, 2892 cm_node->vlan_id,
2875 I40IW_CM_LISTENER_ACTIVE_STATE); 2893 I40IW_CM_LISTENER_ACTIVE_STATE);
2876 if (!loopback_remotelistener) { 2894 if (!loopback_remotelistener) {
2877 i40iw_create_event(cm_node, I40IW_CM_EVENT_ABORTED); 2895 i40iw_rem_ref_cm_node(cm_node);
2896 return ERR_PTR(-ECONNREFUSED);
2878 } else { 2897 } else {
2879 loopback_cm_info = *cm_info; 2898 loopback_cm_info = *cm_info;
2880 loopback_cm_info.loc_port = cm_info->rem_port; 2899 loopback_cm_info.loc_port = cm_info->rem_port;
@@ -2887,7 +2906,7 @@ static struct i40iw_cm_node *i40iw_create_cm_node(
2887 loopback_remotelistener); 2906 loopback_remotelistener);
2888 if (!loopback_remotenode) { 2907 if (!loopback_remotenode) {
2889 i40iw_rem_ref_cm_node(cm_node); 2908 i40iw_rem_ref_cm_node(cm_node);
2890 return NULL; 2909 return ERR_PTR(-ENOMEM);
2891 } 2910 }
2892 cm_core->stats_loopbacks++; 2911 cm_core->stats_loopbacks++;
2893 loopback_remotenode->loopbackpartner = cm_node; 2912 loopback_remotenode->loopbackpartner = cm_node;
@@ -3041,10 +3060,10 @@ static int i40iw_cm_close(struct i40iw_cm_node *cm_node)
3041/** 3060/**
3042 * i40iw_receive_ilq - recv an ETHERNET packet, and process it 3061 * i40iw_receive_ilq - recv an ETHERNET packet, and process it
3043 * through CM 3062 * through CM
3044 * @dev: FPK dev struct 3063 * @vsi: pointer to the vsi structure
3045 * @rbuf: receive buffer 3064 * @rbuf: receive buffer
3046 */ 3065 */
3047void i40iw_receive_ilq(struct i40iw_sc_dev *dev, struct i40iw_puda_buf *rbuf) 3066void i40iw_receive_ilq(struct i40iw_sc_vsi *vsi, struct i40iw_puda_buf *rbuf)
3048{ 3067{
3049 struct i40iw_cm_node *cm_node; 3068 struct i40iw_cm_node *cm_node;
3050 struct i40iw_cm_listener *listener; 3069 struct i40iw_cm_listener *listener;
@@ -3052,9 +3071,11 @@ void i40iw_receive_ilq(struct i40iw_sc_dev *dev, struct i40iw_puda_buf *rbuf)
3052 struct ipv6hdr *ip6h; 3071 struct ipv6hdr *ip6h;
3053 struct tcphdr *tcph; 3072 struct tcphdr *tcph;
3054 struct i40iw_cm_info cm_info; 3073 struct i40iw_cm_info cm_info;
3074 struct i40iw_sc_dev *dev = vsi->dev;
3055 struct i40iw_device *iwdev = (struct i40iw_device *)dev->back_dev; 3075 struct i40iw_device *iwdev = (struct i40iw_device *)dev->back_dev;
3056 struct i40iw_cm_core *cm_core = &iwdev->cm_core; 3076 struct i40iw_cm_core *cm_core = &iwdev->cm_core;
3057 struct vlan_ethhdr *ethh; 3077 struct vlan_ethhdr *ethh;
3078 u16 vtag;
3058 3079
3059 /* if vlan, then maclen = 18 else 14 */ 3080 /* if vlan, then maclen = 18 else 14 */
3060 iph = (struct iphdr *)rbuf->iph; 3081 iph = (struct iphdr *)rbuf->iph;
@@ -3068,7 +3089,9 @@ void i40iw_receive_ilq(struct i40iw_sc_dev *dev, struct i40iw_puda_buf *rbuf)
3068 ethh = (struct vlan_ethhdr *)rbuf->mem.va; 3089 ethh = (struct vlan_ethhdr *)rbuf->mem.va;
3069 3090
3070 if (ethh->h_vlan_proto == htons(ETH_P_8021Q)) { 3091 if (ethh->h_vlan_proto == htons(ETH_P_8021Q)) {
3071 cm_info.vlan_id = ntohs(ethh->h_vlan_TCI) & VLAN_VID_MASK; 3092 vtag = ntohs(ethh->h_vlan_TCI);
3093 cm_info.user_pri = (vtag & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
3094 cm_info.vlan_id = vtag & VLAN_VID_MASK;
3072 i40iw_debug(cm_core->dev, 3095 i40iw_debug(cm_core->dev,
3073 I40IW_DEBUG_CM, 3096 I40IW_DEBUG_CM,
3074 "%s vlan_id=%d\n", 3097 "%s vlan_id=%d\n",
@@ -3083,6 +3106,7 @@ void i40iw_receive_ilq(struct i40iw_sc_dev *dev, struct i40iw_puda_buf *rbuf)
3083 cm_info.loc_addr[0] = ntohl(iph->daddr); 3106 cm_info.loc_addr[0] = ntohl(iph->daddr);
3084 cm_info.rem_addr[0] = ntohl(iph->saddr); 3107 cm_info.rem_addr[0] = ntohl(iph->saddr);
3085 cm_info.ipv4 = true; 3108 cm_info.ipv4 = true;
3109 cm_info.tos = iph->tos;
3086 } else { 3110 } else {
3087 ip6h = (struct ipv6hdr *)rbuf->iph; 3111 ip6h = (struct ipv6hdr *)rbuf->iph;
3088 i40iw_copy_ip_ntohl(cm_info.loc_addr, 3112 i40iw_copy_ip_ntohl(cm_info.loc_addr,
@@ -3090,6 +3114,7 @@ void i40iw_receive_ilq(struct i40iw_sc_dev *dev, struct i40iw_puda_buf *rbuf)
3090 i40iw_copy_ip_ntohl(cm_info.rem_addr, 3114 i40iw_copy_ip_ntohl(cm_info.rem_addr,
3091 ip6h->saddr.in6_u.u6_addr32); 3115 ip6h->saddr.in6_u.u6_addr32);
3092 cm_info.ipv4 = false; 3116 cm_info.ipv4 = false;
3117 cm_info.tos = (ip6h->priority << 4) | (ip6h->flow_lbl[0] >> 4);
3093 } 3118 }
3094 cm_info.loc_port = ntohs(tcph->dest); 3119 cm_info.loc_port = ntohs(tcph->dest);
3095 cm_info.rem_port = ntohs(tcph->source); 3120 cm_info.rem_port = ntohs(tcph->source);
@@ -3309,6 +3334,8 @@ static void i40iw_cm_init_tsa_conn(struct i40iw_qp *iwqp,
3309 3334
3310 ctx_info->tcp_info_valid = true; 3335 ctx_info->tcp_info_valid = true;
3311 ctx_info->iwarp_info_valid = true; 3336 ctx_info->iwarp_info_valid = true;
3337 ctx_info->add_to_qoslist = true;
3338 ctx_info->user_pri = cm_node->user_pri;
3312 3339
3313 i40iw_init_tcp_ctx(cm_node, &tcp_info, iwqp); 3340 i40iw_init_tcp_ctx(cm_node, &tcp_info, iwqp);
3314 if (cm_node->snd_mark_en) { 3341 if (cm_node->snd_mark_en) {
@@ -3320,33 +3347,47 @@ static void i40iw_cm_init_tsa_conn(struct i40iw_qp *iwqp,
3320 cm_node->state = I40IW_CM_STATE_OFFLOADED; 3347 cm_node->state = I40IW_CM_STATE_OFFLOADED;
3321 tcp_info.tcp_state = I40IW_TCP_STATE_ESTABLISHED; 3348 tcp_info.tcp_state = I40IW_TCP_STATE_ESTABLISHED;
3322 tcp_info.src_mac_addr_idx = iwdev->mac_ip_table_idx; 3349 tcp_info.src_mac_addr_idx = iwdev->mac_ip_table_idx;
3350 tcp_info.tos = cm_node->tos;
3323 3351
3324 dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp, (u64 *)(iwqp->host_ctx.va), ctx_info); 3352 dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp, (u64 *)(iwqp->host_ctx.va), ctx_info);
3325 3353
3326 /* once tcp_info is set, no need to do it again */ 3354 /* once tcp_info is set, no need to do it again */
3327 ctx_info->tcp_info_valid = false; 3355 ctx_info->tcp_info_valid = false;
3328 ctx_info->iwarp_info_valid = false; 3356 ctx_info->iwarp_info_valid = false;
3357 ctx_info->add_to_qoslist = false;
3329} 3358}
3330 3359
3331/** 3360/**
3332 * i40iw_cm_disconn - when a connection is being closed 3361 * i40iw_cm_disconn - when a connection is being closed
3333 * @iwqp: associate qp for the connection 3362 * @iwqp: associate qp for the connection
3334 */ 3363 */
3335int i40iw_cm_disconn(struct i40iw_qp *iwqp) 3364void i40iw_cm_disconn(struct i40iw_qp *iwqp)
3336{ 3365{
3337 struct disconn_work *work; 3366 struct disconn_work *work;
3338 struct i40iw_device *iwdev = iwqp->iwdev; 3367 struct i40iw_device *iwdev = iwqp->iwdev;
3339 struct i40iw_cm_core *cm_core = &iwdev->cm_core; 3368 struct i40iw_cm_core *cm_core = &iwdev->cm_core;
3369 unsigned long flags;
3340 3370
3341 work = kzalloc(sizeof(*work), GFP_ATOMIC); 3371 work = kzalloc(sizeof(*work), GFP_ATOMIC);
3342 if (!work) 3372 if (!work)
3343 return -ENOMEM; /* Timer will clean up */ 3373 return; /* Timer will clean up */
3344 3374
3375 spin_lock_irqsave(&iwdev->qptable_lock, flags);
3376 if (!iwdev->qp_table[iwqp->ibqp.qp_num]) {
3377 spin_unlock_irqrestore(&iwdev->qptable_lock, flags);
3378 i40iw_debug(&iwdev->sc_dev, I40IW_DEBUG_CM,
3379 "%s qp_id %d is already freed\n",
3380 __func__, iwqp->ibqp.qp_num);
3381 kfree(work);
3382 return;
3383 }
3345 i40iw_add_ref(&iwqp->ibqp); 3384 i40iw_add_ref(&iwqp->ibqp);
3385 spin_unlock_irqrestore(&iwdev->qptable_lock, flags);
3386
3346 work->iwqp = iwqp; 3387 work->iwqp = iwqp;
3347 INIT_WORK(&work->work, i40iw_disconnect_worker); 3388 INIT_WORK(&work->work, i40iw_disconnect_worker);
3348 queue_work(cm_core->disconn_wq, &work->work); 3389 queue_work(cm_core->disconn_wq, &work->work);
3349 return 0; 3390 return;
3350} 3391}
3351 3392
3352/** 3393/**
@@ -3432,7 +3473,7 @@ static void i40iw_cm_disconn_true(struct i40iw_qp *iwqp)
3432 *terminate-handler to issue cm_disconn which can re-free 3473 *terminate-handler to issue cm_disconn which can re-free
3433 *a QP even after its refcnt=0. 3474 *a QP even after its refcnt=0.
3434 */ 3475 */
3435 del_timer(&iwqp->terminate_timer); 3476 i40iw_terminate_del_timer(qp);
3436 if (!iwqp->flush_issued) { 3477 if (!iwqp->flush_issued) {
3437 iwqp->flush_issued = 1; 3478 iwqp->flush_issued = 1;
3438 issue_flush = 1; 3479 issue_flush = 1;
@@ -3462,7 +3503,7 @@ static void i40iw_cm_disconn_true(struct i40iw_qp *iwqp)
3462 /* Flush the queues */ 3503 /* Flush the queues */
3463 i40iw_flush_wqes(iwdev, iwqp); 3504 i40iw_flush_wqes(iwdev, iwqp);
3464 3505
3465 if (qp->term_flags) { 3506 if (qp->term_flags && iwqp->ibqp.event_handler) {
3466 ibevent.device = iwqp->ibqp.device; 3507 ibevent.device = iwqp->ibqp.device;
3467 ibevent.event = (qp->eventtype == TERM_EVENT_QP_FATAL) ? 3508 ibevent.event = (qp->eventtype == TERM_EVENT_QP_FATAL) ?
3468 IB_EVENT_QP_FATAL : IB_EVENT_QP_ACCESS_ERR; 3509 IB_EVENT_QP_FATAL : IB_EVENT_QP_ACCESS_ERR;
@@ -3571,7 +3612,7 @@ int i40iw_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3571 iwqp->cm_node = (void *)cm_node; 3612 iwqp->cm_node = (void *)cm_node;
3572 cm_node->iwqp = iwqp; 3613 cm_node->iwqp = iwqp;
3573 3614
3574 buf_len = conn_param->private_data_len + I40IW_MAX_IETF_SIZE + MPA_ZERO_PAD_LEN; 3615 buf_len = conn_param->private_data_len + I40IW_MAX_IETF_SIZE;
3575 3616
3576 status = i40iw_allocate_dma_mem(dev->hw, &iwqp->ietf_mem, buf_len, 1); 3617 status = i40iw_allocate_dma_mem(dev->hw, &iwqp->ietf_mem, buf_len, 1);
3577 3618
@@ -3605,18 +3646,10 @@ int i40iw_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3605 iwqp->lsmm_mr = ibmr; 3646 iwqp->lsmm_mr = ibmr;
3606 if (iwqp->page) 3647 if (iwqp->page)
3607 iwqp->sc_qp.qp_uk.sq_base = kmap(iwqp->page); 3648 iwqp->sc_qp.qp_uk.sq_base = kmap(iwqp->page);
3608 if (is_remote_ne020_or_chelsio(cm_node)) 3649 dev->iw_priv_qp_ops->qp_send_lsmm(&iwqp->sc_qp,
3609 dev->iw_priv_qp_ops->qp_send_lsmm(
3610 &iwqp->sc_qp,
3611 iwqp->ietf_mem.va, 3650 iwqp->ietf_mem.va,
3612 (accept.size + conn_param->private_data_len), 3651 (accept.size + conn_param->private_data_len),
3613 ibmr->lkey); 3652 ibmr->lkey);
3614 else
3615 dev->iw_priv_qp_ops->qp_send_lsmm(
3616 &iwqp->sc_qp,
3617 iwqp->ietf_mem.va,
3618 (accept.size + conn_param->private_data_len + MPA_ZERO_PAD_LEN),
3619 ibmr->lkey);
3620 3653
3621 } else { 3654 } else {
3622 if (iwqp->page) 3655 if (iwqp->page)
@@ -3714,6 +3747,7 @@ int i40iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3714 struct sockaddr_in6 *raddr6; 3747 struct sockaddr_in6 *raddr6;
3715 bool qhash_set = false; 3748 bool qhash_set = false;
3716 int apbvt_set = 0; 3749 int apbvt_set = 0;
3750 int err = 0;
3717 enum i40iw_status_code status; 3751 enum i40iw_status_code status;
3718 3752
3719 ibqp = i40iw_get_qp(cm_id->device, conn_param->qpn); 3753 ibqp = i40iw_get_qp(cm_id->device, conn_param->qpn);
@@ -3759,6 +3793,10 @@ int i40iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3759 i40iw_netdev_vlan_ipv6(cm_info.loc_addr, &cm_info.vlan_id, NULL); 3793 i40iw_netdev_vlan_ipv6(cm_info.loc_addr, &cm_info.vlan_id, NULL);
3760 } 3794 }
3761 cm_info.cm_id = cm_id; 3795 cm_info.cm_id = cm_id;
3796 cm_info.tos = cm_id->tos;
3797 cm_info.user_pri = rt_tos2priority(cm_id->tos);
3798 i40iw_debug(&iwdev->sc_dev, I40IW_DEBUG_DCB, "%s TOS:[%d] UP:[%d]\n",
3799 __func__, cm_id->tos, cm_info.user_pri);
3762 if ((cm_info.ipv4 && (laddr->sin_addr.s_addr != raddr->sin_addr.s_addr)) || 3800 if ((cm_info.ipv4 && (laddr->sin_addr.s_addr != raddr->sin_addr.s_addr)) ||
3763 (!cm_info.ipv4 && memcmp(laddr6->sin6_addr.in6_u.u6_addr32, 3801 (!cm_info.ipv4 && memcmp(laddr6->sin6_addr.in6_u.u6_addr32,
3764 raddr6->sin6_addr.in6_u.u6_addr32, 3802 raddr6->sin6_addr.in6_u.u6_addr32,
@@ -3790,8 +3828,11 @@ int i40iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3790 conn_param->private_data_len, 3828 conn_param->private_data_len,
3791 (void *)conn_param->private_data, 3829 (void *)conn_param->private_data,
3792 &cm_info); 3830 &cm_info);
3793 if (!cm_node) 3831
3794 goto err; 3832 if (IS_ERR(cm_node)) {
3833 err = PTR_ERR(cm_node);
3834 goto err_out;
3835 }
3795 3836
3796 i40iw_record_ird_ord(cm_node, (u16)conn_param->ird, (u16)conn_param->ord); 3837 i40iw_record_ird_ord(cm_node, (u16)conn_param->ird, (u16)conn_param->ord);
3797 if (cm_node->send_rdma0_op == SEND_RDMA_READ_ZERO && 3838 if (cm_node->send_rdma0_op == SEND_RDMA_READ_ZERO &&
@@ -3805,10 +3846,12 @@ int i40iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3805 iwqp->cm_id = cm_id; 3846 iwqp->cm_id = cm_id;
3806 i40iw_add_ref(&iwqp->ibqp); 3847 i40iw_add_ref(&iwqp->ibqp);
3807 3848
3808 if (cm_node->state == I40IW_CM_STATE_SYN_SENT) { 3849 if (cm_node->state != I40IW_CM_STATE_OFFLOADED) {
3809 if (i40iw_send_syn(cm_node, 0)) { 3850 cm_node->state = I40IW_CM_STATE_SYN_SENT;
3851 err = i40iw_send_syn(cm_node, 0);
3852 if (err) {
3810 i40iw_rem_ref_cm_node(cm_node); 3853 i40iw_rem_ref_cm_node(cm_node);
3811 goto err; 3854 goto err_out;
3812 } 3855 }
3813 } 3856 }
3814 3857
@@ -3820,24 +3863,25 @@ int i40iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
3820 cm_node->cm_id); 3863 cm_node->cm_id);
3821 return 0; 3864 return 0;
3822 3865
3823err: 3866err_out:
3824 if (cm_node) { 3867 if (cm_info.ipv4)
3825 if (cm_node->ipv4) 3868 i40iw_debug(&iwdev->sc_dev,
3826 i40iw_debug(cm_node->dev, 3869 I40IW_DEBUG_CM,
3827 I40IW_DEBUG_CM, 3870 "Api - connect() FAILED: dest addr=%pI4",
3828 "Api - connect() FAILED: dest addr=%pI4", 3871 cm_info.rem_addr);
3829 cm_node->rem_addr); 3872 else
3830 else 3873 i40iw_debug(&iwdev->sc_dev,
3831 i40iw_debug(cm_node->dev, I40IW_DEBUG_CM, 3874 I40IW_DEBUG_CM,
3832 "Api - connect() FAILED: dest addr=%pI6", 3875 "Api - connect() FAILED: dest addr=%pI6",
3833 cm_node->rem_addr); 3876 cm_info.rem_addr);
3834 } 3877
3835 i40iw_manage_qhash(iwdev, 3878 if (qhash_set)
3836 &cm_info, 3879 i40iw_manage_qhash(iwdev,
3837 I40IW_QHASH_TYPE_TCP_ESTABLISHED, 3880 &cm_info,
3838 I40IW_QHASH_MANAGE_TYPE_DELETE, 3881 I40IW_QHASH_TYPE_TCP_ESTABLISHED,
3839 NULL, 3882 I40IW_QHASH_MANAGE_TYPE_DELETE,
3840 false); 3883 NULL,
3884 false);
3841 3885
3842 if (apbvt_set && !i40iw_listen_port_in_use(&iwdev->cm_core, 3886 if (apbvt_set && !i40iw_listen_port_in_use(&iwdev->cm_core,
3843 cm_info.loc_port)) 3887 cm_info.loc_port))
@@ -3846,7 +3890,7 @@ err:
3846 I40IW_MANAGE_APBVT_DEL); 3890 I40IW_MANAGE_APBVT_DEL);
3847 cm_id->rem_ref(cm_id); 3891 cm_id->rem_ref(cm_id);
3848 iwdev->cm_core.stats_connect_errs++; 3892 iwdev->cm_core.stats_connect_errs++;
3849 return -ENOMEM; 3893 return err;
3850} 3894}
3851 3895
3852/** 3896/**
@@ -3904,6 +3948,10 @@ int i40iw_create_listen(struct iw_cm_id *cm_id, int backlog)
3904 3948
3905 cm_id->provider_data = cm_listen_node; 3949 cm_id->provider_data = cm_listen_node;
3906 3950
3951 cm_listen_node->tos = cm_id->tos;
3952 cm_listen_node->user_pri = rt_tos2priority(cm_id->tos);
3953 cm_info.user_pri = cm_listen_node->user_pri;
3954
3907 if (!cm_listen_node->reused_node) { 3955 if (!cm_listen_node->reused_node) {
3908 if (wildcard) { 3956 if (wildcard) {
3909 if (cm_info.ipv4) 3957 if (cm_info.ipv4)
@@ -4124,3 +4172,158 @@ static void i40iw_cm_post_event(struct i40iw_cm_event *event)
4124 4172
4125 queue_work(event->cm_node->cm_core->event_wq, &event->event_work); 4173 queue_work(event->cm_node->cm_core->event_wq, &event->event_work);
4126} 4174}
4175
4176/**
4177 * i40iw_qhash_ctrl - enable/disable qhash for list
4178 * @iwdev: device pointer
4179 * @parent_listen_node: parent listen node
4180 * @nfo: cm info node
4181 * @ipaddr: Pointer to IPv4 or IPv6 address
4182 * @ipv4: flag indicating IPv4 when true
4183 * @ifup: flag indicating interface up when true
4184 *
4185 * Enables or disables the qhash for the node in the child
4186 * listen list that matches ipaddr. If no matching IP was found
4187 * it will allocate and add a new child listen node to the
4188 * parent listen node. The listen_list_lock is assumed to be
4189 * held when called.
4190 */
4191static void i40iw_qhash_ctrl(struct i40iw_device *iwdev,
4192 struct i40iw_cm_listener *parent_listen_node,
4193 struct i40iw_cm_info *nfo,
4194 u32 *ipaddr, bool ipv4, bool ifup)
4195{
4196 struct list_head *child_listen_list = &parent_listen_node->child_listen_list;
4197 struct i40iw_cm_listener *child_listen_node;
4198 struct list_head *pos, *tpos;
4199 enum i40iw_status_code ret;
4200 bool node_allocated = false;
4201 enum i40iw_quad_hash_manage_type op =
4202 ifup ? I40IW_QHASH_MANAGE_TYPE_ADD : I40IW_QHASH_MANAGE_TYPE_DELETE;
4203
4204 list_for_each_safe(pos, tpos, child_listen_list) {
4205 child_listen_node =
4206 list_entry(pos,
4207 struct i40iw_cm_listener,
4208 child_listen_list);
4209 if (!memcmp(child_listen_node->loc_addr, ipaddr, ipv4 ? 4 : 16))
4210 goto set_qhash;
4211 }
4212
4213 /* if not found then add a child listener if interface is going up */
4214 if (!ifup)
4215 return;
4216 child_listen_node = kzalloc(sizeof(*child_listen_node), GFP_ATOMIC);
4217 if (!child_listen_node)
4218 return;
4219 node_allocated = true;
4220 memcpy(child_listen_node, parent_listen_node, sizeof(*child_listen_node));
4221
4222 memcpy(child_listen_node->loc_addr, ipaddr, ipv4 ? 4 : 16);
4223
4224set_qhash:
4225 memcpy(nfo->loc_addr,
4226 child_listen_node->loc_addr,
4227 sizeof(nfo->loc_addr));
4228 nfo->vlan_id = child_listen_node->vlan_id;
4229 ret = i40iw_manage_qhash(iwdev, nfo,
4230 I40IW_QHASH_TYPE_TCP_SYN,
4231 op,
4232 NULL, false);
4233 if (!ret) {
4234 child_listen_node->qhash_set = ifup;
4235 if (node_allocated)
4236 list_add(&child_listen_node->child_listen_list,
4237 &parent_listen_node->child_listen_list);
4238 } else if (node_allocated) {
4239 kfree(child_listen_node);
4240 }
4241}
4242
4243/**
4244 * i40iw_cm_disconnect_all - disconnect all connected qp's
4245 * @iwdev: device pointer
4246 */
4247void i40iw_cm_disconnect_all(struct i40iw_device *iwdev)
4248{
4249 struct i40iw_cm_core *cm_core = &iwdev->cm_core;
4250 struct list_head *list_core_temp;
4251 struct list_head *list_node;
4252 struct i40iw_cm_node *cm_node;
4253 unsigned long flags;
4254 struct list_head connected_list;
4255 struct ib_qp_attr attr;
4256
4257 INIT_LIST_HEAD(&connected_list);
4258 spin_lock_irqsave(&cm_core->ht_lock, flags);
4259 list_for_each_safe(list_node, list_core_temp, &cm_core->connected_nodes) {
4260 cm_node = container_of(list_node, struct i40iw_cm_node, list);
4261 atomic_inc(&cm_node->ref_count);
4262 list_add(&cm_node->connected_entry, &connected_list);
4263 }
4264 spin_unlock_irqrestore(&cm_core->ht_lock, flags);
4265
4266 list_for_each_safe(list_node, list_core_temp, &connected_list) {
4267 cm_node = container_of(list_node, struct i40iw_cm_node, connected_entry);
4268 attr.qp_state = IB_QPS_ERR;
4269 i40iw_modify_qp(&cm_node->iwqp->ibqp, &attr, IB_QP_STATE, NULL);
4270 i40iw_rem_ref_cm_node(cm_node);
4271 }
4272}
4273
4274/**
4275 * i40iw_ifdown_notify - process an ifdown on an interface
4276 * @iwdev: device pointer
4277 * @ipaddr: Pointer to IPv4 or IPv6 address
4278 * @ipv4: flag indicating IPv4 when true
4279 * @ifup: flag indicating interface up when true
4280 */
4281void i40iw_if_notify(struct i40iw_device *iwdev, struct net_device *netdev,
4282 u32 *ipaddr, bool ipv4, bool ifup)
4283{
4284 struct i40iw_cm_core *cm_core = &iwdev->cm_core;
4285 unsigned long flags;
4286 struct i40iw_cm_listener *listen_node;
4287 static const u32 ip_zero[4] = { 0, 0, 0, 0 };
4288 struct i40iw_cm_info nfo;
4289 u16 vlan_id = rdma_vlan_dev_vlan_id(netdev);
4290 enum i40iw_status_code ret;
4291 enum i40iw_quad_hash_manage_type op =
4292 ifup ? I40IW_QHASH_MANAGE_TYPE_ADD : I40IW_QHASH_MANAGE_TYPE_DELETE;
4293
4294 /* Disable or enable qhash for listeners */
4295 spin_lock_irqsave(&cm_core->listen_list_lock, flags);
4296 list_for_each_entry(listen_node, &cm_core->listen_nodes, list) {
4297 if (vlan_id == listen_node->vlan_id &&
4298 (!memcmp(listen_node->loc_addr, ipaddr, ipv4 ? 4 : 16) ||
4299 !memcmp(listen_node->loc_addr, ip_zero, ipv4 ? 4 : 16))) {
4300 memcpy(nfo.loc_addr, listen_node->loc_addr,
4301 sizeof(nfo.loc_addr));
4302 nfo.loc_port = listen_node->loc_port;
4303 nfo.ipv4 = listen_node->ipv4;
4304 nfo.vlan_id = listen_node->vlan_id;
4305 nfo.user_pri = listen_node->user_pri;
4306 if (!list_empty(&listen_node->child_listen_list)) {
4307 i40iw_qhash_ctrl(iwdev,
4308 listen_node,
4309 &nfo,
4310 ipaddr, ipv4, ifup);
4311 } else if (memcmp(listen_node->loc_addr, ip_zero,
4312 ipv4 ? 4 : 16)) {
4313 ret = i40iw_manage_qhash(iwdev,
4314 &nfo,
4315 I40IW_QHASH_TYPE_TCP_SYN,
4316 op,
4317 NULL,
4318 false);
4319 if (!ret)
4320 listen_node->qhash_set = ifup;
4321 }
4322 }
4323 }
4324 spin_unlock_irqrestore(&cm_core->listen_list_lock, flags);
4325
4326 /* disconnect any connected qp's on ifdown */
4327 if (!ifup)
4328 i40iw_cm_disconnect_all(iwdev);
4329}
diff --git a/drivers/infiniband/hw/i40iw/i40iw_cm.h b/drivers/infiniband/hw/i40iw/i40iw_cm.h
index e9046d9f9645..2e52e38ffcf3 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_cm.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_cm.h
@@ -56,8 +56,6 @@
56 56
57#define I40IW_MAX_IETF_SIZE 32 57#define I40IW_MAX_IETF_SIZE 32
58 58
59#define MPA_ZERO_PAD_LEN 4
60
61/* IETF RTR MSG Fields */ 59/* IETF RTR MSG Fields */
62#define IETF_PEER_TO_PEER 0x8000 60#define IETF_PEER_TO_PEER 0x8000
63#define IETF_FLPDU_ZERO_LEN 0x4000 61#define IETF_FLPDU_ZERO_LEN 0x4000
@@ -299,6 +297,7 @@ struct i40iw_cm_listener {
299 enum i40iw_cm_listener_state listener_state; 297 enum i40iw_cm_listener_state listener_state;
300 u32 reused_node; 298 u32 reused_node;
301 u8 user_pri; 299 u8 user_pri;
300 u8 tos;
302 u16 vlan_id; 301 u16 vlan_id;
303 bool qhash_set; 302 bool qhash_set;
304 bool ipv4; 303 bool ipv4;
@@ -341,9 +340,11 @@ struct i40iw_cm_node {
341 int accept_pend; 340 int accept_pend;
342 struct list_head timer_entry; 341 struct list_head timer_entry;
343 struct list_head reset_entry; 342 struct list_head reset_entry;
343 struct list_head connected_entry;
344 atomic_t passive_state; 344 atomic_t passive_state;
345 bool qhash_set; 345 bool qhash_set;
346 u8 user_pri; 346 u8 user_pri;
347 u8 tos;
347 bool ipv4; 348 bool ipv4;
348 bool snd_mark_en; 349 bool snd_mark_en;
349 u16 lsmm_size; 350 u16 lsmm_size;
@@ -368,7 +369,8 @@ struct i40iw_cm_info {
368 u32 rem_addr[4]; 369 u32 rem_addr[4];
369 u16 vlan_id; 370 u16 vlan_id;
370 int backlog; 371 int backlog;
371 u16 user_pri; 372 u8 user_pri;
373 u8 tos;
372 bool ipv4; 374 bool ipv4;
373}; 375};
374 376
@@ -445,4 +447,7 @@ int i40iw_arp_table(struct i40iw_device *iwdev,
445 u8 *mac_addr, 447 u8 *mac_addr,
446 u32 action); 448 u32 action);
447 449
450void i40iw_if_notify(struct i40iw_device *iwdev, struct net_device *netdev,
451 u32 *ipaddr, bool ipv4, bool ifup);
452void i40iw_cm_disconnect_all(struct i40iw_device *iwdev);
448#endif /* I40IW_CM_H */ 453#endif /* I40IW_CM_H */
diff --git a/drivers/infiniband/hw/i40iw/i40iw_ctrl.c b/drivers/infiniband/hw/i40iw/i40iw_ctrl.c
index 2c4b4d072d6a..392f78384a60 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_ctrl.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_ctrl.c
@@ -103,6 +103,7 @@ static enum i40iw_status_code i40iw_cqp_poll_registers(
103 if (newtail != tail) { 103 if (newtail != tail) {
104 /* SUCCESS */ 104 /* SUCCESS */
105 I40IW_RING_MOVE_TAIL(cqp->sq_ring); 105 I40IW_RING_MOVE_TAIL(cqp->sq_ring);
106 cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]++;
106 return 0; 107 return 0;
107 } 108 }
108 udelay(I40IW_SLEEP_COUNT); 109 udelay(I40IW_SLEEP_COUNT);
@@ -223,6 +224,136 @@ static enum i40iw_status_code i40iw_sc_parse_fpm_query_buf(
223} 224}
224 225
225/** 226/**
227 * i40iw_fill_qos_list - Change all unknown qs handles to available ones
228 * @qs_list: list of qs_handles to be fixed with valid qs_handles
229 */
230static void i40iw_fill_qos_list(u16 *qs_list)
231{
232 u16 qshandle = qs_list[0];
233 int i;
234
235 for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
236 if (qs_list[i] == QS_HANDLE_UNKNOWN)
237 qs_list[i] = qshandle;
238 else
239 qshandle = qs_list[i];
240 }
241}
242
243/**
244 * i40iw_qp_from_entry - Given entry, get to the qp structure
245 * @entry: Points to list of qp structure
246 */
247static struct i40iw_sc_qp *i40iw_qp_from_entry(struct list_head *entry)
248{
249 if (!entry)
250 return NULL;
251
252 return (struct i40iw_sc_qp *)((char *)entry - offsetof(struct i40iw_sc_qp, list));
253}
254
255/**
256 * i40iw_get_qp - get the next qp from the list given current qp
257 * @head: Listhead of qp's
258 * @qp: current qp
259 */
260static struct i40iw_sc_qp *i40iw_get_qp(struct list_head *head, struct i40iw_sc_qp *qp)
261{
262 struct list_head *entry = NULL;
263 struct list_head *lastentry;
264
265 if (list_empty(head))
266 return NULL;
267
268 if (!qp) {
269 entry = head->next;
270 } else {
271 lastentry = &qp->list;
272 entry = (lastentry != head) ? lastentry->next : NULL;
273 }
274
275 return i40iw_qp_from_entry(entry);
276}
277
278/**
279 * i40iw_change_l2params - given the new l2 parameters, change all qp
280 * @vsi: pointer to the vsi structure
281 * @l2params: New paramaters from l2
282 */
283void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2params)
284{
285 struct i40iw_sc_dev *dev = vsi->dev;
286 struct i40iw_sc_qp *qp = NULL;
287 bool qs_handle_change = false;
288 bool mss_change = false;
289 unsigned long flags;
290 u16 qs_handle;
291 int i;
292
293 if (vsi->mss != l2params->mss) {
294 mss_change = true;
295 vsi->mss = l2params->mss;
296 }
297
298 i40iw_fill_qos_list(l2params->qs_handle_list);
299 for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
300 qs_handle = l2params->qs_handle_list[i];
301 if (vsi->qos[i].qs_handle != qs_handle)
302 qs_handle_change = true;
303 else if (!mss_change)
304 continue; /* no MSS nor qs handle change */
305 spin_lock_irqsave(&vsi->qos[i].lock, flags);
306 qp = i40iw_get_qp(&vsi->qos[i].qplist, qp);
307 while (qp) {
308 if (mss_change)
309 i40iw_qp_mss_modify(dev, qp);
310 if (qs_handle_change) {
311 qp->qs_handle = qs_handle;
312 /* issue cqp suspend command */
313 i40iw_qp_suspend_resume(dev, qp, true);
314 }
315 qp = i40iw_get_qp(&vsi->qos[i].qplist, qp);
316 }
317 spin_unlock_irqrestore(&vsi->qos[i].lock, flags);
318 vsi->qos[i].qs_handle = qs_handle;
319 }
320}
321
322/**
323 * i40iw_qp_rem_qos - remove qp from qos lists during destroy qp
324 * @qp: qp to be removed from qos
325 */
326static void i40iw_qp_rem_qos(struct i40iw_sc_qp *qp)
327{
328 struct i40iw_sc_vsi *vsi = qp->vsi;
329 unsigned long flags;
330
331 if (!qp->on_qoslist)
332 return;
333 spin_lock_irqsave(&vsi->qos[qp->user_pri].lock, flags);
334 list_del(&qp->list);
335 spin_unlock_irqrestore(&vsi->qos[qp->user_pri].lock, flags);
336}
337
338/**
339 * i40iw_qp_add_qos - called during setctx fot qp to be added to qos
340 * @qp: qp to be added to qos
341 */
342void i40iw_qp_add_qos(struct i40iw_sc_qp *qp)
343{
344 struct i40iw_sc_vsi *vsi = qp->vsi;
345 unsigned long flags;
346
347 if (qp->on_qoslist)
348 return;
349 spin_lock_irqsave(&vsi->qos[qp->user_pri].lock, flags);
350 qp->qs_handle = vsi->qos[qp->user_pri].qs_handle;
351 list_add(&qp->list, &vsi->qos[qp->user_pri].qplist);
352 qp->on_qoslist = true;
353 spin_unlock_irqrestore(&vsi->qos[qp->user_pri].lock, flags);
354}
355
356/**
226 * i40iw_sc_pd_init - initialize sc pd struct 357 * i40iw_sc_pd_init - initialize sc pd struct
227 * @dev: sc device struct 358 * @dev: sc device struct
228 * @pd: sc pd ptr 359 * @pd: sc pd ptr
@@ -292,6 +423,9 @@ static enum i40iw_status_code i40iw_sc_cqp_init(struct i40iw_sc_cqp *cqp,
292 info->dev->cqp = cqp; 423 info->dev->cqp = cqp;
293 424
294 I40IW_RING_INIT(cqp->sq_ring, cqp->sq_size); 425 I40IW_RING_INIT(cqp->sq_ring, cqp->sq_size);
426 cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS] = 0;
427 cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS] = 0;
428
295 i40iw_debug(cqp->dev, I40IW_DEBUG_WQE, 429 i40iw_debug(cqp->dev, I40IW_DEBUG_WQE,
296 "%s: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%llxh] cqp[%p] polarity[x%04X]\n", 430 "%s: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%llxh] cqp[%p] polarity[x%04X]\n",
297 __func__, cqp->sq_size, cqp->hw_sq_size, 431 __func__, cqp->sq_size, cqp->hw_sq_size,
@@ -302,12 +436,10 @@ static enum i40iw_status_code i40iw_sc_cqp_init(struct i40iw_sc_cqp *cqp,
302/** 436/**
303 * i40iw_sc_cqp_create - create cqp during bringup 437 * i40iw_sc_cqp_create - create cqp during bringup
304 * @cqp: struct for cqp hw 438 * @cqp: struct for cqp hw
305 * @disable_pfpdus: if pfpdu to be disabled
306 * @maj_err: If error, major err number 439 * @maj_err: If error, major err number
307 * @min_err: If error, minor err number 440 * @min_err: If error, minor err number
308 */ 441 */
309static enum i40iw_status_code i40iw_sc_cqp_create(struct i40iw_sc_cqp *cqp, 442static enum i40iw_status_code i40iw_sc_cqp_create(struct i40iw_sc_cqp *cqp,
310 bool disable_pfpdus,
311 u16 *maj_err, 443 u16 *maj_err,
312 u16 *min_err) 444 u16 *min_err)
313{ 445{
@@ -326,9 +458,6 @@ static enum i40iw_status_code i40iw_sc_cqp_create(struct i40iw_sc_cqp *cqp,
326 temp = LS_64(cqp->hw_sq_size, I40IW_CQPHC_SQSIZE) | 458 temp = LS_64(cqp->hw_sq_size, I40IW_CQPHC_SQSIZE) |
327 LS_64(cqp->struct_ver, I40IW_CQPHC_SVER); 459 LS_64(cqp->struct_ver, I40IW_CQPHC_SVER);
328 460
329 if (disable_pfpdus)
330 temp |= LS_64(1, I40IW_CQPHC_DISABLE_PFPDUS);
331
332 set_64bit_val(cqp->host_ctx, 0, temp); 461 set_64bit_val(cqp->host_ctx, 0, temp);
333 set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa); 462 set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa);
334 temp = LS_64(cqp->enabled_vf_count, I40IW_CQPHC_ENABLED_VFS) | 463 temp = LS_64(cqp->enabled_vf_count, I40IW_CQPHC_ENABLED_VFS) |
@@ -424,6 +553,7 @@ u64 *i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp *cqp, u64 scratch)
424 return NULL; 553 return NULL;
425 } 554 }
426 I40IW_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, wqe_idx, ret_code); 555 I40IW_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, wqe_idx, ret_code);
556 cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS]++;
427 if (ret_code) 557 if (ret_code)
428 return NULL; 558 return NULL;
429 if (!wqe_idx) 559 if (!wqe_idx)
@@ -559,6 +689,8 @@ static enum i40iw_status_code i40iw_sc_ccq_get_cqe_info(
559 I40IW_RING_GETCURRENT_HEAD(ccq->cq_uk.cq_ring)); 689 I40IW_RING_GETCURRENT_HEAD(ccq->cq_uk.cq_ring));
560 wmb(); /* write shadow area before tail */ 690 wmb(); /* write shadow area before tail */
561 I40IW_RING_MOVE_TAIL(cqp->sq_ring); 691 I40IW_RING_MOVE_TAIL(cqp->sq_ring);
692 ccq->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]++;
693
562 return ret_code; 694 return ret_code;
563} 695}
564 696
@@ -1051,6 +1183,7 @@ static enum i40iw_status_code i40iw_sc_manage_qhash_table_entry(
1051 u64 qw1 = 0; 1183 u64 qw1 = 0;
1052 u64 qw2 = 0; 1184 u64 qw2 = 0;
1053 u64 temp; 1185 u64 temp;
1186 struct i40iw_sc_vsi *vsi = info->vsi;
1054 1187
1055 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); 1188 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
1056 if (!wqe) 1189 if (!wqe)
@@ -1082,7 +1215,7 @@ static enum i40iw_status_code i40iw_sc_manage_qhash_table_entry(
1082 LS_64(info->dest_ip[2], I40IW_CQPSQ_QHASH_ADDR2) | 1215 LS_64(info->dest_ip[2], I40IW_CQPSQ_QHASH_ADDR2) |
1083 LS_64(info->dest_ip[3], I40IW_CQPSQ_QHASH_ADDR3)); 1216 LS_64(info->dest_ip[3], I40IW_CQPSQ_QHASH_ADDR3));
1084 } 1217 }
1085 qw2 = LS_64(cqp->dev->qs_handle, I40IW_CQPSQ_QHASH_QS_HANDLE); 1218 qw2 = LS_64(vsi->qos[info->user_pri].qs_handle, I40IW_CQPSQ_QHASH_QS_HANDLE);
1086 if (info->vlan_valid) 1219 if (info->vlan_valid)
1087 qw2 |= LS_64(info->vlan_id, I40IW_CQPSQ_QHASH_VLANID); 1220 qw2 |= LS_64(info->vlan_id, I40IW_CQPSQ_QHASH_VLANID);
1088 set_64bit_val(wqe, 16, qw2); 1221 set_64bit_val(wqe, 16, qw2);
@@ -2103,6 +2236,7 @@ static enum i40iw_status_code i40iw_sc_qp_init(struct i40iw_sc_qp *qp,
2103 u32 offset; 2236 u32 offset;
2104 2237
2105 qp->dev = info->pd->dev; 2238 qp->dev = info->pd->dev;
2239 qp->vsi = info->vsi;
2106 qp->sq_pa = info->sq_pa; 2240 qp->sq_pa = info->sq_pa;
2107 qp->rq_pa = info->rq_pa; 2241 qp->rq_pa = info->rq_pa;
2108 qp->hw_host_ctx_pa = info->host_ctx_pa; 2242 qp->hw_host_ctx_pa = info->host_ctx_pa;
@@ -2151,7 +2285,7 @@ static enum i40iw_status_code i40iw_sc_qp_init(struct i40iw_sc_qp *qp,
2151 qp->rq_tph_en = info->rq_tph_en; 2285 qp->rq_tph_en = info->rq_tph_en;
2152 qp->rcv_tph_en = info->rcv_tph_en; 2286 qp->rcv_tph_en = info->rcv_tph_en;
2153 qp->xmit_tph_en = info->xmit_tph_en; 2287 qp->xmit_tph_en = info->xmit_tph_en;
2154 qp->qs_handle = qp->pd->dev->qs_handle; 2288 qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle;
2155 qp->exception_lan_queue = qp->pd->dev->exception_lan_queue; 2289 qp->exception_lan_queue = qp->pd->dev->exception_lan_queue;
2156 2290
2157 return 0; 2291 return 0;
@@ -2296,6 +2430,7 @@ static enum i40iw_status_code i40iw_sc_qp_destroy(
2296 struct i40iw_sc_cqp *cqp; 2430 struct i40iw_sc_cqp *cqp;
2297 u64 header; 2431 u64 header;
2298 2432
2433 i40iw_qp_rem_qos(qp);
2299 cqp = qp->pd->dev->cqp; 2434 cqp = qp->pd->dev->cqp;
2300 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); 2435 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2301 if (!wqe) 2436 if (!wqe)
@@ -2443,10 +2578,20 @@ static enum i40iw_status_code i40iw_sc_qp_setctx(
2443{ 2578{
2444 struct i40iwarp_offload_info *iw; 2579 struct i40iwarp_offload_info *iw;
2445 struct i40iw_tcp_offload_info *tcp; 2580 struct i40iw_tcp_offload_info *tcp;
2581 struct i40iw_sc_vsi *vsi;
2582 struct i40iw_sc_dev *dev;
2446 u64 qw0, qw3, qw7 = 0; 2583 u64 qw0, qw3, qw7 = 0;
2447 2584
2448 iw = info->iwarp_info; 2585 iw = info->iwarp_info;
2449 tcp = info->tcp_info; 2586 tcp = info->tcp_info;
2587 vsi = qp->vsi;
2588 dev = qp->dev;
2589 if (info->add_to_qoslist) {
2590 qp->user_pri = info->user_pri;
2591 i40iw_qp_add_qos(qp);
2592 i40iw_debug(qp->dev, I40IW_DEBUG_DCB, "%s qp[%d] UP[%d] qset[%d]\n",
2593 __func__, qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle);
2594 }
2450 qw0 = LS_64(qp->qp_uk.rq_wqe_size, I40IWQPC_RQWQESIZE) | 2595 qw0 = LS_64(qp->qp_uk.rq_wqe_size, I40IWQPC_RQWQESIZE) |
2451 LS_64(info->err_rq_idx_valid, I40IWQPC_ERR_RQ_IDX_VALID) | 2596 LS_64(info->err_rq_idx_valid, I40IWQPC_ERR_RQ_IDX_VALID) |
2452 LS_64(qp->rcv_tph_en, I40IWQPC_RCVTPHEN) | 2597 LS_64(qp->rcv_tph_en, I40IWQPC_RCVTPHEN) |
@@ -2487,16 +2632,14 @@ static enum i40iw_status_code i40iw_sc_qp_setctx(
2487 LS_64(iw->rdmap_ver, I40IWQPC_RDMAP_VER); 2632 LS_64(iw->rdmap_ver, I40IWQPC_RDMAP_VER);
2488 2633
2489 qw7 |= LS_64(iw->pd_id, I40IWQPC_PDIDX); 2634 qw7 |= LS_64(iw->pd_id, I40IWQPC_PDIDX);
2490 set_64bit_val(qp_ctx, 144, qp->q2_pa); 2635 set_64bit_val(qp_ctx,
2636 144,
2637 LS_64(qp->q2_pa, I40IWQPC_Q2ADDR) |
2638 LS_64(vsi->fcn_id, I40IWQPC_STAT_INDEX));
2491 set_64bit_val(qp_ctx, 2639 set_64bit_val(qp_ctx,
2492 152, 2640 152,
2493 LS_64(iw->last_byte_sent, I40IWQPC_LASTBYTESENT)); 2641 LS_64(iw->last_byte_sent, I40IWQPC_LASTBYTESENT));
2494 2642
2495 /*
2496 * Hard-code IRD_SIZE to hw-limit, 128, in qpctx, i.e matching an
2497 *advertisable IRD of 64
2498 */
2499 iw->ird_size = I40IW_QPCTX_ENCD_MAXIRD;
2500 set_64bit_val(qp_ctx, 2643 set_64bit_val(qp_ctx,
2501 160, 2644 160,
2502 LS_64(iw->ord_size, I40IWQPC_ORDSIZE) | 2645 LS_64(iw->ord_size, I40IWQPC_ORDSIZE) |
@@ -2507,6 +2650,9 @@ static enum i40iw_status_code i40iw_sc_qp_setctx(
2507 LS_64(iw->bind_en, I40IWQPC_BINDEN) | 2650 LS_64(iw->bind_en, I40IWQPC_BINDEN) |
2508 LS_64(iw->fast_reg_en, I40IWQPC_FASTREGEN) | 2651 LS_64(iw->fast_reg_en, I40IWQPC_FASTREGEN) |
2509 LS_64(iw->priv_mode_en, I40IWQPC_PRIVEN) | 2652 LS_64(iw->priv_mode_en, I40IWQPC_PRIVEN) |
2653 LS_64((((vsi->stats_fcn_id_alloc) &&
2654 (dev->is_pf) && (vsi->fcn_id >= I40IW_FIRST_NON_PF_STAT)) ? 1 : 0),
2655 I40IWQPC_USESTATSINSTANCE) |
2510 LS_64(1, I40IWQPC_IWARPMODE) | 2656 LS_64(1, I40IWQPC_IWARPMODE) |
2511 LS_64(iw->rcv_mark_en, I40IWQPC_RCVMARKERS) | 2657 LS_64(iw->rcv_mark_en, I40IWQPC_RCVMARKERS) |
2512 LS_64(iw->align_hdrs, I40IWQPC_ALIGNHDRS) | 2658 LS_64(iw->align_hdrs, I40IWQPC_ALIGNHDRS) |
@@ -2623,7 +2769,9 @@ static enum i40iw_status_code i40iw_sc_alloc_stag(
2623 u64 *wqe; 2769 u64 *wqe;
2624 struct i40iw_sc_cqp *cqp; 2770 struct i40iw_sc_cqp *cqp;
2625 u64 header; 2771 u64 header;
2772 enum i40iw_page_size page_size;
2626 2773
2774 page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
2627 cqp = dev->cqp; 2775 cqp = dev->cqp;
2628 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch); 2776 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
2629 if (!wqe) 2777 if (!wqe)
@@ -2643,7 +2791,7 @@ static enum i40iw_status_code i40iw_sc_alloc_stag(
2643 LS_64(1, I40IW_CQPSQ_STAG_MR) | 2791 LS_64(1, I40IW_CQPSQ_STAG_MR) |
2644 LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) | 2792 LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
2645 LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) | 2793 LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) |
2646 LS_64(info->page_size, I40IW_CQPSQ_STAG_HPAGESIZE) | 2794 LS_64(page_size, I40IW_CQPSQ_STAG_HPAGESIZE) |
2647 LS_64(info->remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) | 2795 LS_64(info->remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) |
2648 LS_64(info->use_hmc_fcn_index, I40IW_CQPSQ_STAG_USEHMCFNIDX) | 2796 LS_64(info->use_hmc_fcn_index, I40IW_CQPSQ_STAG_USEHMCFNIDX) |
2649 LS_64(info->use_pf_rid, I40IW_CQPSQ_STAG_USEPFRID) | 2797 LS_64(info->use_pf_rid, I40IW_CQPSQ_STAG_USEPFRID) |
@@ -2679,7 +2827,9 @@ static enum i40iw_status_code i40iw_sc_mr_reg_non_shared(
2679 u32 pble_obj_cnt; 2827 u32 pble_obj_cnt;
2680 bool remote_access; 2828 bool remote_access;
2681 u8 addr_type; 2829 u8 addr_type;
2830 enum i40iw_page_size page_size;
2682 2831
2832 page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
2683 if (info->access_rights & (I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY | 2833 if (info->access_rights & (I40IW_ACCESS_FLAGS_REMOTEREAD_ONLY |
2684 I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY)) 2834 I40IW_ACCESS_FLAGS_REMOTEWRITE_ONLY))
2685 remote_access = true; 2835 remote_access = true;
@@ -2722,7 +2872,7 @@ static enum i40iw_status_code i40iw_sc_mr_reg_non_shared(
2722 header = LS_64(I40IW_CQP_OP_REG_MR, I40IW_CQPSQ_OPCODE) | 2872 header = LS_64(I40IW_CQP_OP_REG_MR, I40IW_CQPSQ_OPCODE) |
2723 LS_64(1, I40IW_CQPSQ_STAG_MR) | 2873 LS_64(1, I40IW_CQPSQ_STAG_MR) |
2724 LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) | 2874 LS_64(info->chunk_size, I40IW_CQPSQ_STAG_LPBLSIZE) |
2725 LS_64(info->page_size, I40IW_CQPSQ_STAG_HPAGESIZE) | 2875 LS_64(page_size, I40IW_CQPSQ_STAG_HPAGESIZE) |
2726 LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) | 2876 LS_64(info->access_rights, I40IW_CQPSQ_STAG_ARIGHTS) |
2727 LS_64(remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) | 2877 LS_64(remote_access, I40IW_CQPSQ_STAG_REMACCENABLED) |
2728 LS_64(addr_type, I40IW_CQPSQ_STAG_VABASEDTO) | 2878 LS_64(addr_type, I40IW_CQPSQ_STAG_VABASEDTO) |
@@ -2937,7 +3087,9 @@ enum i40iw_status_code i40iw_sc_mr_fast_register(
2937 u64 temp, header; 3087 u64 temp, header;
2938 u64 *wqe; 3088 u64 *wqe;
2939 u32 wqe_idx; 3089 u32 wqe_idx;
3090 enum i40iw_page_size page_size;
2940 3091
3092 page_size = (info->page_size == 0x200000) ? I40IW_PAGE_SIZE_2M : I40IW_PAGE_SIZE_4K;
2941 wqe = i40iw_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, I40IW_QP_WQE_MIN_SIZE, 3093 wqe = i40iw_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, I40IW_QP_WQE_MIN_SIZE,
2942 0, info->wr_id); 3094 0, info->wr_id);
2943 if (!wqe) 3095 if (!wqe)
@@ -2964,7 +3116,7 @@ enum i40iw_status_code i40iw_sc_mr_fast_register(
2964 LS_64(info->stag_idx, I40IWQPSQ_STAGINDEX) | 3116 LS_64(info->stag_idx, I40IWQPSQ_STAGINDEX) |
2965 LS_64(I40IWQP_OP_FAST_REGISTER, I40IWQPSQ_OPCODE) | 3117 LS_64(I40IWQP_OP_FAST_REGISTER, I40IWQPSQ_OPCODE) |
2966 LS_64(info->chunk_size, I40IWQPSQ_LPBLSIZE) | 3118 LS_64(info->chunk_size, I40IWQPSQ_LPBLSIZE) |
2967 LS_64(info->page_size, I40IWQPSQ_HPAGESIZE) | 3119 LS_64(page_size, I40IWQPSQ_HPAGESIZE) |
2968 LS_64(info->access_rights, I40IWQPSQ_STAGRIGHTS) | 3120 LS_64(info->access_rights, I40IWQPSQ_STAGRIGHTS) |
2969 LS_64(info->addr_type, I40IWQPSQ_VABASEDTO) | 3121 LS_64(info->addr_type, I40IWQPSQ_VABASEDTO) |
2970 LS_64(info->read_fence, I40IWQPSQ_READFENCE) | 3122 LS_64(info->read_fence, I40IWQPSQ_READFENCE) |
@@ -3959,7 +4111,7 @@ enum i40iw_status_code i40iw_process_cqp_cmd(struct i40iw_sc_dev *dev,
3959 struct cqp_commands_info *pcmdinfo) 4111 struct cqp_commands_info *pcmdinfo)
3960{ 4112{
3961 enum i40iw_status_code status = 0; 4113 enum i40iw_status_code status = 0;
3962 unsigned long flags; 4114 unsigned long flags;
3963 4115
3964 spin_lock_irqsave(&dev->cqp_lock, flags); 4116 spin_lock_irqsave(&dev->cqp_lock, flags);
3965 if (list_empty(&dev->cqp_cmd_head) && !i40iw_ring_full(dev->cqp)) 4117 if (list_empty(&dev->cqp_cmd_head) && !i40iw_ring_full(dev->cqp))
@@ -3978,7 +4130,7 @@ enum i40iw_status_code i40iw_process_bh(struct i40iw_sc_dev *dev)
3978{ 4130{
3979 enum i40iw_status_code status = 0; 4131 enum i40iw_status_code status = 0;
3980 struct cqp_commands_info *pcmdinfo; 4132 struct cqp_commands_info *pcmdinfo;
3981 unsigned long flags; 4133 unsigned long flags;
3982 4134
3983 spin_lock_irqsave(&dev->cqp_lock, flags); 4135 spin_lock_irqsave(&dev->cqp_lock, flags);
3984 while (!list_empty(&dev->cqp_cmd_head) && !i40iw_ring_full(dev->cqp)) { 4136 while (!list_empty(&dev->cqp_cmd_head) && !i40iw_ring_full(dev->cqp)) {
@@ -4055,7 +4207,6 @@ static int i40iw_bld_terminate_hdr(struct i40iw_sc_qp *qp,
4055 u16 ddp_seg_len; 4207 u16 ddp_seg_len;
4056 int copy_len = 0; 4208 int copy_len = 0;
4057 u8 is_tagged = 0; 4209 u8 is_tagged = 0;
4058 enum i40iw_flush_opcode flush_code = FLUSH_INVALID;
4059 u32 opcode; 4210 u32 opcode;
4060 struct i40iw_terminate_hdr *termhdr; 4211 struct i40iw_terminate_hdr *termhdr;
4061 4212
@@ -4228,9 +4379,6 @@ static int i40iw_bld_terminate_hdr(struct i40iw_sc_qp *qp,
4228 if (copy_len) 4379 if (copy_len)
4229 memcpy(termhdr + 1, pkt, copy_len); 4380 memcpy(termhdr + 1, pkt, copy_len);
4230 4381
4231 if (flush_code && !info->in_rdrsp_wr)
4232 qp->sq_flush = (info->sq) ? true : false;
4233
4234 return sizeof(struct i40iw_terminate_hdr) + copy_len; 4382 return sizeof(struct i40iw_terminate_hdr) + copy_len;
4235} 4383}
4236 4384
@@ -4321,286 +4469,370 @@ void i40iw_terminate_received(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *in
4321} 4469}
4322 4470
4323/** 4471/**
4324 * i40iw_hw_stat_init - Initiliaze HW stats table 4472 * i40iw_sc_vsi_init - Initialize virtual device
4325 * @devstat: pestat struct 4473 * @vsi: pointer to the vsi structure
4474 * @info: parameters to initialize vsi
4475 **/
4476void i40iw_sc_vsi_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_init_info *info)
4477{
4478 int i;
4479
4480 vsi->dev = info->dev;
4481 vsi->back_vsi = info->back_vsi;
4482 vsi->mss = info->params->mss;
4483 i40iw_fill_qos_list(info->params->qs_handle_list);
4484
4485 for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
4486 vsi->qos[i].qs_handle =
4487 info->params->qs_handle_list[i];
4488 i40iw_debug(vsi->dev, I40IW_DEBUG_DCB, "qset[%d]: %d\n", i, vsi->qos[i].qs_handle);
4489 spin_lock_init(&vsi->qos[i].lock);
4490 INIT_LIST_HEAD(&vsi->qos[i].qplist);
4491 }
4492}
4493
4494/**
4495 * i40iw_hw_stats_init - Initiliaze HW stats table
4496 * @stats: pestat struct
4326 * @fcn_idx: PCI fn id 4497 * @fcn_idx: PCI fn id
4327 * @hw: PF i40iw_hw structure.
4328 * @is_pf: Is it a PF? 4498 * @is_pf: Is it a PF?
4329 * 4499 *
4330 * Populate the HW stat table with register offset addr for each 4500 * Populate the HW stats table with register offset addr for each
4331 * stat. And start the perioidic stats timer. 4501 * stats. And start the perioidic stats timer.
4332 */ 4502 */
4333static void i40iw_hw_stat_init(struct i40iw_dev_pestat *devstat, 4503void i40iw_hw_stats_init(struct i40iw_vsi_pestat *stats, u8 fcn_idx, bool is_pf)
4334 u8 fcn_idx,
4335 struct i40iw_hw *hw, bool is_pf)
4336{ 4504{
4337 u32 stat_reg_offset; 4505 u32 stats_reg_offset;
4338 u32 stat_index; 4506 u32 stats_index;
4339 struct i40iw_dev_hw_stat_offsets *stat_table = 4507 struct i40iw_dev_hw_stats_offsets *stats_table =
4340 &devstat->hw_stat_offsets; 4508 &stats->hw_stats_offsets;
4341 struct i40iw_dev_hw_stats *last_rd_stats = &devstat->last_read_hw_stats; 4509 struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats;
4342
4343 devstat->hw = hw;
4344 4510
4345 if (is_pf) { 4511 if (is_pf) {
4346 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] = 4512 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] =
4347 I40E_GLPES_PFIP4RXDISCARD(fcn_idx); 4513 I40E_GLPES_PFIP4RXDISCARD(fcn_idx);
4348 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] = 4514 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] =
4349 I40E_GLPES_PFIP4RXTRUNC(fcn_idx); 4515 I40E_GLPES_PFIP4RXTRUNC(fcn_idx);
4350 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = 4516 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] =
4351 I40E_GLPES_PFIP4TXNOROUTE(fcn_idx); 4517 I40E_GLPES_PFIP4TXNOROUTE(fcn_idx);
4352 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD] = 4518 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD] =
4353 I40E_GLPES_PFIP6RXDISCARD(fcn_idx); 4519 I40E_GLPES_PFIP6RXDISCARD(fcn_idx);
4354 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC] = 4520 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC] =
4355 I40E_GLPES_PFIP6RXTRUNC(fcn_idx); 4521 I40E_GLPES_PFIP6RXTRUNC(fcn_idx);
4356 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = 4522 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE] =
4357 I40E_GLPES_PFIP6TXNOROUTE(fcn_idx); 4523 I40E_GLPES_PFIP6TXNOROUTE(fcn_idx);
4358 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_TCPRTXSEG] = 4524 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRTXSEG] =
4359 I40E_GLPES_PFTCPRTXSEG(fcn_idx); 4525 I40E_GLPES_PFTCPRTXSEG(fcn_idx);
4360 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_TCPRXOPTERR] = 4526 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXOPTERR] =
4361 I40E_GLPES_PFTCPRXOPTERR(fcn_idx); 4527 I40E_GLPES_PFTCPRXOPTERR(fcn_idx);
4362 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = 4528 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXPROTOERR] =
4363 I40E_GLPES_PFTCPRXPROTOERR(fcn_idx); 4529 I40E_GLPES_PFTCPRXPROTOERR(fcn_idx);
4364 4530
4365 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4RXOCTS] = 4531 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXOCTS] =
4366 I40E_GLPES_PFIP4RXOCTSLO(fcn_idx); 4532 I40E_GLPES_PFIP4RXOCTSLO(fcn_idx);
4367 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] = 4533 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] =
4368 I40E_GLPES_PFIP4RXPKTSLO(fcn_idx); 4534 I40E_GLPES_PFIP4RXPKTSLO(fcn_idx);
4369 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] = 4535 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] =
4370 I40E_GLPES_PFIP4RXFRAGSLO(fcn_idx); 4536 I40E_GLPES_PFIP4RXFRAGSLO(fcn_idx);
4371 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] = 4537 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] =
4372 I40E_GLPES_PFIP4RXMCPKTSLO(fcn_idx); 4538 I40E_GLPES_PFIP4RXMCPKTSLO(fcn_idx);
4373 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4TXOCTS] = 4539 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXOCTS] =
4374 I40E_GLPES_PFIP4TXOCTSLO(fcn_idx); 4540 I40E_GLPES_PFIP4TXOCTSLO(fcn_idx);
4375 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4TXPKTS] = 4541 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXPKTS] =
4376 I40E_GLPES_PFIP4TXPKTSLO(fcn_idx); 4542 I40E_GLPES_PFIP4TXPKTSLO(fcn_idx);
4377 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] = 4543 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] =
4378 I40E_GLPES_PFIP4TXFRAGSLO(fcn_idx); 4544 I40E_GLPES_PFIP4TXFRAGSLO(fcn_idx);
4379 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] = 4545 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] =
4380 I40E_GLPES_PFIP4TXMCPKTSLO(fcn_idx); 4546 I40E_GLPES_PFIP4TXMCPKTSLO(fcn_idx);
4381 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6RXOCTS] = 4547 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXOCTS] =
4382 I40E_GLPES_PFIP6RXOCTSLO(fcn_idx); 4548 I40E_GLPES_PFIP6RXOCTSLO(fcn_idx);
4383 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6RXPKTS] = 4549 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXPKTS] =
4384 I40E_GLPES_PFIP6RXPKTSLO(fcn_idx); 4550 I40E_GLPES_PFIP6RXPKTSLO(fcn_idx);
4385 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS] = 4551 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS] =
4386 I40E_GLPES_PFIP6RXFRAGSLO(fcn_idx); 4552 I40E_GLPES_PFIP6RXFRAGSLO(fcn_idx);
4387 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS] = 4553 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS] =
4388 I40E_GLPES_PFIP6RXMCPKTSLO(fcn_idx); 4554 I40E_GLPES_PFIP6RXMCPKTSLO(fcn_idx);
4389 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6TXOCTS] = 4555 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXOCTS] =
4390 I40E_GLPES_PFIP6TXOCTSLO(fcn_idx); 4556 I40E_GLPES_PFIP6TXOCTSLO(fcn_idx);
4391 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] = 4557 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4392 I40E_GLPES_PFIP6TXPKTSLO(fcn_idx); 4558 I40E_GLPES_PFIP6TXPKTSLO(fcn_idx);
4393 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] = 4559 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4394 I40E_GLPES_PFIP6TXPKTSLO(fcn_idx); 4560 I40E_GLPES_PFIP6TXPKTSLO(fcn_idx);
4395 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS] = 4561 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS] =
4396 I40E_GLPES_PFIP6TXFRAGSLO(fcn_idx); 4562 I40E_GLPES_PFIP6TXFRAGSLO(fcn_idx);
4397 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_TCPRXSEGS] = 4563 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPRXSEGS] =
4398 I40E_GLPES_PFTCPRXSEGSLO(fcn_idx); 4564 I40E_GLPES_PFTCPRXSEGSLO(fcn_idx);
4399 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_TCPTXSEG] = 4565 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPTXSEG] =
4400 I40E_GLPES_PFTCPTXSEGLO(fcn_idx); 4566 I40E_GLPES_PFTCPTXSEGLO(fcn_idx);
4401 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMARXRDS] = 4567 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXRDS] =
4402 I40E_GLPES_PFRDMARXRDSLO(fcn_idx); 4568 I40E_GLPES_PFRDMARXRDSLO(fcn_idx);
4403 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMARXSNDS] = 4569 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXSNDS] =
4404 I40E_GLPES_PFRDMARXSNDSLO(fcn_idx); 4570 I40E_GLPES_PFRDMARXSNDSLO(fcn_idx);
4405 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMARXWRS] = 4571 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXWRS] =
4406 I40E_GLPES_PFRDMARXWRSLO(fcn_idx); 4572 I40E_GLPES_PFRDMARXWRSLO(fcn_idx);
4407 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMATXRDS] = 4573 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXRDS] =
4408 I40E_GLPES_PFRDMATXRDSLO(fcn_idx); 4574 I40E_GLPES_PFRDMATXRDSLO(fcn_idx);
4409 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMATXSNDS] = 4575 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXSNDS] =
4410 I40E_GLPES_PFRDMATXSNDSLO(fcn_idx); 4576 I40E_GLPES_PFRDMATXSNDSLO(fcn_idx);
4411 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMATXWRS] = 4577 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXWRS] =
4412 I40E_GLPES_PFRDMATXWRSLO(fcn_idx); 4578 I40E_GLPES_PFRDMATXWRSLO(fcn_idx);
4413 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMAVBND] = 4579 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVBND] =
4414 I40E_GLPES_PFRDMAVBNDLO(fcn_idx); 4580 I40E_GLPES_PFRDMAVBNDLO(fcn_idx);
4415 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMAVINV] = 4581 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVINV] =
4416 I40E_GLPES_PFRDMAVINVLO(fcn_idx); 4582 I40E_GLPES_PFRDMAVINVLO(fcn_idx);
4417 } else { 4583 } else {
4418 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] = 4584 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXDISCARD] =
4419 I40E_GLPES_VFIP4RXDISCARD(fcn_idx); 4585 I40E_GLPES_VFIP4RXDISCARD(fcn_idx);
4420 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] = 4586 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4RXTRUNC] =
4421 I40E_GLPES_VFIP4RXTRUNC(fcn_idx); 4587 I40E_GLPES_VFIP4RXTRUNC(fcn_idx);
4422 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] = 4588 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP4TXNOROUTE] =
4423 I40E_GLPES_VFIP4TXNOROUTE(fcn_idx); 4589 I40E_GLPES_VFIP4TXNOROUTE(fcn_idx);
4424 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD] = 4590 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXDISCARD] =
4425 I40E_GLPES_VFIP6RXDISCARD(fcn_idx); 4591 I40E_GLPES_VFIP6RXDISCARD(fcn_idx);
4426 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC] = 4592 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6RXTRUNC] =
4427 I40E_GLPES_VFIP6RXTRUNC(fcn_idx); 4593 I40E_GLPES_VFIP6RXTRUNC(fcn_idx);
4428 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE] = 4594 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_IP6TXNOROUTE] =
4429 I40E_GLPES_VFIP6TXNOROUTE(fcn_idx); 4595 I40E_GLPES_VFIP6TXNOROUTE(fcn_idx);
4430 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_TCPRTXSEG] = 4596 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRTXSEG] =
4431 I40E_GLPES_VFTCPRTXSEG(fcn_idx); 4597 I40E_GLPES_VFTCPRTXSEG(fcn_idx);
4432 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_TCPRXOPTERR] = 4598 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXOPTERR] =
4433 I40E_GLPES_VFTCPRXOPTERR(fcn_idx); 4599 I40E_GLPES_VFTCPRXOPTERR(fcn_idx);
4434 stat_table->stat_offset_32[I40IW_HW_STAT_INDEX_TCPRXPROTOERR] = 4600 stats_table->stats_offset_32[I40IW_HW_STAT_INDEX_TCPRXPROTOERR] =
4435 I40E_GLPES_VFTCPRXPROTOERR(fcn_idx); 4601 I40E_GLPES_VFTCPRXPROTOERR(fcn_idx);
4436 4602
4437 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4RXOCTS] = 4603 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXOCTS] =
4438 I40E_GLPES_VFIP4RXOCTSLO(fcn_idx); 4604 I40E_GLPES_VFIP4RXOCTSLO(fcn_idx);
4439 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] = 4605 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXPKTS] =
4440 I40E_GLPES_VFIP4RXPKTSLO(fcn_idx); 4606 I40E_GLPES_VFIP4RXPKTSLO(fcn_idx);
4441 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] = 4607 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXFRAGS] =
4442 I40E_GLPES_VFIP4RXFRAGSLO(fcn_idx); 4608 I40E_GLPES_VFIP4RXFRAGSLO(fcn_idx);
4443 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] = 4609 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4RXMCPKTS] =
4444 I40E_GLPES_VFIP4RXMCPKTSLO(fcn_idx); 4610 I40E_GLPES_VFIP4RXMCPKTSLO(fcn_idx);
4445 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4TXOCTS] = 4611 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXOCTS] =
4446 I40E_GLPES_VFIP4TXOCTSLO(fcn_idx); 4612 I40E_GLPES_VFIP4TXOCTSLO(fcn_idx);
4447 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4TXPKTS] = 4613 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXPKTS] =
4448 I40E_GLPES_VFIP4TXPKTSLO(fcn_idx); 4614 I40E_GLPES_VFIP4TXPKTSLO(fcn_idx);
4449 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] = 4615 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXFRAGS] =
4450 I40E_GLPES_VFIP4TXFRAGSLO(fcn_idx); 4616 I40E_GLPES_VFIP4TXFRAGSLO(fcn_idx);
4451 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] = 4617 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP4TXMCPKTS] =
4452 I40E_GLPES_VFIP4TXMCPKTSLO(fcn_idx); 4618 I40E_GLPES_VFIP4TXMCPKTSLO(fcn_idx);
4453 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6RXOCTS] = 4619 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXOCTS] =
4454 I40E_GLPES_VFIP6RXOCTSLO(fcn_idx); 4620 I40E_GLPES_VFIP6RXOCTSLO(fcn_idx);
4455 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6RXPKTS] = 4621 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXPKTS] =
4456 I40E_GLPES_VFIP6RXPKTSLO(fcn_idx); 4622 I40E_GLPES_VFIP6RXPKTSLO(fcn_idx);
4457 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS] = 4623 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXFRAGS] =
4458 I40E_GLPES_VFIP6RXFRAGSLO(fcn_idx); 4624 I40E_GLPES_VFIP6RXFRAGSLO(fcn_idx);
4459 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS] = 4625 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6RXMCPKTS] =
4460 I40E_GLPES_VFIP6RXMCPKTSLO(fcn_idx); 4626 I40E_GLPES_VFIP6RXMCPKTSLO(fcn_idx);
4461 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6TXOCTS] = 4627 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXOCTS] =
4462 I40E_GLPES_VFIP6TXOCTSLO(fcn_idx); 4628 I40E_GLPES_VFIP6TXOCTSLO(fcn_idx);
4463 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] = 4629 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4464 I40E_GLPES_VFIP6TXPKTSLO(fcn_idx); 4630 I40E_GLPES_VFIP6TXPKTSLO(fcn_idx);
4465 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] = 4631 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXPKTS] =
4466 I40E_GLPES_VFIP6TXPKTSLO(fcn_idx); 4632 I40E_GLPES_VFIP6TXPKTSLO(fcn_idx);
4467 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS] = 4633 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_IP6TXFRAGS] =
4468 I40E_GLPES_VFIP6TXFRAGSLO(fcn_idx); 4634 I40E_GLPES_VFIP6TXFRAGSLO(fcn_idx);
4469 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_TCPRXSEGS] = 4635 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPRXSEGS] =
4470 I40E_GLPES_VFTCPRXSEGSLO(fcn_idx); 4636 I40E_GLPES_VFTCPRXSEGSLO(fcn_idx);
4471 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_TCPTXSEG] = 4637 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_TCPTXSEG] =
4472 I40E_GLPES_VFTCPTXSEGLO(fcn_idx); 4638 I40E_GLPES_VFTCPTXSEGLO(fcn_idx);
4473 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMARXRDS] = 4639 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXRDS] =
4474 I40E_GLPES_VFRDMARXRDSLO(fcn_idx); 4640 I40E_GLPES_VFRDMARXRDSLO(fcn_idx);
4475 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMARXSNDS] = 4641 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXSNDS] =
4476 I40E_GLPES_VFRDMARXSNDSLO(fcn_idx); 4642 I40E_GLPES_VFRDMARXSNDSLO(fcn_idx);
4477 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMARXWRS] = 4643 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMARXWRS] =
4478 I40E_GLPES_VFRDMARXWRSLO(fcn_idx); 4644 I40E_GLPES_VFRDMARXWRSLO(fcn_idx);
4479 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMATXRDS] = 4645 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXRDS] =
4480 I40E_GLPES_VFRDMATXRDSLO(fcn_idx); 4646 I40E_GLPES_VFRDMATXRDSLO(fcn_idx);
4481 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMATXSNDS] = 4647 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXSNDS] =
4482 I40E_GLPES_VFRDMATXSNDSLO(fcn_idx); 4648 I40E_GLPES_VFRDMATXSNDSLO(fcn_idx);
4483 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMATXWRS] = 4649 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMATXWRS] =
4484 I40E_GLPES_VFRDMATXWRSLO(fcn_idx); 4650 I40E_GLPES_VFRDMATXWRSLO(fcn_idx);
4485 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMAVBND] = 4651 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVBND] =
4486 I40E_GLPES_VFRDMAVBNDLO(fcn_idx); 4652 I40E_GLPES_VFRDMAVBNDLO(fcn_idx);
4487 stat_table->stat_offset_64[I40IW_HW_STAT_INDEX_RDMAVINV] = 4653 stats_table->stats_offset_64[I40IW_HW_STAT_INDEX_RDMAVINV] =
4488 I40E_GLPES_VFRDMAVINVLO(fcn_idx); 4654 I40E_GLPES_VFRDMAVINVLO(fcn_idx);
4489 } 4655 }
4490 4656
4491 for (stat_index = 0; stat_index < I40IW_HW_STAT_INDEX_MAX_64; 4657 for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64;
4492 stat_index++) { 4658 stats_index++) {
4493 stat_reg_offset = stat_table->stat_offset_64[stat_index]; 4659 stats_reg_offset = stats_table->stats_offset_64[stats_index];
4494 last_rd_stats->stat_value_64[stat_index] = 4660 last_rd_stats->stats_value_64[stats_index] =
4495 readq(devstat->hw->hw_addr + stat_reg_offset); 4661 readq(stats->hw->hw_addr + stats_reg_offset);
4496 } 4662 }
4497 4663
4498 for (stat_index = 0; stat_index < I40IW_HW_STAT_INDEX_MAX_32; 4664 for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32;
4499 stat_index++) { 4665 stats_index++) {
4500 stat_reg_offset = stat_table->stat_offset_32[stat_index]; 4666 stats_reg_offset = stats_table->stats_offset_32[stats_index];
4501 last_rd_stats->stat_value_32[stat_index] = 4667 last_rd_stats->stats_value_32[stats_index] =
4502 i40iw_rd32(devstat->hw, stat_reg_offset); 4668 i40iw_rd32(stats->hw, stats_reg_offset);
4503 } 4669 }
4504} 4670}
4505 4671
4506/** 4672/**
4507 * i40iw_hw_stat_read_32 - Read 32-bit HW stat counters and accommodates for roll-overs. 4673 * i40iw_hw_stats_read_32 - Read 32-bit HW stats counters and accommodates for roll-overs.
4508 * @devstat: pestat struct 4674 * @stat: pestat struct
4509 * @index: index in HW stat table which contains offset reg-addr 4675 * @index: index in HW stats table which contains offset reg-addr
4510 * @value: hw stat value 4676 * @value: hw stats value
4511 */ 4677 */
4512static void i40iw_hw_stat_read_32(struct i40iw_dev_pestat *devstat, 4678void i40iw_hw_stats_read_32(struct i40iw_vsi_pestat *stats,
4513 enum i40iw_hw_stat_index_32b index, 4679 enum i40iw_hw_stats_index_32b index,
4514 u64 *value) 4680 u64 *value)
4515{ 4681{
4516 struct i40iw_dev_hw_stat_offsets *stat_table = 4682 struct i40iw_dev_hw_stats_offsets *stats_table =
4517 &devstat->hw_stat_offsets; 4683 &stats->hw_stats_offsets;
4518 struct i40iw_dev_hw_stats *last_rd_stats = &devstat->last_read_hw_stats; 4684 struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats;
4519 struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats; 4685 struct i40iw_dev_hw_stats *hw_stats = &stats->hw_stats;
4520 u64 new_stat_value = 0; 4686 u64 new_stats_value = 0;
4521 u32 stat_reg_offset = stat_table->stat_offset_32[index]; 4687 u32 stats_reg_offset = stats_table->stats_offset_32[index];
4522 4688
4523 new_stat_value = i40iw_rd32(devstat->hw, stat_reg_offset); 4689 new_stats_value = i40iw_rd32(stats->hw, stats_reg_offset);
4524 /*roll-over case */ 4690 /*roll-over case */
4525 if (new_stat_value < last_rd_stats->stat_value_32[index]) 4691 if (new_stats_value < last_rd_stats->stats_value_32[index])
4526 hw_stats->stat_value_32[index] += new_stat_value; 4692 hw_stats->stats_value_32[index] += new_stats_value;
4527 else 4693 else
4528 hw_stats->stat_value_32[index] += 4694 hw_stats->stats_value_32[index] +=
4529 new_stat_value - last_rd_stats->stat_value_32[index]; 4695 new_stats_value - last_rd_stats->stats_value_32[index];
4530 last_rd_stats->stat_value_32[index] = new_stat_value; 4696 last_rd_stats->stats_value_32[index] = new_stats_value;
4531 *value = hw_stats->stat_value_32[index]; 4697 *value = hw_stats->stats_value_32[index];
4532} 4698}
4533 4699
4534/** 4700/**
4535 * i40iw_hw_stat_read_64 - Read HW stat counters (greater than 32-bit) and accommodates for roll-overs. 4701 * i40iw_hw_stats_read_64 - Read HW stats counters (greater than 32-bit) and accommodates for roll-overs.
4536 * @devstat: pestat struct 4702 * @stats: pestat struct
4537 * @index: index in HW stat table which contains offset reg-addr 4703 * @index: index in HW stats table which contains offset reg-addr
4538 * @value: hw stat value 4704 * @value: hw stats value
4539 */ 4705 */
4540static void i40iw_hw_stat_read_64(struct i40iw_dev_pestat *devstat, 4706void i40iw_hw_stats_read_64(struct i40iw_vsi_pestat *stats,
4541 enum i40iw_hw_stat_index_64b index, 4707 enum i40iw_hw_stats_index_64b index,
4542 u64 *value) 4708 u64 *value)
4543{ 4709{
4544 struct i40iw_dev_hw_stat_offsets *stat_table = 4710 struct i40iw_dev_hw_stats_offsets *stats_table =
4545 &devstat->hw_stat_offsets; 4711 &stats->hw_stats_offsets;
4546 struct i40iw_dev_hw_stats *last_rd_stats = &devstat->last_read_hw_stats; 4712 struct i40iw_dev_hw_stats *last_rd_stats = &stats->last_read_hw_stats;
4547 struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats; 4713 struct i40iw_dev_hw_stats *hw_stats = &stats->hw_stats;
4548 u64 new_stat_value = 0; 4714 u64 new_stats_value = 0;
4549 u32 stat_reg_offset = stat_table->stat_offset_64[index]; 4715 u32 stats_reg_offset = stats_table->stats_offset_64[index];
4550 4716
4551 new_stat_value = readq(devstat->hw->hw_addr + stat_reg_offset); 4717 new_stats_value = readq(stats->hw->hw_addr + stats_reg_offset);
4552 /*roll-over case */ 4718 /*roll-over case */
4553 if (new_stat_value < last_rd_stats->stat_value_64[index]) 4719 if (new_stats_value < last_rd_stats->stats_value_64[index])
4554 hw_stats->stat_value_64[index] += new_stat_value; 4720 hw_stats->stats_value_64[index] += new_stats_value;
4555 else 4721 else
4556 hw_stats->stat_value_64[index] += 4722 hw_stats->stats_value_64[index] +=
4557 new_stat_value - last_rd_stats->stat_value_64[index]; 4723 new_stats_value - last_rd_stats->stats_value_64[index];
4558 last_rd_stats->stat_value_64[index] = new_stat_value; 4724 last_rd_stats->stats_value_64[index] = new_stats_value;
4559 *value = hw_stats->stat_value_64[index]; 4725 *value = hw_stats->stats_value_64[index];
4560} 4726}
4561 4727
4562/** 4728/**
4563 * i40iw_hw_stat_read_all - read all HW stat counters 4729 * i40iw_hw_stats_read_all - read all HW stat counters
4564 * @devstat: pestat struct 4730 * @stats: pestat struct
4565 * @stat_values: hw stats structure 4731 * @stats_values: hw stats structure
4566 * 4732 *
4567 * Read all the HW stat counters and populates hw_stats structure 4733 * Read all the HW stat counters and populates hw_stats structure
4568 * of passed-in dev's pestat as well as copy created in stat_values. 4734 * of passed-in vsi's pestat as well as copy created in stat_values.
4569 */ 4735 */
4570static void i40iw_hw_stat_read_all(struct i40iw_dev_pestat *devstat, 4736void i40iw_hw_stats_read_all(struct i40iw_vsi_pestat *stats,
4571 struct i40iw_dev_hw_stats *stat_values) 4737 struct i40iw_dev_hw_stats *stats_values)
4572{ 4738{
4573 u32 stat_index; 4739 u32 stats_index;
4574 4740 unsigned long flags;
4575 for (stat_index = 0; stat_index < I40IW_HW_STAT_INDEX_MAX_32; 4741
4576 stat_index++) 4742 spin_lock_irqsave(&stats->lock, flags);
4577 i40iw_hw_stat_read_32(devstat, stat_index, 4743
4578 &stat_values->stat_value_32[stat_index]); 4744 for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32;
4579 for (stat_index = 0; stat_index < I40IW_HW_STAT_INDEX_MAX_64; 4745 stats_index++)
4580 stat_index++) 4746 i40iw_hw_stats_read_32(stats, stats_index,
4581 i40iw_hw_stat_read_64(devstat, stat_index, 4747 &stats_values->stats_value_32[stats_index]);
4582 &stat_values->stat_value_64[stat_index]); 4748 for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64;
4749 stats_index++)
4750 i40iw_hw_stats_read_64(stats, stats_index,
4751 &stats_values->stats_value_64[stats_index]);
4752 spin_unlock_irqrestore(&stats->lock, flags);
4583} 4753}
4584 4754
4585/** 4755/**
4586 * i40iw_hw_stat_refresh_all - Update all HW stat structs 4756 * i40iw_hw_stats_refresh_all - Update all HW stats structs
4587 * @devstat: pestat struct 4757 * @stats: pestat struct
4588 * @stat_values: hw stats structure
4589 * 4758 *
4590 * Read all the HW stat counters to refresh values in hw_stats structure 4759 * Read all the HW stats counters to refresh values in hw_stats structure
4591 * of passed-in dev's pestat 4760 * of passed-in dev's pestat
4592 */ 4761 */
4593static void i40iw_hw_stat_refresh_all(struct i40iw_dev_pestat *devstat) 4762void i40iw_hw_stats_refresh_all(struct i40iw_vsi_pestat *stats)
4763{
4764 u64 stats_value;
4765 u32 stats_index;
4766 unsigned long flags;
4767
4768 spin_lock_irqsave(&stats->lock, flags);
4769
4770 for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_32;
4771 stats_index++)
4772 i40iw_hw_stats_read_32(stats, stats_index, &stats_value);
4773 for (stats_index = 0; stats_index < I40IW_HW_STAT_INDEX_MAX_64;
4774 stats_index++)
4775 i40iw_hw_stats_read_64(stats, stats_index, &stats_value);
4776 spin_unlock_irqrestore(&stats->lock, flags);
4777}
4778
4779/**
4780 * i40iw_get_fcn_id - Return the function id
4781 * @dev: pointer to the device
4782 */
4783static u8 i40iw_get_fcn_id(struct i40iw_sc_dev *dev)
4784{
4785 u8 fcn_id = I40IW_INVALID_FCN_ID;
4786 u8 i;
4787
4788 for (i = I40IW_FIRST_NON_PF_STAT; i < I40IW_MAX_STATS_COUNT; i++)
4789 if (!dev->fcn_id_array[i]) {
4790 fcn_id = i;
4791 dev->fcn_id_array[i] = true;
4792 break;
4793 }
4794 return fcn_id;
4795}
4796
4797/**
4798 * i40iw_vsi_stats_init - Initialize the vsi statistics
4799 * @vsi: pointer to the vsi structure
4800 * @info: The info structure used for initialization
4801 */
4802enum i40iw_status_code i40iw_vsi_stats_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_stats_info *info)
4594{ 4803{
4595 u64 stat_value; 4804 u8 fcn_id = info->fcn_id;
4596 u32 stat_index; 4805
4597 4806 if (info->alloc_fcn_id)
4598 for (stat_index = 0; stat_index < I40IW_HW_STAT_INDEX_MAX_32; 4807 fcn_id = i40iw_get_fcn_id(vsi->dev);
4599 stat_index++) 4808
4600 i40iw_hw_stat_read_32(devstat, stat_index, &stat_value); 4809 if (fcn_id == I40IW_INVALID_FCN_ID)
4601 for (stat_index = 0; stat_index < I40IW_HW_STAT_INDEX_MAX_64; 4810 return I40IW_ERR_NOT_READY;
4602 stat_index++) 4811
4603 i40iw_hw_stat_read_64(devstat, stat_index, &stat_value); 4812 vsi->pestat = info->pestat;
4813 vsi->pestat->hw = vsi->dev->hw;
4814
4815 if (info->stats_initialize) {
4816 i40iw_hw_stats_init(vsi->pestat, fcn_id, true);
4817 spin_lock_init(&vsi->pestat->lock);
4818 i40iw_hw_stats_start_timer(vsi);
4819 }
4820 vsi->stats_fcn_id_alloc = info->alloc_fcn_id;
4821 vsi->fcn_id = fcn_id;
4822 return I40IW_SUCCESS;
4823}
4824
4825/**
4826 * i40iw_vsi_stats_free - Free the vsi stats
4827 * @vsi: pointer to the vsi structure
4828 */
4829void i40iw_vsi_stats_free(struct i40iw_sc_vsi *vsi)
4830{
4831 u8 fcn_id = vsi->fcn_id;
4832
4833 if ((vsi->stats_fcn_id_alloc) && (fcn_id != I40IW_INVALID_FCN_ID))
4834 vsi->dev->fcn_id_array[fcn_id] = false;
4835 i40iw_hw_stats_stop_timer(vsi);
4604} 4836}
4605 4837
4606static struct i40iw_cqp_ops iw_cqp_ops = { 4838static struct i40iw_cqp_ops iw_cqp_ops = {
@@ -4711,24 +4943,6 @@ static struct i40iw_hmc_ops iw_hmc_ops = {
4711 NULL 4943 NULL
4712}; 4944};
4713 4945
4714static const struct i40iw_device_pestat_ops iw_device_pestat_ops = {
4715 i40iw_hw_stat_init,
4716 i40iw_hw_stat_read_32,
4717 i40iw_hw_stat_read_64,
4718 i40iw_hw_stat_read_all,
4719 i40iw_hw_stat_refresh_all
4720};
4721
4722/**
4723 * i40iw_device_init_pestat - Initialize the pestat structure
4724 * @dev: pestat struct
4725 */
4726enum i40iw_status_code i40iw_device_init_pestat(struct i40iw_dev_pestat *devstat)
4727{
4728 devstat->ops = iw_device_pestat_ops;
4729 return 0;
4730}
4731
4732/** 4946/**
4733 * i40iw_device_init - Initialize IWARP device 4947 * i40iw_device_init - Initialize IWARP device
4734 * @dev: IWARP device pointer 4948 * @dev: IWARP device pointer
@@ -4750,14 +4964,7 @@ enum i40iw_status_code i40iw_device_init(struct i40iw_sc_dev *dev,
4750 4964
4751 dev->debug_mask = info->debug_mask; 4965 dev->debug_mask = info->debug_mask;
4752 4966
4753 ret_code = i40iw_device_init_pestat(&dev->dev_pestat);
4754 if (ret_code) {
4755 i40iw_debug(dev, I40IW_DEBUG_DEV,
4756 "%s: i40iw_device_init_pestat failed\n", __func__);
4757 return ret_code;
4758 }
4759 dev->hmc_fn_id = info->hmc_fn_id; 4967 dev->hmc_fn_id = info->hmc_fn_id;
4760 dev->qs_handle = info->qs_handle;
4761 dev->exception_lan_queue = info->exception_lan_queue; 4968 dev->exception_lan_queue = info->exception_lan_queue;
4762 dev->is_pf = info->is_pf; 4969 dev->is_pf = info->is_pf;
4763 4970
@@ -4770,15 +4977,10 @@ enum i40iw_status_code i40iw_device_init(struct i40iw_sc_dev *dev,
4770 dev->hw = info->hw; 4977 dev->hw = info->hw;
4771 dev->hw->hw_addr = info->bar0; 4978 dev->hw->hw_addr = info->bar0;
4772 4979
4773 val = i40iw_rd32(dev->hw, I40E_GLPCI_DREVID);
4774 dev->hw_rev = (u8)RS_32(val, I40E_GLPCI_DREVID_DEFAULT_REVID);
4775
4776 if (dev->is_pf) { 4980 if (dev->is_pf) {
4777 dev->dev_pestat.ops.iw_hw_stat_init(&dev->dev_pestat, 4981 val = i40iw_rd32(dev->hw, I40E_GLPCI_DREVID);
4778 dev->hmc_fn_id, dev->hw, true); 4982 dev->hw_rev = (u8)RS_32(val, I40E_GLPCI_DREVID_DEFAULT_REVID);
4779 spin_lock_init(&dev->dev_pestat.stats_lock); 4983
4780 /*start the periodic stats_timer */
4781 i40iw_hw_stats_start_timer(dev);
4782 val = i40iw_rd32(dev->hw, I40E_GLPCI_LBARCTRL); 4984 val = i40iw_rd32(dev->hw, I40E_GLPCI_LBARCTRL);
4783 db_size = (u8)RS_32(val, I40E_GLPCI_LBARCTRL_PE_DB_SIZE); 4985 db_size = (u8)RS_32(val, I40E_GLPCI_LBARCTRL_PE_DB_SIZE);
4784 if ((db_size != I40IW_PE_DB_SIZE_4M) && 4986 if ((db_size != I40IW_PE_DB_SIZE_4M) &&
diff --git a/drivers/infiniband/hw/i40iw/i40iw_d.h b/drivers/infiniband/hw/i40iw/i40iw_d.h
index 2fac1db0e0a0..a39ac12b6a7e 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_d.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_d.h
@@ -35,6 +35,8 @@
35#ifndef I40IW_D_H 35#ifndef I40IW_D_H
36#define I40IW_D_H 36#define I40IW_D_H
37 37
38#define I40IW_FIRST_USER_QP_ID 2
39
38#define I40IW_DB_ADDR_OFFSET (4 * 1024 * 1024 - 64 * 1024) 40#define I40IW_DB_ADDR_OFFSET (4 * 1024 * 1024 - 64 * 1024)
39#define I40IW_VF_DB_ADDR_OFFSET (64 * 1024) 41#define I40IW_VF_DB_ADDR_OFFSET (64 * 1024)
40 42
@@ -67,6 +69,9 @@
67#define I40IW_STAG_TYPE_NONSHARED 1 69#define I40IW_STAG_TYPE_NONSHARED 1
68 70
69#define I40IW_MAX_USER_PRIORITY 8 71#define I40IW_MAX_USER_PRIORITY 8
72#define I40IW_MAX_STATS_COUNT 16
73#define I40IW_FIRST_NON_PF_STAT 4
74
70 75
71#define LS_64_1(val, bits) ((u64)(uintptr_t)val << bits) 76#define LS_64_1(val, bits) ((u64)(uintptr_t)val << bits)
72#define RS_64_1(val, bits) ((u64)(uintptr_t)val >> bits) 77#define RS_64_1(val, bits) ((u64)(uintptr_t)val >> bits)
@@ -74,6 +79,8 @@
74#define RS_32_1(val, bits) (u32)(val >> bits) 79#define RS_32_1(val, bits) (u32)(val >> bits)
75#define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 80#define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
76 81
82#define QS_HANDLE_UNKNOWN 0xffff
83
77#define LS_64(val, field) (((u64)val << field ## _SHIFT) & (field ## _MASK)) 84#define LS_64(val, field) (((u64)val << field ## _SHIFT) & (field ## _MASK))
78 85
79#define RS_64(val, field) ((u64)(val & field ## _MASK) >> field ## _SHIFT) 86#define RS_64(val, field) ((u64)(val & field ## _MASK) >> field ## _SHIFT)
@@ -1199,8 +1206,11 @@
1199#define I40IWQPC_RXCQNUM_SHIFT 32 1206#define I40IWQPC_RXCQNUM_SHIFT 32
1200#define I40IWQPC_RXCQNUM_MASK (0x1ffffULL << I40IWQPC_RXCQNUM_SHIFT) 1207#define I40IWQPC_RXCQNUM_MASK (0x1ffffULL << I40IWQPC_RXCQNUM_SHIFT)
1201 1208
1202#define I40IWQPC_Q2ADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT 1209#define I40IWQPC_STAT_INDEX_SHIFT 0
1203#define I40IWQPC_Q2ADDR_MASK I40IW_CQPHC_QPCTX_MASK 1210#define I40IWQPC_STAT_INDEX_MASK (0x1fULL << I40IWQPC_STAT_INDEX_SHIFT)
1211
1212#define I40IWQPC_Q2ADDR_SHIFT 0
1213#define I40IWQPC_Q2ADDR_MASK (0xffffffffffffff00ULL << I40IWQPC_Q2ADDR_SHIFT)
1204 1214
1205#define I40IWQPC_LASTBYTESENT_SHIFT 0 1215#define I40IWQPC_LASTBYTESENT_SHIFT 0
1206#define I40IWQPC_LASTBYTESENT_MASK (0xffUL << I40IWQPC_LASTBYTESENT_SHIFT) 1216#define I40IWQPC_LASTBYTESENT_MASK (0xffUL << I40IWQPC_LASTBYTESENT_SHIFT)
@@ -1232,11 +1242,8 @@
1232#define I40IWQPC_PRIVEN_SHIFT 25 1242#define I40IWQPC_PRIVEN_SHIFT 25
1233#define I40IWQPC_PRIVEN_MASK (1UL << I40IWQPC_PRIVEN_SHIFT) 1243#define I40IWQPC_PRIVEN_MASK (1UL << I40IWQPC_PRIVEN_SHIFT)
1234 1244
1235#define I40IWQPC_LSMMPRESENT_SHIFT 26 1245#define I40IWQPC_USESTATSINSTANCE_SHIFT 26
1236#define I40IWQPC_LSMMPRESENT_MASK (1UL << I40IWQPC_LSMMPRESENT_SHIFT) 1246#define I40IWQPC_USESTATSINSTANCE_MASK (1UL << I40IWQPC_USESTATSINSTANCE_SHIFT)
1237
1238#define I40IWQPC_ADJUSTFORLSMM_SHIFT 27
1239#define I40IWQPC_ADJUSTFORLSMM_MASK (1UL << I40IWQPC_ADJUSTFORLSMM_SHIFT)
1240 1247
1241#define I40IWQPC_IWARPMODE_SHIFT 28 1248#define I40IWQPC_IWARPMODE_SHIFT 28
1242#define I40IWQPC_IWARPMODE_MASK (1UL << I40IWQPC_IWARPMODE_SHIFT) 1249#define I40IWQPC_IWARPMODE_MASK (1UL << I40IWQPC_IWARPMODE_SHIFT)
@@ -1713,6 +1720,8 @@ enum i40iw_alignment {
1713#define OP_MANAGE_VF_PBLE_BP 28 1720#define OP_MANAGE_VF_PBLE_BP 28
1714#define OP_QUERY_FPM_VALUES 29 1721#define OP_QUERY_FPM_VALUES 29
1715#define OP_COMMIT_FPM_VALUES 30 1722#define OP_COMMIT_FPM_VALUES 30
1716#define OP_SIZE_CQP_STAT_ARRAY 31 1723#define OP_REQUESTED_COMMANDS 31
1724#define OP_COMPLETED_COMMANDS 32
1725#define OP_SIZE_CQP_STAT_ARRAY 33
1717 1726
1718#endif 1727#endif
diff --git a/drivers/infiniband/hw/i40iw/i40iw_hw.c b/drivers/infiniband/hw/i40iw/i40iw_hw.c
index 0c92a40b3e86..476867a3f584 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_hw.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_hw.c
@@ -62,7 +62,7 @@ u32 i40iw_initialize_hw_resources(struct i40iw_device *iwdev)
62 max_mr = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt; 62 max_mr = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt;
63 arp_table_size = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_ARP].cnt; 63 arp_table_size = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_ARP].cnt;
64 iwdev->max_cqe = 0xFFFFF; 64 iwdev->max_cqe = 0xFFFFF;
65 num_pds = max_qp * 4; 65 num_pds = I40IW_MAX_PDS;
66 resources_size = sizeof(struct i40iw_arp_entry) * arp_table_size; 66 resources_size = sizeof(struct i40iw_arp_entry) * arp_table_size;
67 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_qp); 67 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_qp);
68 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_mr); 68 resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_mr);
@@ -308,7 +308,9 @@ void i40iw_process_aeq(struct i40iw_device *iwdev)
308 iwqp = iwdev->qp_table[info->qp_cq_id]; 308 iwqp = iwdev->qp_table[info->qp_cq_id];
309 if (!iwqp) { 309 if (!iwqp) {
310 spin_unlock_irqrestore(&iwdev->qptable_lock, flags); 310 spin_unlock_irqrestore(&iwdev->qptable_lock, flags);
311 i40iw_pr_err("qp_id %d is already freed\n", info->qp_cq_id); 311 i40iw_debug(dev, I40IW_DEBUG_AEQ,
312 "%s qp_id %d is already freed\n",
313 __func__, info->qp_cq_id);
312 continue; 314 continue;
313 } 315 }
314 i40iw_add_ref(&iwqp->ibqp); 316 i40iw_add_ref(&iwqp->ibqp);
@@ -359,6 +361,9 @@ void i40iw_process_aeq(struct i40iw_device *iwdev)
359 continue; 361 continue;
360 i40iw_cm_disconn(iwqp); 362 i40iw_cm_disconn(iwqp);
361 break; 363 break;
364 case I40IW_AE_QP_SUSPEND_COMPLETE:
365 i40iw_qp_suspend_resume(dev, &iwqp->sc_qp, false);
366 break;
362 case I40IW_AE_TERMINATE_SENT: 367 case I40IW_AE_TERMINATE_SENT:
363 i40iw_terminate_send_fin(qp); 368 i40iw_terminate_send_fin(qp);
364 break; 369 break;
@@ -404,19 +409,18 @@ void i40iw_process_aeq(struct i40iw_device *iwdev)
404 case I40IW_AE_LCE_CQ_CATASTROPHIC: 409 case I40IW_AE_LCE_CQ_CATASTROPHIC:
405 case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG: 410 case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG:
406 case I40IW_AE_UDA_XMIT_IPADDR_MISMATCH: 411 case I40IW_AE_UDA_XMIT_IPADDR_MISMATCH:
407 case I40IW_AE_QP_SUSPEND_COMPLETE:
408 ctx_info->err_rq_idx_valid = false; 412 ctx_info->err_rq_idx_valid = false;
409 default: 413 default:
410 if (!info->sq && ctx_info->err_rq_idx_valid) { 414 if (!info->sq && ctx_info->err_rq_idx_valid) {
411 ctx_info->err_rq_idx = info->wqe_idx; 415 ctx_info->err_rq_idx = info->wqe_idx;
412 ctx_info->tcp_info_valid = false; 416 ctx_info->tcp_info_valid = false;
413 ctx_info->iwarp_info_valid = false; 417 ctx_info->iwarp_info_valid = false;
414 ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp, 418 ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
415 iwqp->host_ctx.va, 419 iwqp->host_ctx.va,
416 ctx_info); 420 ctx_info);
417 } 421 }
418 i40iw_terminate_connection(qp, info); 422 i40iw_terminate_connection(qp, info);
419 break; 423 break;
420 } 424 }
421 if (info->qp) 425 if (info->qp)
422 i40iw_rem_ref(&iwqp->ibqp); 426 i40iw_rem_ref(&iwqp->ibqp);
@@ -538,6 +542,7 @@ enum i40iw_status_code i40iw_manage_qhash(struct i40iw_device *iwdev,
538{ 542{
539 struct i40iw_qhash_table_info *info; 543 struct i40iw_qhash_table_info *info;
540 struct i40iw_sc_dev *dev = &iwdev->sc_dev; 544 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
545 struct i40iw_sc_vsi *vsi = &iwdev->vsi;
541 enum i40iw_status_code status; 546 enum i40iw_status_code status;
542 struct i40iw_cqp *iwcqp = &iwdev->cqp; 547 struct i40iw_cqp *iwcqp = &iwdev->cqp;
543 struct i40iw_cqp_request *cqp_request; 548 struct i40iw_cqp_request *cqp_request;
@@ -550,6 +555,7 @@ enum i40iw_status_code i40iw_manage_qhash(struct i40iw_device *iwdev,
550 info = &cqp_info->in.u.manage_qhash_table_entry.info; 555 info = &cqp_info->in.u.manage_qhash_table_entry.info;
551 memset(info, 0, sizeof(*info)); 556 memset(info, 0, sizeof(*info));
552 557
558 info->vsi = &iwdev->vsi;
553 info->manage = mtype; 559 info->manage = mtype;
554 info->entry_type = etype; 560 info->entry_type = etype;
555 if (cminfo->vlan_id != 0xFFFF) { 561 if (cminfo->vlan_id != 0xFFFF) {
@@ -560,8 +566,9 @@ enum i40iw_status_code i40iw_manage_qhash(struct i40iw_device *iwdev,
560 } 566 }
561 567
562 info->ipv4_valid = cminfo->ipv4; 568 info->ipv4_valid = cminfo->ipv4;
569 info->user_pri = cminfo->user_pri;
563 ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr); 570 ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr);
564 info->qp_num = cpu_to_le32(dev->ilq->qp_id); 571 info->qp_num = cpu_to_le32(vsi->ilq->qp_id);
565 info->dest_port = cpu_to_le16(cminfo->loc_port); 572 info->dest_port = cpu_to_le16(cminfo->loc_port);
566 info->dest_ip[0] = cpu_to_le32(cminfo->loc_addr[0]); 573 info->dest_ip[0] = cpu_to_le32(cminfo->loc_addr[0]);
567 info->dest_ip[1] = cpu_to_le32(cminfo->loc_addr[1]); 574 info->dest_ip[1] = cpu_to_le32(cminfo->loc_addr[1]);
@@ -617,6 +624,7 @@ enum i40iw_status_code i40iw_hw_flush_wqes(struct i40iw_device *iwdev,
617 struct i40iw_qp_flush_info *hw_info; 624 struct i40iw_qp_flush_info *hw_info;
618 struct i40iw_cqp_request *cqp_request; 625 struct i40iw_cqp_request *cqp_request;
619 struct cqp_commands_info *cqp_info; 626 struct cqp_commands_info *cqp_info;
627 struct i40iw_qp *iwqp = (struct i40iw_qp *)qp->back_qp;
620 628
621 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait); 629 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
622 if (!cqp_request) 630 if (!cqp_request)
@@ -631,9 +639,30 @@ enum i40iw_status_code i40iw_hw_flush_wqes(struct i40iw_device *iwdev,
631 cqp_info->in.u.qp_flush_wqes.qp = qp; 639 cqp_info->in.u.qp_flush_wqes.qp = qp;
632 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request; 640 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request;
633 status = i40iw_handle_cqp_op(iwdev, cqp_request); 641 status = i40iw_handle_cqp_op(iwdev, cqp_request);
634 if (status) 642 if (status) {
635 i40iw_pr_err("CQP-OP Flush WQE's fail"); 643 i40iw_pr_err("CQP-OP Flush WQE's fail");
636 return status; 644 complete(&iwqp->sq_drained);
645 complete(&iwqp->rq_drained);
646 return status;
647 }
648 if (!cqp_request->compl_info.maj_err_code) {
649 switch (cqp_request->compl_info.min_err_code) {
650 case I40IW_CQP_COMPL_RQ_WQE_FLUSHED:
651 complete(&iwqp->sq_drained);
652 break;
653 case I40IW_CQP_COMPL_SQ_WQE_FLUSHED:
654 complete(&iwqp->rq_drained);
655 break;
656 case I40IW_CQP_COMPL_RQ_SQ_WQE_FLUSHED:
657 break;
658 default:
659 complete(&iwqp->sq_drained);
660 complete(&iwqp->rq_drained);
661 break;
662 }
663 }
664
665 return 0;
637} 666}
638 667
639/** 668/**
diff --git a/drivers/infiniband/hw/i40iw/i40iw_main.c b/drivers/infiniband/hw/i40iw/i40iw_main.c
index ac2f3cd9478c..2728af3103ce 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_main.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_main.c
@@ -237,14 +237,11 @@ static irqreturn_t i40iw_irq_handler(int irq, void *data)
237 */ 237 */
238static void i40iw_destroy_cqp(struct i40iw_device *iwdev, bool free_hwcqp) 238static void i40iw_destroy_cqp(struct i40iw_device *iwdev, bool free_hwcqp)
239{ 239{
240 enum i40iw_status_code status = 0;
241 struct i40iw_sc_dev *dev = &iwdev->sc_dev; 240 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
242 struct i40iw_cqp *cqp = &iwdev->cqp; 241 struct i40iw_cqp *cqp = &iwdev->cqp;
243 242
244 if (free_hwcqp && dev->cqp_ops->cqp_destroy) 243 if (free_hwcqp)
245 status = dev->cqp_ops->cqp_destroy(dev->cqp); 244 dev->cqp_ops->cqp_destroy(dev->cqp);
246 if (status)
247 i40iw_pr_err("destroy cqp failed");
248 245
249 i40iw_free_dma_mem(dev->hw, &cqp->sq); 246 i40iw_free_dma_mem(dev->hw, &cqp->sq);
250 kfree(cqp->scratch_array); 247 kfree(cqp->scratch_array);
@@ -270,6 +267,7 @@ static void i40iw_disable_irq(struct i40iw_sc_dev *dev,
270 i40iw_wr32(dev->hw, I40E_PFINT_DYN_CTLN(msix_vec->idx - 1), 0); 267 i40iw_wr32(dev->hw, I40E_PFINT_DYN_CTLN(msix_vec->idx - 1), 0);
271 else 268 else
272 i40iw_wr32(dev->hw, I40E_VFINT_DYN_CTLN1(msix_vec->idx - 1), 0); 269 i40iw_wr32(dev->hw, I40E_VFINT_DYN_CTLN1(msix_vec->idx - 1), 0);
270 irq_set_affinity_hint(msix_vec->irq, NULL);
273 free_irq(msix_vec->irq, dev_id); 271 free_irq(msix_vec->irq, dev_id);
274} 272}
275 273
@@ -603,7 +601,7 @@ static enum i40iw_status_code i40iw_create_cqp(struct i40iw_device *iwdev)
603 i40iw_pr_err("cqp init status %d\n", status); 601 i40iw_pr_err("cqp init status %d\n", status);
604 goto exit; 602 goto exit;
605 } 603 }
606 status = dev->cqp_ops->cqp_create(dev->cqp, true, &maj_err, &min_err); 604 status = dev->cqp_ops->cqp_create(dev->cqp, &maj_err, &min_err);
607 if (status) { 605 if (status) {
608 i40iw_pr_err("cqp create status %d maj_err %d min_err %d\n", 606 i40iw_pr_err("cqp create status %d maj_err %d min_err %d\n",
609 status, maj_err, min_err); 607 status, maj_err, min_err);
@@ -688,6 +686,7 @@ static enum i40iw_status_code i40iw_configure_ceq_vector(struct i40iw_device *iw
688 struct i40iw_msix_vector *msix_vec) 686 struct i40iw_msix_vector *msix_vec)
689{ 687{
690 enum i40iw_status_code status; 688 enum i40iw_status_code status;
689 cpumask_t mask;
691 690
692 if (iwdev->msix_shared && !ceq_id) { 691 if (iwdev->msix_shared && !ceq_id) {
693 tasklet_init(&iwdev->dpc_tasklet, i40iw_dpc, (unsigned long)iwdev); 692 tasklet_init(&iwdev->dpc_tasklet, i40iw_dpc, (unsigned long)iwdev);
@@ -697,12 +696,15 @@ static enum i40iw_status_code i40iw_configure_ceq_vector(struct i40iw_device *iw
697 status = request_irq(msix_vec->irq, i40iw_ceq_handler, 0, "CEQ", iwceq); 696 status = request_irq(msix_vec->irq, i40iw_ceq_handler, 0, "CEQ", iwceq);
698 } 697 }
699 698
699 cpumask_clear(&mask);
700 cpumask_set_cpu(msix_vec->cpu_affinity, &mask);
701 irq_set_affinity_hint(msix_vec->irq, &mask);
702
700 if (status) { 703 if (status) {
701 i40iw_pr_err("ceq irq config fail\n"); 704 i40iw_pr_err("ceq irq config fail\n");
702 return I40IW_ERR_CONFIG; 705 return I40IW_ERR_CONFIG;
703 } 706 }
704 msix_vec->ceq_id = ceq_id; 707 msix_vec->ceq_id = ceq_id;
705 msix_vec->cpu_affinity = 0;
706 708
707 return 0; 709 return 0;
708} 710}
@@ -930,6 +932,7 @@ static enum i40iw_status_code i40iw_initialize_ilq(struct i40iw_device *iwdev)
930 struct i40iw_puda_rsrc_info info; 932 struct i40iw_puda_rsrc_info info;
931 enum i40iw_status_code status; 933 enum i40iw_status_code status;
932 934
935 memset(&info, 0, sizeof(info));
933 info.type = I40IW_PUDA_RSRC_TYPE_ILQ; 936 info.type = I40IW_PUDA_RSRC_TYPE_ILQ;
934 info.cq_id = 1; 937 info.cq_id = 1;
935 info.qp_id = 0; 938 info.qp_id = 0;
@@ -939,10 +942,9 @@ static enum i40iw_status_code i40iw_initialize_ilq(struct i40iw_device *iwdev)
939 info.rq_size = 8192; 942 info.rq_size = 8192;
940 info.buf_size = 1024; 943 info.buf_size = 1024;
941 info.tx_buf_cnt = 16384; 944 info.tx_buf_cnt = 16384;
942 info.mss = iwdev->mss;
943 info.receive = i40iw_receive_ilq; 945 info.receive = i40iw_receive_ilq;
944 info.xmit_complete = i40iw_free_sqbuf; 946 info.xmit_complete = i40iw_free_sqbuf;
945 status = i40iw_puda_create_rsrc(&iwdev->sc_dev, &info); 947 status = i40iw_puda_create_rsrc(&iwdev->vsi, &info);
946 if (status) 948 if (status)
947 i40iw_pr_err("ilq create fail\n"); 949 i40iw_pr_err("ilq create fail\n");
948 return status; 950 return status;
@@ -959,6 +961,7 @@ static enum i40iw_status_code i40iw_initialize_ieq(struct i40iw_device *iwdev)
959 struct i40iw_puda_rsrc_info info; 961 struct i40iw_puda_rsrc_info info;
960 enum i40iw_status_code status; 962 enum i40iw_status_code status;
961 963
964 memset(&info, 0, sizeof(info));
962 info.type = I40IW_PUDA_RSRC_TYPE_IEQ; 965 info.type = I40IW_PUDA_RSRC_TYPE_IEQ;
963 info.cq_id = 2; 966 info.cq_id = 2;
964 info.qp_id = iwdev->sc_dev.exception_lan_queue; 967 info.qp_id = iwdev->sc_dev.exception_lan_queue;
@@ -967,9 +970,8 @@ static enum i40iw_status_code i40iw_initialize_ieq(struct i40iw_device *iwdev)
967 info.sq_size = 8192; 970 info.sq_size = 8192;
968 info.rq_size = 8192; 971 info.rq_size = 8192;
969 info.buf_size = 2048; 972 info.buf_size = 2048;
970 info.mss = iwdev->mss;
971 info.tx_buf_cnt = 16384; 973 info.tx_buf_cnt = 16384;
972 status = i40iw_puda_create_rsrc(&iwdev->sc_dev, &info); 974 status = i40iw_puda_create_rsrc(&iwdev->vsi, &info);
973 if (status) 975 if (status)
974 i40iw_pr_err("ieq create fail\n"); 976 i40iw_pr_err("ieq create fail\n");
975 return status; 977 return status;
@@ -1159,7 +1161,7 @@ static void i40iw_add_ipv6_addr(struct i40iw_device *iwdev)
1159{ 1161{
1160 struct net_device *ip_dev; 1162 struct net_device *ip_dev;
1161 struct inet6_dev *idev; 1163 struct inet6_dev *idev;
1162 struct inet6_ifaddr *ifp; 1164 struct inet6_ifaddr *ifp, *tmp;
1163 u32 local_ipaddr6[4]; 1165 u32 local_ipaddr6[4];
1164 1166
1165 rcu_read_lock(); 1167 rcu_read_lock();
@@ -1172,7 +1174,7 @@ static void i40iw_add_ipv6_addr(struct i40iw_device *iwdev)
1172 i40iw_pr_err("ipv6 inet device not found\n"); 1174 i40iw_pr_err("ipv6 inet device not found\n");
1173 break; 1175 break;
1174 } 1176 }
1175 list_for_each_entry(ifp, &idev->addr_list, if_list) { 1177 list_for_each_entry_safe(ifp, tmp, &idev->addr_list, if_list) {
1176 i40iw_pr_info("IP=%pI6, vlan_id=%d, MAC=%pM\n", &ifp->addr, 1178 i40iw_pr_info("IP=%pI6, vlan_id=%d, MAC=%pM\n", &ifp->addr,
1177 rdma_vlan_dev_vlan_id(ip_dev), ip_dev->dev_addr); 1179 rdma_vlan_dev_vlan_id(ip_dev), ip_dev->dev_addr);
1178 i40iw_copy_ip_ntohl(local_ipaddr6, 1180 i40iw_copy_ip_ntohl(local_ipaddr6,
@@ -1294,17 +1296,23 @@ static enum i40iw_status_code i40iw_initialize_dev(struct i40iw_device *iwdev,
1294 enum i40iw_status_code status; 1296 enum i40iw_status_code status;
1295 struct i40iw_sc_dev *dev = &iwdev->sc_dev; 1297 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1296 struct i40iw_device_init_info info; 1298 struct i40iw_device_init_info info;
1299 struct i40iw_vsi_init_info vsi_info;
1297 struct i40iw_dma_mem mem; 1300 struct i40iw_dma_mem mem;
1301 struct i40iw_l2params l2params;
1298 u32 size; 1302 u32 size;
1303 struct i40iw_vsi_stats_info stats_info;
1304 u16 last_qset = I40IW_NO_QSET;
1305 u16 qset;
1306 u32 i;
1299 1307
1308 memset(&l2params, 0, sizeof(l2params));
1300 memset(&info, 0, sizeof(info)); 1309 memset(&info, 0, sizeof(info));
1301 size = sizeof(struct i40iw_hmc_pble_rsrc) + sizeof(struct i40iw_hmc_info) + 1310 size = sizeof(struct i40iw_hmc_pble_rsrc) + sizeof(struct i40iw_hmc_info) +
1302 (sizeof(struct i40iw_hmc_obj_info) * I40IW_HMC_IW_MAX); 1311 (sizeof(struct i40iw_hmc_obj_info) * I40IW_HMC_IW_MAX);
1303 iwdev->hmc_info_mem = kzalloc(size, GFP_KERNEL); 1312 iwdev->hmc_info_mem = kzalloc(size, GFP_KERNEL);
1304 if (!iwdev->hmc_info_mem) { 1313 if (!iwdev->hmc_info_mem)
1305 i40iw_pr_err("memory alloc fail\n");
1306 return I40IW_ERR_NO_MEMORY; 1314 return I40IW_ERR_NO_MEMORY;
1307 } 1315
1308 iwdev->pble_rsrc = (struct i40iw_hmc_pble_rsrc *)iwdev->hmc_info_mem; 1316 iwdev->pble_rsrc = (struct i40iw_hmc_pble_rsrc *)iwdev->hmc_info_mem;
1309 dev->hmc_info = &iwdev->hw.hmc; 1317 dev->hmc_info = &iwdev->hw.hmc;
1310 dev->hmc_info->hmc_obj = (struct i40iw_hmc_obj_info *)(iwdev->pble_rsrc + 1); 1318 dev->hmc_info->hmc_obj = (struct i40iw_hmc_obj_info *)(iwdev->pble_rsrc + 1);
@@ -1325,7 +1333,17 @@ static enum i40iw_status_code i40iw_initialize_dev(struct i40iw_device *iwdev,
1325 info.bar0 = ldev->hw_addr; 1333 info.bar0 = ldev->hw_addr;
1326 info.hw = &iwdev->hw; 1334 info.hw = &iwdev->hw;
1327 info.debug_mask = debug; 1335 info.debug_mask = debug;
1328 info.qs_handle = ldev->params.qos.prio_qos[0].qs_handle; 1336 l2params.mss =
1337 (ldev->params.mtu) ? ldev->params.mtu - I40IW_MTU_TO_MSS : I40IW_DEFAULT_MSS;
1338 for (i = 0; i < I40E_CLIENT_MAX_USER_PRIORITY; i++) {
1339 qset = ldev->params.qos.prio_qos[i].qs_handle;
1340 l2params.qs_handle_list[i] = qset;
1341 if (last_qset == I40IW_NO_QSET)
1342 last_qset = qset;
1343 else if ((qset != last_qset) && (qset != I40IW_NO_QSET))
1344 iwdev->dcb = true;
1345 }
1346 i40iw_pr_info("DCB is set/clear = %d\n", iwdev->dcb);
1329 info.exception_lan_queue = 1; 1347 info.exception_lan_queue = 1;
1330 info.vchnl_send = i40iw_virtchnl_send; 1348 info.vchnl_send = i40iw_virtchnl_send;
1331 status = i40iw_device_init(&iwdev->sc_dev, &info); 1349 status = i40iw_device_init(&iwdev->sc_dev, &info);
@@ -1334,6 +1352,20 @@ exit:
1334 kfree(iwdev->hmc_info_mem); 1352 kfree(iwdev->hmc_info_mem);
1335 iwdev->hmc_info_mem = NULL; 1353 iwdev->hmc_info_mem = NULL;
1336 } 1354 }
1355 memset(&vsi_info, 0, sizeof(vsi_info));
1356 vsi_info.dev = &iwdev->sc_dev;
1357 vsi_info.back_vsi = (void *)iwdev;
1358 vsi_info.params = &l2params;
1359 i40iw_sc_vsi_init(&iwdev->vsi, &vsi_info);
1360
1361 if (dev->is_pf) {
1362 memset(&stats_info, 0, sizeof(stats_info));
1363 stats_info.fcn_id = ldev->fid;
1364 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL);
1365 stats_info.stats_initialize = true;
1366 if (stats_info.pestat)
1367 i40iw_vsi_stats_init(&iwdev->vsi, &stats_info);
1368 }
1337 return status; 1369 return status;
1338} 1370}
1339 1371
@@ -1384,6 +1416,7 @@ static enum i40iw_status_code i40iw_save_msix_info(struct i40iw_device *iwdev,
1384 for (i = 0, ceq_idx = 0; i < iwdev->msix_count; i++, iw_qvinfo++) { 1416 for (i = 0, ceq_idx = 0; i < iwdev->msix_count; i++, iw_qvinfo++) {
1385 iwdev->iw_msixtbl[i].idx = ldev->msix_entries[i].entry; 1417 iwdev->iw_msixtbl[i].idx = ldev->msix_entries[i].entry;
1386 iwdev->iw_msixtbl[i].irq = ldev->msix_entries[i].vector; 1418 iwdev->iw_msixtbl[i].irq = ldev->msix_entries[i].vector;
1419 iwdev->iw_msixtbl[i].cpu_affinity = ceq_idx;
1387 if (i == 0) { 1420 if (i == 0) {
1388 iw_qvinfo->aeq_idx = 0; 1421 iw_qvinfo->aeq_idx = 0;
1389 if (iwdev->msix_shared) 1422 if (iwdev->msix_shared)
@@ -1404,18 +1437,19 @@ static enum i40iw_status_code i40iw_save_msix_info(struct i40iw_device *iwdev,
1404 * i40iw_deinit_device - clean up the device resources 1437 * i40iw_deinit_device - clean up the device resources
1405 * @iwdev: iwarp device 1438 * @iwdev: iwarp device
1406 * @reset: true if called before reset 1439 * @reset: true if called before reset
1407 * @del_hdl: true if delete hdl entry
1408 * 1440 *
1409 * Destroy the ib device interface, remove the mac ip entry and ipv4/ipv6 addresses, 1441 * Destroy the ib device interface, remove the mac ip entry and ipv4/ipv6 addresses,
1410 * destroy the device queues and free the pble and the hmc objects 1442 * destroy the device queues and free the pble and the hmc objects
1411 */ 1443 */
1412static void i40iw_deinit_device(struct i40iw_device *iwdev, bool reset, bool del_hdl) 1444static void i40iw_deinit_device(struct i40iw_device *iwdev, bool reset)
1413{ 1445{
1414 struct i40e_info *ldev = iwdev->ldev; 1446 struct i40e_info *ldev = iwdev->ldev;
1415 1447
1416 struct i40iw_sc_dev *dev = &iwdev->sc_dev; 1448 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1417 1449
1418 i40iw_pr_info("state = %d\n", iwdev->init_state); 1450 i40iw_pr_info("state = %d\n", iwdev->init_state);
1451 if (iwdev->param_wq)
1452 destroy_workqueue(iwdev->param_wq);
1419 1453
1420 switch (iwdev->init_state) { 1454 switch (iwdev->init_state) {
1421 case RDMA_DEV_REGISTERED: 1455 case RDMA_DEV_REGISTERED:
@@ -1441,10 +1475,10 @@ static void i40iw_deinit_device(struct i40iw_device *iwdev, bool reset, bool del
1441 i40iw_destroy_aeq(iwdev, reset); 1475 i40iw_destroy_aeq(iwdev, reset);
1442 /* fallthrough */ 1476 /* fallthrough */
1443 case IEQ_CREATED: 1477 case IEQ_CREATED:
1444 i40iw_puda_dele_resources(dev, I40IW_PUDA_RSRC_TYPE_IEQ, reset); 1478 i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_IEQ, reset);
1445 /* fallthrough */ 1479 /* fallthrough */
1446 case ILQ_CREATED: 1480 case ILQ_CREATED:
1447 i40iw_puda_dele_resources(dev, I40IW_PUDA_RSRC_TYPE_ILQ, reset); 1481 i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_ILQ, reset);
1448 /* fallthrough */ 1482 /* fallthrough */
1449 case CCQ_CREATED: 1483 case CCQ_CREATED:
1450 i40iw_destroy_ccq(iwdev, reset); 1484 i40iw_destroy_ccq(iwdev, reset);
@@ -1456,13 +1490,14 @@ static void i40iw_deinit_device(struct i40iw_device *iwdev, bool reset, bool del
1456 i40iw_del_hmc_objects(dev, dev->hmc_info, true, reset); 1490 i40iw_del_hmc_objects(dev, dev->hmc_info, true, reset);
1457 /* fallthrough */ 1491 /* fallthrough */
1458 case CQP_CREATED: 1492 case CQP_CREATED:
1459 i40iw_destroy_cqp(iwdev, !reset); 1493 i40iw_destroy_cqp(iwdev, true);
1460 /* fallthrough */ 1494 /* fallthrough */
1461 case INITIAL_STATE: 1495 case INITIAL_STATE:
1462 i40iw_cleanup_cm_core(&iwdev->cm_core); 1496 i40iw_cleanup_cm_core(&iwdev->cm_core);
1463 if (dev->is_pf) 1497 if (iwdev->vsi.pestat) {
1464 i40iw_hw_stats_del_timer(dev); 1498 i40iw_vsi_stats_free(&iwdev->vsi);
1465 1499 kfree(iwdev->vsi.pestat);
1500 }
1466 i40iw_del_init_mem(iwdev); 1501 i40iw_del_init_mem(iwdev);
1467 break; 1502 break;
1468 case INVALID_STATE: 1503 case INVALID_STATE:
@@ -1472,8 +1507,7 @@ static void i40iw_deinit_device(struct i40iw_device *iwdev, bool reset, bool del
1472 break; 1507 break;
1473 } 1508 }
1474 1509
1475 if (del_hdl) 1510 i40iw_del_handler(i40iw_find_i40e_handler(ldev));
1476 i40iw_del_handler(i40iw_find_i40e_handler(ldev));
1477 kfree(iwdev->hdl); 1511 kfree(iwdev->hdl);
1478} 1512}
1479 1513
@@ -1508,7 +1542,6 @@ static enum i40iw_status_code i40iw_setup_init_state(struct i40iw_handler *hdl,
1508 iwdev->max_enabled_vfs = iwdev->max_rdma_vfs; 1542 iwdev->max_enabled_vfs = iwdev->max_rdma_vfs;
1509 iwdev->netdev = ldev->netdev; 1543 iwdev->netdev = ldev->netdev;
1510 hdl->client = client; 1544 hdl->client = client;
1511 iwdev->mss = (!ldev->params.mtu) ? I40IW_DEFAULT_MSS : ldev->params.mtu - I40IW_MTU_TO_MSS;
1512 if (!ldev->ftype) 1545 if (!ldev->ftype)
1513 iwdev->db_start = pci_resource_start(ldev->pcidev, 0) + I40IW_DB_ADDR_OFFSET; 1546 iwdev->db_start = pci_resource_start(ldev->pcidev, 0) + I40IW_DB_ADDR_OFFSET;
1514 else 1547 else
@@ -1528,6 +1561,7 @@ static enum i40iw_status_code i40iw_setup_init_state(struct i40iw_handler *hdl,
1528 1561
1529 init_waitqueue_head(&iwdev->vchnl_waitq); 1562 init_waitqueue_head(&iwdev->vchnl_waitq);
1530 init_waitqueue_head(&dev->vf_reqs); 1563 init_waitqueue_head(&dev->vf_reqs);
1564 init_waitqueue_head(&iwdev->close_wq);
1531 1565
1532 status = i40iw_initialize_dev(iwdev, ldev); 1566 status = i40iw_initialize_dev(iwdev, ldev);
1533exit: 1567exit:
@@ -1540,6 +1574,20 @@ exit:
1540} 1574}
1541 1575
1542/** 1576/**
1577 * i40iw_get_used_rsrc - determine resources used internally
1578 * @iwdev: iwarp device
1579 *
1580 * Called after internal allocations
1581 */
1582static void i40iw_get_used_rsrc(struct i40iw_device *iwdev)
1583{
1584 iwdev->used_pds = find_next_zero_bit(iwdev->allocated_pds, iwdev->max_pd, 0);
1585 iwdev->used_qps = find_next_zero_bit(iwdev->allocated_qps, iwdev->max_qp, 0);
1586 iwdev->used_cqs = find_next_zero_bit(iwdev->allocated_cqs, iwdev->max_cq, 0);
1587 iwdev->used_mrs = find_next_zero_bit(iwdev->allocated_mrs, iwdev->max_mr, 0);
1588}
1589
1590/**
1543 * i40iw_open - client interface operation open for iwarp/uda device 1591 * i40iw_open - client interface operation open for iwarp/uda device
1544 * @ldev: lan device information 1592 * @ldev: lan device information
1545 * @client: iwarp client information, provided during registration 1593 * @client: iwarp client information, provided during registration
@@ -1611,6 +1659,7 @@ static int i40iw_open(struct i40e_info *ldev, struct i40e_client *client)
1611 status = i40iw_initialize_hw_resources(iwdev); 1659 status = i40iw_initialize_hw_resources(iwdev);
1612 if (status) 1660 if (status)
1613 break; 1661 break;
1662 i40iw_get_used_rsrc(iwdev);
1614 dev->ccq_ops->ccq_arm(dev->ccq); 1663 dev->ccq_ops->ccq_arm(dev->ccq);
1615 status = i40iw_hmc_init_pble(&iwdev->sc_dev, iwdev->pble_rsrc); 1664 status = i40iw_hmc_init_pble(&iwdev->sc_dev, iwdev->pble_rsrc);
1616 if (status) 1665 if (status)
@@ -1630,35 +1679,73 @@ static int i40iw_open(struct i40e_info *ldev, struct i40e_client *client)
1630 iwdev->init_state = RDMA_DEV_REGISTERED; 1679 iwdev->init_state = RDMA_DEV_REGISTERED;
1631 iwdev->iw_status = 1; 1680 iwdev->iw_status = 1;
1632 i40iw_port_ibevent(iwdev); 1681 i40iw_port_ibevent(iwdev);
1682 iwdev->param_wq = alloc_ordered_workqueue("l2params", WQ_MEM_RECLAIM);
1683 if(iwdev->param_wq == NULL)
1684 break;
1633 i40iw_pr_info("i40iw_open completed\n"); 1685 i40iw_pr_info("i40iw_open completed\n");
1634 return 0; 1686 return 0;
1635 } while (0); 1687 } while (0);
1636 1688
1637 i40iw_pr_err("status = %d last completion = %d\n", status, iwdev->init_state); 1689 i40iw_pr_err("status = %d last completion = %d\n", status, iwdev->init_state);
1638 i40iw_deinit_device(iwdev, false, false); 1690 i40iw_deinit_device(iwdev, false);
1639 return -ERESTART; 1691 return -ERESTART;
1640} 1692}
1641 1693
1642/** 1694/**
1643 * i40iw_l2param_change : handle qs handles for qos and mss change 1695 * i40iw_l2params_worker - worker for l2 params change
1696 * @work: work pointer for l2 params
1697 */
1698static void i40iw_l2params_worker(struct work_struct *work)
1699{
1700 struct l2params_work *dwork =
1701 container_of(work, struct l2params_work, work);
1702 struct i40iw_device *iwdev = dwork->iwdev;
1703
1704 i40iw_change_l2params(&iwdev->vsi, &dwork->l2params);
1705 atomic_dec(&iwdev->params_busy);
1706 kfree(work);
1707}
1708
1709/**
1710 * i40iw_l2param_change - handle qs handles for qos and mss change
1644 * @ldev: lan device information 1711 * @ldev: lan device information
1645 * @client: client for paramater change 1712 * @client: client for paramater change
1646 * @params: new parameters from L2 1713 * @params: new parameters from L2
1647 */ 1714 */
1648static void i40iw_l2param_change(struct i40e_info *ldev, 1715static void i40iw_l2param_change(struct i40e_info *ldev, struct i40e_client *client,
1649 struct i40e_client *client,
1650 struct i40e_params *params) 1716 struct i40e_params *params)
1651{ 1717{
1652 struct i40iw_handler *hdl; 1718 struct i40iw_handler *hdl;
1719 struct i40iw_l2params *l2params;
1720 struct l2params_work *work;
1653 struct i40iw_device *iwdev; 1721 struct i40iw_device *iwdev;
1722 int i;
1654 1723
1655 hdl = i40iw_find_i40e_handler(ldev); 1724 hdl = i40iw_find_i40e_handler(ldev);
1656 if (!hdl) 1725 if (!hdl)
1657 return; 1726 return;
1658 1727
1659 iwdev = &hdl->device; 1728 iwdev = &hdl->device;
1660 if (params->mtu) 1729
1661 iwdev->mss = params->mtu - I40IW_MTU_TO_MSS; 1730 if (atomic_read(&iwdev->params_busy))
1731 return;
1732
1733
1734 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1735 if (!work)
1736 return;
1737
1738 atomic_inc(&iwdev->params_busy);
1739
1740 work->iwdev = iwdev;
1741 l2params = &work->l2params;
1742 for (i = 0; i < I40E_CLIENT_MAX_USER_PRIORITY; i++)
1743 l2params->qs_handle_list[i] = params->qos.prio_qos[i].qs_handle;
1744
1745 l2params->mss = (params->mtu) ? params->mtu - I40IW_MTU_TO_MSS : iwdev->vsi.mss;
1746
1747 INIT_WORK(&work->work, i40iw_l2params_worker);
1748 queue_work(iwdev->param_wq, &work->work);
1662} 1749}
1663 1750
1664/** 1751/**
@@ -1679,8 +1766,11 @@ static void i40iw_close(struct i40e_info *ldev, struct i40e_client *client, bool
1679 return; 1766 return;
1680 1767
1681 iwdev = &hdl->device; 1768 iwdev = &hdl->device;
1769 iwdev->closing = true;
1770
1771 i40iw_cm_disconnect_all(iwdev);
1682 destroy_workqueue(iwdev->virtchnl_wq); 1772 destroy_workqueue(iwdev->virtchnl_wq);
1683 i40iw_deinit_device(iwdev, reset, true); 1773 i40iw_deinit_device(iwdev, reset);
1684} 1774}
1685 1775
1686/** 1776/**
@@ -1701,21 +1791,23 @@ static void i40iw_vf_reset(struct i40e_info *ldev, struct i40e_client *client, u
1701 struct i40iw_vfdev *tmp_vfdev; 1791 struct i40iw_vfdev *tmp_vfdev;
1702 unsigned int i; 1792 unsigned int i;
1703 unsigned long flags; 1793 unsigned long flags;
1794 struct i40iw_device *iwdev;
1704 1795
1705 hdl = i40iw_find_i40e_handler(ldev); 1796 hdl = i40iw_find_i40e_handler(ldev);
1706 if (!hdl) 1797 if (!hdl)
1707 return; 1798 return;
1708 1799
1709 dev = &hdl->device.sc_dev; 1800 dev = &hdl->device.sc_dev;
1801 iwdev = (struct i40iw_device *)dev->back_dev;
1710 1802
1711 for (i = 0; i < I40IW_MAX_PE_ENABLED_VF_COUNT; i++) { 1803 for (i = 0; i < I40IW_MAX_PE_ENABLED_VF_COUNT; i++) {
1712 if (!dev->vf_dev[i] || (dev->vf_dev[i]->vf_id != vf_id)) 1804 if (!dev->vf_dev[i] || (dev->vf_dev[i]->vf_id != vf_id))
1713 continue; 1805 continue;
1714 /* free all resources allocated on behalf of vf */ 1806 /* free all resources allocated on behalf of vf */
1715 tmp_vfdev = dev->vf_dev[i]; 1807 tmp_vfdev = dev->vf_dev[i];
1716 spin_lock_irqsave(&dev->dev_pestat.stats_lock, flags); 1808 spin_lock_irqsave(&iwdev->vsi.pestat->lock, flags);
1717 dev->vf_dev[i] = NULL; 1809 dev->vf_dev[i] = NULL;
1718 spin_unlock_irqrestore(&dev->dev_pestat.stats_lock, flags); 1810 spin_unlock_irqrestore(&iwdev->vsi.pestat->lock, flags);
1719 i40iw_del_hmc_objects(dev, &tmp_vfdev->hmc_info, false, false); 1811 i40iw_del_hmc_objects(dev, &tmp_vfdev->hmc_info, false, false);
1720 /* remove vf hmc function */ 1812 /* remove vf hmc function */
1721 memset(&hmc_fcn_info, 0, sizeof(hmc_fcn_info)); 1813 memset(&hmc_fcn_info, 0, sizeof(hmc_fcn_info));
diff --git a/drivers/infiniband/hw/i40iw/i40iw_osdep.h b/drivers/infiniband/hw/i40iw/i40iw_osdep.h
index 80f422bf3967..aa66c1c63dfa 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_osdep.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_osdep.h
@@ -198,6 +198,8 @@ enum i40iw_status_code i40iw_cqp_manage_vf_pble_bp(struct i40iw_sc_dev *dev,
198void i40iw_cqp_spawn_worker(struct i40iw_sc_dev *dev, 198void i40iw_cqp_spawn_worker(struct i40iw_sc_dev *dev,
199 struct i40iw_virtchnl_work_info *work_info, u32 iw_vf_idx); 199 struct i40iw_virtchnl_work_info *work_info, u32 iw_vf_idx);
200void *i40iw_remove_head(struct list_head *list); 200void *i40iw_remove_head(struct list_head *list);
201void i40iw_qp_suspend_resume(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp, bool suspend);
202void i40iw_qp_mss_modify(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
201 203
202void i40iw_term_modify_qp(struct i40iw_sc_qp *qp, u8 next_state, u8 term, u8 term_len); 204void i40iw_term_modify_qp(struct i40iw_sc_qp *qp, u8 next_state, u8 term, u8 term_len);
203void i40iw_terminate_done(struct i40iw_sc_qp *qp, int timeout_occurred); 205void i40iw_terminate_done(struct i40iw_sc_qp *qp, int timeout_occurred);
@@ -207,9 +209,9 @@ void i40iw_terminate_del_timer(struct i40iw_sc_qp *qp);
207enum i40iw_status_code i40iw_hw_manage_vf_pble_bp(struct i40iw_device *iwdev, 209enum i40iw_status_code i40iw_hw_manage_vf_pble_bp(struct i40iw_device *iwdev,
208 struct i40iw_manage_vf_pble_info *info, 210 struct i40iw_manage_vf_pble_info *info,
209 bool wait); 211 bool wait);
210struct i40iw_dev_pestat; 212struct i40iw_sc_vsi;
211void i40iw_hw_stats_start_timer(struct i40iw_sc_dev *); 213void i40iw_hw_stats_start_timer(struct i40iw_sc_vsi *vsi);
212void i40iw_hw_stats_del_timer(struct i40iw_sc_dev *); 214void i40iw_hw_stats_stop_timer(struct i40iw_sc_vsi *vsi);
213#define i40iw_mmiowb() mmiowb() 215#define i40iw_mmiowb() mmiowb()
214void i40iw_wr32(struct i40iw_hw *hw, u32 reg, u32 value); 216void i40iw_wr32(struct i40iw_hw *hw, u32 reg, u32 value);
215u32 i40iw_rd32(struct i40iw_hw *hw, u32 reg); 217u32 i40iw_rd32(struct i40iw_hw *hw, u32 reg);
diff --git a/drivers/infiniband/hw/i40iw/i40iw_p.h b/drivers/infiniband/hw/i40iw/i40iw_p.h
index a0b8ca10d67e..28a92fee0822 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_p.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_p.h
@@ -47,8 +47,6 @@ void i40iw_debug_buf(struct i40iw_sc_dev *dev, enum i40iw_debug_flag mask,
47enum i40iw_status_code i40iw_device_init(struct i40iw_sc_dev *dev, 47enum i40iw_status_code i40iw_device_init(struct i40iw_sc_dev *dev,
48 struct i40iw_device_init_info *info); 48 struct i40iw_device_init_info *info);
49 49
50enum i40iw_status_code i40iw_device_init_pestat(struct i40iw_dev_pestat *);
51
52void i40iw_sc_cqp_post_sq(struct i40iw_sc_cqp *cqp); 50void i40iw_sc_cqp_post_sq(struct i40iw_sc_cqp *cqp);
53 51
54u64 *i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp *cqp, u64 scratch); 52u64 *i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp *cqp, u64 scratch);
@@ -64,7 +62,24 @@ enum i40iw_status_code i40iw_sc_init_iw_hmc(struct i40iw_sc_dev *dev,
64enum i40iw_status_code i40iw_pf_init_vfhmc(struct i40iw_sc_dev *dev, u8 vf_hmc_fn_id, 62enum i40iw_status_code i40iw_pf_init_vfhmc(struct i40iw_sc_dev *dev, u8 vf_hmc_fn_id,
65 u32 *vf_cnt_array); 63 u32 *vf_cnt_array);
66 64
67/* cqp misc functions */ 65/* stats functions */
66void i40iw_hw_stats_refresh_all(struct i40iw_vsi_pestat *stats);
67void i40iw_hw_stats_read_all(struct i40iw_vsi_pestat *stats, struct i40iw_dev_hw_stats *stats_values);
68void i40iw_hw_stats_read_32(struct i40iw_vsi_pestat *stats,
69 enum i40iw_hw_stats_index_32b index,
70 u64 *value);
71void i40iw_hw_stats_read_64(struct i40iw_vsi_pestat *stats,
72 enum i40iw_hw_stats_index_64b index,
73 u64 *value);
74void i40iw_hw_stats_init(struct i40iw_vsi_pestat *stats, u8 index, bool is_pf);
75
76/* vsi misc functions */
77enum i40iw_status_code i40iw_vsi_stats_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_stats_info *info);
78void i40iw_vsi_stats_free(struct i40iw_sc_vsi *vsi);
79void i40iw_sc_vsi_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_init_info *info);
80
81void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2params);
82void i40iw_qp_add_qos(struct i40iw_sc_qp *qp);
68 83
69void i40iw_terminate_send_fin(struct i40iw_sc_qp *qp); 84void i40iw_terminate_send_fin(struct i40iw_sc_qp *qp);
70 85
diff --git a/drivers/infiniband/hw/i40iw/i40iw_pble.c b/drivers/infiniband/hw/i40iw/i40iw_pble.c
index 85993dc44f6e..c87ba1617087 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_pble.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_pble.c
@@ -353,10 +353,6 @@ static enum i40iw_status_code add_pble_pool(struct i40iw_sc_dev *dev,
353 pages = (idx->rel_pd_idx) ? (I40IW_HMC_PD_CNT_IN_SD - 353 pages = (idx->rel_pd_idx) ? (I40IW_HMC_PD_CNT_IN_SD -
354 idx->rel_pd_idx) : I40IW_HMC_PD_CNT_IN_SD; 354 idx->rel_pd_idx) : I40IW_HMC_PD_CNT_IN_SD;
355 pages = min(pages, pble_rsrc->unallocated_pble >> PBLE_512_SHIFT); 355 pages = min(pages, pble_rsrc->unallocated_pble >> PBLE_512_SHIFT);
356 if (!pages) {
357 ret_code = I40IW_ERR_NO_PBLCHUNKS_AVAILABLE;
358 goto error;
359 }
360 info.chunk = chunk; 356 info.chunk = chunk;
361 info.hmc_info = hmc_info; 357 info.hmc_info = hmc_info;
362 info.pages = pages; 358 info.pages = pages;
diff --git a/drivers/infiniband/hw/i40iw/i40iw_puda.c b/drivers/infiniband/hw/i40iw/i40iw_puda.c
index c62d354f7810..449ba8c81ce7 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_puda.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_puda.c
@@ -42,12 +42,13 @@
42#include "i40iw_p.h" 42#include "i40iw_p.h"
43#include "i40iw_puda.h" 43#include "i40iw_puda.h"
44 44
45static void i40iw_ieq_receive(struct i40iw_sc_dev *dev, 45static void i40iw_ieq_receive(struct i40iw_sc_vsi *vsi,
46 struct i40iw_puda_buf *buf); 46 struct i40iw_puda_buf *buf);
47static void i40iw_ieq_tx_compl(struct i40iw_sc_dev *dev, void *sqwrid); 47static void i40iw_ieq_tx_compl(struct i40iw_sc_vsi *vsi, void *sqwrid);
48static void i40iw_ilq_putback_rcvbuf(struct i40iw_sc_qp *qp, u32 wqe_idx); 48static void i40iw_ilq_putback_rcvbuf(struct i40iw_sc_qp *qp, u32 wqe_idx);
49static enum i40iw_status_code i40iw_puda_replenish_rq(struct i40iw_puda_rsrc 49static enum i40iw_status_code i40iw_puda_replenish_rq(struct i40iw_puda_rsrc
50 *rsrc, bool initial); 50 *rsrc, bool initial);
51static void i40iw_ieq_cleanup_qp(struct i40iw_puda_rsrc *ieq, struct i40iw_sc_qp *qp);
51/** 52/**
52 * i40iw_puda_get_listbuf - get buffer from puda list 53 * i40iw_puda_get_listbuf - get buffer from puda list
53 * @list: list to use for buffers (ILQ or IEQ) 54 * @list: list to use for buffers (ILQ or IEQ)
@@ -292,7 +293,7 @@ enum i40iw_status_code i40iw_puda_poll_completion(struct i40iw_sc_dev *dev,
292 unsigned long flags; 293 unsigned long flags;
293 294
294 if ((cq_type == I40IW_CQ_TYPE_ILQ) || (cq_type == I40IW_CQ_TYPE_IEQ)) { 295 if ((cq_type == I40IW_CQ_TYPE_ILQ) || (cq_type == I40IW_CQ_TYPE_IEQ)) {
295 rsrc = (cq_type == I40IW_CQ_TYPE_ILQ) ? dev->ilq : dev->ieq; 296 rsrc = (cq_type == I40IW_CQ_TYPE_ILQ) ? cq->vsi->ilq : cq->vsi->ieq;
296 } else { 297 } else {
297 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s qp_type error\n", __func__); 298 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s qp_type error\n", __func__);
298 return I40IW_ERR_BAD_PTR; 299 return I40IW_ERR_BAD_PTR;
@@ -335,7 +336,7 @@ enum i40iw_status_code i40iw_puda_poll_completion(struct i40iw_sc_dev *dev,
335 rsrc->stats_pkt_rcvd++; 336 rsrc->stats_pkt_rcvd++;
336 rsrc->compl_rxwqe_idx = info.wqe_idx; 337 rsrc->compl_rxwqe_idx = info.wqe_idx;
337 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s RQ completion\n", __func__); 338 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s RQ completion\n", __func__);
338 rsrc->receive(rsrc->dev, buf); 339 rsrc->receive(rsrc->vsi, buf);
339 if (cq_type == I40IW_CQ_TYPE_ILQ) 340 if (cq_type == I40IW_CQ_TYPE_ILQ)
340 i40iw_ilq_putback_rcvbuf(&rsrc->qp, info.wqe_idx); 341 i40iw_ilq_putback_rcvbuf(&rsrc->qp, info.wqe_idx);
341 else 342 else
@@ -345,12 +346,12 @@ enum i40iw_status_code i40iw_puda_poll_completion(struct i40iw_sc_dev *dev,
345 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s SQ completion\n", __func__); 346 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s SQ completion\n", __func__);
346 sqwrid = (void *)(uintptr_t)qp->sq_wrtrk_array[info.wqe_idx].wrid; 347 sqwrid = (void *)(uintptr_t)qp->sq_wrtrk_array[info.wqe_idx].wrid;
347 I40IW_RING_SET_TAIL(qp->sq_ring, info.wqe_idx); 348 I40IW_RING_SET_TAIL(qp->sq_ring, info.wqe_idx);
348 rsrc->xmit_complete(rsrc->dev, sqwrid); 349 rsrc->xmit_complete(rsrc->vsi, sqwrid);
349 spin_lock_irqsave(&rsrc->bufpool_lock, flags); 350 spin_lock_irqsave(&rsrc->bufpool_lock, flags);
350 rsrc->tx_wqe_avail_cnt++; 351 rsrc->tx_wqe_avail_cnt++;
351 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); 352 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags);
352 if (!list_empty(&dev->ilq->txpend)) 353 if (!list_empty(&rsrc->vsi->ilq->txpend))
353 i40iw_puda_send_buf(dev->ilq, NULL); 354 i40iw_puda_send_buf(rsrc->vsi->ilq, NULL);
354 } 355 }
355 356
356done: 357done:
@@ -513,10 +514,8 @@ static void i40iw_puda_qp_setctx(struct i40iw_puda_rsrc *rsrc)
513 * i40iw_puda_qp_wqe - setup wqe for qp create 514 * i40iw_puda_qp_wqe - setup wqe for qp create
514 * @rsrc: resource for qp 515 * @rsrc: resource for qp
515 */ 516 */
516static enum i40iw_status_code i40iw_puda_qp_wqe(struct i40iw_puda_rsrc *rsrc) 517static enum i40iw_status_code i40iw_puda_qp_wqe(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp)
517{ 518{
518 struct i40iw_sc_qp *qp = &rsrc->qp;
519 struct i40iw_sc_dev *dev = rsrc->dev;
520 struct i40iw_sc_cqp *cqp; 519 struct i40iw_sc_cqp *cqp;
521 u64 *wqe; 520 u64 *wqe;
522 u64 header; 521 u64 header;
@@ -582,6 +581,7 @@ static enum i40iw_status_code i40iw_puda_qp_create(struct i40iw_puda_rsrc *rsrc)
582 qp->back_qp = (void *)rsrc; 581 qp->back_qp = (void *)rsrc;
583 qp->sq_pa = mem->pa; 582 qp->sq_pa = mem->pa;
584 qp->rq_pa = qp->sq_pa + sq_size; 583 qp->rq_pa = qp->sq_pa + sq_size;
584 qp->vsi = rsrc->vsi;
585 ukqp->sq_base = mem->va; 585 ukqp->sq_base = mem->va;
586 ukqp->rq_base = &ukqp->sq_base[rsrc->sq_size]; 586 ukqp->rq_base = &ukqp->sq_base[rsrc->sq_size];
587 ukqp->shadow_area = ukqp->rq_base[rsrc->rq_size].elem; 587 ukqp->shadow_area = ukqp->rq_base[rsrc->rq_size].elem;
@@ -608,15 +608,63 @@ static enum i40iw_status_code i40iw_puda_qp_create(struct i40iw_puda_rsrc *rsrc)
608 ukqp->wqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(qp->pd->dev) + 608 ukqp->wqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(qp->pd->dev) +
609 I40E_VFPE_WQEALLOC1); 609 I40E_VFPE_WQEALLOC1);
610 610
611 qp->qs_handle = qp->dev->qs_handle; 611 qp->user_pri = 0;
612 i40iw_qp_add_qos(qp);
612 i40iw_puda_qp_setctx(rsrc); 613 i40iw_puda_qp_setctx(rsrc);
613 ret = i40iw_puda_qp_wqe(rsrc); 614 if (rsrc->ceq_valid)
615 ret = i40iw_cqp_qp_create_cmd(rsrc->dev, qp);
616 else
617 ret = i40iw_puda_qp_wqe(rsrc->dev, qp);
614 if (ret) 618 if (ret)
615 i40iw_free_dma_mem(rsrc->dev->hw, &rsrc->qpmem); 619 i40iw_free_dma_mem(rsrc->dev->hw, &rsrc->qpmem);
616 return ret; 620 return ret;
617} 621}
618 622
619/** 623/**
624 * i40iw_puda_cq_wqe - setup wqe for cq create
625 * @rsrc: resource for cq
626 */
627static enum i40iw_status_code i40iw_puda_cq_wqe(struct i40iw_sc_dev *dev, struct i40iw_sc_cq *cq)
628{
629 u64 *wqe;
630 struct i40iw_sc_cqp *cqp;
631 u64 header;
632 struct i40iw_ccq_cqe_info compl_info;
633 enum i40iw_status_code status = 0;
634
635 cqp = dev->cqp;
636 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, 0);
637 if (!wqe)
638 return I40IW_ERR_RING_FULL;
639
640 set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
641 set_64bit_val(wqe, 8, RS_64_1(cq, 1));
642 set_64bit_val(wqe, 16,
643 LS_64(cq->shadow_read_threshold,
644 I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
645 set_64bit_val(wqe, 32, cq->cq_pa);
646
647 set_64bit_val(wqe, 40, cq->shadow_area_pa);
648
649 header = cq->cq_uk.cq_id |
650 LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) |
651 LS_64(1, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
652 LS_64(1, I40IW_CQPSQ_CQ_ENCEQEMASK) |
653 LS_64(1, I40IW_CQPSQ_CQ_CEQIDVALID) |
654 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
655 set_64bit_val(wqe, 24, header);
656
657 i40iw_debug_buf(dev, I40IW_DEBUG_PUDA, "PUDA CQE",
658 wqe, I40IW_CQP_WQE_SIZE * 8);
659
660 i40iw_sc_cqp_post_sq(dev->cqp);
661 status = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
662 I40IW_CQP_OP_CREATE_CQ,
663 &compl_info);
664 return status;
665}
666
667/**
620 * i40iw_puda_cq_create - create cq for resource 668 * i40iw_puda_cq_create - create cq for resource
621 * @rsrc: resource for which cq to create 669 * @rsrc: resource for which cq to create
622 */ 670 */
@@ -624,18 +672,13 @@ static enum i40iw_status_code i40iw_puda_cq_create(struct i40iw_puda_rsrc *rsrc)
624{ 672{
625 struct i40iw_sc_dev *dev = rsrc->dev; 673 struct i40iw_sc_dev *dev = rsrc->dev;
626 struct i40iw_sc_cq *cq = &rsrc->cq; 674 struct i40iw_sc_cq *cq = &rsrc->cq;
627 u64 *wqe;
628 struct i40iw_sc_cqp *cqp;
629 u64 header;
630 enum i40iw_status_code ret = 0; 675 enum i40iw_status_code ret = 0;
631 u32 tsize, cqsize; 676 u32 tsize, cqsize;
632 u32 shadow_read_threshold = 128;
633 struct i40iw_dma_mem *mem; 677 struct i40iw_dma_mem *mem;
634 struct i40iw_ccq_cqe_info compl_info;
635 struct i40iw_cq_init_info info; 678 struct i40iw_cq_init_info info;
636 struct i40iw_cq_uk_init_info *init_info = &info.cq_uk_init_info; 679 struct i40iw_cq_uk_init_info *init_info = &info.cq_uk_init_info;
637 680
638 cq->back_cq = (void *)rsrc; 681 cq->vsi = rsrc->vsi;
639 cqsize = rsrc->cq_size * (sizeof(struct i40iw_cqe)); 682 cqsize = rsrc->cq_size * (sizeof(struct i40iw_cqe));
640 tsize = cqsize + sizeof(struct i40iw_cq_shadow_area); 683 tsize = cqsize + sizeof(struct i40iw_cq_shadow_area);
641 ret = i40iw_allocate_dma_mem(dev->hw, &rsrc->cqmem, tsize, 684 ret = i40iw_allocate_dma_mem(dev->hw, &rsrc->cqmem, tsize,
@@ -656,43 +699,84 @@ static enum i40iw_status_code i40iw_puda_cq_create(struct i40iw_puda_rsrc *rsrc)
656 init_info->shadow_area = (u64 *)((u8 *)mem->va + cqsize); 699 init_info->shadow_area = (u64 *)((u8 *)mem->va + cqsize);
657 init_info->cq_size = rsrc->cq_size; 700 init_info->cq_size = rsrc->cq_size;
658 init_info->cq_id = rsrc->cq_id; 701 init_info->cq_id = rsrc->cq_id;
702 info.ceqe_mask = true;
703 info.ceq_id_valid = true;
659 ret = dev->iw_priv_cq_ops->cq_init(cq, &info); 704 ret = dev->iw_priv_cq_ops->cq_init(cq, &info);
660 if (ret) 705 if (ret)
661 goto error; 706 goto error;
662 cqp = dev->cqp; 707 if (rsrc->ceq_valid)
663 wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, 0); 708 ret = i40iw_cqp_cq_create_cmd(dev, cq);
664 if (!wqe) { 709 else
665 ret = I40IW_ERR_RING_FULL; 710 ret = i40iw_puda_cq_wqe(dev, cq);
666 goto error; 711error:
667 } 712 if (ret)
713 i40iw_free_dma_mem(dev->hw, &rsrc->cqmem);
714 return ret;
715}
668 716
669 set_64bit_val(wqe, 0, rsrc->cq_size); 717/**
670 set_64bit_val(wqe, 8, RS_64_1(cq, 1)); 718 * i40iw_puda_free_qp - free qp for resource
671 set_64bit_val(wqe, 16, LS_64(shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD)); 719 * @rsrc: resource for which qp to free
672 set_64bit_val(wqe, 32, cq->cq_pa); 720 */
721static void i40iw_puda_free_qp(struct i40iw_puda_rsrc *rsrc)
722{
723 enum i40iw_status_code ret;
724 struct i40iw_ccq_cqe_info compl_info;
725 struct i40iw_sc_dev *dev = rsrc->dev;
673 726
674 set_64bit_val(wqe, 40, cq->shadow_area_pa); 727 if (rsrc->ceq_valid) {
728 i40iw_cqp_qp_destroy_cmd(dev, &rsrc->qp);
729 return;
730 }
675 731
676 header = rsrc->cq_id | 732 ret = dev->iw_priv_qp_ops->qp_destroy(&rsrc->qp,
677 LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) | 733 0, false, true, true);
678 LS_64(1, I40IW_CQPSQ_CQ_CHKOVERFLOW) | 734 if (ret)
679 LS_64(1, I40IW_CQPSQ_CQ_ENCEQEMASK) | 735 i40iw_debug(dev, I40IW_DEBUG_PUDA,
680 LS_64(1, I40IW_CQPSQ_CQ_CEQIDVALID) | 736 "%s error puda qp destroy wqe\n",
681 LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID); 737 __func__);
682 set_64bit_val(wqe, 24, header);
683 738
684 i40iw_debug_buf(dev, I40IW_DEBUG_PUDA, "PUDA CQE", 739 if (!ret) {
685 wqe, I40IW_CQP_WQE_SIZE * 8); 740 ret = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
741 I40IW_CQP_OP_DESTROY_QP,
742 &compl_info);
743 if (ret)
744 i40iw_debug(dev, I40IW_DEBUG_PUDA,
745 "%s error puda qp destroy failed\n",
746 __func__);
747 }
748}
686 749
687 i40iw_sc_cqp_post_sq(dev->cqp); 750/**
688 ret = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp, 751 * i40iw_puda_free_cq - free cq for resource
689 I40IW_CQP_OP_CREATE_CQ, 752 * @rsrc: resource for which cq to free
690 &compl_info); 753 */
754static void i40iw_puda_free_cq(struct i40iw_puda_rsrc *rsrc)
755{
756 enum i40iw_status_code ret;
757 struct i40iw_ccq_cqe_info compl_info;
758 struct i40iw_sc_dev *dev = rsrc->dev;
759
760 if (rsrc->ceq_valid) {
761 i40iw_cqp_cq_destroy_cmd(dev, &rsrc->cq);
762 return;
763 }
764 ret = dev->iw_priv_cq_ops->cq_destroy(&rsrc->cq, 0, true);
691 765
692error:
693 if (ret) 766 if (ret)
694 i40iw_free_dma_mem(dev->hw, &rsrc->cqmem); 767 i40iw_debug(dev, I40IW_DEBUG_PUDA,
695 return ret; 768 "%s error ieq cq destroy\n",
769 __func__);
770
771 if (!ret) {
772 ret = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
773 I40IW_CQP_OP_DESTROY_CQ,
774 &compl_info);
775 if (ret)
776 i40iw_debug(dev, I40IW_DEBUG_PUDA,
777 "%s error ieq qp destroy done\n",
778 __func__);
779 }
696} 780}
697 781
698/** 782/**
@@ -701,25 +785,24 @@ error:
701 * @type: type of resource to dele 785 * @type: type of resource to dele
702 * @reset: true if reset chip 786 * @reset: true if reset chip
703 */ 787 */
704void i40iw_puda_dele_resources(struct i40iw_sc_dev *dev, 788void i40iw_puda_dele_resources(struct i40iw_sc_vsi *vsi,
705 enum puda_resource_type type, 789 enum puda_resource_type type,
706 bool reset) 790 bool reset)
707{ 791{
708 struct i40iw_ccq_cqe_info compl_info; 792 struct i40iw_sc_dev *dev = vsi->dev;
709 struct i40iw_puda_rsrc *rsrc; 793 struct i40iw_puda_rsrc *rsrc;
710 struct i40iw_puda_buf *buf = NULL; 794 struct i40iw_puda_buf *buf = NULL;
711 struct i40iw_puda_buf *nextbuf = NULL; 795 struct i40iw_puda_buf *nextbuf = NULL;
712 struct i40iw_virt_mem *vmem; 796 struct i40iw_virt_mem *vmem;
713 enum i40iw_status_code ret;
714 797
715 switch (type) { 798 switch (type) {
716 case I40IW_PUDA_RSRC_TYPE_ILQ: 799 case I40IW_PUDA_RSRC_TYPE_ILQ:
717 rsrc = dev->ilq; 800 rsrc = vsi->ilq;
718 vmem = &dev->ilq_mem; 801 vmem = &vsi->ilq_mem;
719 break; 802 break;
720 case I40IW_PUDA_RSRC_TYPE_IEQ: 803 case I40IW_PUDA_RSRC_TYPE_IEQ:
721 rsrc = dev->ieq; 804 rsrc = vsi->ieq;
722 vmem = &dev->ieq_mem; 805 vmem = &vsi->ieq_mem;
723 break; 806 break;
724 default: 807 default:
725 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s: error resource type = 0x%x\n", 808 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s: error resource type = 0x%x\n",
@@ -731,45 +814,14 @@ void i40iw_puda_dele_resources(struct i40iw_sc_dev *dev,
731 case PUDA_HASH_CRC_COMPLETE: 814 case PUDA_HASH_CRC_COMPLETE:
732 i40iw_free_hash_desc(rsrc->hash_desc); 815 i40iw_free_hash_desc(rsrc->hash_desc);
733 case PUDA_QP_CREATED: 816 case PUDA_QP_CREATED:
734 do { 817 if (!reset)
735 if (reset) 818 i40iw_puda_free_qp(rsrc);
736 break;
737 ret = dev->iw_priv_qp_ops->qp_destroy(&rsrc->qp,
738 0, false, true, true);
739 if (ret)
740 i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA,
741 "%s error ieq qp destroy\n",
742 __func__);
743
744 ret = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
745 I40IW_CQP_OP_DESTROY_QP,
746 &compl_info);
747 if (ret)
748 i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA,
749 "%s error ieq qp destroy done\n",
750 __func__);
751 } while (0);
752 819
753 i40iw_free_dma_mem(dev->hw, &rsrc->qpmem); 820 i40iw_free_dma_mem(dev->hw, &rsrc->qpmem);
754 /* fallthrough */ 821 /* fallthrough */
755 case PUDA_CQ_CREATED: 822 case PUDA_CQ_CREATED:
756 do { 823 if (!reset)
757 if (reset) 824 i40iw_puda_free_cq(rsrc);
758 break;
759 ret = dev->iw_priv_cq_ops->cq_destroy(&rsrc->cq, 0, true);
760 if (ret)
761 i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA,
762 "%s error ieq cq destroy\n",
763 __func__);
764
765 ret = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
766 I40IW_CQP_OP_DESTROY_CQ,
767 &compl_info);
768 if (ret)
769 i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA,
770 "%s error ieq qp destroy done\n",
771 __func__);
772 } while (0);
773 825
774 i40iw_free_dma_mem(dev->hw, &rsrc->cqmem); 826 i40iw_free_dma_mem(dev->hw, &rsrc->cqmem);
775 break; 827 break;
@@ -825,9 +877,10 @@ static enum i40iw_status_code i40iw_puda_allocbufs(struct i40iw_puda_rsrc *rsrc,
825 * @dev: iwarp device 877 * @dev: iwarp device
826 * @info: resource information 878 * @info: resource information
827 */ 879 */
828enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_dev *dev, 880enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_vsi *vsi,
829 struct i40iw_puda_rsrc_info *info) 881 struct i40iw_puda_rsrc_info *info)
830{ 882{
883 struct i40iw_sc_dev *dev = vsi->dev;
831 enum i40iw_status_code ret = 0; 884 enum i40iw_status_code ret = 0;
832 struct i40iw_puda_rsrc *rsrc; 885 struct i40iw_puda_rsrc *rsrc;
833 u32 pudasize; 886 u32 pudasize;
@@ -840,10 +893,10 @@ enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_dev *dev,
840 rqwridsize = info->rq_size * 8; 893 rqwridsize = info->rq_size * 8;
841 switch (info->type) { 894 switch (info->type) {
842 case I40IW_PUDA_RSRC_TYPE_ILQ: 895 case I40IW_PUDA_RSRC_TYPE_ILQ:
843 vmem = &dev->ilq_mem; 896 vmem = &vsi->ilq_mem;
844 break; 897 break;
845 case I40IW_PUDA_RSRC_TYPE_IEQ: 898 case I40IW_PUDA_RSRC_TYPE_IEQ:
846 vmem = &dev->ieq_mem; 899 vmem = &vsi->ieq_mem;
847 break; 900 break;
848 default: 901 default:
849 return I40IW_NOT_SUPPORTED; 902 return I40IW_NOT_SUPPORTED;
@@ -856,22 +909,22 @@ enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_dev *dev,
856 rsrc = (struct i40iw_puda_rsrc *)vmem->va; 909 rsrc = (struct i40iw_puda_rsrc *)vmem->va;
857 spin_lock_init(&rsrc->bufpool_lock); 910 spin_lock_init(&rsrc->bufpool_lock);
858 if (info->type == I40IW_PUDA_RSRC_TYPE_ILQ) { 911 if (info->type == I40IW_PUDA_RSRC_TYPE_ILQ) {
859 dev->ilq = (struct i40iw_puda_rsrc *)vmem->va; 912 vsi->ilq = (struct i40iw_puda_rsrc *)vmem->va;
860 dev->ilq_count = info->count; 913 vsi->ilq_count = info->count;
861 rsrc->receive = info->receive; 914 rsrc->receive = info->receive;
862 rsrc->xmit_complete = info->xmit_complete; 915 rsrc->xmit_complete = info->xmit_complete;
863 } else { 916 } else {
864 vmem = &dev->ieq_mem; 917 vmem = &vsi->ieq_mem;
865 dev->ieq_count = info->count; 918 vsi->ieq_count = info->count;
866 dev->ieq = (struct i40iw_puda_rsrc *)vmem->va; 919 vsi->ieq = (struct i40iw_puda_rsrc *)vmem->va;
867 rsrc->receive = i40iw_ieq_receive; 920 rsrc->receive = i40iw_ieq_receive;
868 rsrc->xmit_complete = i40iw_ieq_tx_compl; 921 rsrc->xmit_complete = i40iw_ieq_tx_compl;
869 } 922 }
870 923
924 rsrc->ceq_valid = info->ceq_valid;
871 rsrc->type = info->type; 925 rsrc->type = info->type;
872 rsrc->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)((u8 *)vmem->va + pudasize); 926 rsrc->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)((u8 *)vmem->va + pudasize);
873 rsrc->rq_wrid_array = (u64 *)((u8 *)vmem->va + pudasize + sqwridsize); 927 rsrc->rq_wrid_array = (u64 *)((u8 *)vmem->va + pudasize + sqwridsize);
874 rsrc->mss = info->mss;
875 /* Initialize all ieq lists */ 928 /* Initialize all ieq lists */
876 INIT_LIST_HEAD(&rsrc->bufpool); 929 INIT_LIST_HEAD(&rsrc->bufpool);
877 INIT_LIST_HEAD(&rsrc->txpend); 930 INIT_LIST_HEAD(&rsrc->txpend);
@@ -885,6 +938,7 @@ enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_dev *dev,
885 rsrc->cq_size = info->rq_size + info->sq_size; 938 rsrc->cq_size = info->rq_size + info->sq_size;
886 rsrc->buf_size = info->buf_size; 939 rsrc->buf_size = info->buf_size;
887 rsrc->dev = dev; 940 rsrc->dev = dev;
941 rsrc->vsi = vsi;
888 942
889 ret = i40iw_puda_cq_create(rsrc); 943 ret = i40iw_puda_cq_create(rsrc);
890 if (!ret) { 944 if (!ret) {
@@ -919,7 +973,7 @@ enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_dev *dev,
919 dev->ccq_ops->ccq_arm(&rsrc->cq); 973 dev->ccq_ops->ccq_arm(&rsrc->cq);
920 return ret; 974 return ret;
921 error: 975 error:
922 i40iw_puda_dele_resources(dev, info->type, false); 976 i40iw_puda_dele_resources(vsi, info->type, false);
923 977
924 return ret; 978 return ret;
925} 979}
@@ -1131,7 +1185,7 @@ static enum i40iw_status_code i40iw_ieq_handle_partial(struct i40iw_puda_rsrc *i
1131 list_add(&buf->list, &pbufl); 1185 list_add(&buf->list, &pbufl);
1132 1186
1133 status = i40iw_ieq_create_pbufl(pfpdu, rxlist, &pbufl, buf, fpdu_len); 1187 status = i40iw_ieq_create_pbufl(pfpdu, rxlist, &pbufl, buf, fpdu_len);
1134 if (!status) 1188 if (status)
1135 goto error; 1189 goto error;
1136 1190
1137 txbuf = i40iw_puda_get_bufpool(ieq); 1191 txbuf = i40iw_puda_get_bufpool(ieq);
@@ -1332,7 +1386,7 @@ static void i40iw_ieq_handle_exception(struct i40iw_puda_rsrc *ieq,
1332 } 1386 }
1333 if (pfpdu->mode && (fps != pfpdu->fps)) { 1387 if (pfpdu->mode && (fps != pfpdu->fps)) {
1334 /* clean up qp as it is new partial sequence */ 1388 /* clean up qp as it is new partial sequence */
1335 i40iw_ieq_cleanup_qp(ieq->dev, qp); 1389 i40iw_ieq_cleanup_qp(ieq, qp);
1336 i40iw_debug(ieq->dev, I40IW_DEBUG_IEQ, 1390 i40iw_debug(ieq->dev, I40IW_DEBUG_IEQ,
1337 "%s: restarting new partial\n", __func__); 1391 "%s: restarting new partial\n", __func__);
1338 pfpdu->mode = false; 1392 pfpdu->mode = false;
@@ -1344,7 +1398,7 @@ static void i40iw_ieq_handle_exception(struct i40iw_puda_rsrc *ieq,
1344 pfpdu->rcv_nxt = fps; 1398 pfpdu->rcv_nxt = fps;
1345 pfpdu->fps = fps; 1399 pfpdu->fps = fps;
1346 pfpdu->mode = true; 1400 pfpdu->mode = true;
1347 pfpdu->max_fpdu_data = ieq->mss; 1401 pfpdu->max_fpdu_data = ieq->vsi->mss;
1348 pfpdu->pmode_count++; 1402 pfpdu->pmode_count++;
1349 INIT_LIST_HEAD(rxlist); 1403 INIT_LIST_HEAD(rxlist);
1350 i40iw_ieq_check_first_buf(buf, fps); 1404 i40iw_ieq_check_first_buf(buf, fps);
@@ -1379,14 +1433,14 @@ static void i40iw_ieq_handle_exception(struct i40iw_puda_rsrc *ieq,
1379 * @dev: iwarp device 1433 * @dev: iwarp device
1380 * @buf: exception buffer received 1434 * @buf: exception buffer received
1381 */ 1435 */
1382static void i40iw_ieq_receive(struct i40iw_sc_dev *dev, 1436static void i40iw_ieq_receive(struct i40iw_sc_vsi *vsi,
1383 struct i40iw_puda_buf *buf) 1437 struct i40iw_puda_buf *buf)
1384{ 1438{
1385 struct i40iw_puda_rsrc *ieq = dev->ieq; 1439 struct i40iw_puda_rsrc *ieq = vsi->ieq;
1386 struct i40iw_sc_qp *qp = NULL; 1440 struct i40iw_sc_qp *qp = NULL;
1387 u32 wqe_idx = ieq->compl_rxwqe_idx; 1441 u32 wqe_idx = ieq->compl_rxwqe_idx;
1388 1442
1389 qp = i40iw_ieq_get_qp(dev, buf); 1443 qp = i40iw_ieq_get_qp(vsi->dev, buf);
1390 if (!qp) { 1444 if (!qp) {
1391 ieq->stats_bad_qp_id++; 1445 ieq->stats_bad_qp_id++;
1392 i40iw_puda_ret_bufpool(ieq, buf); 1446 i40iw_puda_ret_bufpool(ieq, buf);
@@ -1404,12 +1458,12 @@ static void i40iw_ieq_receive(struct i40iw_sc_dev *dev,
1404 1458
1405/** 1459/**
1406 * i40iw_ieq_tx_compl - put back after sending completed exception buffer 1460 * i40iw_ieq_tx_compl - put back after sending completed exception buffer
1407 * @dev: iwarp device 1461 * @vsi: pointer to the vsi structure
1408 * @sqwrid: pointer to puda buffer 1462 * @sqwrid: pointer to puda buffer
1409 */ 1463 */
1410static void i40iw_ieq_tx_compl(struct i40iw_sc_dev *dev, void *sqwrid) 1464static void i40iw_ieq_tx_compl(struct i40iw_sc_vsi *vsi, void *sqwrid)
1411{ 1465{
1412 struct i40iw_puda_rsrc *ieq = dev->ieq; 1466 struct i40iw_puda_rsrc *ieq = vsi->ieq;
1413 struct i40iw_puda_buf *buf = (struct i40iw_puda_buf *)sqwrid; 1467 struct i40iw_puda_buf *buf = (struct i40iw_puda_buf *)sqwrid;
1414 1468
1415 i40iw_puda_ret_bufpool(ieq, buf); 1469 i40iw_puda_ret_bufpool(ieq, buf);
@@ -1421,15 +1475,14 @@ static void i40iw_ieq_tx_compl(struct i40iw_sc_dev *dev, void *sqwrid)
1421 1475
1422/** 1476/**
1423 * i40iw_ieq_cleanup_qp - qp is being destroyed 1477 * i40iw_ieq_cleanup_qp - qp is being destroyed
1424 * @dev: iwarp device 1478 * @ieq: ieq resource
1425 * @qp: all pending fpdu buffers 1479 * @qp: all pending fpdu buffers
1426 */ 1480 */
1427void i40iw_ieq_cleanup_qp(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp) 1481static void i40iw_ieq_cleanup_qp(struct i40iw_puda_rsrc *ieq, struct i40iw_sc_qp *qp)
1428{ 1482{
1429 struct i40iw_puda_buf *buf; 1483 struct i40iw_puda_buf *buf;
1430 struct i40iw_pfpdu *pfpdu = &qp->pfpdu; 1484 struct i40iw_pfpdu *pfpdu = &qp->pfpdu;
1431 struct list_head *rxlist = &pfpdu->rxlist; 1485 struct list_head *rxlist = &pfpdu->rxlist;
1432 struct i40iw_puda_rsrc *ieq = dev->ieq;
1433 1486
1434 if (!pfpdu->mode) 1487 if (!pfpdu->mode)
1435 return; 1488 return;
diff --git a/drivers/infiniband/hw/i40iw/i40iw_puda.h b/drivers/infiniband/hw/i40iw/i40iw_puda.h
index 52bf7826ce4e..dba05ce7d392 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_puda.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_puda.h
@@ -100,6 +100,7 @@ struct i40iw_puda_rsrc_info {
100 enum puda_resource_type type; /* ILQ or IEQ */ 100 enum puda_resource_type type; /* ILQ or IEQ */
101 u32 count; 101 u32 count;
102 u16 pd_id; 102 u16 pd_id;
103 bool ceq_valid;
103 u32 cq_id; 104 u32 cq_id;
104 u32 qp_id; 105 u32 qp_id;
105 u32 sq_size; 106 u32 sq_size;
@@ -107,8 +108,8 @@ struct i40iw_puda_rsrc_info {
107 u16 buf_size; 108 u16 buf_size;
108 u16 mss; 109 u16 mss;
109 u32 tx_buf_cnt; /* total bufs allocated will be rq_size + tx_buf_cnt */ 110 u32 tx_buf_cnt; /* total bufs allocated will be rq_size + tx_buf_cnt */
110 void (*receive)(struct i40iw_sc_dev *, struct i40iw_puda_buf *); 111 void (*receive)(struct i40iw_sc_vsi *, struct i40iw_puda_buf *);
111 void (*xmit_complete)(struct i40iw_sc_dev *, void *); 112 void (*xmit_complete)(struct i40iw_sc_vsi *, void *);
112}; 113};
113 114
114struct i40iw_puda_rsrc { 115struct i40iw_puda_rsrc {
@@ -116,6 +117,7 @@ struct i40iw_puda_rsrc {
116 struct i40iw_sc_qp qp; 117 struct i40iw_sc_qp qp;
117 struct i40iw_sc_pd sc_pd; 118 struct i40iw_sc_pd sc_pd;
118 struct i40iw_sc_dev *dev; 119 struct i40iw_sc_dev *dev;
120 struct i40iw_sc_vsi *vsi;
119 struct i40iw_dma_mem cqmem; 121 struct i40iw_dma_mem cqmem;
120 struct i40iw_dma_mem qpmem; 122 struct i40iw_dma_mem qpmem;
121 struct i40iw_virt_mem ilq_mem; 123 struct i40iw_virt_mem ilq_mem;
@@ -123,6 +125,7 @@ struct i40iw_puda_rsrc {
123 enum puda_resource_type type; 125 enum puda_resource_type type;
124 u16 buf_size; /*buffer must be max datalen + tcpip hdr + mac */ 126 u16 buf_size; /*buffer must be max datalen + tcpip hdr + mac */
125 u16 mss; 127 u16 mss;
128 bool ceq_valid;
126 u32 cq_id; 129 u32 cq_id;
127 u32 qp_id; 130 u32 qp_id;
128 u32 sq_size; 131 u32 sq_size;
@@ -142,8 +145,8 @@ struct i40iw_puda_rsrc {
142 u32 avail_buf_count; /* snapshot of currently available buffers */ 145 u32 avail_buf_count; /* snapshot of currently available buffers */
143 spinlock_t bufpool_lock; 146 spinlock_t bufpool_lock;
144 struct i40iw_puda_buf *alloclist; 147 struct i40iw_puda_buf *alloclist;
145 void (*receive)(struct i40iw_sc_dev *, struct i40iw_puda_buf *); 148 void (*receive)(struct i40iw_sc_vsi *, struct i40iw_puda_buf *);
146 void (*xmit_complete)(struct i40iw_sc_dev *, void *); 149 void (*xmit_complete)(struct i40iw_sc_vsi *, void *);
147 /* puda stats */ 150 /* puda stats */
148 u64 stats_buf_alloc_fail; 151 u64 stats_buf_alloc_fail;
149 u64 stats_pkt_rcvd; 152 u64 stats_pkt_rcvd;
@@ -160,14 +163,13 @@ void i40iw_puda_send_buf(struct i40iw_puda_rsrc *rsrc,
160 struct i40iw_puda_buf *buf); 163 struct i40iw_puda_buf *buf);
161enum i40iw_status_code i40iw_puda_send(struct i40iw_sc_qp *qp, 164enum i40iw_status_code i40iw_puda_send(struct i40iw_sc_qp *qp,
162 struct i40iw_puda_send_info *info); 165 struct i40iw_puda_send_info *info);
163enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_dev *dev, 166enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_vsi *vsi,
164 struct i40iw_puda_rsrc_info *info); 167 struct i40iw_puda_rsrc_info *info);
165void i40iw_puda_dele_resources(struct i40iw_sc_dev *dev, 168void i40iw_puda_dele_resources(struct i40iw_sc_vsi *vsi,
166 enum puda_resource_type type, 169 enum puda_resource_type type,
167 bool reset); 170 bool reset);
168enum i40iw_status_code i40iw_puda_poll_completion(struct i40iw_sc_dev *dev, 171enum i40iw_status_code i40iw_puda_poll_completion(struct i40iw_sc_dev *dev,
169 struct i40iw_sc_cq *cq, u32 *compl_err); 172 struct i40iw_sc_cq *cq, u32 *compl_err);
170void i40iw_ieq_cleanup_qp(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
171 173
172struct i40iw_sc_qp *i40iw_ieq_get_qp(struct i40iw_sc_dev *dev, 174struct i40iw_sc_qp *i40iw_ieq_get_qp(struct i40iw_sc_dev *dev,
173 struct i40iw_puda_buf *buf); 175 struct i40iw_puda_buf *buf);
@@ -180,4 +182,8 @@ void i40iw_ieq_mpa_crc_ae(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
180void i40iw_free_hash_desc(struct shash_desc *desc); 182void i40iw_free_hash_desc(struct shash_desc *desc);
181void i40iw_ieq_update_tcpip_info(struct i40iw_puda_buf *buf, u16 length, 183void i40iw_ieq_update_tcpip_info(struct i40iw_puda_buf *buf, u16 length,
182 u32 seqnum); 184 u32 seqnum);
185enum i40iw_status_code i40iw_cqp_qp_create_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
186enum i40iw_status_code i40iw_cqp_cq_create_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_cq *cq);
187void i40iw_cqp_qp_destroy_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
188void i40iw_cqp_cq_destroy_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_cq *cq);
183#endif 189#endif
diff --git a/drivers/infiniband/hw/i40iw/i40iw_type.h b/drivers/infiniband/hw/i40iw/i40iw_type.h
index 2b1a04e9ca3c..f3f8e9cc3c05 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_type.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_type.h
@@ -61,7 +61,7 @@ struct i40iw_cq_shadow_area {
61 61
62struct i40iw_sc_dev; 62struct i40iw_sc_dev;
63struct i40iw_hmc_info; 63struct i40iw_hmc_info;
64struct i40iw_dev_pestat; 64struct i40iw_vsi_pestat;
65 65
66struct i40iw_cqp_ops; 66struct i40iw_cqp_ops;
67struct i40iw_ccq_ops; 67struct i40iw_ccq_ops;
@@ -74,6 +74,11 @@ struct i40iw_priv_qp_ops;
74struct i40iw_priv_cq_ops; 74struct i40iw_priv_cq_ops;
75struct i40iw_hmc_ops; 75struct i40iw_hmc_ops;
76 76
77enum i40iw_page_size {
78 I40IW_PAGE_SIZE_4K,
79 I40IW_PAGE_SIZE_2M
80};
81
77enum i40iw_resource_indicator_type { 82enum i40iw_resource_indicator_type {
78 I40IW_RSRC_INDICATOR_TYPE_ADAPTER = 0, 83 I40IW_RSRC_INDICATOR_TYPE_ADAPTER = 0,
79 I40IW_RSRC_INDICATOR_TYPE_CQ, 84 I40IW_RSRC_INDICATOR_TYPE_CQ,
@@ -186,7 +191,7 @@ enum i40iw_debug_flag {
186 I40IW_DEBUG_ALL = 0xFFFFFFFF 191 I40IW_DEBUG_ALL = 0xFFFFFFFF
187}; 192};
188 193
189enum i40iw_hw_stat_index_32b { 194enum i40iw_hw_stats_index_32b {
190 I40IW_HW_STAT_INDEX_IP4RXDISCARD = 0, 195 I40IW_HW_STAT_INDEX_IP4RXDISCARD = 0,
191 I40IW_HW_STAT_INDEX_IP4RXTRUNC, 196 I40IW_HW_STAT_INDEX_IP4RXTRUNC,
192 I40IW_HW_STAT_INDEX_IP4TXNOROUTE, 197 I40IW_HW_STAT_INDEX_IP4TXNOROUTE,
@@ -199,7 +204,7 @@ enum i40iw_hw_stat_index_32b {
199 I40IW_HW_STAT_INDEX_MAX_32 204 I40IW_HW_STAT_INDEX_MAX_32
200}; 205};
201 206
202enum i40iw_hw_stat_index_64b { 207enum i40iw_hw_stats_index_64b {
203 I40IW_HW_STAT_INDEX_IP4RXOCTS = 0, 208 I40IW_HW_STAT_INDEX_IP4RXOCTS = 0,
204 I40IW_HW_STAT_INDEX_IP4RXPKTS, 209 I40IW_HW_STAT_INDEX_IP4RXPKTS,
205 I40IW_HW_STAT_INDEX_IP4RXFRAGS, 210 I40IW_HW_STAT_INDEX_IP4RXFRAGS,
@@ -229,32 +234,23 @@ enum i40iw_hw_stat_index_64b {
229 I40IW_HW_STAT_INDEX_MAX_64 234 I40IW_HW_STAT_INDEX_MAX_64
230}; 235};
231 236
232struct i40iw_dev_hw_stat_offsets { 237struct i40iw_dev_hw_stats_offsets {
233 u32 stat_offset_32[I40IW_HW_STAT_INDEX_MAX_32]; 238 u32 stats_offset_32[I40IW_HW_STAT_INDEX_MAX_32];
234 u32 stat_offset_64[I40IW_HW_STAT_INDEX_MAX_64]; 239 u32 stats_offset_64[I40IW_HW_STAT_INDEX_MAX_64];
235}; 240};
236 241
237struct i40iw_dev_hw_stats { 242struct i40iw_dev_hw_stats {
238 u64 stat_value_32[I40IW_HW_STAT_INDEX_MAX_32]; 243 u64 stats_value_32[I40IW_HW_STAT_INDEX_MAX_32];
239 u64 stat_value_64[I40IW_HW_STAT_INDEX_MAX_64]; 244 u64 stats_value_64[I40IW_HW_STAT_INDEX_MAX_64];
240};
241
242struct i40iw_device_pestat_ops {
243 void (*iw_hw_stat_init)(struct i40iw_dev_pestat *, u8, struct i40iw_hw *, bool);
244 void (*iw_hw_stat_read_32)(struct i40iw_dev_pestat *, enum i40iw_hw_stat_index_32b, u64 *);
245 void (*iw_hw_stat_read_64)(struct i40iw_dev_pestat *, enum i40iw_hw_stat_index_64b, u64 *);
246 void (*iw_hw_stat_read_all)(struct i40iw_dev_pestat *, struct i40iw_dev_hw_stats *);
247 void (*iw_hw_stat_refresh_all)(struct i40iw_dev_pestat *);
248}; 245};
249 246
250struct i40iw_dev_pestat { 247struct i40iw_vsi_pestat {
251 struct i40iw_hw *hw; 248 struct i40iw_hw *hw;
252 struct i40iw_device_pestat_ops ops;
253 struct i40iw_dev_hw_stats hw_stats; 249 struct i40iw_dev_hw_stats hw_stats;
254 struct i40iw_dev_hw_stats last_read_hw_stats; 250 struct i40iw_dev_hw_stats last_read_hw_stats;
255 struct i40iw_dev_hw_stat_offsets hw_stat_offsets; 251 struct i40iw_dev_hw_stats_offsets hw_stats_offsets;
256 struct timer_list stats_timer; 252 struct timer_list stats_timer;
257 spinlock_t stats_lock; /* rdma stats lock */ 253 spinlock_t lock; /* rdma stats lock */
258}; 254};
259 255
260struct i40iw_hw { 256struct i40iw_hw {
@@ -350,6 +346,7 @@ struct i40iw_sc_cq {
350 u64 cq_pa; 346 u64 cq_pa;
351 u64 shadow_area_pa; 347 u64 shadow_area_pa;
352 struct i40iw_sc_dev *dev; 348 struct i40iw_sc_dev *dev;
349 struct i40iw_sc_vsi *vsi;
353 void *pbl_list; 350 void *pbl_list;
354 void *back_cq; 351 void *back_cq;
355 u32 ceq_id; 352 u32 ceq_id;
@@ -373,6 +370,7 @@ struct i40iw_sc_qp {
373 u64 shadow_area_pa; 370 u64 shadow_area_pa;
374 u64 q2_pa; 371 u64 q2_pa;
375 struct i40iw_sc_dev *dev; 372 struct i40iw_sc_dev *dev;
373 struct i40iw_sc_vsi *vsi;
376 struct i40iw_sc_pd *pd; 374 struct i40iw_sc_pd *pd;
377 u64 *hw_host_ctx; 375 u64 *hw_host_ctx;
378 void *llp_stream_handle; 376 void *llp_stream_handle;
@@ -397,6 +395,9 @@ struct i40iw_sc_qp {
397 bool virtual_map; 395 bool virtual_map;
398 bool flush_sq; 396 bool flush_sq;
399 bool flush_rq; 397 bool flush_rq;
398 u8 user_pri;
399 struct list_head list;
400 bool on_qoslist;
400 bool sq_flush; 401 bool sq_flush;
401 enum i40iw_flush_opcode flush_code; 402 enum i40iw_flush_opcode flush_code;
402 enum i40iw_term_eventtypes eventtype; 403 enum i40iw_term_eventtypes eventtype;
@@ -424,10 +425,16 @@ struct i40iw_vchnl_vf_msg_buffer {
424 char parm_buffer[I40IW_VCHNL_MAX_VF_MSG_SIZE - 1]; 425 char parm_buffer[I40IW_VCHNL_MAX_VF_MSG_SIZE - 1];
425}; 426};
426 427
428struct i40iw_qos {
429 struct list_head qplist;
430 spinlock_t lock; /* qos list */
431 u16 qs_handle;
432};
433
427struct i40iw_vfdev { 434struct i40iw_vfdev {
428 struct i40iw_sc_dev *pf_dev; 435 struct i40iw_sc_dev *pf_dev;
429 u8 *hmc_info_mem; 436 u8 *hmc_info_mem;
430 struct i40iw_dev_pestat dev_pestat; 437 struct i40iw_vsi_pestat pestat;
431 struct i40iw_hmc_pble_info *pble_info; 438 struct i40iw_hmc_pble_info *pble_info;
432 struct i40iw_hmc_info hmc_info; 439 struct i40iw_hmc_info hmc_info;
433 struct i40iw_vchnl_vf_msg_buffer vf_msg_buffer; 440 struct i40iw_vchnl_vf_msg_buffer vf_msg_buffer;
@@ -441,11 +448,28 @@ struct i40iw_vfdev {
441 bool stats_initialized; 448 bool stats_initialized;
442}; 449};
443 450
451#define I40IW_INVALID_FCN_ID 0xff
452struct i40iw_sc_vsi {
453 struct i40iw_sc_dev *dev;
454 void *back_vsi; /* Owned by OS */
455 u32 ilq_count;
456 struct i40iw_virt_mem ilq_mem;
457 struct i40iw_puda_rsrc *ilq;
458 u32 ieq_count;
459 struct i40iw_virt_mem ieq_mem;
460 struct i40iw_puda_rsrc *ieq;
461 u16 mss;
462 u8 fcn_id;
463 bool stats_fcn_id_alloc;
464 struct i40iw_qos qos[I40IW_MAX_USER_PRIORITY];
465 struct i40iw_vsi_pestat *pestat;
466};
467
444struct i40iw_sc_dev { 468struct i40iw_sc_dev {
445 struct list_head cqp_cmd_head; /* head of the CQP command list */ 469 struct list_head cqp_cmd_head; /* head of the CQP command list */
446 spinlock_t cqp_lock; /* cqp list sync */ 470 spinlock_t cqp_lock; /* cqp list sync */
447 struct i40iw_dev_uk dev_uk; 471 struct i40iw_dev_uk dev_uk;
448 struct i40iw_dev_pestat dev_pestat; 472 bool fcn_id_array[I40IW_MAX_STATS_COUNT];
449 struct i40iw_dma_mem vf_fpm_query_buf[I40IW_MAX_PE_ENABLED_VF_COUNT]; 473 struct i40iw_dma_mem vf_fpm_query_buf[I40IW_MAX_PE_ENABLED_VF_COUNT];
450 u64 fpm_query_buf_pa; 474 u64 fpm_query_buf_pa;
451 u64 fpm_commit_buf_pa; 475 u64 fpm_commit_buf_pa;
@@ -472,17 +496,9 @@ struct i40iw_sc_dev {
472 struct i40iw_cqp_misc_ops *cqp_misc_ops; 496 struct i40iw_cqp_misc_ops *cqp_misc_ops;
473 struct i40iw_hmc_ops *hmc_ops; 497 struct i40iw_hmc_ops *hmc_ops;
474 struct i40iw_vchnl_if vchnl_if; 498 struct i40iw_vchnl_if vchnl_if;
475 u32 ilq_count;
476 struct i40iw_virt_mem ilq_mem;
477 struct i40iw_puda_rsrc *ilq;
478 u32 ieq_count;
479 struct i40iw_virt_mem ieq_mem;
480 struct i40iw_puda_rsrc *ieq;
481
482 const struct i40iw_vf_cqp_ops *iw_vf_cqp_ops; 499 const struct i40iw_vf_cqp_ops *iw_vf_cqp_ops;
483 500
484 struct i40iw_hmc_fpm_misc hmc_fpm_misc; 501 struct i40iw_hmc_fpm_misc hmc_fpm_misc;
485 u16 qs_handle;
486 u32 debug_mask; 502 u32 debug_mask;
487 u16 exception_lan_queue; 503 u16 exception_lan_queue;
488 u8 hmc_fn_id; 504 u8 hmc_fn_id;
@@ -556,6 +572,19 @@ struct i40iw_l2params {
556 u16 mss; 572 u16 mss;
557}; 573};
558 574
575struct i40iw_vsi_init_info {
576 struct i40iw_sc_dev *dev;
577 void *back_vsi;
578 struct i40iw_l2params *params;
579};
580
581struct i40iw_vsi_stats_info {
582 struct i40iw_vsi_pestat *pestat;
583 u8 fcn_id;
584 bool alloc_fcn_id;
585 bool stats_initialize;
586};
587
559struct i40iw_device_init_info { 588struct i40iw_device_init_info {
560 u64 fpm_query_buf_pa; 589 u64 fpm_query_buf_pa;
561 u64 fpm_commit_buf_pa; 590 u64 fpm_commit_buf_pa;
@@ -564,7 +593,6 @@ struct i40iw_device_init_info {
564 struct i40iw_hw *hw; 593 struct i40iw_hw *hw;
565 void __iomem *bar0; 594 void __iomem *bar0;
566 enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *, u32, u8 *, u16); 595 enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *, u32, u8 *, u16);
567 u16 qs_handle;
568 u16 exception_lan_queue; 596 u16 exception_lan_queue;
569 u8 hmc_fn_id; 597 u8 hmc_fn_id;
570 bool is_pf; 598 bool is_pf;
@@ -722,6 +750,8 @@ struct i40iw_qp_host_ctx_info {
722 bool iwarp_info_valid; 750 bool iwarp_info_valid;
723 bool err_rq_idx_valid; 751 bool err_rq_idx_valid;
724 u16 err_rq_idx; 752 u16 err_rq_idx;
753 bool add_to_qoslist;
754 u8 user_pri;
725}; 755};
726 756
727struct i40iw_aeqe_info { 757struct i40iw_aeqe_info {
@@ -814,6 +844,7 @@ struct i40iw_register_shared_stag {
814struct i40iw_qp_init_info { 844struct i40iw_qp_init_info {
815 struct i40iw_qp_uk_init_info qp_uk_init_info; 845 struct i40iw_qp_uk_init_info qp_uk_init_info;
816 struct i40iw_sc_pd *pd; 846 struct i40iw_sc_pd *pd;
847 struct i40iw_sc_vsi *vsi;
817 u64 *host_ctx; 848 u64 *host_ctx;
818 u8 *q2; 849 u8 *q2;
819 u64 sq_pa; 850 u64 sq_pa;
@@ -880,13 +911,14 @@ enum i40iw_quad_hash_manage_type {
880}; 911};
881 912
882struct i40iw_qhash_table_info { 913struct i40iw_qhash_table_info {
914 struct i40iw_sc_vsi *vsi;
883 enum i40iw_quad_hash_manage_type manage; 915 enum i40iw_quad_hash_manage_type manage;
884 enum i40iw_quad_entry_type entry_type; 916 enum i40iw_quad_entry_type entry_type;
885 bool vlan_valid; 917 bool vlan_valid;
886 bool ipv4_valid; 918 bool ipv4_valid;
887 u8 mac_addr[6]; 919 u8 mac_addr[6];
888 u16 vlan_id; 920 u16 vlan_id;
889 u16 qs_handle; 921 u8 user_pri;
890 u32 qp_num; 922 u32 qp_num;
891 u32 dest_ip[4]; 923 u32 dest_ip[4];
892 u32 src_ip[4]; 924 u32 src_ip[4];
@@ -976,7 +1008,7 @@ struct i40iw_cqp_query_fpm_values {
976struct i40iw_cqp_ops { 1008struct i40iw_cqp_ops {
977 enum i40iw_status_code (*cqp_init)(struct i40iw_sc_cqp *, 1009 enum i40iw_status_code (*cqp_init)(struct i40iw_sc_cqp *,
978 struct i40iw_cqp_init_info *); 1010 struct i40iw_cqp_init_info *);
979 enum i40iw_status_code (*cqp_create)(struct i40iw_sc_cqp *, bool, u16 *, u16 *); 1011 enum i40iw_status_code (*cqp_create)(struct i40iw_sc_cqp *, u16 *, u16 *);
980 void (*cqp_post_sq)(struct i40iw_sc_cqp *); 1012 void (*cqp_post_sq)(struct i40iw_sc_cqp *);
981 u64 *(*cqp_get_next_send_wqe)(struct i40iw_sc_cqp *, u64 scratch); 1013 u64 *(*cqp_get_next_send_wqe)(struct i40iw_sc_cqp *, u64 scratch);
982 enum i40iw_status_code (*cqp_destroy)(struct i40iw_sc_cqp *); 1014 enum i40iw_status_code (*cqp_destroy)(struct i40iw_sc_cqp *);
diff --git a/drivers/infiniband/hw/i40iw/i40iw_uk.c b/drivers/infiniband/hw/i40iw/i40iw_uk.c
index 4d28c3cb03cc..4376cd628774 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_uk.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_uk.c
@@ -175,12 +175,10 @@ u64 *i40iw_qp_get_next_send_wqe(struct i40iw_qp_uk *qp,
175 if (!*wqe_idx) 175 if (!*wqe_idx)
176 qp->swqe_polarity = !qp->swqe_polarity; 176 qp->swqe_polarity = !qp->swqe_polarity;
177 } 177 }
178 178 I40IW_RING_MOVE_HEAD_BY_COUNT(qp->sq_ring,
179 for (i = 0; i < wqe_size / I40IW_QP_WQE_MIN_SIZE; i++) { 179 wqe_size / I40IW_QP_WQE_MIN_SIZE, ret_code);
180 I40IW_RING_MOVE_HEAD(qp->sq_ring, ret_code); 180 if (ret_code)
181 if (ret_code) 181 return NULL;
182 return NULL;
183 }
184 182
185 wqe = qp->sq_base[*wqe_idx].elem; 183 wqe = qp->sq_base[*wqe_idx].elem;
186 184
@@ -430,7 +428,7 @@ static enum i40iw_status_code i40iw_inline_rdma_write(struct i40iw_qp_uk *qp,
430 struct i40iw_inline_rdma_write *op_info; 428 struct i40iw_inline_rdma_write *op_info;
431 u64 *push; 429 u64 *push;
432 u64 header = 0; 430 u64 header = 0;
433 u32 i, wqe_idx; 431 u32 wqe_idx;
434 enum i40iw_status_code ret_code; 432 enum i40iw_status_code ret_code;
435 bool read_fence = false; 433 bool read_fence = false;
436 u8 wqe_size; 434 u8 wqe_size;
@@ -465,14 +463,12 @@ static enum i40iw_status_code i40iw_inline_rdma_write(struct i40iw_qp_uk *qp,
465 src = (u8 *)(op_info->data); 463 src = (u8 *)(op_info->data);
466 464
467 if (op_info->len <= 16) { 465 if (op_info->len <= 16) {
468 for (i = 0; i < op_info->len; i++, src++, dest++) 466 memcpy(dest, src, op_info->len);
469 *dest = *src;
470 } else { 467 } else {
471 for (i = 0; i < 16; i++, src++, dest++) 468 memcpy(dest, src, 16);
472 *dest = *src; 469 src += 16;
473 dest = (u8 *)wqe + 32; 470 dest = (u8 *)wqe + 32;
474 for (; i < op_info->len; i++, src++, dest++) 471 memcpy(dest, src, op_info->len - 16);
475 *dest = *src;
476 } 472 }
477 473
478 wmb(); /* make sure WQE is populated before valid bit is set */ 474 wmb(); /* make sure WQE is populated before valid bit is set */
@@ -507,7 +503,7 @@ static enum i40iw_status_code i40iw_inline_send(struct i40iw_qp_uk *qp,
507 u8 *dest, *src; 503 u8 *dest, *src;
508 struct i40iw_post_inline_send *op_info; 504 struct i40iw_post_inline_send *op_info;
509 u64 header; 505 u64 header;
510 u32 wqe_idx, i; 506 u32 wqe_idx;
511 enum i40iw_status_code ret_code; 507 enum i40iw_status_code ret_code;
512 bool read_fence = false; 508 bool read_fence = false;
513 u8 wqe_size; 509 u8 wqe_size;
@@ -540,14 +536,12 @@ static enum i40iw_status_code i40iw_inline_send(struct i40iw_qp_uk *qp,
540 src = (u8 *)(op_info->data); 536 src = (u8 *)(op_info->data);
541 537
542 if (op_info->len <= 16) { 538 if (op_info->len <= 16) {
543 for (i = 0; i < op_info->len; i++, src++, dest++) 539 memcpy(dest, src, op_info->len);
544 *dest = *src;
545 } else { 540 } else {
546 for (i = 0; i < 16; i++, src++, dest++) 541 memcpy(dest, src, 16);
547 *dest = *src; 542 src += 16;
548 dest = (u8 *)wqe + 32; 543 dest = (u8 *)wqe + 32;
549 for (; i < op_info->len; i++, src++, dest++) 544 memcpy(dest, src, op_info->len - 16);
550 *dest = *src;
551 } 545 }
552 546
553 wmb(); /* make sure WQE is populated before valid bit is set */ 547 wmb(); /* make sure WQE is populated before valid bit is set */
@@ -1190,12 +1184,8 @@ enum i40iw_status_code i40iw_inline_data_size_to_wqesize(u32 data_size,
1190 1184
1191 if (data_size <= 16) 1185 if (data_size <= 16)
1192 *wqe_size = I40IW_QP_WQE_MIN_SIZE; 1186 *wqe_size = I40IW_QP_WQE_MIN_SIZE;
1193 else if (data_size <= 48)
1194 *wqe_size = 64;
1195 else if (data_size <= 80)
1196 *wqe_size = 96;
1197 else 1187 else
1198 *wqe_size = 128; 1188 *wqe_size = 64;
1199 1189
1200 return 0; 1190 return 0;
1201} 1191}
diff --git a/drivers/infiniband/hw/i40iw/i40iw_user.h b/drivers/infiniband/hw/i40iw/i40iw_user.h
index 276bcefffd7e..80d9f464f65e 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_user.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_user.h
@@ -72,12 +72,12 @@ enum i40iw_device_capabilities_const {
72 I40IW_MAX_SQ_PAYLOAD_SIZE = 2145386496, 72 I40IW_MAX_SQ_PAYLOAD_SIZE = 2145386496,
73 I40IW_MAX_INLINE_DATA_SIZE = 48, 73 I40IW_MAX_INLINE_DATA_SIZE = 48,
74 I40IW_MAX_PUSHMODE_INLINE_DATA_SIZE = 48, 74 I40IW_MAX_PUSHMODE_INLINE_DATA_SIZE = 48,
75 I40IW_MAX_IRD_SIZE = 32, 75 I40IW_MAX_IRD_SIZE = 63,
76 I40IW_QPCTX_ENCD_MAXIRD = 3, 76 I40IW_MAX_ORD_SIZE = 127,
77 I40IW_MAX_WQ_ENTRIES = 2048, 77 I40IW_MAX_WQ_ENTRIES = 2048,
78 I40IW_MAX_ORD_SIZE = 32,
79 I40IW_Q2_BUFFER_SIZE = (248 + 100), 78 I40IW_Q2_BUFFER_SIZE = (248 + 100),
80 I40IW_QP_CTX_SIZE = 248 79 I40IW_QP_CTX_SIZE = 248,
80 I40IW_MAX_PDS = 32768
81}; 81};
82 82
83#define i40iw_handle void * 83#define i40iw_handle void *
@@ -96,12 +96,6 @@ enum i40iw_device_capabilities_const {
96#define i40iw_physical_fragment u64 96#define i40iw_physical_fragment u64
97#define i40iw_address_list u64 * 97#define i40iw_address_list u64 *
98 98
99#define I40IW_CREATE_STAG(index, key) (((index) << 8) + (key))
100
101#define I40IW_STAG_KEY_FROM_STAG(stag) ((stag) && 0x000000FF)
102
103#define I40IW_STAG_INDEX_FROM_STAG(stag) (((stag) && 0xFFFFFF00) >> 8)
104
105#define I40IW_MAX_MR_SIZE 0x10000000000L 99#define I40IW_MAX_MR_SIZE 0x10000000000L
106 100
107struct i40iw_qp_uk; 101struct i40iw_qp_uk;
diff --git a/drivers/infiniband/hw/i40iw/i40iw_utils.c b/drivers/infiniband/hw/i40iw/i40iw_utils.c
index 6fd043b1d714..0f5d43d1f5fc 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_utils.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_utils.c
@@ -153,6 +153,7 @@ int i40iw_inetaddr_event(struct notifier_block *notifier,
153 struct i40iw_device *iwdev; 153 struct i40iw_device *iwdev;
154 struct i40iw_handler *hdl; 154 struct i40iw_handler *hdl;
155 u32 local_ipaddr; 155 u32 local_ipaddr;
156 u32 action = I40IW_ARP_ADD;
156 157
157 hdl = i40iw_find_netdev(event_netdev); 158 hdl = i40iw_find_netdev(event_netdev);
158 if (!hdl) 159 if (!hdl)
@@ -164,44 +165,25 @@ int i40iw_inetaddr_event(struct notifier_block *notifier,
164 if (netdev != event_netdev) 165 if (netdev != event_netdev)
165 return NOTIFY_DONE; 166 return NOTIFY_DONE;
166 167
168 if (upper_dev)
169 local_ipaddr = ntohl(
170 ((struct in_device *)upper_dev->ip_ptr)->ifa_list->ifa_address);
171 else
172 local_ipaddr = ntohl(ifa->ifa_address);
167 switch (event) { 173 switch (event) {
168 case NETDEV_DOWN: 174 case NETDEV_DOWN:
169 if (upper_dev) 175 action = I40IW_ARP_DELETE;
170 local_ipaddr = ntohl( 176 /* Fall through */
171 ((struct in_device *)upper_dev->ip_ptr)->ifa_list->ifa_address);
172 else
173 local_ipaddr = ntohl(ifa->ifa_address);
174 i40iw_manage_arp_cache(iwdev,
175 netdev->dev_addr,
176 &local_ipaddr,
177 true,
178 I40IW_ARP_DELETE);
179 return NOTIFY_OK;
180 case NETDEV_UP: 177 case NETDEV_UP:
181 if (upper_dev) 178 /* Fall through */
182 local_ipaddr = ntohl(
183 ((struct in_device *)upper_dev->ip_ptr)->ifa_list->ifa_address);
184 else
185 local_ipaddr = ntohl(ifa->ifa_address);
186 i40iw_manage_arp_cache(iwdev,
187 netdev->dev_addr,
188 &local_ipaddr,
189 true,
190 I40IW_ARP_ADD);
191 break;
192 case NETDEV_CHANGEADDR: 179 case NETDEV_CHANGEADDR:
193 /* Add the address to the IP table */
194 if (upper_dev)
195 local_ipaddr = ntohl(
196 ((struct in_device *)upper_dev->ip_ptr)->ifa_list->ifa_address);
197 else
198 local_ipaddr = ntohl(ifa->ifa_address);
199
200 i40iw_manage_arp_cache(iwdev, 180 i40iw_manage_arp_cache(iwdev,
201 netdev->dev_addr, 181 netdev->dev_addr,
202 &local_ipaddr, 182 &local_ipaddr,
203 true, 183 true,
204 I40IW_ARP_ADD); 184 action);
185 i40iw_if_notify(iwdev, netdev, &local_ipaddr, true,
186 (action == I40IW_ARP_ADD) ? true : false);
205 break; 187 break;
206 default: 188 default:
207 break; 189 break;
@@ -225,6 +207,7 @@ int i40iw_inet6addr_event(struct notifier_block *notifier,
225 struct i40iw_device *iwdev; 207 struct i40iw_device *iwdev;
226 struct i40iw_handler *hdl; 208 struct i40iw_handler *hdl;
227 u32 local_ipaddr6[4]; 209 u32 local_ipaddr6[4];
210 u32 action = I40IW_ARP_ADD;
228 211
229 hdl = i40iw_find_netdev(event_netdev); 212 hdl = i40iw_find_netdev(event_netdev);
230 if (!hdl) 213 if (!hdl)
@@ -235,24 +218,21 @@ int i40iw_inet6addr_event(struct notifier_block *notifier,
235 if (netdev != event_netdev) 218 if (netdev != event_netdev)
236 return NOTIFY_DONE; 219 return NOTIFY_DONE;
237 220
221 i40iw_copy_ip_ntohl(local_ipaddr6, ifa->addr.in6_u.u6_addr32);
238 switch (event) { 222 switch (event) {
239 case NETDEV_DOWN: 223 case NETDEV_DOWN:
240 i40iw_copy_ip_ntohl(local_ipaddr6, ifa->addr.in6_u.u6_addr32); 224 action = I40IW_ARP_DELETE;
241 i40iw_manage_arp_cache(iwdev, 225 /* Fall through */
242 netdev->dev_addr,
243 local_ipaddr6,
244 false,
245 I40IW_ARP_DELETE);
246 return NOTIFY_OK;
247 case NETDEV_UP: 226 case NETDEV_UP:
248 /* Fall through */ 227 /* Fall through */
249 case NETDEV_CHANGEADDR: 228 case NETDEV_CHANGEADDR:
250 i40iw_copy_ip_ntohl(local_ipaddr6, ifa->addr.in6_u.u6_addr32);
251 i40iw_manage_arp_cache(iwdev, 229 i40iw_manage_arp_cache(iwdev,
252 netdev->dev_addr, 230 netdev->dev_addr,
253 local_ipaddr6, 231 local_ipaddr6,
254 false, 232 false,
255 I40IW_ARP_ADD); 233 action);
234 i40iw_if_notify(iwdev, netdev, local_ipaddr6, false,
235 (action == I40IW_ARP_ADD) ? true : false);
256 break; 236 break;
257 default: 237 default:
258 break; 238 break;
@@ -392,6 +372,7 @@ static void i40iw_free_qp(struct i40iw_cqp_request *cqp_request, u32 num)
392 372
393 i40iw_rem_pdusecount(iwqp->iwpd, iwdev); 373 i40iw_rem_pdusecount(iwqp->iwpd, iwdev);
394 i40iw_free_qp_resources(iwdev, iwqp, qp_num); 374 i40iw_free_qp_resources(iwdev, iwqp, qp_num);
375 i40iw_rem_devusecount(iwdev);
395} 376}
396 377
397/** 378/**
@@ -415,7 +396,10 @@ static int i40iw_wait_event(struct i40iw_device *iwdev,
415 i40iw_pr_err("error cqp command 0x%x timed out ret = %d\n", 396 i40iw_pr_err("error cqp command 0x%x timed out ret = %d\n",
416 info->cqp_cmd, timeout_ret); 397 info->cqp_cmd, timeout_ret);
417 err_code = -ETIME; 398 err_code = -ETIME;
418 i40iw_request_reset(iwdev); 399 if (!iwdev->reset) {
400 iwdev->reset = true;
401 i40iw_request_reset(iwdev);
402 }
419 goto done; 403 goto done;
420 } 404 }
421 cqp_error = cqp_request->compl_info.error; 405 cqp_error = cqp_request->compl_info.error;
@@ -445,6 +429,11 @@ enum i40iw_status_code i40iw_handle_cqp_op(struct i40iw_device *iwdev,
445 struct cqp_commands_info *info = &cqp_request->info; 429 struct cqp_commands_info *info = &cqp_request->info;
446 int err_code = 0; 430 int err_code = 0;
447 431
432 if (iwdev->reset) {
433 i40iw_free_cqp_request(&iwdev->cqp, cqp_request);
434 return I40IW_ERR_CQP_COMPL_ERROR;
435 }
436
448 status = i40iw_process_cqp_cmd(dev, info); 437 status = i40iw_process_cqp_cmd(dev, info);
449 if (status) { 438 if (status) {
450 i40iw_pr_err("error cqp command 0x%x failed\n", info->cqp_cmd); 439 i40iw_pr_err("error cqp command 0x%x failed\n", info->cqp_cmd);
@@ -459,6 +448,26 @@ enum i40iw_status_code i40iw_handle_cqp_op(struct i40iw_device *iwdev,
459} 448}
460 449
461/** 450/**
451 * i40iw_add_devusecount - add dev refcount
452 * @iwdev: dev for refcount
453 */
454void i40iw_add_devusecount(struct i40iw_device *iwdev)
455{
456 atomic64_inc(&iwdev->use_count);
457}
458
459/**
460 * i40iw_rem_devusecount - decrement refcount for dev
461 * @iwdev: device
462 */
463void i40iw_rem_devusecount(struct i40iw_device *iwdev)
464{
465 if (!atomic64_dec_and_test(&iwdev->use_count))
466 return;
467 wake_up(&iwdev->close_wq);
468}
469
470/**
462 * i40iw_add_pdusecount - add pd refcount 471 * i40iw_add_pdusecount - add pd refcount
463 * @iwpd: pd for refcount 472 * @iwpd: pd for refcount
464 */ 473 */
@@ -712,6 +721,51 @@ enum i40iw_status_code i40iw_cqp_sds_cmd(struct i40iw_sc_dev *dev,
712} 721}
713 722
714/** 723/**
724 * i40iw_qp_suspend_resume - cqp command for suspend/resume
725 * @dev: hardware control device structure
726 * @qp: hardware control qp
727 * @suspend: flag if suspend or resume
728 */
729void i40iw_qp_suspend_resume(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp, bool suspend)
730{
731 struct i40iw_device *iwdev = (struct i40iw_device *)dev->back_dev;
732 struct i40iw_cqp_request *cqp_request;
733 struct i40iw_sc_cqp *cqp = dev->cqp;
734 struct cqp_commands_info *cqp_info;
735 enum i40iw_status_code status;
736
737 cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
738 if (!cqp_request)
739 return;
740
741 cqp_info = &cqp_request->info;
742 cqp_info->cqp_cmd = (suspend) ? OP_SUSPEND : OP_RESUME;
743 cqp_info->in.u.suspend_resume.cqp = cqp;
744 cqp_info->in.u.suspend_resume.qp = qp;
745 cqp_info->in.u.suspend_resume.scratch = (uintptr_t)cqp_request;
746 status = i40iw_handle_cqp_op(iwdev, cqp_request);
747 if (status)
748 i40iw_pr_err("CQP-OP QP Suspend/Resume fail");
749}
750
751/**
752 * i40iw_qp_mss_modify - modify mss for qp
753 * @dev: hardware control device structure
754 * @qp: hardware control qp
755 */
756void i40iw_qp_mss_modify(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp)
757{
758 struct i40iw_device *iwdev = (struct i40iw_device *)dev->back_dev;
759 struct i40iw_qp *iwqp = (struct i40iw_qp *)qp->back_qp;
760 struct i40iw_modify_qp_info info;
761
762 memset(&info, 0, sizeof(info));
763 info.mss_change = true;
764 info.new_mss = qp->vsi->mss;
765 i40iw_hw_modify_qp(iwdev, iwqp, &info, false);
766}
767
768/**
715 * i40iw_term_modify_qp - modify qp for term message 769 * i40iw_term_modify_qp - modify qp for term message
716 * @qp: hardware control qp 770 * @qp: hardware control qp
717 * @next_state: qp's next state 771 * @next_state: qp's next state
@@ -769,6 +823,7 @@ static void i40iw_terminate_timeout(unsigned long context)
769 struct i40iw_sc_qp *qp = (struct i40iw_sc_qp *)&iwqp->sc_qp; 823 struct i40iw_sc_qp *qp = (struct i40iw_sc_qp *)&iwqp->sc_qp;
770 824
771 i40iw_terminate_done(qp, 1); 825 i40iw_terminate_done(qp, 1);
826 i40iw_rem_ref(&iwqp->ibqp);
772} 827}
773 828
774/** 829/**
@@ -780,6 +835,7 @@ void i40iw_terminate_start_timer(struct i40iw_sc_qp *qp)
780 struct i40iw_qp *iwqp; 835 struct i40iw_qp *iwqp;
781 836
782 iwqp = (struct i40iw_qp *)qp->back_qp; 837 iwqp = (struct i40iw_qp *)qp->back_qp;
838 i40iw_add_ref(&iwqp->ibqp);
783 init_timer(&iwqp->terminate_timer); 839 init_timer(&iwqp->terminate_timer);
784 iwqp->terminate_timer.function = i40iw_terminate_timeout; 840 iwqp->terminate_timer.function = i40iw_terminate_timeout;
785 iwqp->terminate_timer.expires = jiffies + HZ; 841 iwqp->terminate_timer.expires = jiffies + HZ;
@@ -796,7 +852,8 @@ void i40iw_terminate_del_timer(struct i40iw_sc_qp *qp)
796 struct i40iw_qp *iwqp; 852 struct i40iw_qp *iwqp;
797 853
798 iwqp = (struct i40iw_qp *)qp->back_qp; 854 iwqp = (struct i40iw_qp *)qp->back_qp;
799 del_timer(&iwqp->terminate_timer); 855 if (del_timer(&iwqp->terminate_timer))
856 i40iw_rem_ref(&iwqp->ibqp);
800} 857}
801 858
802/** 859/**
@@ -1011,6 +1068,116 @@ enum i40iw_status_code i40iw_vf_wait_vchnl_resp(struct i40iw_sc_dev *dev)
1011} 1068}
1012 1069
1013/** 1070/**
1071 * i40iw_cqp_cq_create_cmd - create a cq for the cqp
1072 * @dev: device pointer
1073 * @cq: pointer to created cq
1074 */
1075enum i40iw_status_code i40iw_cqp_cq_create_cmd(struct i40iw_sc_dev *dev,
1076 struct i40iw_sc_cq *cq)
1077{
1078 struct i40iw_device *iwdev = (struct i40iw_device *)dev->back_dev;
1079 struct i40iw_cqp *iwcqp = &iwdev->cqp;
1080 struct i40iw_cqp_request *cqp_request;
1081 struct cqp_commands_info *cqp_info;
1082 enum i40iw_status_code status;
1083
1084 cqp_request = i40iw_get_cqp_request(iwcqp, true);
1085 if (!cqp_request)
1086 return I40IW_ERR_NO_MEMORY;
1087
1088 cqp_info = &cqp_request->info;
1089 cqp_info->cqp_cmd = OP_CQ_CREATE;
1090 cqp_info->post_sq = 1;
1091 cqp_info->in.u.cq_create.cq = cq;
1092 cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;
1093 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1094 if (status)
1095 i40iw_pr_err("CQP-OP Create QP fail");
1096
1097 return status;
1098}
1099
1100/**
1101 * i40iw_cqp_qp_create_cmd - create a qp for the cqp
1102 * @dev: device pointer
1103 * @qp: pointer to created qp
1104 */
1105enum i40iw_status_code i40iw_cqp_qp_create_cmd(struct i40iw_sc_dev *dev,
1106 struct i40iw_sc_qp *qp)
1107{
1108 struct i40iw_device *iwdev = (struct i40iw_device *)dev->back_dev;
1109 struct i40iw_cqp *iwcqp = &iwdev->cqp;
1110 struct i40iw_cqp_request *cqp_request;
1111 struct cqp_commands_info *cqp_info;
1112 struct i40iw_create_qp_info *qp_info;
1113 enum i40iw_status_code status;
1114
1115 cqp_request = i40iw_get_cqp_request(iwcqp, true);
1116 if (!cqp_request)
1117 return I40IW_ERR_NO_MEMORY;
1118
1119 cqp_info = &cqp_request->info;
1120 qp_info = &cqp_request->info.in.u.qp_create.info;
1121
1122 memset(qp_info, 0, sizeof(*qp_info));
1123
1124 qp_info->cq_num_valid = true;
1125 qp_info->next_iwarp_state = I40IW_QP_STATE_RTS;
1126
1127 cqp_info->cqp_cmd = OP_QP_CREATE;
1128 cqp_info->post_sq = 1;
1129 cqp_info->in.u.qp_create.qp = qp;
1130 cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;
1131 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1132 if (status)
1133 i40iw_pr_err("CQP-OP QP create fail");
1134 return status;
1135}
1136
1137/**
1138 * i40iw_cqp_cq_destroy_cmd - destroy the cqp cq
1139 * @dev: device pointer
1140 * @cq: pointer to cq
1141 */
1142void i40iw_cqp_cq_destroy_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_cq *cq)
1143{
1144 struct i40iw_device *iwdev = (struct i40iw_device *)dev->back_dev;
1145
1146 i40iw_cq_wq_destroy(iwdev, cq);
1147}
1148
1149/**
1150 * i40iw_cqp_qp_destroy_cmd - destroy the cqp
1151 * @dev: device pointer
1152 * @qp: pointer to qp
1153 */
1154void i40iw_cqp_qp_destroy_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp)
1155{
1156 struct i40iw_device *iwdev = (struct i40iw_device *)dev->back_dev;
1157 struct i40iw_cqp *iwcqp = &iwdev->cqp;
1158 struct i40iw_cqp_request *cqp_request;
1159 struct cqp_commands_info *cqp_info;
1160 enum i40iw_status_code status;
1161
1162 cqp_request = i40iw_get_cqp_request(iwcqp, true);
1163 if (!cqp_request)
1164 return;
1165
1166 cqp_info = &cqp_request->info;
1167 memset(cqp_info, 0, sizeof(*cqp_info));
1168
1169 cqp_info->cqp_cmd = OP_QP_DESTROY;
1170 cqp_info->post_sq = 1;
1171 cqp_info->in.u.qp_destroy.qp = qp;
1172 cqp_info->in.u.qp_destroy.scratch = (uintptr_t)cqp_request;
1173 cqp_info->in.u.qp_destroy.remove_hash_idx = true;
1174 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1175 if (status)
1176 i40iw_pr_err("CQP QP_DESTROY fail");
1177}
1178
1179
1180/**
1014 * i40iw_ieq_mpa_crc_ae - generate AE for crc error 1181 * i40iw_ieq_mpa_crc_ae - generate AE for crc error
1015 * @dev: hardware control device structure 1182 * @dev: hardware control device structure
1016 * @qp: hardware control qp 1183 * @qp: hardware control qp
@@ -1208,7 +1375,7 @@ enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_in
1208 1375
1209 buf->totallen = pkt_len + buf->maclen; 1376 buf->totallen = pkt_len + buf->maclen;
1210 1377
1211 if (info->payload_len < buf->totallen - 4) { 1378 if (info->payload_len < buf->totallen) {
1212 i40iw_pr_err("payload_len = 0x%x totallen expected0x%x\n", 1379 i40iw_pr_err("payload_len = 0x%x totallen expected0x%x\n",
1213 info->payload_len, buf->totallen); 1380 info->payload_len, buf->totallen);
1214 return I40IW_ERR_INVALID_SIZE; 1381 return I40IW_ERR_INVALID_SIZE;
@@ -1224,27 +1391,29 @@ enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_in
1224 1391
1225/** 1392/**
1226 * i40iw_hw_stats_timeout - Stats timer-handler which updates all HW stats 1393 * i40iw_hw_stats_timeout - Stats timer-handler which updates all HW stats
1227 * @dev: hardware control device structure 1394 * @vsi: pointer to the vsi structure
1228 */ 1395 */
1229static void i40iw_hw_stats_timeout(unsigned long dev) 1396static void i40iw_hw_stats_timeout(unsigned long vsi)
1230{ 1397{
1231 struct i40iw_sc_dev *pf_dev = (struct i40iw_sc_dev *)dev; 1398 struct i40iw_sc_vsi *sc_vsi = (struct i40iw_sc_vsi *)vsi;
1232 struct i40iw_dev_pestat *pf_devstat = &pf_dev->dev_pestat; 1399 struct i40iw_sc_dev *pf_dev = sc_vsi->dev;
1233 struct i40iw_dev_pestat *vf_devstat = NULL; 1400 struct i40iw_vsi_pestat *pf_devstat = sc_vsi->pestat;
1401 struct i40iw_vsi_pestat *vf_devstat = NULL;
1234 u16 iw_vf_idx; 1402 u16 iw_vf_idx;
1235 unsigned long flags; 1403 unsigned long flags;
1236 1404
1237 /*PF*/ 1405 /*PF*/
1238 pf_devstat->ops.iw_hw_stat_read_all(pf_devstat, &pf_devstat->hw_stats); 1406 i40iw_hw_stats_read_all(pf_devstat, &pf_devstat->hw_stats);
1407
1239 for (iw_vf_idx = 0; iw_vf_idx < I40IW_MAX_PE_ENABLED_VF_COUNT; iw_vf_idx++) { 1408 for (iw_vf_idx = 0; iw_vf_idx < I40IW_MAX_PE_ENABLED_VF_COUNT; iw_vf_idx++) {
1240 spin_lock_irqsave(&pf_devstat->stats_lock, flags); 1409 spin_lock_irqsave(&pf_devstat->lock, flags);
1241 if (pf_dev->vf_dev[iw_vf_idx]) { 1410 if (pf_dev->vf_dev[iw_vf_idx]) {
1242 if (pf_dev->vf_dev[iw_vf_idx]->stats_initialized) { 1411 if (pf_dev->vf_dev[iw_vf_idx]->stats_initialized) {
1243 vf_devstat = &pf_dev->vf_dev[iw_vf_idx]->dev_pestat; 1412 vf_devstat = &pf_dev->vf_dev[iw_vf_idx]->pestat;
1244 vf_devstat->ops.iw_hw_stat_read_all(vf_devstat, &vf_devstat->hw_stats); 1413 i40iw_hw_stats_read_all(vf_devstat, &vf_devstat->hw_stats);
1245 } 1414 }
1246 } 1415 }
1247 spin_unlock_irqrestore(&pf_devstat->stats_lock, flags); 1416 spin_unlock_irqrestore(&pf_devstat->lock, flags);
1248 } 1417 }
1249 1418
1250 mod_timer(&pf_devstat->stats_timer, 1419 mod_timer(&pf_devstat->stats_timer,
@@ -1253,26 +1422,26 @@ static void i40iw_hw_stats_timeout(unsigned long dev)
1253 1422
1254/** 1423/**
1255 * i40iw_hw_stats_start_timer - Start periodic stats timer 1424 * i40iw_hw_stats_start_timer - Start periodic stats timer
1256 * @dev: hardware control device structure 1425 * @vsi: pointer to the vsi structure
1257 */ 1426 */
1258void i40iw_hw_stats_start_timer(struct i40iw_sc_dev *dev) 1427void i40iw_hw_stats_start_timer(struct i40iw_sc_vsi *vsi)
1259{ 1428{
1260 struct i40iw_dev_pestat *devstat = &dev->dev_pestat; 1429 struct i40iw_vsi_pestat *devstat = vsi->pestat;
1261 1430
1262 init_timer(&devstat->stats_timer); 1431 init_timer(&devstat->stats_timer);
1263 devstat->stats_timer.function = i40iw_hw_stats_timeout; 1432 devstat->stats_timer.function = i40iw_hw_stats_timeout;
1264 devstat->stats_timer.data = (unsigned long)dev; 1433 devstat->stats_timer.data = (unsigned long)vsi;
1265 mod_timer(&devstat->stats_timer, 1434 mod_timer(&devstat->stats_timer,
1266 jiffies + msecs_to_jiffies(STATS_TIMER_DELAY)); 1435 jiffies + msecs_to_jiffies(STATS_TIMER_DELAY));
1267} 1436}
1268 1437
1269/** 1438/**
1270 * i40iw_hw_stats_del_timer - Delete periodic stats timer 1439 * i40iw_hw_stats_stop_timer - Delete periodic stats timer
1271 * @dev: hardware control device structure 1440 * @vsi: pointer to the vsi structure
1272 */ 1441 */
1273void i40iw_hw_stats_del_timer(struct i40iw_sc_dev *dev) 1442void i40iw_hw_stats_stop_timer(struct i40iw_sc_vsi *vsi)
1274{ 1443{
1275 struct i40iw_dev_pestat *devstat = &dev->dev_pestat; 1444 struct i40iw_vsi_pestat *devstat = vsi->pestat;
1276 1445
1277 del_timer_sync(&devstat->stats_timer); 1446 del_timer_sync(&devstat->stats_timer);
1278} 1447}
diff --git a/drivers/infiniband/hw/i40iw/i40iw_verbs.c b/drivers/infiniband/hw/i40iw/i40iw_verbs.c
index 6329c971c22f..7368a50bbdaa 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_verbs.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_verbs.c
@@ -37,6 +37,7 @@
37#include <linux/random.h> 37#include <linux/random.h>
38#include <linux/highmem.h> 38#include <linux/highmem.h>
39#include <linux/time.h> 39#include <linux/time.h>
40#include <linux/hugetlb.h>
40#include <asm/byteorder.h> 41#include <asm/byteorder.h>
41#include <net/ip.h> 42#include <net/ip.h>
42#include <rdma/ib_verbs.h> 43#include <rdma/ib_verbs.h>
@@ -67,13 +68,13 @@ static int i40iw_query_device(struct ib_device *ibdev,
67 props->vendor_part_id = iwdev->ldev->pcidev->device; 68 props->vendor_part_id = iwdev->ldev->pcidev->device;
68 props->hw_ver = (u32)iwdev->sc_dev.hw_rev; 69 props->hw_ver = (u32)iwdev->sc_dev.hw_rev;
69 props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE; 70 props->max_mr_size = I40IW_MAX_OUTBOUND_MESSAGE_SIZE;
70 props->max_qp = iwdev->max_qp; 71 props->max_qp = iwdev->max_qp - iwdev->used_qps;
71 props->max_qp_wr = (I40IW_MAX_WQ_ENTRIES >> 2) - 1; 72 props->max_qp_wr = (I40IW_MAX_WQ_ENTRIES >> 2) - 1;
72 props->max_sge = I40IW_MAX_WQ_FRAGMENT_COUNT; 73 props->max_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
73 props->max_cq = iwdev->max_cq; 74 props->max_cq = iwdev->max_cq - iwdev->used_cqs;
74 props->max_cqe = iwdev->max_cqe; 75 props->max_cqe = iwdev->max_cqe;
75 props->max_mr = iwdev->max_mr; 76 props->max_mr = iwdev->max_mr - iwdev->used_mrs;
76 props->max_pd = iwdev->max_pd; 77 props->max_pd = iwdev->max_pd - iwdev->used_pds;
77 props->max_sge_rd = I40IW_MAX_SGE_RD; 78 props->max_sge_rd = I40IW_MAX_SGE_RD;
78 props->max_qp_rd_atom = I40IW_MAX_IRD_SIZE; 79 props->max_qp_rd_atom = I40IW_MAX_IRD_SIZE;
79 props->max_qp_init_rd_atom = props->max_qp_rd_atom; 80 props->max_qp_init_rd_atom = props->max_qp_rd_atom;
@@ -254,7 +255,6 @@ static void i40iw_alloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp
254{ 255{
255 struct i40iw_cqp_request *cqp_request; 256 struct i40iw_cqp_request *cqp_request;
256 struct cqp_commands_info *cqp_info; 257 struct cqp_commands_info *cqp_info;
257 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
258 enum i40iw_status_code status; 258 enum i40iw_status_code status;
259 259
260 if (qp->push_idx != I40IW_INVALID_PUSH_PAGE_INDEX) 260 if (qp->push_idx != I40IW_INVALID_PUSH_PAGE_INDEX)
@@ -270,7 +270,7 @@ static void i40iw_alloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_qp
270 cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE; 270 cqp_info->cqp_cmd = OP_MANAGE_PUSH_PAGE;
271 cqp_info->post_sq = 1; 271 cqp_info->post_sq = 1;
272 272
273 cqp_info->in.u.manage_push_page.info.qs_handle = dev->qs_handle; 273 cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
274 cqp_info->in.u.manage_push_page.info.free_page = 0; 274 cqp_info->in.u.manage_push_page.info.free_page = 0;
275 cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp; 275 cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
276 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request; 276 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
@@ -292,7 +292,6 @@ static void i40iw_dealloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_
292{ 292{
293 struct i40iw_cqp_request *cqp_request; 293 struct i40iw_cqp_request *cqp_request;
294 struct cqp_commands_info *cqp_info; 294 struct cqp_commands_info *cqp_info;
295 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
296 enum i40iw_status_code status; 295 enum i40iw_status_code status;
297 296
298 if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX) 297 if (qp->push_idx == I40IW_INVALID_PUSH_PAGE_INDEX)
@@ -307,7 +306,7 @@ static void i40iw_dealloc_push_page(struct i40iw_device *iwdev, struct i40iw_sc_
307 cqp_info->post_sq = 1; 306 cqp_info->post_sq = 1;
308 307
309 cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx; 308 cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx;
310 cqp_info->in.u.manage_push_page.info.qs_handle = dev->qs_handle; 309 cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;
311 cqp_info->in.u.manage_push_page.info.free_page = 1; 310 cqp_info->in.u.manage_push_page.info.free_page = 1;
312 cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp; 311 cqp_info->in.u.manage_push_page.cqp = &iwdev->cqp.sc_cqp;
313 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request; 312 cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;
@@ -337,6 +336,9 @@ static struct ib_pd *i40iw_alloc_pd(struct ib_device *ibdev,
337 u32 pd_id = 0; 336 u32 pd_id = 0;
338 int err; 337 int err;
339 338
339 if (iwdev->closing)
340 return ERR_PTR(-ENODEV);
341
340 err = i40iw_alloc_resource(iwdev, iwdev->allocated_pds, 342 err = i40iw_alloc_resource(iwdev, iwdev->allocated_pds,
341 iwdev->max_pd, &pd_id, &iwdev->next_pd); 343 iwdev->max_pd, &pd_id, &iwdev->next_pd);
342 if (err) { 344 if (err) {
@@ -602,6 +604,9 @@ static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd,
602 struct i40iwarp_offload_info *iwarp_info; 604 struct i40iwarp_offload_info *iwarp_info;
603 unsigned long flags; 605 unsigned long flags;
604 606
607 if (iwdev->closing)
608 return ERR_PTR(-ENODEV);
609
605 if (init_attr->create_flags) 610 if (init_attr->create_flags)
606 return ERR_PTR(-EINVAL); 611 return ERR_PTR(-EINVAL);
607 if (init_attr->cap.max_inline_data > I40IW_MAX_INLINE_DATA_SIZE) 612 if (init_attr->cap.max_inline_data > I40IW_MAX_INLINE_DATA_SIZE)
@@ -610,11 +615,15 @@ static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd,
610 if (init_attr->cap.max_send_sge > I40IW_MAX_WQ_FRAGMENT_COUNT) 615 if (init_attr->cap.max_send_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
611 init_attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT; 616 init_attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
612 617
618 if (init_attr->cap.max_recv_sge > I40IW_MAX_WQ_FRAGMENT_COUNT)
619 init_attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
620
613 memset(&init_info, 0, sizeof(init_info)); 621 memset(&init_info, 0, sizeof(init_info));
614 622
615 sq_size = init_attr->cap.max_send_wr; 623 sq_size = init_attr->cap.max_send_wr;
616 rq_size = init_attr->cap.max_recv_wr; 624 rq_size = init_attr->cap.max_recv_wr;
617 625
626 init_info.vsi = &iwdev->vsi;
618 init_info.qp_uk_init_info.sq_size = sq_size; 627 init_info.qp_uk_init_info.sq_size = sq_size;
619 init_info.qp_uk_init_info.rq_size = rq_size; 628 init_info.qp_uk_init_info.rq_size = rq_size;
620 init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge; 629 init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge;
@@ -774,6 +783,7 @@ static struct ib_qp *i40iw_create_qp(struct ib_pd *ibpd,
774 iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0; 783 iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
775 iwdev->qp_table[qp_num] = iwqp; 784 iwdev->qp_table[qp_num] = iwqp;
776 i40iw_add_pdusecount(iwqp->iwpd); 785 i40iw_add_pdusecount(iwqp->iwpd);
786 i40iw_add_devusecount(iwdev);
777 if (ibpd->uobject && udata) { 787 if (ibpd->uobject && udata) {
778 memset(&uresp, 0, sizeof(uresp)); 788 memset(&uresp, 0, sizeof(uresp));
779 uresp.actual_sq_size = sq_size; 789 uresp.actual_sq_size = sq_size;
@@ -815,8 +825,9 @@ static int i40iw_query_qp(struct ib_qp *ibqp,
815 attr->qp_access_flags = 0; 825 attr->qp_access_flags = 0;
816 attr->cap.max_send_wr = qp->qp_uk.sq_size; 826 attr->cap.max_send_wr = qp->qp_uk.sq_size;
817 attr->cap.max_recv_wr = qp->qp_uk.rq_size; 827 attr->cap.max_recv_wr = qp->qp_uk.rq_size;
818 attr->cap.max_recv_sge = 1;
819 attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE; 828 attr->cap.max_inline_data = I40IW_MAX_INLINE_DATA_SIZE;
829 attr->cap.max_send_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
830 attr->cap.max_recv_sge = I40IW_MAX_WQ_FRAGMENT_COUNT;
820 init_attr->event_handler = iwqp->ibqp.event_handler; 831 init_attr->event_handler = iwqp->ibqp.event_handler;
821 init_attr->qp_context = iwqp->ibqp.qp_context; 832 init_attr->qp_context = iwqp->ibqp.qp_context;
822 init_attr->send_cq = iwqp->ibqp.send_cq; 833 init_attr->send_cq = iwqp->ibqp.send_cq;
@@ -884,6 +895,11 @@ int i40iw_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
884 spin_lock_irqsave(&iwqp->lock, flags); 895 spin_lock_irqsave(&iwqp->lock, flags);
885 896
886 if (attr_mask & IB_QP_STATE) { 897 if (attr_mask & IB_QP_STATE) {
898 if (iwdev->closing && attr->qp_state != IB_QPS_ERR) {
899 err = -EINVAL;
900 goto exit;
901 }
902
887 switch (attr->qp_state) { 903 switch (attr->qp_state) {
888 case IB_QPS_INIT: 904 case IB_QPS_INIT:
889 case IB_QPS_RTR: 905 case IB_QPS_RTR:
@@ -944,7 +960,7 @@ int i40iw_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
944 goto exit; 960 goto exit;
945 } 961 }
946 if (iwqp->sc_qp.term_flags) 962 if (iwqp->sc_qp.term_flags)
947 del_timer(&iwqp->terminate_timer); 963 i40iw_terminate_del_timer(&iwqp->sc_qp);
948 info.next_iwarp_state = I40IW_QP_STATE_ERROR; 964 info.next_iwarp_state = I40IW_QP_STATE_ERROR;
949 if ((iwqp->hw_tcp_state > I40IW_TCP_STATE_CLOSED) && 965 if ((iwqp->hw_tcp_state > I40IW_TCP_STATE_CLOSED) &&
950 iwdev->iw_status && 966 iwdev->iw_status &&
@@ -1037,11 +1053,11 @@ static void cq_free_resources(struct i40iw_device *iwdev, struct i40iw_cq *iwcq)
1037} 1053}
1038 1054
1039/** 1055/**
1040 * cq_wq_destroy - send cq destroy cqp 1056 * i40iw_cq_wq_destroy - send cq destroy cqp
1041 * @iwdev: iwarp device 1057 * @iwdev: iwarp device
1042 * @cq: hardware control cq 1058 * @cq: hardware control cq
1043 */ 1059 */
1044static void cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq) 1060void i40iw_cq_wq_destroy(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq)
1045{ 1061{
1046 enum i40iw_status_code status; 1062 enum i40iw_status_code status;
1047 struct i40iw_cqp_request *cqp_request; 1063 struct i40iw_cqp_request *cqp_request;
@@ -1080,9 +1096,10 @@ static int i40iw_destroy_cq(struct ib_cq *ib_cq)
1080 iwcq = to_iwcq(ib_cq); 1096 iwcq = to_iwcq(ib_cq);
1081 iwdev = to_iwdev(ib_cq->device); 1097 iwdev = to_iwdev(ib_cq->device);
1082 cq = &iwcq->sc_cq; 1098 cq = &iwcq->sc_cq;
1083 cq_wq_destroy(iwdev, cq); 1099 i40iw_cq_wq_destroy(iwdev, cq);
1084 cq_free_resources(iwdev, iwcq); 1100 cq_free_resources(iwdev, iwcq);
1085 kfree(iwcq); 1101 kfree(iwcq);
1102 i40iw_rem_devusecount(iwdev);
1086 return 0; 1103 return 0;
1087} 1104}
1088 1105
@@ -1113,6 +1130,9 @@ static struct ib_cq *i40iw_create_cq(struct ib_device *ibdev,
1113 int err_code; 1130 int err_code;
1114 int entries = attr->cqe; 1131 int entries = attr->cqe;
1115 1132
1133 if (iwdev->closing)
1134 return ERR_PTR(-ENODEV);
1135
1116 if (entries > iwdev->max_cqe) 1136 if (entries > iwdev->max_cqe)
1117 return ERR_PTR(-EINVAL); 1137 return ERR_PTR(-EINVAL);
1118 1138
@@ -1137,7 +1157,8 @@ static struct ib_cq *i40iw_create_cq(struct ib_device *ibdev,
1137 ukinfo->cq_id = cq_num; 1157 ukinfo->cq_id = cq_num;
1138 iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size; 1158 iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size;
1139 info.ceqe_mask = 0; 1159 info.ceqe_mask = 0;
1140 info.ceq_id = 0; 1160 if (attr->comp_vector < iwdev->ceqs_count)
1161 info.ceq_id = attr->comp_vector;
1141 info.ceq_id_valid = true; 1162 info.ceq_id_valid = true;
1142 info.ceqe_mask = 1; 1163 info.ceqe_mask = 1;
1143 info.type = I40IW_CQ_TYPE_IWARP; 1164 info.type = I40IW_CQ_TYPE_IWARP;
@@ -1229,10 +1250,11 @@ static struct ib_cq *i40iw_create_cq(struct ib_device *ibdev,
1229 } 1250 }
1230 } 1251 }
1231 1252
1253 i40iw_add_devusecount(iwdev);
1232 return (struct ib_cq *)iwcq; 1254 return (struct ib_cq *)iwcq;
1233 1255
1234cq_destroy: 1256cq_destroy:
1235 cq_wq_destroy(iwdev, cq); 1257 i40iw_cq_wq_destroy(iwdev, cq);
1236cq_free_resources: 1258cq_free_resources:
1237 cq_free_resources(iwdev, iwcq); 1259 cq_free_resources(iwdev, iwcq);
1238error: 1260error:
@@ -1266,6 +1288,7 @@ static void i40iw_free_stag(struct i40iw_device *iwdev, u32 stag)
1266 1288
1267 stag_idx = (stag & iwdev->mr_stagmask) >> I40IW_CQPSQ_STAG_IDX_SHIFT; 1289 stag_idx = (stag & iwdev->mr_stagmask) >> I40IW_CQPSQ_STAG_IDX_SHIFT;
1268 i40iw_free_resource(iwdev, iwdev->allocated_mrs, stag_idx); 1290 i40iw_free_resource(iwdev, iwdev->allocated_mrs, stag_idx);
1291 i40iw_rem_devusecount(iwdev);
1269} 1292}
1270 1293
1271/** 1294/**
@@ -1296,19 +1319,18 @@ static u32 i40iw_create_stag(struct i40iw_device *iwdev)
1296 stag = stag_index << I40IW_CQPSQ_STAG_IDX_SHIFT; 1319 stag = stag_index << I40IW_CQPSQ_STAG_IDX_SHIFT;
1297 stag |= driver_key; 1320 stag |= driver_key;
1298 stag += (u32)consumer_key; 1321 stag += (u32)consumer_key;
1322 i40iw_add_devusecount(iwdev);
1299 } 1323 }
1300 return stag; 1324 return stag;
1301} 1325}
1302 1326
1303/** 1327/**
1304 * i40iw_next_pbl_addr - Get next pbl address 1328 * i40iw_next_pbl_addr - Get next pbl address
1305 * @palloc: Poiner to allocated pbles
1306 * @pbl: pointer to a pble 1329 * @pbl: pointer to a pble
1307 * @pinfo: info pointer 1330 * @pinfo: info pointer
1308 * @idx: index 1331 * @idx: index
1309 */ 1332 */
1310static inline u64 *i40iw_next_pbl_addr(struct i40iw_pble_alloc *palloc, 1333static inline u64 *i40iw_next_pbl_addr(u64 *pbl,
1311 u64 *pbl,
1312 struct i40iw_pble_info **pinfo, 1334 struct i40iw_pble_info **pinfo,
1313 u32 *idx) 1335 u32 *idx)
1314{ 1336{
@@ -1336,9 +1358,11 @@ static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr,
1336 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc; 1358 struct i40iw_pble_alloc *palloc = &iwpbl->pble_alloc;
1337 struct i40iw_pble_info *pinfo; 1359 struct i40iw_pble_info *pinfo;
1338 struct scatterlist *sg; 1360 struct scatterlist *sg;
1361 u64 pg_addr = 0;
1339 u32 idx = 0; 1362 u32 idx = 0;
1340 1363
1341 pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf; 1364 pinfo = (level == I40IW_LEVEL_1) ? NULL : palloc->level2.leaf;
1365
1342 pg_shift = ffs(region->page_size) - 1; 1366 pg_shift = ffs(region->page_size) - 1;
1343 for_each_sg(region->sg_head.sgl, sg, region->nmap, entry) { 1367 for_each_sg(region->sg_head.sgl, sg, region->nmap, entry) {
1344 chunk_pages = sg_dma_len(sg) >> pg_shift; 1368 chunk_pages = sg_dma_len(sg) >> pg_shift;
@@ -1346,17 +1370,96 @@ static void i40iw_copy_user_pgaddrs(struct i40iw_mr *iwmr,
1346 !iwpbl->qp_mr.sq_page) 1370 !iwpbl->qp_mr.sq_page)
1347 iwpbl->qp_mr.sq_page = sg_page(sg); 1371 iwpbl->qp_mr.sq_page = sg_page(sg);
1348 for (i = 0; i < chunk_pages; i++) { 1372 for (i = 0; i < chunk_pages; i++) {
1349 *pbl = cpu_to_le64(sg_dma_address(sg) + region->page_size * i); 1373 pg_addr = sg_dma_address(sg) + region->page_size * i;
1350 pbl = i40iw_next_pbl_addr(palloc, pbl, &pinfo, &idx); 1374
1375 if ((entry + i) == 0)
1376 *pbl = cpu_to_le64(pg_addr & iwmr->page_msk);
1377 else if (!(pg_addr & ~iwmr->page_msk))
1378 *pbl = cpu_to_le64(pg_addr);
1379 else
1380 continue;
1381 pbl = i40iw_next_pbl_addr(pbl, &pinfo, &idx);
1382 }
1383 }
1384}
1385
1386/**
1387 * i40iw_set_hugetlb_params - set MR pg size and mask to huge pg values.
1388 * @addr: virtual address
1389 * @iwmr: mr pointer for this memory registration
1390 */
1391static void i40iw_set_hugetlb_values(u64 addr, struct i40iw_mr *iwmr)
1392{
1393 struct vm_area_struct *vma;
1394 struct hstate *h;
1395
1396 vma = find_vma(current->mm, addr);
1397 if (vma && is_vm_hugetlb_page(vma)) {
1398 h = hstate_vma(vma);
1399 if (huge_page_size(h) == 0x200000) {
1400 iwmr->page_size = huge_page_size(h);
1401 iwmr->page_msk = huge_page_mask(h);
1351 } 1402 }
1352 } 1403 }
1353} 1404}
1354 1405
1355/** 1406/**
1407 * i40iw_check_mem_contiguous - check if pbls stored in arr are contiguous
1408 * @arr: lvl1 pbl array
1409 * @npages: page count
1410 * pg_size: page size
1411 *
1412 */
1413static bool i40iw_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size)
1414{
1415 u32 pg_idx;
1416
1417 for (pg_idx = 0; pg_idx < npages; pg_idx++) {
1418 if ((*arr + (pg_size * pg_idx)) != arr[pg_idx])
1419 return false;
1420 }
1421 return true;
1422}
1423
1424/**
1425 * i40iw_check_mr_contiguous - check if MR is physically contiguous
1426 * @palloc: pbl allocation struct
1427 * pg_size: page size
1428 */
1429static bool i40iw_check_mr_contiguous(struct i40iw_pble_alloc *palloc, u32 pg_size)
1430{
1431 struct i40iw_pble_level2 *lvl2 = &palloc->level2;
1432 struct i40iw_pble_info *leaf = lvl2->leaf;
1433 u64 *arr = NULL;
1434 u64 *start_addr = NULL;
1435 int i;
1436 bool ret;
1437
1438 if (palloc->level == I40IW_LEVEL_1) {
1439 arr = (u64 *)palloc->level1.addr;
1440 ret = i40iw_check_mem_contiguous(arr, palloc->total_cnt, pg_size);
1441 return ret;
1442 }
1443
1444 start_addr = (u64 *)leaf->addr;
1445
1446 for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) {
1447 arr = (u64 *)leaf->addr;
1448 if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr)
1449 return false;
1450 ret = i40iw_check_mem_contiguous(arr, leaf->cnt, pg_size);
1451 if (!ret)
1452 return false;
1453 }
1454
1455 return true;
1456}
1457
1458/**
1356 * i40iw_setup_pbles - copy user pg address to pble's 1459 * i40iw_setup_pbles - copy user pg address to pble's
1357 * @iwdev: iwarp device 1460 * @iwdev: iwarp device
1358 * @iwmr: mr pointer for this memory registration 1461 * @iwmr: mr pointer for this memory registration
1359 * @use_pbles: flag if to use pble's or memory (level 0) 1462 * @use_pbles: flag if to use pble's
1360 */ 1463 */
1361static int i40iw_setup_pbles(struct i40iw_device *iwdev, 1464static int i40iw_setup_pbles(struct i40iw_device *iwdev,
1362 struct i40iw_mr *iwmr, 1465 struct i40iw_mr *iwmr,
@@ -1369,9 +1472,6 @@ static int i40iw_setup_pbles(struct i40iw_device *iwdev,
1369 enum i40iw_status_code status; 1472 enum i40iw_status_code status;
1370 enum i40iw_pble_level level = I40IW_LEVEL_1; 1473 enum i40iw_pble_level level = I40IW_LEVEL_1;
1371 1474
1372 if (!use_pbles && (iwmr->page_cnt > MAX_SAVE_PAGE_ADDRS))
1373 return -ENOMEM;
1374
1375 if (use_pbles) { 1475 if (use_pbles) {
1376 mutex_lock(&iwdev->pbl_mutex); 1476 mutex_lock(&iwdev->pbl_mutex);
1377 status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt); 1477 status = i40iw_get_pble(&iwdev->sc_dev, iwdev->pble_rsrc, palloc, iwmr->page_cnt);
@@ -1388,6 +1488,10 @@ static int i40iw_setup_pbles(struct i40iw_device *iwdev,
1388 } 1488 }
1389 1489
1390 i40iw_copy_user_pgaddrs(iwmr, pbl, level); 1490 i40iw_copy_user_pgaddrs(iwmr, pbl, level);
1491
1492 if (use_pbles)
1493 iwmr->pgaddrmem[0] = *pbl;
1494
1391 return 0; 1495 return 0;
1392} 1496}
1393 1497
@@ -1409,14 +1513,18 @@ static int i40iw_handle_q_mem(struct i40iw_device *iwdev,
1409 struct i40iw_cq_mr *cqmr = &iwpbl->cq_mr; 1513 struct i40iw_cq_mr *cqmr = &iwpbl->cq_mr;
1410 struct i40iw_hmc_pble *hmc_p; 1514 struct i40iw_hmc_pble *hmc_p;
1411 u64 *arr = iwmr->pgaddrmem; 1515 u64 *arr = iwmr->pgaddrmem;
1516 u32 pg_size;
1412 int err; 1517 int err;
1413 int total; 1518 int total;
1519 bool ret = true;
1414 1520
1415 total = req->sq_pages + req->rq_pages + req->cq_pages; 1521 total = req->sq_pages + req->rq_pages + req->cq_pages;
1522 pg_size = iwmr->page_size;
1416 1523
1417 err = i40iw_setup_pbles(iwdev, iwmr, use_pbles); 1524 err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
1418 if (err) 1525 if (err)
1419 return err; 1526 return err;
1527
1420 if (use_pbles && (palloc->level != I40IW_LEVEL_1)) { 1528 if (use_pbles && (palloc->level != I40IW_LEVEL_1)) {
1421 i40iw_free_pble(iwdev->pble_rsrc, palloc); 1529 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1422 iwpbl->pbl_allocated = false; 1530 iwpbl->pbl_allocated = false;
@@ -1425,26 +1533,44 @@ static int i40iw_handle_q_mem(struct i40iw_device *iwdev,
1425 1533
1426 if (use_pbles) 1534 if (use_pbles)
1427 arr = (u64 *)palloc->level1.addr; 1535 arr = (u64 *)palloc->level1.addr;
1428 if (req->reg_type == IW_MEMREG_TYPE_QP) { 1536
1537 if (iwmr->type == IW_MEMREG_TYPE_QP) {
1429 hmc_p = &qpmr->sq_pbl; 1538 hmc_p = &qpmr->sq_pbl;
1430 qpmr->shadow = (dma_addr_t)arr[total]; 1539 qpmr->shadow = (dma_addr_t)arr[total];
1540
1431 if (use_pbles) { 1541 if (use_pbles) {
1542 ret = i40iw_check_mem_contiguous(arr, req->sq_pages, pg_size);
1543 if (ret)
1544 ret = i40iw_check_mem_contiguous(&arr[req->sq_pages], req->rq_pages, pg_size);
1545 }
1546
1547 if (!ret) {
1432 hmc_p->idx = palloc->level1.idx; 1548 hmc_p->idx = palloc->level1.idx;
1433 hmc_p = &qpmr->rq_pbl; 1549 hmc_p = &qpmr->rq_pbl;
1434 hmc_p->idx = palloc->level1.idx + req->sq_pages; 1550 hmc_p->idx = palloc->level1.idx + req->sq_pages;
1435 } else { 1551 } else {
1436 hmc_p->addr = arr[0]; 1552 hmc_p->addr = arr[0];
1437 hmc_p = &qpmr->rq_pbl; 1553 hmc_p = &qpmr->rq_pbl;
1438 hmc_p->addr = arr[1]; 1554 hmc_p->addr = arr[req->sq_pages];
1439 } 1555 }
1440 } else { /* CQ */ 1556 } else { /* CQ */
1441 hmc_p = &cqmr->cq_pbl; 1557 hmc_p = &cqmr->cq_pbl;
1442 cqmr->shadow = (dma_addr_t)arr[total]; 1558 cqmr->shadow = (dma_addr_t)arr[total];
1559
1443 if (use_pbles) 1560 if (use_pbles)
1561 ret = i40iw_check_mem_contiguous(arr, req->cq_pages, pg_size);
1562
1563 if (!ret)
1444 hmc_p->idx = palloc->level1.idx; 1564 hmc_p->idx = palloc->level1.idx;
1445 else 1565 else
1446 hmc_p->addr = arr[0]; 1566 hmc_p->addr = arr[0];
1447 } 1567 }
1568
1569 if (use_pbles && ret) {
1570 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1571 iwpbl->pbl_allocated = false;
1572 }
1573
1448 return err; 1574 return err;
1449} 1575}
1450 1576
@@ -1642,8 +1768,9 @@ static int i40iw_hwreg_mr(struct i40iw_device *iwdev,
1642 stag_info->access_rights = access; 1768 stag_info->access_rights = access;
1643 stag_info->pd_id = iwpd->sc_pd.pd_id; 1769 stag_info->pd_id = iwpd->sc_pd.pd_id;
1644 stag_info->addr_type = I40IW_ADDR_TYPE_VA_BASED; 1770 stag_info->addr_type = I40IW_ADDR_TYPE_VA_BASED;
1771 stag_info->page_size = iwmr->page_size;
1645 1772
1646 if (iwmr->page_cnt > 1) { 1773 if (iwpbl->pbl_allocated) {
1647 if (palloc->level == I40IW_LEVEL_1) { 1774 if (palloc->level == I40IW_LEVEL_1) {
1648 stag_info->first_pm_pbl_index = palloc->level1.idx; 1775 stag_info->first_pm_pbl_index = palloc->level1.idx;
1649 stag_info->chunk_size = 1; 1776 stag_info->chunk_size = 1;
@@ -1699,6 +1826,11 @@ static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
1699 bool use_pbles = false; 1826 bool use_pbles = false;
1700 unsigned long flags; 1827 unsigned long flags;
1701 int err = -ENOSYS; 1828 int err = -ENOSYS;
1829 int ret;
1830 int pg_shift;
1831
1832 if (iwdev->closing)
1833 return ERR_PTR(-ENODEV);
1702 1834
1703 if (length > I40IW_MAX_MR_SIZE) 1835 if (length > I40IW_MAX_MR_SIZE)
1704 return ERR_PTR(-EINVAL); 1836 return ERR_PTR(-EINVAL);
@@ -1723,9 +1855,17 @@ static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
1723 iwmr->ibmr.pd = pd; 1855 iwmr->ibmr.pd = pd;
1724 iwmr->ibmr.device = pd->device; 1856 iwmr->ibmr.device = pd->device;
1725 ucontext = to_ucontext(pd->uobject->context); 1857 ucontext = to_ucontext(pd->uobject->context);
1726 region_length = region->length + (start & 0xfff); 1858
1727 pbl_depth = region_length >> 12; 1859 iwmr->page_size = region->page_size;
1728 pbl_depth += (region_length & (4096 - 1)) ? 1 : 0; 1860 iwmr->page_msk = PAGE_MASK;
1861
1862 if (region->hugetlb && (req.reg_type == IW_MEMREG_TYPE_MEM))
1863 i40iw_set_hugetlb_values(start, iwmr);
1864
1865 region_length = region->length + (start & (iwmr->page_size - 1));
1866 pg_shift = ffs(iwmr->page_size) - 1;
1867 pbl_depth = region_length >> pg_shift;
1868 pbl_depth += (region_length & (iwmr->page_size - 1)) ? 1 : 0;
1729 iwmr->length = region->length; 1869 iwmr->length = region->length;
1730 1870
1731 iwpbl->user_base = virt; 1871 iwpbl->user_base = virt;
@@ -1755,13 +1895,21 @@ static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
1755 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); 1895 spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags);
1756 break; 1896 break;
1757 case IW_MEMREG_TYPE_MEM: 1897 case IW_MEMREG_TYPE_MEM:
1898 use_pbles = (iwmr->page_cnt != 1);
1758 access = I40IW_ACCESS_FLAGS_LOCALREAD; 1899 access = I40IW_ACCESS_FLAGS_LOCALREAD;
1759 1900
1760 use_pbles = (iwmr->page_cnt != 1);
1761 err = i40iw_setup_pbles(iwdev, iwmr, use_pbles); 1901 err = i40iw_setup_pbles(iwdev, iwmr, use_pbles);
1762 if (err) 1902 if (err)
1763 goto error; 1903 goto error;
1764 1904
1905 if (use_pbles) {
1906 ret = i40iw_check_mr_contiguous(palloc, iwmr->page_size);
1907 if (ret) {
1908 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1909 iwpbl->pbl_allocated = false;
1910 }
1911 }
1912
1765 access |= i40iw_get_user_access(acc); 1913 access |= i40iw_get_user_access(acc);
1766 stag = i40iw_create_stag(iwdev); 1914 stag = i40iw_create_stag(iwdev);
1767 if (!stag) { 1915 if (!stag) {
@@ -1778,6 +1926,7 @@ static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
1778 i40iw_free_stag(iwdev, stag); 1926 i40iw_free_stag(iwdev, stag);
1779 goto error; 1927 goto error;
1780 } 1928 }
1929
1781 break; 1930 break;
1782 default: 1931 default:
1783 goto error; 1932 goto error;
@@ -1789,7 +1938,7 @@ static struct ib_mr *i40iw_reg_user_mr(struct ib_pd *pd,
1789 return &iwmr->ibmr; 1938 return &iwmr->ibmr;
1790 1939
1791error: 1940error:
1792 if (palloc->level != I40IW_LEVEL_0) 1941 if (palloc->level != I40IW_LEVEL_0 && iwpbl->pbl_allocated)
1793 i40iw_free_pble(iwdev->pble_rsrc, palloc); 1942 i40iw_free_pble(iwdev->pble_rsrc, palloc);
1794 ib_umem_release(region); 1943 ib_umem_release(region);
1795 kfree(iwmr); 1944 kfree(iwmr);
@@ -2142,7 +2291,6 @@ static int i40iw_post_send(struct ib_qp *ibqp,
2142 case IB_WR_REG_MR: 2291 case IB_WR_REG_MR:
2143 { 2292 {
2144 struct i40iw_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr); 2293 struct i40iw_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr);
2145 int page_shift = ilog2(reg_wr(ib_wr)->mr->page_size);
2146 int flags = reg_wr(ib_wr)->access; 2294 int flags = reg_wr(ib_wr)->access;
2147 struct i40iw_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc; 2295 struct i40iw_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc;
2148 struct i40iw_sc_dev *dev = &iwqp->iwdev->sc_dev; 2296 struct i40iw_sc_dev *dev = &iwqp->iwdev->sc_dev;
@@ -2153,6 +2301,7 @@ static int i40iw_post_send(struct ib_qp *ibqp,
2153 info.access_rights |= i40iw_get_user_access(flags); 2301 info.access_rights |= i40iw_get_user_access(flags);
2154 info.stag_key = reg_wr(ib_wr)->key & 0xff; 2302 info.stag_key = reg_wr(ib_wr)->key & 0xff;
2155 info.stag_idx = reg_wr(ib_wr)->key >> 8; 2303 info.stag_idx = reg_wr(ib_wr)->key >> 8;
2304 info.page_size = reg_wr(ib_wr)->mr->page_size;
2156 info.wr_id = ib_wr->wr_id; 2305 info.wr_id = ib_wr->wr_id;
2157 2306
2158 info.addr_type = I40IW_ADDR_TYPE_VA_BASED; 2307 info.addr_type = I40IW_ADDR_TYPE_VA_BASED;
@@ -2166,9 +2315,6 @@ static int i40iw_post_send(struct ib_qp *ibqp,
2166 if (iwmr->npages > I40IW_MIN_PAGES_PER_FMR) 2315 if (iwmr->npages > I40IW_MIN_PAGES_PER_FMR)
2167 info.chunk_size = 1; 2316 info.chunk_size = 1;
2168 2317
2169 if (page_shift == 21)
2170 info.page_size = 1; /* 2M page */
2171
2172 ret = dev->iw_priv_qp_ops->iw_mr_fast_register(&iwqp->sc_qp, &info, true); 2318 ret = dev->iw_priv_qp_ops->iw_mr_fast_register(&iwqp->sc_qp, &info, true);
2173 if (ret) 2319 if (ret)
2174 err = -ENOMEM; 2320 err = -ENOMEM;
@@ -2487,21 +2633,17 @@ static int i40iw_get_hw_stats(struct ib_device *ibdev,
2487{ 2633{
2488 struct i40iw_device *iwdev = to_iwdev(ibdev); 2634 struct i40iw_device *iwdev = to_iwdev(ibdev);
2489 struct i40iw_sc_dev *dev = &iwdev->sc_dev; 2635 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
2490 struct i40iw_dev_pestat *devstat = &dev->dev_pestat; 2636 struct i40iw_vsi_pestat *devstat = iwdev->vsi.pestat;
2491 struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats; 2637 struct i40iw_dev_hw_stats *hw_stats = &devstat->hw_stats;
2492 unsigned long flags;
2493 2638
2494 if (dev->is_pf) { 2639 if (dev->is_pf) {
2495 spin_lock_irqsave(&devstat->stats_lock, flags); 2640 i40iw_hw_stats_read_all(devstat, &devstat->hw_stats);
2496 devstat->ops.iw_hw_stat_read_all(devstat,
2497 &devstat->hw_stats);
2498 spin_unlock_irqrestore(&devstat->stats_lock, flags);
2499 } else { 2641 } else {
2500 if (i40iw_vchnl_vf_get_pe_stats(dev, &devstat->hw_stats)) 2642 if (i40iw_vchnl_vf_get_pe_stats(dev, &devstat->hw_stats))
2501 return -ENOSYS; 2643 return -ENOSYS;
2502 } 2644 }
2503 2645
2504 memcpy(&stats->value[0], &hw_stats, sizeof(*hw_stats)); 2646 memcpy(&stats->value[0], hw_stats, sizeof(*hw_stats));
2505 2647
2506 return stats->num_counters; 2648 return stats->num_counters;
2507} 2649}
@@ -2562,7 +2704,9 @@ static int i40iw_query_pkey(struct ib_device *ibdev,
2562 * @ah_attr: address handle attributes 2704 * @ah_attr: address handle attributes
2563 */ 2705 */
2564static struct ib_ah *i40iw_create_ah(struct ib_pd *ibpd, 2706static struct ib_ah *i40iw_create_ah(struct ib_pd *ibpd,
2565 struct ib_ah_attr *attr) 2707 struct ib_ah_attr *attr,
2708 struct ib_udata *udata)
2709
2566{ 2710{
2567 return ERR_PTR(-ENOSYS); 2711 return ERR_PTR(-ENOSYS);
2568} 2712}
@@ -2621,7 +2765,7 @@ static struct i40iw_ib_device *i40iw_init_rdma_device(struct i40iw_device *iwdev
2621 (1ull << IB_USER_VERBS_CMD_POST_RECV) | 2765 (1ull << IB_USER_VERBS_CMD_POST_RECV) |
2622 (1ull << IB_USER_VERBS_CMD_POST_SEND); 2766 (1ull << IB_USER_VERBS_CMD_POST_SEND);
2623 iwibdev->ibdev.phys_port_cnt = 1; 2767 iwibdev->ibdev.phys_port_cnt = 1;
2624 iwibdev->ibdev.num_comp_vectors = 1; 2768 iwibdev->ibdev.num_comp_vectors = iwdev->ceqs_count;
2625 iwibdev->ibdev.dma_device = &pcidev->dev; 2769 iwibdev->ibdev.dma_device = &pcidev->dev;
2626 iwibdev->ibdev.dev.parent = &pcidev->dev; 2770 iwibdev->ibdev.dev.parent = &pcidev->dev;
2627 iwibdev->ibdev.query_port = i40iw_query_port; 2771 iwibdev->ibdev.query_port = i40iw_query_port;
@@ -2654,7 +2798,6 @@ static struct i40iw_ib_device *i40iw_init_rdma_device(struct i40iw_device *iwdev
2654 iwibdev->ibdev.iwcm = kzalloc(sizeof(*iwibdev->ibdev.iwcm), GFP_KERNEL); 2798 iwibdev->ibdev.iwcm = kzalloc(sizeof(*iwibdev->ibdev.iwcm), GFP_KERNEL);
2655 if (!iwibdev->ibdev.iwcm) { 2799 if (!iwibdev->ibdev.iwcm) {
2656 ib_dealloc_device(&iwibdev->ibdev); 2800 ib_dealloc_device(&iwibdev->ibdev);
2657 i40iw_pr_err("iwcm == NULL\n");
2658 return NULL; 2801 return NULL;
2659 } 2802 }
2660 2803
@@ -2719,6 +2862,9 @@ void i40iw_destroy_rdma_device(struct i40iw_ib_device *iwibdev)
2719 i40iw_unregister_rdma_device(iwibdev); 2862 i40iw_unregister_rdma_device(iwibdev);
2720 kfree(iwibdev->ibdev.iwcm); 2863 kfree(iwibdev->ibdev.iwcm);
2721 iwibdev->ibdev.iwcm = NULL; 2864 iwibdev->ibdev.iwcm = NULL;
2865 wait_event_timeout(iwibdev->iwdev->close_wq,
2866 !atomic64_read(&iwibdev->iwdev->use_count),
2867 I40IW_EVENT_TIMEOUT);
2722 ib_dealloc_device(&iwibdev->ibdev); 2868 ib_dealloc_device(&iwibdev->ibdev);
2723} 2869}
2724 2870
diff --git a/drivers/infiniband/hw/i40iw/i40iw_verbs.h b/drivers/infiniband/hw/i40iw/i40iw_verbs.h
index 0069be8a5a38..6549c939500f 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_verbs.h
+++ b/drivers/infiniband/hw/i40iw/i40iw_verbs.h
@@ -92,6 +92,8 @@ struct i40iw_mr {
92 struct ib_umem *region; 92 struct ib_umem *region;
93 u16 type; 93 u16 type;
94 u32 page_cnt; 94 u32 page_cnt;
95 u32 page_size;
96 u64 page_msk;
95 u32 npages; 97 u32 npages;
96 u32 stag; 98 u32 stag;
97 u64 length; 99 u64 length;
diff --git a/drivers/infiniband/hw/i40iw/i40iw_virtchnl.c b/drivers/infiniband/hw/i40iw/i40iw_virtchnl.c
index 3041003c94d2..f4d13683a403 100644
--- a/drivers/infiniband/hw/i40iw/i40iw_virtchnl.c
+++ b/drivers/infiniband/hw/i40iw/i40iw_virtchnl.c
@@ -403,6 +403,19 @@ del_out:
403} 403}
404 404
405/** 405/**
406 * i40iw_vf_init_pestat - Initialize stats for VF
407 * @devL pointer to the VF Device
408 * @stats: Statistics structure pointer
409 * @index: Stats index
410 */
411static void i40iw_vf_init_pestat(struct i40iw_sc_dev *dev, struct i40iw_vsi_pestat *stats, u16 index)
412{
413 stats->hw = dev->hw;
414 i40iw_hw_stats_init(stats, (u8)index, false);
415 spin_lock_init(&stats->lock);
416}
417
418/**
406 * i40iw_vchnl_recv_pf - Receive PF virtual channel messages 419 * i40iw_vchnl_recv_pf - Receive PF virtual channel messages
407 * @dev: IWARP device pointer 420 * @dev: IWARP device pointer
408 * @vf_id: Virtual function ID associated with the message 421 * @vf_id: Virtual function ID associated with the message
@@ -421,9 +434,8 @@ enum i40iw_status_code i40iw_vchnl_recv_pf(struct i40iw_sc_dev *dev,
421 u16 first_avail_iw_vf = I40IW_MAX_PE_ENABLED_VF_COUNT; 434 u16 first_avail_iw_vf = I40IW_MAX_PE_ENABLED_VF_COUNT;
422 struct i40iw_virt_mem vf_dev_mem; 435 struct i40iw_virt_mem vf_dev_mem;
423 struct i40iw_virtchnl_work_info work_info; 436 struct i40iw_virtchnl_work_info work_info;
424 struct i40iw_dev_pestat *devstat; 437 struct i40iw_vsi_pestat *stats;
425 enum i40iw_status_code ret_code; 438 enum i40iw_status_code ret_code;
426 unsigned long flags;
427 439
428 if (!dev || !msg || !len) 440 if (!dev || !msg || !len)
429 return I40IW_ERR_PARAM; 441 return I40IW_ERR_PARAM;
@@ -496,14 +508,7 @@ enum i40iw_status_code i40iw_vchnl_recv_pf(struct i40iw_sc_dev *dev,
496 i40iw_debug(dev, I40IW_DEBUG_VIRT, 508 i40iw_debug(dev, I40IW_DEBUG_VIRT,
497 "VF%u error CQP HMC Function operation.\n", 509 "VF%u error CQP HMC Function operation.\n",
498 vf_id); 510 vf_id);
499 ret_code = i40iw_device_init_pestat(&vf_dev->dev_pestat); 511 i40iw_vf_init_pestat(dev, &vf_dev->pestat, vf_dev->pmf_index);
500 if (ret_code)
501 i40iw_debug(dev, I40IW_DEBUG_VIRT,
502 "VF%u - i40iw_device_init_pestat failed\n",
503 vf_id);
504 vf_dev->dev_pestat.ops.iw_hw_stat_init(&vf_dev->dev_pestat,
505 (u8)vf_dev->pmf_index,
506 dev->hw, false);
507 vf_dev->stats_initialized = true; 512 vf_dev->stats_initialized = true;
508 } else { 513 } else {
509 if (vf_dev) { 514 if (vf_dev) {
@@ -534,12 +539,10 @@ enum i40iw_status_code i40iw_vchnl_recv_pf(struct i40iw_sc_dev *dev,
534 case I40IW_VCHNL_OP_GET_STATS: 539 case I40IW_VCHNL_OP_GET_STATS:
535 if (!vf_dev) 540 if (!vf_dev)
536 return I40IW_ERR_BAD_PTR; 541 return I40IW_ERR_BAD_PTR;
537 devstat = &vf_dev->dev_pestat; 542 stats = &vf_dev->pestat;
538 spin_lock_irqsave(&dev->dev_pestat.stats_lock, flags); 543 i40iw_hw_stats_read_all(stats, &stats->hw_stats);
539 devstat->ops.iw_hw_stat_read_all(devstat, &devstat->hw_stats);
540 spin_unlock_irqrestore(&dev->dev_pestat.stats_lock, flags);
541 vf_dev->msg_count--; 544 vf_dev->msg_count--;
542 vchnl_pf_send_get_pe_stats_resp(dev, vf_id, vchnl_msg, &devstat->hw_stats); 545 vchnl_pf_send_get_pe_stats_resp(dev, vf_id, vchnl_msg, &stats->hw_stats);
543 break; 546 break;
544 default: 547 default:
545 i40iw_debug(dev, I40IW_DEBUG_VIRT, 548 i40iw_debug(dev, I40IW_DEBUG_VIRT,
diff --git a/drivers/infiniband/hw/mlx4/ah.c b/drivers/infiniband/hw/mlx4/ah.c
index b9bf0759f10a..077c33d2dc75 100644
--- a/drivers/infiniband/hw/mlx4/ah.c
+++ b/drivers/infiniband/hw/mlx4/ah.c
@@ -114,7 +114,9 @@ static struct ib_ah *create_iboe_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr
114 !(1 << ah->av.eth.stat_rate & dev->caps.stat_rate_support)) 114 !(1 << ah->av.eth.stat_rate & dev->caps.stat_rate_support))
115 --ah->av.eth.stat_rate; 115 --ah->av.eth.stat_rate;
116 } 116 }
117 117 ah->av.eth.sl_tclass_flowlabel |=
118 cpu_to_be32((ah_attr->grh.traffic_class << 20) |
119 ah_attr->grh.flow_label);
118 /* 120 /*
119 * HW requires multicast LID so we just choose one. 121 * HW requires multicast LID so we just choose one.
120 */ 122 */
@@ -122,12 +124,14 @@ static struct ib_ah *create_iboe_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr
122 ah->av.ib.dlid = cpu_to_be16(0xc000); 124 ah->av.ib.dlid = cpu_to_be16(0xc000);
123 125
124 memcpy(ah->av.eth.dgid, ah_attr->grh.dgid.raw, 16); 126 memcpy(ah->av.eth.dgid, ah_attr->grh.dgid.raw, 16);
125 ah->av.eth.sl_tclass_flowlabel = cpu_to_be32(ah_attr->sl << 29); 127 ah->av.eth.sl_tclass_flowlabel |= cpu_to_be32(ah_attr->sl << 29);
126 128
127 return &ah->ibah; 129 return &ah->ibah;
128} 130}
129 131
130struct ib_ah *mlx4_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr) 132struct ib_ah *mlx4_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr,
133 struct ib_udata *udata)
134
131{ 135{
132 struct mlx4_ib_ah *ah; 136 struct mlx4_ib_ah *ah;
133 struct ib_ah *ret; 137 struct ib_ah *ret;
diff --git a/drivers/infiniband/hw/mlx4/alias_GUID.c b/drivers/infiniband/hw/mlx4/alias_GUID.c
index 5e9939045852..06020c54db20 100644
--- a/drivers/infiniband/hw/mlx4/alias_GUID.c
+++ b/drivers/infiniband/hw/mlx4/alias_GUID.c
@@ -755,10 +755,8 @@ static void alias_guid_work(struct work_struct *work)
755 struct mlx4_ib_dev *dev = container_of(ib_sriov, struct mlx4_ib_dev, sriov); 755 struct mlx4_ib_dev *dev = container_of(ib_sriov, struct mlx4_ib_dev, sriov);
756 756
757 rec = kzalloc(sizeof *rec, GFP_KERNEL); 757 rec = kzalloc(sizeof *rec, GFP_KERNEL);
758 if (!rec) { 758 if (!rec)
759 pr_err("alias_guid_work: No Memory\n");
760 return; 759 return;
761 }
762 760
763 pr_debug("starting [port: %d]...\n", sriov_alias_port->port + 1); 761 pr_debug("starting [port: %d]...\n", sriov_alias_port->port + 1);
764 ret = get_next_record_to_update(dev, sriov_alias_port->port, rec); 762 ret = get_next_record_to_update(dev, sriov_alias_port->port, rec);
diff --git a/drivers/infiniband/hw/mlx4/cm.c b/drivers/infiniband/hw/mlx4/cm.c
index 39a488889fc7..d64845335e87 100644
--- a/drivers/infiniband/hw/mlx4/cm.c
+++ b/drivers/infiniband/hw/mlx4/cm.c
@@ -247,10 +247,8 @@ id_map_alloc(struct ib_device *ibdev, int slave_id, u32 sl_cm_id)
247 struct mlx4_ib_sriov *sriov = &to_mdev(ibdev)->sriov; 247 struct mlx4_ib_sriov *sriov = &to_mdev(ibdev)->sriov;
248 248
249 ent = kmalloc(sizeof (struct id_map_entry), GFP_KERNEL); 249 ent = kmalloc(sizeof (struct id_map_entry), GFP_KERNEL);
250 if (!ent) { 250 if (!ent)
251 mlx4_ib_warn(ibdev, "Couldn't allocate id cache entry - out of memory\n");
252 return ERR_PTR(-ENOMEM); 251 return ERR_PTR(-ENOMEM);
253 }
254 252
255 ent->sl_cm_id = sl_cm_id; 253 ent->sl_cm_id = sl_cm_id;
256 ent->slave_id = slave_id; 254 ent->slave_id = slave_id;
diff --git a/drivers/infiniband/hw/mlx4/mad.c b/drivers/infiniband/hw/mlx4/mad.c
index 1672907ff219..db564ccc0f92 100644
--- a/drivers/infiniband/hw/mlx4/mad.c
+++ b/drivers/infiniband/hw/mlx4/mad.c
@@ -39,6 +39,8 @@
39#include <linux/mlx4/cmd.h> 39#include <linux/mlx4/cmd.h>
40#include <linux/gfp.h> 40#include <linux/gfp.h>
41#include <rdma/ib_pma.h> 41#include <rdma/ib_pma.h>
42#include <linux/ip.h>
43#include <net/ipv6.h>
42 44
43#include <linux/mlx4/driver.h> 45#include <linux/mlx4/driver.h>
44#include "mlx4_ib.h" 46#include "mlx4_ib.h"
@@ -480,6 +482,23 @@ static int find_slave_port_pkey_ix(struct mlx4_ib_dev *dev, int slave,
480 return -EINVAL; 482 return -EINVAL;
481} 483}
482 484
485static int get_gids_from_l3_hdr(struct ib_grh *grh, union ib_gid *sgid,
486 union ib_gid *dgid)
487{
488 int version = ib_get_rdma_header_version((const union rdma_network_hdr *)grh);
489 enum rdma_network_type net_type;
490
491 if (version == 4)
492 net_type = RDMA_NETWORK_IPV4;
493 else if (version == 6)
494 net_type = RDMA_NETWORK_IPV6;
495 else
496 return -EINVAL;
497
498 return ib_get_gids_from_rdma_hdr((union rdma_network_hdr *)grh, net_type,
499 sgid, dgid);
500}
501
483int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port, 502int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port,
484 enum ib_qp_type dest_qpt, struct ib_wc *wc, 503 enum ib_qp_type dest_qpt, struct ib_wc *wc,
485 struct ib_grh *grh, struct ib_mad *mad) 504 struct ib_grh *grh, struct ib_mad *mad)
@@ -538,7 +557,10 @@ int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port,
538 memset(&attr, 0, sizeof attr); 557 memset(&attr, 0, sizeof attr);
539 attr.port_num = port; 558 attr.port_num = port;
540 if (is_eth) { 559 if (is_eth) {
541 memcpy(&attr.grh.dgid.raw[0], &grh->dgid.raw[0], 16); 560 union ib_gid sgid;
561
562 if (get_gids_from_l3_hdr(grh, &sgid, &attr.grh.dgid))
563 return -EINVAL;
542 attr.ah_flags = IB_AH_GRH; 564 attr.ah_flags = IB_AH_GRH;
543 } 565 }
544 ah = ib_create_ah(tun_ctx->pd, &attr); 566 ah = ib_create_ah(tun_ctx->pd, &attr);
@@ -651,6 +673,11 @@ static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port,
651 is_eth = 1; 673 is_eth = 1;
652 674
653 if (is_eth) { 675 if (is_eth) {
676 union ib_gid dgid;
677 union ib_gid sgid;
678
679 if (get_gids_from_l3_hdr(grh, &sgid, &dgid))
680 return -EINVAL;
654 if (!(wc->wc_flags & IB_WC_GRH)) { 681 if (!(wc->wc_flags & IB_WC_GRH)) {
655 mlx4_ib_warn(ibdev, "RoCE grh not present.\n"); 682 mlx4_ib_warn(ibdev, "RoCE grh not present.\n");
656 return -EINVAL; 683 return -EINVAL;
@@ -659,10 +686,10 @@ static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port,
659 mlx4_ib_warn(ibdev, "RoCE mgmt class is not CM\n"); 686 mlx4_ib_warn(ibdev, "RoCE mgmt class is not CM\n");
660 return -EINVAL; 687 return -EINVAL;
661 } 688 }
662 err = mlx4_get_slave_from_roce_gid(dev->dev, port, grh->dgid.raw, &slave); 689 err = mlx4_get_slave_from_roce_gid(dev->dev, port, dgid.raw, &slave);
663 if (err && mlx4_is_mf_bonded(dev->dev)) { 690 if (err && mlx4_is_mf_bonded(dev->dev)) {
664 other_port = (port == 1) ? 2 : 1; 691 other_port = (port == 1) ? 2 : 1;
665 err = mlx4_get_slave_from_roce_gid(dev->dev, other_port, grh->dgid.raw, &slave); 692 err = mlx4_get_slave_from_roce_gid(dev->dev, other_port, dgid.raw, &slave);
666 if (!err) { 693 if (!err) {
667 port = other_port; 694 port = other_port;
668 pr_debug("resolved slave %d from gid %pI6 wire port %d other %d\n", 695 pr_debug("resolved slave %d from gid %pI6 wire port %d other %d\n",
@@ -702,10 +729,18 @@ static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port,
702 729
703 /* If a grh is present, we demux according to it */ 730 /* If a grh is present, we demux according to it */
704 if (wc->wc_flags & IB_WC_GRH) { 731 if (wc->wc_flags & IB_WC_GRH) {
705 slave = mlx4_ib_find_real_gid(ibdev, port, grh->dgid.global.interface_id); 732 if (grh->dgid.global.interface_id ==
706 if (slave < 0) { 733 cpu_to_be64(IB_SA_WELL_KNOWN_GUID) &&
707 mlx4_ib_warn(ibdev, "failed matching grh\n"); 734 grh->dgid.global.subnet_prefix == cpu_to_be64(
708 return -ENOENT; 735 atomic64_read(&dev->sriov.demux[port - 1].subnet_prefix))) {
736 slave = 0;
737 } else {
738 slave = mlx4_ib_find_real_gid(ibdev, port,
739 grh->dgid.global.interface_id);
740 if (slave < 0) {
741 mlx4_ib_warn(ibdev, "failed matching grh\n");
742 return -ENOENT;
743 }
709 } 744 }
710 } 745 }
711 /* Class-specific handling */ 746 /* Class-specific handling */
@@ -1102,10 +1137,8 @@ static void handle_slaves_guid_change(struct mlx4_ib_dev *dev, u8 port_num,
1102 1137
1103 in_mad = kmalloc(sizeof *in_mad, GFP_KERNEL); 1138 in_mad = kmalloc(sizeof *in_mad, GFP_KERNEL);
1104 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 1139 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
1105 if (!in_mad || !out_mad) { 1140 if (!in_mad || !out_mad)
1106 mlx4_ib_warn(&dev->ib_dev, "failed to allocate memory for guid info mads\n");
1107 goto out; 1141 goto out;
1108 }
1109 1142
1110 guid_tbl_blk_num *= 4; 1143 guid_tbl_blk_num *= 4;
1111 1144
@@ -1916,11 +1949,8 @@ static int alloc_pv_object(struct mlx4_ib_dev *dev, int slave, int port,
1916 1949
1917 *ret_ctx = NULL; 1950 *ret_ctx = NULL;
1918 ctx = kzalloc(sizeof (struct mlx4_ib_demux_pv_ctx), GFP_KERNEL); 1951 ctx = kzalloc(sizeof (struct mlx4_ib_demux_pv_ctx), GFP_KERNEL);
1919 if (!ctx) { 1952 if (!ctx)
1920 pr_err("failed allocating pv resource context "
1921 "for port %d, slave %d\n", port, slave);
1922 return -ENOMEM; 1953 return -ENOMEM;
1923 }
1924 1954
1925 ctx->ib_dev = &dev->ib_dev; 1955 ctx->ib_dev = &dev->ib_dev;
1926 ctx->port = port; 1956 ctx->port = port;
diff --git a/drivers/infiniband/hw/mlx4/main.c b/drivers/infiniband/hw/mlx4/main.c
index b597e8227591..c8413fc120e6 100644
--- a/drivers/infiniband/hw/mlx4/main.c
+++ b/drivers/infiniband/hw/mlx4/main.c
@@ -430,7 +430,7 @@ static int mlx4_ib_query_device(struct ib_device *ibdev,
430 struct mlx4_ib_dev *dev = to_mdev(ibdev); 430 struct mlx4_ib_dev *dev = to_mdev(ibdev);
431 struct ib_smp *in_mad = NULL; 431 struct ib_smp *in_mad = NULL;
432 struct ib_smp *out_mad = NULL; 432 struct ib_smp *out_mad = NULL;
433 int err = -ENOMEM; 433 int err;
434 int have_ib_ports; 434 int have_ib_ports;
435 struct mlx4_uverbs_ex_query_device cmd; 435 struct mlx4_uverbs_ex_query_device cmd;
436 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0}; 436 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
@@ -455,6 +455,7 @@ static int mlx4_ib_query_device(struct ib_device *ibdev,
455 sizeof(resp.response_length); 455 sizeof(resp.response_length);
456 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL); 456 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
457 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 457 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
458 err = -ENOMEM;
458 if (!in_mad || !out_mad) 459 if (!in_mad || !out_mad)
459 goto out; 460 goto out;
460 461
@@ -547,6 +548,7 @@ static int mlx4_ib_query_device(struct ib_device *ibdev,
547 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps; 548 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
548 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL; 549 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
549 props->timestamp_mask = 0xFFFFFFFFFFFFULL; 550 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
551 props->max_ah = INT_MAX;
550 552
551 if (!mlx4_is_slave(dev->dev)) 553 if (!mlx4_is_slave(dev->dev))
552 err = mlx4_get_internal_clock_params(dev->dev, &clock_params); 554 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
@@ -697,9 +699,11 @@ static int eth_link_query_port(struct ib_device *ibdev, u8 port,
697 if (err) 699 if (err)
698 goto out; 700 goto out;
699 701
700 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ? 702 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
701 IB_WIDTH_4X : IB_WIDTH_1X; 703 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
702 props->active_speed = IB_SPEED_QDR; 704 IB_WIDTH_4X : IB_WIDTH_1X;
705 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
706 IB_SPEED_FDR : IB_SPEED_QDR;
703 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS; 707 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
704 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port]; 708 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
705 props->max_msg_sz = mdev->dev->caps.max_msg_sz; 709 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
@@ -2814,20 +2818,22 @@ static void *mlx4_ib_add(struct mlx4_dev *dev)
2814 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) * 2818 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
2815 sizeof(long), 2819 sizeof(long),
2816 GFP_KERNEL); 2820 GFP_KERNEL);
2817 if (!ibdev->ib_uc_qpns_bitmap) { 2821 if (!ibdev->ib_uc_qpns_bitmap)
2818 dev_err(&dev->persist->pdev->dev,
2819 "bit map alloc failed\n");
2820 goto err_steer_qp_release; 2822 goto err_steer_qp_release;
2821 }
2822 2823
2823 bitmap_zero(ibdev->ib_uc_qpns_bitmap, ibdev->steer_qpn_count); 2824 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
2824 2825 bitmap_zero(ibdev->ib_uc_qpns_bitmap,
2825 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE( 2826 ibdev->steer_qpn_count);
2826 dev, ibdev->steer_qpn_base, 2827 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2827 ibdev->steer_qpn_base + 2828 dev, ibdev->steer_qpn_base,
2828 ibdev->steer_qpn_count - 1); 2829 ibdev->steer_qpn_base +
2829 if (err) 2830 ibdev->steer_qpn_count - 1);
2830 goto err_steer_free_bitmap; 2831 if (err)
2832 goto err_steer_free_bitmap;
2833 } else {
2834 bitmap_fill(ibdev->ib_uc_qpns_bitmap,
2835 ibdev->steer_qpn_count);
2836 }
2831 } 2837 }
2832 2838
2833 for (j = 1; j <= ibdev->dev->caps.num_ports; j++) 2839 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
@@ -3055,15 +3061,12 @@ static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
3055 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 3061 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
3056 3062
3057 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC); 3063 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
3058 if (!dm) { 3064 if (!dm)
3059 pr_err("failed to allocate memory for tunneling qp update\n");
3060 return; 3065 return;
3061 }
3062 3066
3063 for (i = 0; i < ports; i++) { 3067 for (i = 0; i < ports; i++) {
3064 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC); 3068 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
3065 if (!dm[i]) { 3069 if (!dm[i]) {
3066 pr_err("failed to allocate memory for tunneling qp update work struct\n");
3067 while (--i >= 0) 3070 while (--i >= 0)
3068 kfree(dm[i]); 3071 kfree(dm[i]);
3069 goto out; 3072 goto out;
@@ -3223,8 +3226,6 @@ void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
3223 ew->port = port; 3226 ew->port = port;
3224 ew->ib_dev = ibdev; 3227 ew->ib_dev = ibdev;
3225 queue_work(wq, &ew->work); 3228 queue_work(wq, &ew->work);
3226 } else {
3227 pr_err("failed to allocate memory for sl2vl update work\n");
3228 } 3229 }
3229} 3230}
3230 3231
@@ -3284,10 +3285,8 @@ static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
3284 3285
3285 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE: 3286 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
3286 ew = kmalloc(sizeof *ew, GFP_ATOMIC); 3287 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
3287 if (!ew) { 3288 if (!ew)
3288 pr_err("failed to allocate memory for events work\n");
3289 break; 3289 break;
3290 }
3291 3290
3292 INIT_WORK(&ew->work, handle_port_mgmt_change_event); 3291 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
3293 memcpy(&ew->ib_eqe, eqe, sizeof *eqe); 3292 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
diff --git a/drivers/infiniband/hw/mlx4/mcg.c b/drivers/infiniband/hw/mlx4/mcg.c
index a21d37f02f35..e010fe459e67 100644
--- a/drivers/infiniband/hw/mlx4/mcg.c
+++ b/drivers/infiniband/hw/mlx4/mcg.c
@@ -1142,7 +1142,6 @@ void mlx4_ib_mcg_port_cleanup(struct mlx4_ib_demux_ctx *ctx, int destroy_wq)
1142 work = kmalloc(sizeof *work, GFP_KERNEL); 1142 work = kmalloc(sizeof *work, GFP_KERNEL);
1143 if (!work) { 1143 if (!work) {
1144 ctx->flushing = 0; 1144 ctx->flushing = 0;
1145 mcg_warn("failed allocating work for cleanup\n");
1146 return; 1145 return;
1147 } 1146 }
1148 1147
@@ -1202,10 +1201,8 @@ static int push_deleteing_req(struct mcast_group *group, int slave)
1202 return 0; 1201 return 0;
1203 1202
1204 req = kzalloc(sizeof *req, GFP_KERNEL); 1203 req = kzalloc(sizeof *req, GFP_KERNEL);
1205 if (!req) { 1204 if (!req)
1206 mcg_warn_group(group, "failed allocation - may leave stall groups\n");
1207 return -ENOMEM; 1205 return -ENOMEM;
1208 }
1209 1206
1210 if (!list_empty(&group->func[slave].pending)) { 1207 if (!list_empty(&group->func[slave].pending)) {
1211 pend_req = list_entry(group->func[slave].pending.prev, struct mcast_req, group_list); 1208 pend_req = list_entry(group->func[slave].pending.prev, struct mcast_req, group_list);
diff --git a/drivers/infiniband/hw/mlx4/mlx4_ib.h b/drivers/infiniband/hw/mlx4/mlx4_ib.h
index 35141f451e5c..7f3d976d81ed 100644
--- a/drivers/infiniband/hw/mlx4/mlx4_ib.h
+++ b/drivers/infiniband/hw/mlx4/mlx4_ib.h
@@ -742,7 +742,8 @@ int mlx4_ib_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
742void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq); 742void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq);
743void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq); 743void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq);
744 744
745struct ib_ah *mlx4_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); 745struct ib_ah *mlx4_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr,
746 struct ib_udata *udata);
746int mlx4_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 747int mlx4_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
747int mlx4_ib_destroy_ah(struct ib_ah *ah); 748int mlx4_ib_destroy_ah(struct ib_ah *ah);
748 749
diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c
index 570bc866b1d6..c068add8838b 100644
--- a/drivers/infiniband/hw/mlx4/qp.c
+++ b/drivers/infiniband/hw/mlx4/qp.c
@@ -644,7 +644,7 @@ static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
644 int qpn; 644 int qpn;
645 int err; 645 int err;
646 struct ib_qp_cap backup_cap; 646 struct ib_qp_cap backup_cap;
647 struct mlx4_ib_sqp *sqp; 647 struct mlx4_ib_sqp *sqp = NULL;
648 struct mlx4_ib_qp *qp; 648 struct mlx4_ib_qp *qp;
649 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 649 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
650 struct mlx4_ib_cq *mcq; 650 struct mlx4_ib_cq *mcq;
@@ -933,7 +933,9 @@ err_db:
933 mlx4_db_free(dev->dev, &qp->db); 933 mlx4_db_free(dev->dev, &qp->db);
934 934
935err: 935err:
936 if (!*caller_qp) 936 if (sqp)
937 kfree(sqp);
938 else if (!*caller_qp)
937 kfree(qp); 939 kfree(qp);
938 return err; 940 return err;
939} 941}
@@ -1280,7 +1282,8 @@ static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
1280 if (is_qp0(dev, mqp)) 1282 if (is_qp0(dev, mqp))
1281 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1283 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1282 1284
1283 if (dev->qp1_proxy[mqp->port - 1] == mqp) { 1285 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1286 dev->qp1_proxy[mqp->port - 1] == mqp) {
1284 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]); 1287 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1285 dev->qp1_proxy[mqp->port - 1] = NULL; 1288 dev->qp1_proxy[mqp->port - 1] = NULL;
1286 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]); 1289 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
@@ -1764,14 +1767,14 @@ static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1764 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 : 1767 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1765 attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 1768 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1766 union ib_gid gid; 1769 union ib_gid gid;
1767 struct ib_gid_attr gid_attr; 1770 struct ib_gid_attr gid_attr = {.gid_type = IB_GID_TYPE_IB};
1768 u16 vlan = 0xffff; 1771 u16 vlan = 0xffff;
1769 u8 smac[ETH_ALEN]; 1772 u8 smac[ETH_ALEN];
1770 int status = 0; 1773 int status = 0;
1771 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, port_num) && 1774 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1772 attr->ah_attr.ah_flags & IB_AH_GRH; 1775 attr->ah_attr.ah_flags & IB_AH_GRH;
1773 1776
1774 if (is_eth) { 1777 if (is_eth && attr->ah_attr.ah_flags & IB_AH_GRH) {
1775 int index = attr->ah_attr.grh.sgid_index; 1778 int index = attr->ah_attr.grh.sgid_index;
1776 1779
1777 status = ib_get_cached_gid(ibqp->device, port_num, 1780 status = ib_get_cached_gid(ibqp->device, port_num,
diff --git a/drivers/infiniband/hw/mlx5/ah.c b/drivers/infiniband/hw/mlx5/ah.c
index 745efa4cfc71..d090e96f6f01 100644
--- a/drivers/infiniband/hw/mlx5/ah.c
+++ b/drivers/infiniband/hw/mlx5/ah.c
@@ -64,7 +64,9 @@ static struct ib_ah *create_ib_ah(struct mlx5_ib_dev *dev,
64 return &ah->ibah; 64 return &ah->ibah;
65} 65}
66 66
67struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr) 67struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr,
68 struct ib_udata *udata)
69
68{ 70{
69 struct mlx5_ib_ah *ah; 71 struct mlx5_ib_ah *ah;
70 struct mlx5_ib_dev *dev = to_mdev(pd->device); 72 struct mlx5_ib_dev *dev = to_mdev(pd->device);
@@ -75,6 +77,27 @@ struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr)
75 if (ll == IB_LINK_LAYER_ETHERNET && !(ah_attr->ah_flags & IB_AH_GRH)) 77 if (ll == IB_LINK_LAYER_ETHERNET && !(ah_attr->ah_flags & IB_AH_GRH))
76 return ERR_PTR(-EINVAL); 78 return ERR_PTR(-EINVAL);
77 79
80 if (ll == IB_LINK_LAYER_ETHERNET && udata) {
81 int err;
82 struct mlx5_ib_create_ah_resp resp = {};
83 u32 min_resp_len = offsetof(typeof(resp), dmac) +
84 sizeof(resp.dmac);
85
86 if (udata->outlen < min_resp_len)
87 return ERR_PTR(-EINVAL);
88
89 resp.response_length = min_resp_len;
90
91 err = ib_resolve_eth_dmac(pd->device, ah_attr);
92 if (err)
93 return ERR_PTR(err);
94
95 memcpy(resp.dmac, ah_attr->dmac, ETH_ALEN);
96 err = ib_copy_to_udata(udata, &resp, resp.response_length);
97 if (err)
98 return ERR_PTR(err);
99 }
100
78 ah = kzalloc(sizeof(*ah), GFP_ATOMIC); 101 ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
79 if (!ah) 102 if (!ah)
80 return ERR_PTR(-ENOMEM); 103 return ERR_PTR(-ENOMEM);
diff --git a/drivers/infiniband/hw/mlx5/cq.c b/drivers/infiniband/hw/mlx5/cq.c
index fcd04b881ec1..b3ef47c3ab73 100644
--- a/drivers/infiniband/hw/mlx5/cq.c
+++ b/drivers/infiniband/hw/mlx5/cq.c
@@ -731,7 +731,7 @@ static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
731 int entries, u32 **cqb, 731 int entries, u32 **cqb,
732 int *cqe_size, int *index, int *inlen) 732 int *cqe_size, int *index, int *inlen)
733{ 733{
734 struct mlx5_ib_create_cq ucmd; 734 struct mlx5_ib_create_cq ucmd = {};
735 size_t ucmdlen; 735 size_t ucmdlen;
736 int page_shift; 736 int page_shift;
737 __be64 *pas; 737 __be64 *pas;
@@ -770,7 +770,7 @@ static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
770 if (err) 770 if (err)
771 goto err_umem; 771 goto err_umem;
772 772
773 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, &npages, &page_shift, 773 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift,
774 &ncont, NULL); 774 &ncont, NULL);
775 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n", 775 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
776 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont); 776 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
@@ -792,8 +792,36 @@ static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
792 792
793 *index = to_mucontext(context)->uuari.uars[0].index; 793 *index = to_mucontext(context)->uuari.uars[0].index;
794 794
795 if (ucmd.cqe_comp_en == 1) {
796 if (unlikely((*cqe_size != 64) ||
797 !MLX5_CAP_GEN(dev->mdev, cqe_compression))) {
798 err = -EOPNOTSUPP;
799 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
800 *cqe_size);
801 goto err_cqb;
802 }
803
804 if (unlikely(!ucmd.cqe_comp_res_format ||
805 !(ucmd.cqe_comp_res_format <
806 MLX5_IB_CQE_RES_RESERVED) ||
807 (ucmd.cqe_comp_res_format &
808 (ucmd.cqe_comp_res_format - 1)))) {
809 err = -EOPNOTSUPP;
810 mlx5_ib_warn(dev, "CQE compression res format %d is not supported!\n",
811 ucmd.cqe_comp_res_format);
812 goto err_cqb;
813 }
814
815 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
816 MLX5_SET(cqc, cqc, mini_cqe_res_format,
817 ilog2(ucmd.cqe_comp_res_format));
818 }
819
795 return 0; 820 return 0;
796 821
822err_cqb:
823 kfree(cqb);
824
797err_db: 825err_db:
798 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db); 826 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
799 827
@@ -1124,7 +1152,7 @@ static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1124 return err; 1152 return err;
1125 } 1153 }
1126 1154
1127 mlx5_ib_cont_pages(umem, ucmd.buf_addr, &npages, page_shift, 1155 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift,
1128 npas, NULL); 1156 npas, NULL);
1129 1157
1130 cq->resize_umem = umem; 1158 cq->resize_umem = umem;
diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c
index 2be65ddf56ba..d566f6738833 100644
--- a/drivers/infiniband/hw/mlx5/main.c
+++ b/drivers/infiniband/hw/mlx5/main.c
@@ -127,7 +127,7 @@ static int mlx5_netdev_event(struct notifier_block *this,
127 127
128 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 128 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
129 && ibdev->ib_active) { 129 && ibdev->ib_active) {
130 struct ib_event ibev = {0}; 130 struct ib_event ibev = { };
131 131
132 ibev.device = &ibdev->ib_dev; 132 ibev.device = &ibdev->ib_dev;
133 ibev.event = (event == NETDEV_UP) ? 133 ibev.event = (event == NETDEV_UP) ?
@@ -496,6 +496,7 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
496 struct mlx5_ib_dev *dev = to_mdev(ibdev); 496 struct mlx5_ib_dev *dev = to_mdev(ibdev);
497 struct mlx5_core_dev *mdev = dev->mdev; 497 struct mlx5_core_dev *mdev = dev->mdev;
498 int err = -ENOMEM; 498 int err = -ENOMEM;
499 int max_sq_desc;
499 int max_rq_sg; 500 int max_rq_sg;
500 int max_sq_sg; 501 int max_sq_sg;
501 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 502 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
@@ -618,9 +619,10 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
618 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 619 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
619 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 620 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
620 sizeof(struct mlx5_wqe_data_seg); 621 sizeof(struct mlx5_wqe_data_seg);
621 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) - 622 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
622 sizeof(struct mlx5_wqe_ctrl_seg)) / 623 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
623 sizeof(struct mlx5_wqe_data_seg); 624 sizeof(struct mlx5_wqe_raddr_seg)) /
625 sizeof(struct mlx5_wqe_data_seg);
624 props->max_sge = min(max_rq_sg, max_sq_sg); 626 props->max_sge = min(max_rq_sg, max_sq_sg);
625 props->max_sge_rd = MLX5_MAX_SGE_RD; 627 props->max_sge_rd = MLX5_MAX_SGE_RD;
626 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 628 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
@@ -643,6 +645,7 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
643 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 645 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
644 props->max_mcast_grp; 646 props->max_mcast_grp;
645 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 647 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
648 props->max_ah = INT_MAX;
646 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 649 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
647 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 650 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
648 651
@@ -669,6 +672,40 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
669 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 672 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
670 } 673 }
671 674
675 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
676 uhw->outlen)) {
677 resp.mlx5_ib_support_multi_pkt_send_wqes =
678 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
679 resp.response_length +=
680 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
681 }
682
683 if (field_avail(typeof(resp), reserved, uhw->outlen))
684 resp.response_length += sizeof(resp.reserved);
685
686 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
687 resp.cqe_comp_caps.max_num =
688 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
689 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
690 resp.cqe_comp_caps.supported_format =
691 MLX5_IB_CQE_RES_FORMAT_HASH |
692 MLX5_IB_CQE_RES_FORMAT_CSUM;
693 resp.response_length += sizeof(resp.cqe_comp_caps);
694 }
695
696 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
697 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
698 MLX5_CAP_GEN(mdev, qos)) {
699 resp.packet_pacing_caps.qp_rate_limit_max =
700 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
701 resp.packet_pacing_caps.qp_rate_limit_min =
702 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
703 resp.packet_pacing_caps.supported_qpts |=
704 1 << IB_QPT_RAW_PACKET;
705 }
706 resp.response_length += sizeof(resp.packet_pacing_caps);
707 }
708
672 if (uhw->outlen) { 709 if (uhw->outlen) {
673 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 710 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
674 711
@@ -1093,7 +1130,8 @@ static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1093 resp.response_length += sizeof(resp.cqe_version); 1130 resp.response_length += sizeof(resp.cqe_version);
1094 1131
1095 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1132 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1096 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE; 1133 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1134 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1097 resp.response_length += sizeof(resp.cmds_supp_uhw); 1135 resp.response_length += sizeof(resp.cmds_supp_uhw);
1098 } 1136 }
1099 1137
@@ -1502,6 +1540,22 @@ static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1502 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1540 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1503} 1541}
1504 1542
1543static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1544 bool inner)
1545{
1546 if (inner) {
1547 MLX5_SET(fte_match_set_misc,
1548 misc_c, inner_ipv6_flow_label, mask);
1549 MLX5_SET(fte_match_set_misc,
1550 misc_v, inner_ipv6_flow_label, val);
1551 } else {
1552 MLX5_SET(fte_match_set_misc,
1553 misc_c, outer_ipv6_flow_label, mask);
1554 MLX5_SET(fte_match_set_misc,
1555 misc_v, outer_ipv6_flow_label, val);
1556 }
1557}
1558
1505static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1559static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1506{ 1560{
1507 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1561 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
@@ -1515,6 +1569,7 @@ static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1515#define LAST_IPV4_FIELD tos 1569#define LAST_IPV4_FIELD tos
1516#define LAST_IPV6_FIELD traffic_class 1570#define LAST_IPV6_FIELD traffic_class
1517#define LAST_TCP_UDP_FIELD src_port 1571#define LAST_TCP_UDP_FIELD src_port
1572#define LAST_TUNNEL_FIELD tunnel_id
1518 1573
1519/* Field is the last supported field */ 1574/* Field is the last supported field */
1520#define FIELDS_NOT_SUPPORTED(filter, field)\ 1575#define FIELDS_NOT_SUPPORTED(filter, field)\
@@ -1527,155 +1582,164 @@ static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1527static int parse_flow_attr(u32 *match_c, u32 *match_v, 1582static int parse_flow_attr(u32 *match_c, u32 *match_v,
1528 const union ib_flow_spec *ib_spec) 1583 const union ib_flow_spec *ib_spec)
1529{ 1584{
1530 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1531 outer_headers);
1532 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1533 outer_headers);
1534 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1585 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1535 misc_parameters); 1586 misc_parameters);
1536 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1587 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1537 misc_parameters); 1588 misc_parameters);
1589 void *headers_c;
1590 void *headers_v;
1591
1592 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1593 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1594 inner_headers);
1595 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1596 inner_headers);
1597 } else {
1598 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1599 outer_headers);
1600 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1601 outer_headers);
1602 }
1538 1603
1539 switch (ib_spec->type) { 1604 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1540 case IB_FLOW_SPEC_ETH: 1605 case IB_FLOW_SPEC_ETH:
1541 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1606 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1542 return -ENOTSUPP; 1607 return -ENOTSUPP;
1543 1608
1544 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1609 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1545 dmac_47_16), 1610 dmac_47_16),
1546 ib_spec->eth.mask.dst_mac); 1611 ib_spec->eth.mask.dst_mac);
1547 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1612 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1548 dmac_47_16), 1613 dmac_47_16),
1549 ib_spec->eth.val.dst_mac); 1614 ib_spec->eth.val.dst_mac);
1550 1615
1551 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1616 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1552 smac_47_16), 1617 smac_47_16),
1553 ib_spec->eth.mask.src_mac); 1618 ib_spec->eth.mask.src_mac);
1554 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1619 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1555 smac_47_16), 1620 smac_47_16),
1556 ib_spec->eth.val.src_mac); 1621 ib_spec->eth.val.src_mac);
1557 1622
1558 if (ib_spec->eth.mask.vlan_tag) { 1623 if (ib_spec->eth.mask.vlan_tag) {
1559 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1624 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1560 vlan_tag, 1); 1625 vlan_tag, 1);
1561 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1626 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1562 vlan_tag, 1); 1627 vlan_tag, 1);
1563 1628
1564 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1629 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1565 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1630 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1566 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1631 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1567 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1632 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1568 1633
1569 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1634 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1570 first_cfi, 1635 first_cfi,
1571 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1636 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1572 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1637 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1573 first_cfi, 1638 first_cfi,
1574 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1639 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1575 1640
1576 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1641 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1577 first_prio, 1642 first_prio,
1578 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1643 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1579 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1644 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1580 first_prio, 1645 first_prio,
1581 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1646 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1582 } 1647 }
1583 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1648 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1584 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1649 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1585 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1650 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1586 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1651 ethertype, ntohs(ib_spec->eth.val.ether_type));
1587 break; 1652 break;
1588 case IB_FLOW_SPEC_IPV4: 1653 case IB_FLOW_SPEC_IPV4:
1589 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1654 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1590 return -ENOTSUPP; 1655 return -ENOTSUPP;
1591 1656
1592 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1657 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1593 ethertype, 0xffff); 1658 ethertype, 0xffff);
1594 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1659 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1595 ethertype, ETH_P_IP); 1660 ethertype, ETH_P_IP);
1596 1661
1597 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1662 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1598 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1663 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1599 &ib_spec->ipv4.mask.src_ip, 1664 &ib_spec->ipv4.mask.src_ip,
1600 sizeof(ib_spec->ipv4.mask.src_ip)); 1665 sizeof(ib_spec->ipv4.mask.src_ip));
1601 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1666 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1602 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1667 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1603 &ib_spec->ipv4.val.src_ip, 1668 &ib_spec->ipv4.val.src_ip,
1604 sizeof(ib_spec->ipv4.val.src_ip)); 1669 sizeof(ib_spec->ipv4.val.src_ip));
1605 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1670 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1606 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1671 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1607 &ib_spec->ipv4.mask.dst_ip, 1672 &ib_spec->ipv4.mask.dst_ip,
1608 sizeof(ib_spec->ipv4.mask.dst_ip)); 1673 sizeof(ib_spec->ipv4.mask.dst_ip));
1609 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1674 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1610 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1675 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1611 &ib_spec->ipv4.val.dst_ip, 1676 &ib_spec->ipv4.val.dst_ip,
1612 sizeof(ib_spec->ipv4.val.dst_ip)); 1677 sizeof(ib_spec->ipv4.val.dst_ip));
1613 1678
1614 set_tos(outer_headers_c, outer_headers_v, 1679 set_tos(headers_c, headers_v,
1615 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1680 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1616 1681
1617 set_proto(outer_headers_c, outer_headers_v, 1682 set_proto(headers_c, headers_v,
1618 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1683 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1619 break; 1684 break;
1620 case IB_FLOW_SPEC_IPV6: 1685 case IB_FLOW_SPEC_IPV6:
1621 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1686 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1622 return -ENOTSUPP; 1687 return -ENOTSUPP;
1623 1688
1624 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1689 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1625 ethertype, 0xffff); 1690 ethertype, 0xffff);
1626 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1691 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1627 ethertype, ETH_P_IPV6); 1692 ethertype, ETH_P_IPV6);
1628 1693
1629 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1694 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1630 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1695 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1631 &ib_spec->ipv6.mask.src_ip, 1696 &ib_spec->ipv6.mask.src_ip,
1632 sizeof(ib_spec->ipv6.mask.src_ip)); 1697 sizeof(ib_spec->ipv6.mask.src_ip));
1633 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1698 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1634 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1699 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1635 &ib_spec->ipv6.val.src_ip, 1700 &ib_spec->ipv6.val.src_ip,
1636 sizeof(ib_spec->ipv6.val.src_ip)); 1701 sizeof(ib_spec->ipv6.val.src_ip));
1637 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1702 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1638 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1703 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1639 &ib_spec->ipv6.mask.dst_ip, 1704 &ib_spec->ipv6.mask.dst_ip,
1640 sizeof(ib_spec->ipv6.mask.dst_ip)); 1705 sizeof(ib_spec->ipv6.mask.dst_ip));
1641 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1706 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1642 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1707 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1643 &ib_spec->ipv6.val.dst_ip, 1708 &ib_spec->ipv6.val.dst_ip,
1644 sizeof(ib_spec->ipv6.val.dst_ip)); 1709 sizeof(ib_spec->ipv6.val.dst_ip));
1645 1710
1646 set_tos(outer_headers_c, outer_headers_v, 1711 set_tos(headers_c, headers_v,
1647 ib_spec->ipv6.mask.traffic_class, 1712 ib_spec->ipv6.mask.traffic_class,
1648 ib_spec->ipv6.val.traffic_class); 1713 ib_spec->ipv6.val.traffic_class);
1649 1714
1650 set_proto(outer_headers_c, outer_headers_v, 1715 set_proto(headers_c, headers_v,
1651 ib_spec->ipv6.mask.next_hdr, 1716 ib_spec->ipv6.mask.next_hdr,
1652 ib_spec->ipv6.val.next_hdr); 1717 ib_spec->ipv6.val.next_hdr);
1653 1718
1654 MLX5_SET(fte_match_set_misc, misc_params_c, 1719 set_flow_label(misc_params_c, misc_params_v,
1655 outer_ipv6_flow_label, 1720 ntohl(ib_spec->ipv6.mask.flow_label),
1656 ntohl(ib_spec->ipv6.mask.flow_label)); 1721 ntohl(ib_spec->ipv6.val.flow_label),
1657 MLX5_SET(fte_match_set_misc, misc_params_v, 1722 ib_spec->type & IB_FLOW_SPEC_INNER);
1658 outer_ipv6_flow_label, 1723
1659 ntohl(ib_spec->ipv6.val.flow_label));
1660 break; 1724 break;
1661 case IB_FLOW_SPEC_TCP: 1725 case IB_FLOW_SPEC_TCP:
1662 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1726 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1663 LAST_TCP_UDP_FIELD)) 1727 LAST_TCP_UDP_FIELD))
1664 return -ENOTSUPP; 1728 return -ENOTSUPP;
1665 1729
1666 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1730 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1667 0xff); 1731 0xff);
1668 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1732 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1669 IPPROTO_TCP); 1733 IPPROTO_TCP);
1670 1734
1671 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1735 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
1672 ntohs(ib_spec->tcp_udp.mask.src_port)); 1736 ntohs(ib_spec->tcp_udp.mask.src_port));
1673 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1737 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
1674 ntohs(ib_spec->tcp_udp.val.src_port)); 1738 ntohs(ib_spec->tcp_udp.val.src_port));
1675 1739
1676 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1740 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
1677 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1741 ntohs(ib_spec->tcp_udp.mask.dst_port));
1678 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1742 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
1679 ntohs(ib_spec->tcp_udp.val.dst_port)); 1743 ntohs(ib_spec->tcp_udp.val.dst_port));
1680 break; 1744 break;
1681 case IB_FLOW_SPEC_UDP: 1745 case IB_FLOW_SPEC_UDP:
@@ -1683,21 +1747,31 @@ static int parse_flow_attr(u32 *match_c, u32 *match_v,
1683 LAST_TCP_UDP_FIELD)) 1747 LAST_TCP_UDP_FIELD))
1684 return -ENOTSUPP; 1748 return -ENOTSUPP;
1685 1749
1686 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1750 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1687 0xff); 1751 0xff);
1688 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1752 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1689 IPPROTO_UDP); 1753 IPPROTO_UDP);
1690 1754
1691 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1755 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
1692 ntohs(ib_spec->tcp_udp.mask.src_port)); 1756 ntohs(ib_spec->tcp_udp.mask.src_port));
1693 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1757 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
1694 ntohs(ib_spec->tcp_udp.val.src_port)); 1758 ntohs(ib_spec->tcp_udp.val.src_port));
1695 1759
1696 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1760 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
1697 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1761 ntohs(ib_spec->tcp_udp.mask.dst_port));
1698 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1762 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1699 ntohs(ib_spec->tcp_udp.val.dst_port)); 1763 ntohs(ib_spec->tcp_udp.val.dst_port));
1700 break; 1764 break;
1765 case IB_FLOW_SPEC_VXLAN_TUNNEL:
1766 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
1767 LAST_TUNNEL_FIELD))
1768 return -ENOTSUPP;
1769
1770 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
1771 ntohl(ib_spec->tunnel.mask.tunnel_id));
1772 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
1773 ntohl(ib_spec->tunnel.val.tunnel_id));
1774 break;
1701 default: 1775 default:
1702 return -EINVAL; 1776 return -EINVAL;
1703 } 1777 }
@@ -2721,6 +2795,8 @@ static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2721 struct ib_port_immutable *immutable) 2795 struct ib_port_immutable *immutable)
2722{ 2796{
2723 struct ib_port_attr attr; 2797 struct ib_port_attr attr;
2798 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2799 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
2724 int err; 2800 int err;
2725 2801
2726 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2802 err = mlx5_ib_query_port(ibdev, port_num, &attr);
@@ -2730,7 +2806,8 @@ static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2730 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2806 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2731 immutable->gid_tbl_len = attr.gid_tbl_len; 2807 immutable->gid_tbl_len = attr.gid_tbl_len;
2732 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2808 immutable->core_cap_flags = get_core_cap_flags(ibdev);
2733 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2809 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
2810 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2734 2811
2735 return 0; 2812 return 0;
2736} 2813}
@@ -2744,7 +2821,7 @@ static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2744 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 2821 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2745} 2822}
2746 2823
2747static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev) 2824static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
2748{ 2825{
2749 struct mlx5_core_dev *mdev = dev->mdev; 2826 struct mlx5_core_dev *mdev = dev->mdev;
2750 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 2827 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
@@ -2773,7 +2850,7 @@ err_destroy_vport_lag:
2773 return err; 2850 return err;
2774} 2851}
2775 2852
2776static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev) 2853static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
2777{ 2854{
2778 struct mlx5_core_dev *mdev = dev->mdev; 2855 struct mlx5_core_dev *mdev = dev->mdev;
2779 2856
@@ -2785,7 +2862,21 @@ static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2785 } 2862 }
2786} 2863}
2787 2864
2788static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev) 2865static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
2866{
2867 int err;
2868
2869 dev->roce.nb.notifier_call = mlx5_netdev_event;
2870 err = register_netdevice_notifier(&dev->roce.nb);
2871 if (err) {
2872 dev->roce.nb.notifier_call = NULL;
2873 return err;
2874 }
2875
2876 return 0;
2877}
2878
2879static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
2789{ 2880{
2790 if (dev->roce.nb.notifier_call) { 2881 if (dev->roce.nb.notifier_call) {
2791 unregister_netdevice_notifier(&dev->roce.nb); 2882 unregister_netdevice_notifier(&dev->roce.nb);
@@ -2793,39 +2884,40 @@ static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2793 } 2884 }
2794} 2885}
2795 2886
2796static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 2887static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
2797{ 2888{
2798 int err; 2889 int err;
2799 2890
2800 dev->roce.nb.notifier_call = mlx5_netdev_event; 2891 err = mlx5_add_netdev_notifier(dev);
2801 err = register_netdevice_notifier(&dev->roce.nb); 2892 if (err)
2802 if (err) {
2803 dev->roce.nb.notifier_call = NULL;
2804 return err; 2893 return err;
2805 }
2806 2894
2807 err = mlx5_nic_vport_enable_roce(dev->mdev); 2895 if (MLX5_CAP_GEN(dev->mdev, roce)) {
2808 if (err) 2896 err = mlx5_nic_vport_enable_roce(dev->mdev);
2809 goto err_unregister_netdevice_notifier; 2897 if (err)
2898 goto err_unregister_netdevice_notifier;
2899 }
2810 2900
2811 err = mlx5_roce_lag_init(dev); 2901 err = mlx5_eth_lag_init(dev);
2812 if (err) 2902 if (err)
2813 goto err_disable_roce; 2903 goto err_disable_roce;
2814 2904
2815 return 0; 2905 return 0;
2816 2906
2817err_disable_roce: 2907err_disable_roce:
2818 mlx5_nic_vport_disable_roce(dev->mdev); 2908 if (MLX5_CAP_GEN(dev->mdev, roce))
2909 mlx5_nic_vport_disable_roce(dev->mdev);
2819 2910
2820err_unregister_netdevice_notifier: 2911err_unregister_netdevice_notifier:
2821 mlx5_remove_roce_notifier(dev); 2912 mlx5_remove_netdev_notifier(dev);
2822 return err; 2913 return err;
2823} 2914}
2824 2915
2825static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 2916static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
2826{ 2917{
2827 mlx5_roce_lag_cleanup(dev); 2918 mlx5_eth_lag_cleanup(dev);
2828 mlx5_nic_vport_disable_roce(dev->mdev); 2919 if (MLX5_CAP_GEN(dev->mdev, roce))
2920 mlx5_nic_vport_disable_roce(dev->mdev);
2829} 2921}
2830 2922
2831static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 2923static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
@@ -2947,9 +3039,6 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2947 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3039 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2948 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3040 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2949 3041
2950 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2951 return NULL;
2952
2953 printk_once(KERN_INFO "%s", mlx5_version); 3042 printk_once(KERN_INFO "%s", mlx5_version);
2954 3043
2955 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3044 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
@@ -2995,6 +3084,8 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2995 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3084 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2996 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3085 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2997 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3086 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
3087 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3088 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
2998 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3089 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2999 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3090 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
3000 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3091 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
@@ -3017,7 +3108,8 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3017 dev->ib_dev.uverbs_ex_cmd_mask = 3108 dev->ib_dev.uverbs_ex_cmd_mask =
3018 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3109 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3019 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3110 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3020 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 3111 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3112 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
3021 3113
3022 dev->ib_dev.query_device = mlx5_ib_query_device; 3114 dev->ib_dev.query_device = mlx5_ib_query_device;
3023 dev->ib_dev.query_port = mlx5_ib_query_port; 3115 dev->ib_dev.query_port = mlx5_ib_query_port;
@@ -3128,14 +3220,14 @@ static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3128 spin_lock_init(&dev->reset_flow_resource_lock); 3220 spin_lock_init(&dev->reset_flow_resource_lock);
3129 3221
3130 if (ll == IB_LINK_LAYER_ETHERNET) { 3222 if (ll == IB_LINK_LAYER_ETHERNET) {
3131 err = mlx5_enable_roce(dev); 3223 err = mlx5_enable_eth(dev);
3132 if (err) 3224 if (err)
3133 goto err_free_port; 3225 goto err_free_port;
3134 } 3226 }
3135 3227
3136 err = create_dev_resources(&dev->devr); 3228 err = create_dev_resources(&dev->devr);
3137 if (err) 3229 if (err)
3138 goto err_disable_roce; 3230 goto err_disable_eth;
3139 3231
3140 err = mlx5_ib_odp_init_one(dev); 3232 err = mlx5_ib_odp_init_one(dev);
3141 if (err) 3233 if (err)
@@ -3179,10 +3271,10 @@ err_odp:
3179err_rsrc: 3271err_rsrc:
3180 destroy_dev_resources(&dev->devr); 3272 destroy_dev_resources(&dev->devr);
3181 3273
3182err_disable_roce: 3274err_disable_eth:
3183 if (ll == IB_LINK_LAYER_ETHERNET) { 3275 if (ll == IB_LINK_LAYER_ETHERNET) {
3184 mlx5_disable_roce(dev); 3276 mlx5_disable_eth(dev);
3185 mlx5_remove_roce_notifier(dev); 3277 mlx5_remove_netdev_notifier(dev);
3186 } 3278 }
3187 3279
3188err_free_port: 3280err_free_port:
@@ -3199,14 +3291,14 @@ static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3199 struct mlx5_ib_dev *dev = context; 3291 struct mlx5_ib_dev *dev = context;
3200 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3292 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3201 3293
3202 mlx5_remove_roce_notifier(dev); 3294 mlx5_remove_netdev_notifier(dev);
3203 ib_unregister_device(&dev->ib_dev); 3295 ib_unregister_device(&dev->ib_dev);
3204 mlx5_ib_dealloc_q_counters(dev); 3296 mlx5_ib_dealloc_q_counters(dev);
3205 destroy_umrc_res(dev); 3297 destroy_umrc_res(dev);
3206 mlx5_ib_odp_remove_one(dev); 3298 mlx5_ib_odp_remove_one(dev);
3207 destroy_dev_resources(&dev->devr); 3299 destroy_dev_resources(&dev->devr);
3208 if (ll == IB_LINK_LAYER_ETHERNET) 3300 if (ll == IB_LINK_LAYER_ETHERNET)
3209 mlx5_disable_roce(dev); 3301 mlx5_disable_eth(dev);
3210 kfree(dev->port); 3302 kfree(dev->port);
3211 ib_dealloc_device(&dev->ib_dev); 3303 ib_dealloc_device(&dev->ib_dev);
3212} 3304}
diff --git a/drivers/infiniband/hw/mlx5/mem.c b/drivers/infiniband/hw/mlx5/mem.c
index 996b54e366b0..6851357c16f4 100644
--- a/drivers/infiniband/hw/mlx5/mem.c
+++ b/drivers/infiniband/hw/mlx5/mem.c
@@ -37,12 +37,15 @@
37 37
38/* @umem: umem object to scan 38/* @umem: umem object to scan
39 * @addr: ib virtual address requested by the user 39 * @addr: ib virtual address requested by the user
40 * @max_page_shift: high limit for page_shift - 0 means no limit
40 * @count: number of PAGE_SIZE pages covered by umem 41 * @count: number of PAGE_SIZE pages covered by umem
41 * @shift: page shift for the compound pages found in the region 42 * @shift: page shift for the compound pages found in the region
42 * @ncont: number of compund pages 43 * @ncont: number of compund pages
43 * @order: log2 of the number of compound pages 44 * @order: log2 of the number of compound pages
44 */ 45 */
45void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift, 46void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr,
47 unsigned long max_page_shift,
48 int *count, int *shift,
46 int *ncont, int *order) 49 int *ncont, int *order)
47{ 50{
48 unsigned long tmp; 51 unsigned long tmp;
@@ -72,6 +75,8 @@ void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift,
72 addr = addr >> page_shift; 75 addr = addr >> page_shift;
73 tmp = (unsigned long)addr; 76 tmp = (unsigned long)addr;
74 m = find_first_bit(&tmp, BITS_PER_LONG); 77 m = find_first_bit(&tmp, BITS_PER_LONG);
78 if (max_page_shift)
79 m = min_t(unsigned long, max_page_shift - page_shift, m);
75 skip = 1 << m; 80 skip = 1 << m;
76 mask = skip - 1; 81 mask = skip - 1;
77 i = 0; 82 i = 0;
diff --git a/drivers/infiniband/hw/mlx5/mlx5_ib.h b/drivers/infiniband/hw/mlx5/mlx5_ib.h
index 854748b61212..6c6057eb60ea 100644
--- a/drivers/infiniband/hw/mlx5/mlx5_ib.h
+++ b/drivers/infiniband/hw/mlx5/mlx5_ib.h
@@ -63,6 +63,8 @@ pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
63#define MLX5_IB_DEFAULT_UIDX 0xffffff 63#define MLX5_IB_DEFAULT_UIDX 0xffffff
64#define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 64#define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
65 65
66#define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
67
66enum { 68enum {
67 MLX5_IB_MMAP_CMD_SHIFT = 8, 69 MLX5_IB_MMAP_CMD_SHIFT = 8,
68 MLX5_IB_MMAP_CMD_MASK = 0xff, 70 MLX5_IB_MMAP_CMD_MASK = 0xff,
@@ -387,6 +389,7 @@ struct mlx5_ib_qp {
387 struct list_head qps_list; 389 struct list_head qps_list;
388 struct list_head cq_recv_list; 390 struct list_head cq_recv_list;
389 struct list_head cq_send_list; 391 struct list_head cq_send_list;
392 u32 rate_limit;
390}; 393};
391 394
392struct mlx5_ib_cq_buf { 395struct mlx5_ib_cq_buf {
@@ -418,7 +421,7 @@ struct mlx5_umr_wr {
418 struct ib_pd *pd; 421 struct ib_pd *pd;
419 unsigned int page_shift; 422 unsigned int page_shift;
420 unsigned int npages; 423 unsigned int npages;
421 u32 length; 424 u64 length;
422 int access_flags; 425 int access_flags;
423 u32 mkey; 426 u32 mkey;
424}; 427};
@@ -739,7 +742,8 @@ void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
739int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey, 742int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
740 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, 743 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
741 const void *in_mad, void *response_mad); 744 const void *in_mad, void *response_mad);
742struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr); 745struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr,
746 struct ib_udata *udata);
743int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr); 747int mlx5_ib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr);
744int mlx5_ib_destroy_ah(struct ib_ah *ah); 748int mlx5_ib_destroy_ah(struct ib_ah *ah);
745struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd, 749struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
@@ -825,7 +829,9 @@ int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
825 struct ib_port_attr *props); 829 struct ib_port_attr *props);
826int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev); 830int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
827void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev); 831void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
828void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, int *count, int *shift, 832void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr,
833 unsigned long max_page_shift,
834 int *count, int *shift,
829 int *ncont, int *order); 835 int *ncont, int *order);
830void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 836void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
831 int page_shift, size_t offset, size_t num_pages, 837 int page_shift, size_t offset, size_t num_pages,
diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c
index 4e9012463c37..8f608debe141 100644
--- a/drivers/infiniband/hw/mlx5/mr.c
+++ b/drivers/infiniband/hw/mlx5/mr.c
@@ -628,7 +628,8 @@ int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
628 ent->order = i + 2; 628 ent->order = i + 2;
629 ent->dev = dev; 629 ent->dev = dev;
630 630
631 if (dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) 631 if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) &&
632 (mlx5_core_is_pf(dev->mdev)))
632 limit = dev->mdev->profile->mr_cache[i].limit; 633 limit = dev->mdev->profile->mr_cache[i].limit;
633 else 634 else
634 limit = 0; 635 limit = 0;
@@ -646,6 +647,33 @@ int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
646 return 0; 647 return 0;
647} 648}
648 649
650static void wait_for_async_commands(struct mlx5_ib_dev *dev)
651{
652 struct mlx5_mr_cache *cache = &dev->cache;
653 struct mlx5_cache_ent *ent;
654 int total = 0;
655 int i;
656 int j;
657
658 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
659 ent = &cache->ent[i];
660 for (j = 0 ; j < 1000; j++) {
661 if (!ent->pending)
662 break;
663 msleep(50);
664 }
665 }
666 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
667 ent = &cache->ent[i];
668 total += ent->pending;
669 }
670
671 if (total)
672 mlx5_ib_warn(dev, "aborted while there are %d pending mr requests\n", total);
673 else
674 mlx5_ib_warn(dev, "done with all pending requests\n");
675}
676
649int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev) 677int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
650{ 678{
651 int i; 679 int i;
@@ -659,6 +687,7 @@ int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
659 clean_keys(dev, i); 687 clean_keys(dev, i);
660 688
661 destroy_workqueue(dev->cache.wq); 689 destroy_workqueue(dev->cache.wq);
690 wait_for_async_commands(dev);
662 del_timer_sync(&dev->delay_timer); 691 del_timer_sync(&dev->delay_timer);
663 692
664 return 0; 693 return 0;
@@ -816,29 +845,34 @@ static void prep_umr_unreg_wqe(struct mlx5_ib_dev *dev,
816 umrwr->mkey = key; 845 umrwr->mkey = key;
817} 846}
818 847
819static struct ib_umem *mr_umem_get(struct ib_pd *pd, u64 start, u64 length, 848static int mr_umem_get(struct ib_pd *pd, u64 start, u64 length,
820 int access_flags, int *npages, 849 int access_flags, struct ib_umem **umem,
821 int *page_shift, int *ncont, int *order) 850 int *npages, int *page_shift, int *ncont,
851 int *order)
822{ 852{
823 struct mlx5_ib_dev *dev = to_mdev(pd->device); 853 struct mlx5_ib_dev *dev = to_mdev(pd->device);
824 struct ib_umem *umem = ib_umem_get(pd->uobject->context, start, length, 854 int err;
825 access_flags, 0); 855
826 if (IS_ERR(umem)) { 856 *umem = ib_umem_get(pd->uobject->context, start, length,
857 access_flags, 0);
858 err = PTR_ERR_OR_ZERO(*umem);
859 if (err < 0) {
827 mlx5_ib_err(dev, "umem get failed (%ld)\n", PTR_ERR(umem)); 860 mlx5_ib_err(dev, "umem get failed (%ld)\n", PTR_ERR(umem));
828 return (void *)umem; 861 return err;
829 } 862 }
830 863
831 mlx5_ib_cont_pages(umem, start, npages, page_shift, ncont, order); 864 mlx5_ib_cont_pages(*umem, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages,
865 page_shift, ncont, order);
832 if (!*npages) { 866 if (!*npages) {
833 mlx5_ib_warn(dev, "avoid zero region\n"); 867 mlx5_ib_warn(dev, "avoid zero region\n");
834 ib_umem_release(umem); 868 ib_umem_release(*umem);
835 return ERR_PTR(-EINVAL); 869 return -EINVAL;
836 } 870 }
837 871
838 mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n", 872 mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n",
839 *npages, *ncont, *order, *page_shift); 873 *npages, *ncont, *order, *page_shift);
840 874
841 return umem; 875 return 0;
842} 876}
843 877
844static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc) 878static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc)
@@ -1164,11 +1198,11 @@ struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1164 1198
1165 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n", 1199 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
1166 start, virt_addr, length, access_flags); 1200 start, virt_addr, length, access_flags);
1167 umem = mr_umem_get(pd, start, length, access_flags, &npages, 1201 err = mr_umem_get(pd, start, length, access_flags, &umem, &npages,
1168 &page_shift, &ncont, &order); 1202 &page_shift, &ncont, &order);
1169 1203
1170 if (IS_ERR(umem)) 1204 if (err < 0)
1171 return (void *)umem; 1205 return ERR_PTR(err);
1172 1206
1173 if (use_umr(order)) { 1207 if (use_umr(order)) {
1174 mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift, 1208 mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift,
@@ -1345,10 +1379,9 @@ int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1345 */ 1379 */
1346 flags |= IB_MR_REREG_TRANS; 1380 flags |= IB_MR_REREG_TRANS;
1347 ib_umem_release(mr->umem); 1381 ib_umem_release(mr->umem);
1348 mr->umem = mr_umem_get(pd, addr, len, access_flags, &npages, 1382 err = mr_umem_get(pd, addr, len, access_flags, &mr->umem,
1349 &page_shift, &ncont, &order); 1383 &npages, &page_shift, &ncont, &order);
1350 if (IS_ERR(mr->umem)) { 1384 if (err < 0) {
1351 err = PTR_ERR(mr->umem);
1352 mr->umem = NULL; 1385 mr->umem = NULL;
1353 return err; 1386 return err;
1354 } 1387 }
diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c
index d1e921816bfe..a1b3125f0a6e 100644
--- a/drivers/infiniband/hw/mlx5/qp.c
+++ b/drivers/infiniband/hw/mlx5/qp.c
@@ -77,12 +77,14 @@ struct mlx5_wqe_eth_pad {
77 77
78enum raw_qp_set_mask_map { 78enum raw_qp_set_mask_map {
79 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, 79 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
80 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
80}; 81};
81 82
82struct mlx5_modify_raw_qp_param { 83struct mlx5_modify_raw_qp_param {
83 u16 operation; 84 u16 operation;
84 85
85 u32 set_mask; /* raw_qp_set_mask_map */ 86 u32 set_mask; /* raw_qp_set_mask_map */
87 u32 rate_limit;
86 u8 rq_q_ctr_id; 88 u8 rq_q_ctr_id;
87}; 89};
88 90
@@ -351,6 +353,29 @@ static int calc_send_wqe(struct ib_qp_init_attr *attr)
351 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); 353 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
352} 354}
353 355
356static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
357{
358 int max_sge;
359
360 if (attr->qp_type == IB_QPT_RC)
361 max_sge = (min_t(int, wqe_size, 512) -
362 sizeof(struct mlx5_wqe_ctrl_seg) -
363 sizeof(struct mlx5_wqe_raddr_seg)) /
364 sizeof(struct mlx5_wqe_data_seg);
365 else if (attr->qp_type == IB_QPT_XRC_INI)
366 max_sge = (min_t(int, wqe_size, 512) -
367 sizeof(struct mlx5_wqe_ctrl_seg) -
368 sizeof(struct mlx5_wqe_xrc_seg) -
369 sizeof(struct mlx5_wqe_raddr_seg)) /
370 sizeof(struct mlx5_wqe_data_seg);
371 else
372 max_sge = (wqe_size - sq_overhead(attr)) /
373 sizeof(struct mlx5_wqe_data_seg);
374
375 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
376 sizeof(struct mlx5_wqe_data_seg));
377}
378
354static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, 379static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
355 struct mlx5_ib_qp *qp) 380 struct mlx5_ib_qp *qp)
356{ 381{
@@ -381,13 +406,18 @@ static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
381 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); 406 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
382 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; 407 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
383 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { 408 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
384 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n", 409 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
410 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
385 qp->sq.wqe_cnt, 411 qp->sq.wqe_cnt,
386 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); 412 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
387 return -ENOMEM; 413 return -ENOMEM;
388 } 414 }
389 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); 415 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
390 qp->sq.max_gs = attr->cap.max_send_sge; 416 qp->sq.max_gs = get_send_sge(attr, wqe_size);
417 if (qp->sq.max_gs < attr->cap.max_send_sge)
418 return -ENOMEM;
419
420 attr->cap.max_send_sge = qp->sq.max_gs;
391 qp->sq.max_post = wq_size / wqe_size; 421 qp->sq.max_post = wq_size / wqe_size;
392 attr->cap.max_send_wr = qp->sq.max_post; 422 attr->cap.max_send_wr = qp->sq.max_post;
393 423
@@ -647,7 +677,7 @@ static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
647 return PTR_ERR(*umem); 677 return PTR_ERR(*umem);
648 } 678 }
649 679
650 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL); 680 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
651 681
652 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); 682 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
653 if (err) { 683 if (err) {
@@ -700,7 +730,7 @@ static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
700 return err; 730 return err;
701 } 731 }
702 732
703 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift, 733 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
704 &ncont, NULL); 734 &ncont, NULL);
705 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, 735 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
706 &rwq->rq_page_offset); 736 &rwq->rq_page_offset);
@@ -2442,8 +2472,14 @@ out:
2442} 2472}
2443 2473
2444static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev, 2474static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2445 struct mlx5_ib_sq *sq, int new_state) 2475 struct mlx5_ib_sq *sq,
2476 int new_state,
2477 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2446{ 2478{
2479 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2480 u32 old_rate = ibqp->rate_limit;
2481 u32 new_rate = old_rate;
2482 u16 rl_index = 0;
2447 void *in; 2483 void *in;
2448 void *sqc; 2484 void *sqc;
2449 int inlen; 2485 int inlen;
@@ -2459,10 +2495,44 @@ static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2459 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 2495 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2460 MLX5_SET(sqc, sqc, state, new_state); 2496 MLX5_SET(sqc, sqc, state, new_state);
2461 2497
2498 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2499 if (new_state != MLX5_SQC_STATE_RDY)
2500 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2501 __func__);
2502 else
2503 new_rate = raw_qp_param->rate_limit;
2504 }
2505
2506 if (old_rate != new_rate) {
2507 if (new_rate) {
2508 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2509 if (err) {
2510 pr_err("Failed configuring rate %u: %d\n",
2511 new_rate, err);
2512 goto out;
2513 }
2514 }
2515
2516 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2517 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2518 }
2519
2462 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); 2520 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2463 if (err) 2521 if (err) {
2522 /* Remove new rate from table if failed */
2523 if (new_rate &&
2524 old_rate != new_rate)
2525 mlx5_rl_remove_rate(dev, new_rate);
2464 goto out; 2526 goto out;
2527 }
2528
2529 /* Only remove the old rate after new rate was set */
2530 if ((old_rate &&
2531 (old_rate != new_rate)) ||
2532 (new_state != MLX5_SQC_STATE_RDY))
2533 mlx5_rl_remove_rate(dev, old_rate);
2465 2534
2535 ibqp->rate_limit = new_rate;
2466 sq->state = new_state; 2536 sq->state = new_state;
2467 2537
2468out: 2538out:
@@ -2477,6 +2547,8 @@ static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2477 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; 2547 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2478 struct mlx5_ib_rq *rq = &raw_packet_qp->rq; 2548 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2479 struct mlx5_ib_sq *sq = &raw_packet_qp->sq; 2549 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2550 int modify_rq = !!qp->rq.wqe_cnt;
2551 int modify_sq = !!qp->sq.wqe_cnt;
2480 int rq_state; 2552 int rq_state;
2481 int sq_state; 2553 int sq_state;
2482 int err; 2554 int err;
@@ -2494,10 +2566,18 @@ static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2494 rq_state = MLX5_RQC_STATE_RST; 2566 rq_state = MLX5_RQC_STATE_RST;
2495 sq_state = MLX5_SQC_STATE_RST; 2567 sq_state = MLX5_SQC_STATE_RST;
2496 break; 2568 break;
2497 case MLX5_CMD_OP_INIT2INIT_QP:
2498 case MLX5_CMD_OP_INIT2RTR_QP:
2499 case MLX5_CMD_OP_RTR2RTS_QP: 2569 case MLX5_CMD_OP_RTR2RTS_QP:
2500 case MLX5_CMD_OP_RTS2RTS_QP: 2570 case MLX5_CMD_OP_RTS2RTS_QP:
2571 if (raw_qp_param->set_mask ==
2572 MLX5_RAW_QP_RATE_LIMIT) {
2573 modify_rq = 0;
2574 sq_state = sq->state;
2575 } else {
2576 return raw_qp_param->set_mask ? -EINVAL : 0;
2577 }
2578 break;
2579 case MLX5_CMD_OP_INIT2INIT_QP:
2580 case MLX5_CMD_OP_INIT2RTR_QP:
2501 if (raw_qp_param->set_mask) 2581 if (raw_qp_param->set_mask)
2502 return -EINVAL; 2582 return -EINVAL;
2503 else 2583 else
@@ -2507,13 +2587,13 @@ static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2507 return -EINVAL; 2587 return -EINVAL;
2508 } 2588 }
2509 2589
2510 if (qp->rq.wqe_cnt) { 2590 if (modify_rq) {
2511 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param); 2591 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2512 if (err) 2592 if (err)
2513 return err; 2593 return err;
2514 } 2594 }
2515 2595
2516 if (qp->sq.wqe_cnt) { 2596 if (modify_sq) {
2517 if (tx_affinity) { 2597 if (tx_affinity) {
2518 err = modify_raw_packet_tx_affinity(dev->mdev, sq, 2598 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2519 tx_affinity); 2599 tx_affinity);
@@ -2521,7 +2601,7 @@ static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2521 return err; 2601 return err;
2522 } 2602 }
2523 2603
2524 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state); 2604 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2525 } 2605 }
2526 2606
2527 return 0; 2607 return 0;
@@ -2577,7 +2657,6 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2577 struct mlx5_ib_port *mibport = NULL; 2657 struct mlx5_ib_port *mibport = NULL;
2578 enum mlx5_qp_state mlx5_cur, mlx5_new; 2658 enum mlx5_qp_state mlx5_cur, mlx5_new;
2579 enum mlx5_qp_optpar optpar; 2659 enum mlx5_qp_optpar optpar;
2580 int sqd_event;
2581 int mlx5_st; 2660 int mlx5_st;
2582 int err; 2661 int err;
2583 u16 op; 2662 u16 op;
@@ -2724,12 +2803,6 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2724 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 2803 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2725 context->db_rec_addr = cpu_to_be64(qp->db.dma); 2804 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2726 2805
2727 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2728 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2729 sqd_event = 1;
2730 else
2731 sqd_event = 0;
2732
2733 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 2806 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2734 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : 2807 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2735 qp->port) - 1; 2808 qp->port) - 1;
@@ -2776,6 +2849,12 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2776 raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id; 2849 raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2777 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; 2850 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2778 } 2851 }
2852
2853 if (attr_mask & IB_QP_RATE_LIMIT) {
2854 raw_qp_param.rate_limit = attr->rate_limit;
2855 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2856 }
2857
2779 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); 2858 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2780 } else { 2859 } else {
2781 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, 2860 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
@@ -3067,10 +3146,10 @@ static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3067{ 3146{
3068 memset(umr, 0, sizeof(*umr)); 3147 memset(umr, 0, sizeof(*umr));
3069 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 3148 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3070 umr->flags = 1 << 7; 3149 umr->flags = MLX5_UMR_INLINE;
3071} 3150}
3072 3151
3073static __be64 get_umr_reg_mr_mask(void) 3152static __be64 get_umr_reg_mr_mask(int atomic)
3074{ 3153{
3075 u64 result; 3154 u64 result;
3076 3155
@@ -3083,9 +3162,11 @@ static __be64 get_umr_reg_mr_mask(void)
3083 MLX5_MKEY_MASK_KEY | 3162 MLX5_MKEY_MASK_KEY |
3084 MLX5_MKEY_MASK_RR | 3163 MLX5_MKEY_MASK_RR |
3085 MLX5_MKEY_MASK_RW | 3164 MLX5_MKEY_MASK_RW |
3086 MLX5_MKEY_MASK_A |
3087 MLX5_MKEY_MASK_FREE; 3165 MLX5_MKEY_MASK_FREE;
3088 3166
3167 if (atomic)
3168 result |= MLX5_MKEY_MASK_A;
3169
3089 return cpu_to_be64(result); 3170 return cpu_to_be64(result);
3090} 3171}
3091 3172
@@ -3146,7 +3227,7 @@ static __be64 get_umr_update_pd_mask(void)
3146} 3227}
3147 3228
3148static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, 3229static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3149 struct ib_send_wr *wr) 3230 struct ib_send_wr *wr, int atomic)
3150{ 3231{
3151 struct mlx5_umr_wr *umrwr = umr_wr(wr); 3232 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3152 3233
@@ -3171,7 +3252,7 @@ static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3171 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD) 3252 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3172 umr->mkey_mask |= get_umr_update_pd_mask(); 3253 umr->mkey_mask |= get_umr_update_pd_mask();
3173 if (!umr->mkey_mask) 3254 if (!umr->mkey_mask)
3174 umr->mkey_mask = get_umr_reg_mr_mask(); 3255 umr->mkey_mask = get_umr_reg_mr_mask(atomic);
3175 } else { 3256 } else {
3176 umr->mkey_mask = get_umr_unreg_mr_mask(); 3257 umr->mkey_mask = get_umr_unreg_mr_mask();
3177 } 3258 }
@@ -4024,7 +4105,7 @@ int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4024 } 4105 }
4025 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; 4106 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4026 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); 4107 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4027 set_reg_umr_segment(seg, wr); 4108 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4028 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); 4109 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4029 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; 4110 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4030 if (unlikely((seg == qend))) 4111 if (unlikely((seg == qend)))
diff --git a/drivers/infiniband/hw/mlx5/srq.c b/drivers/infiniband/hw/mlx5/srq.c
index 3857dbd9c956..6f4397ee1ed6 100644
--- a/drivers/infiniband/hw/mlx5/srq.c
+++ b/drivers/infiniband/hw/mlx5/srq.c
@@ -118,7 +118,7 @@ static int create_srq_user(struct ib_pd *pd, struct mlx5_ib_srq *srq,
118 return err; 118 return err;
119 } 119 }
120 120
121 mlx5_ib_cont_pages(srq->umem, ucmd.buf_addr, &npages, 121 mlx5_ib_cont_pages(srq->umem, ucmd.buf_addr, 0, &npages,
122 &page_shift, &ncont, NULL); 122 &page_shift, &ncont, NULL);
123 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, 123 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift,
124 &offset); 124 &offset);
@@ -203,8 +203,6 @@ static int create_srq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_srq *srq,
203 203
204 srq->wrid = kmalloc(srq->msrq.max * sizeof(u64), GFP_KERNEL); 204 srq->wrid = kmalloc(srq->msrq.max * sizeof(u64), GFP_KERNEL);
205 if (!srq->wrid) { 205 if (!srq->wrid) {
206 mlx5_ib_dbg(dev, "kmalloc failed %lu\n",
207 (unsigned long)(srq->msrq.max * sizeof(u64)));
208 err = -ENOMEM; 206 err = -ENOMEM;
209 goto err_in; 207 goto err_in;
210 } 208 }
@@ -282,6 +280,7 @@ struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
282 mlx5_ib_dbg(dev, "desc_size 0x%x, req wr 0x%x, srq size 0x%x, max_gs 0x%x, max_avail_gather 0x%x\n", 280 mlx5_ib_dbg(dev, "desc_size 0x%x, req wr 0x%x, srq size 0x%x, max_gs 0x%x, max_avail_gather 0x%x\n",
283 desc_size, init_attr->attr.max_wr, srq->msrq.max, srq->msrq.max_gs, 281 desc_size, init_attr->attr.max_wr, srq->msrq.max, srq->msrq.max_gs,
284 srq->msrq.max_avail_gather); 282 srq->msrq.max_avail_gather);
283 in.type = init_attr->srq_type;
285 284
286 if (pd->uobject) 285 if (pd->uobject)
287 err = create_srq_user(pd, srq, &in, udata, buf_size); 286 err = create_srq_user(pd, srq, &in, udata, buf_size);
@@ -294,7 +293,6 @@ struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
294 goto err_srq; 293 goto err_srq;
295 } 294 }
296 295
297 in.type = init_attr->srq_type;
298 in.log_size = ilog2(srq->msrq.max); 296 in.log_size = ilog2(srq->msrq.max);
299 in.wqe_shift = srq->msrq.wqe_shift - 4; 297 in.wqe_shift = srq->msrq.wqe_shift - 4;
300 if (srq->wq_sig) 298 if (srq->wq_sig)
diff --git a/drivers/infiniband/hw/mthca/mthca_av.c b/drivers/infiniband/hw/mthca/mthca_av.c
index bcac294042f5..c9f0f364f484 100644
--- a/drivers/infiniband/hw/mthca/mthca_av.c
+++ b/drivers/infiniband/hw/mthca/mthca_av.c
@@ -186,8 +186,8 @@ int mthca_create_ah(struct mthca_dev *dev,
186 186
187on_hca_fail: 187on_hca_fail:
188 if (ah->type == MTHCA_AH_PCI_POOL) { 188 if (ah->type == MTHCA_AH_PCI_POOL) {
189 ah->av = pci_pool_alloc(dev->av_table.pool, 189 ah->av = pci_pool_zalloc(dev->av_table.pool,
190 GFP_ATOMIC, &ah->avdma); 190 GFP_ATOMIC, &ah->avdma);
191 if (!ah->av) 191 if (!ah->av)
192 return -ENOMEM; 192 return -ENOMEM;
193 193
@@ -196,8 +196,6 @@ on_hca_fail:
196 196
197 ah->key = pd->ntmr.ibmr.lkey; 197 ah->key = pd->ntmr.ibmr.lkey;
198 198
199 memset(av, 0, MTHCA_AV_SIZE);
200
201 av->port_pd = cpu_to_be32(pd->pd_num | (ah_attr->port_num << 24)); 199 av->port_pd = cpu_to_be32(pd->pd_num | (ah_attr->port_num << 24));
202 av->g_slid = ah_attr->src_path_bits; 200 av->g_slid = ah_attr->src_path_bits;
203 av->dlid = cpu_to_be16(ah_attr->dlid); 201 av->dlid = cpu_to_be16(ah_attr->dlid);
diff --git a/drivers/infiniband/hw/mthca/mthca_provider.c b/drivers/infiniband/hw/mthca/mthca_provider.c
index 358930a41e36..d31708742ba5 100644
--- a/drivers/infiniband/hw/mthca/mthca_provider.c
+++ b/drivers/infiniband/hw/mthca/mthca_provider.c
@@ -410,7 +410,9 @@ static int mthca_dealloc_pd(struct ib_pd *pd)
410} 410}
411 411
412static struct ib_ah *mthca_ah_create(struct ib_pd *pd, 412static struct ib_ah *mthca_ah_create(struct ib_pd *pd,
413 struct ib_ah_attr *ah_attr) 413 struct ib_ah_attr *ah_attr,
414 struct ib_udata *udata)
415
414{ 416{
415 int err; 417 int err;
416 struct mthca_ah *ah; 418 struct mthca_ah *ah;
diff --git a/drivers/infiniband/hw/mthca/mthca_reset.c b/drivers/infiniband/hw/mthca/mthca_reset.c
index 6727af27c017..2a6979e4ae1c 100644
--- a/drivers/infiniband/hw/mthca/mthca_reset.c
+++ b/drivers/infiniband/hw/mthca/mthca_reset.c
@@ -96,8 +96,6 @@ int mthca_reset(struct mthca_dev *mdev)
96 hca_header = kmalloc(256, GFP_KERNEL); 96 hca_header = kmalloc(256, GFP_KERNEL);
97 if (!hca_header) { 97 if (!hca_header) {
98 err = -ENOMEM; 98 err = -ENOMEM;
99 mthca_err(mdev, "Couldn't allocate memory to save HCA "
100 "PCI header, aborting.\n");
101 goto put_dev; 99 goto put_dev;
102 } 100 }
103 101
@@ -119,8 +117,6 @@ int mthca_reset(struct mthca_dev *mdev)
119 bridge_header = kmalloc(256, GFP_KERNEL); 117 bridge_header = kmalloc(256, GFP_KERNEL);
120 if (!bridge_header) { 118 if (!bridge_header) {
121 err = -ENOMEM; 119 err = -ENOMEM;
122 mthca_err(mdev, "Couldn't allocate memory to save HCA "
123 "bridge PCI header, aborting.\n");
124 goto free_hca; 120 goto free_hca;
125 } 121 }
126 122
diff --git a/drivers/infiniband/hw/nes/nes.c b/drivers/infiniband/hw/nes/nes.c
index 2baa45a8e401..5b9601014f0c 100644
--- a/drivers/infiniband/hw/nes/nes.c
+++ b/drivers/infiniband/hw/nes/nes.c
@@ -515,7 +515,6 @@ static int nes_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
515 /* Allocate hardware structure */ 515 /* Allocate hardware structure */
516 nesdev = kzalloc(sizeof(struct nes_device), GFP_KERNEL); 516 nesdev = kzalloc(sizeof(struct nes_device), GFP_KERNEL);
517 if (!nesdev) { 517 if (!nesdev) {
518 printk(KERN_ERR PFX "%s: Unable to alloc hardware struct\n", pci_name(pcidev));
519 ret = -ENOMEM; 518 ret = -ENOMEM;
520 goto bail2; 519 goto bail2;
521 } 520 }
diff --git a/drivers/infiniband/hw/nes/nes_cm.c b/drivers/infiniband/hw/nes/nes_cm.c
index 57db9b332f44..8e703479e7ce 100644
--- a/drivers/infiniband/hw/nes/nes_cm.c
+++ b/drivers/infiniband/hw/nes/nes_cm.c
@@ -2282,10 +2282,8 @@ static struct nes_cm_listener *mini_cm_listen(struct nes_cm_core *cm_core,
2282 if (!listener) { 2282 if (!listener) {
2283 /* create a CM listen node (1/2 node to compare incoming traffic to) */ 2283 /* create a CM listen node (1/2 node to compare incoming traffic to) */
2284 listener = kzalloc(sizeof(*listener), GFP_ATOMIC); 2284 listener = kzalloc(sizeof(*listener), GFP_ATOMIC);
2285 if (!listener) { 2285 if (!listener)
2286 nes_debug(NES_DBG_CM, "Not creating listener memory allocation failed\n");
2287 return NULL; 2286 return NULL;
2288 }
2289 2287
2290 listener->loc_addr = cm_info->loc_addr; 2288 listener->loc_addr = cm_info->loc_addr;
2291 listener->loc_port = cm_info->loc_port; 2289 listener->loc_port = cm_info->loc_port;
diff --git a/drivers/infiniband/hw/nes/nes_hw.c b/drivers/infiniband/hw/nes/nes_hw.c
index a1c6481d8038..19acd13c6cb1 100644
--- a/drivers/infiniband/hw/nes/nes_hw.c
+++ b/drivers/infiniband/hw/nes/nes_hw.c
@@ -351,9 +351,8 @@ struct nes_adapter *nes_init_adapter(struct nes_device *nesdev, u8 hw_rev) {
351 351
352 /* allocate a new adapter struct */ 352 /* allocate a new adapter struct */
353 nesadapter = kzalloc(adapter_size, GFP_KERNEL); 353 nesadapter = kzalloc(adapter_size, GFP_KERNEL);
354 if (nesadapter == NULL) { 354 if (!nesadapter)
355 return NULL; 355 return NULL;
356 }
357 356
358 nes_debug(NES_DBG_INIT, "Allocating new nesadapter @ %p, size = %u (actual size = %u).\n", 357 nes_debug(NES_DBG_INIT, "Allocating new nesadapter @ %p, size = %u (actual size = %u).\n",
359 nesadapter, (u32)sizeof(struct nes_adapter), adapter_size); 358 nesadapter, (u32)sizeof(struct nes_adapter), adapter_size);
@@ -1007,8 +1006,7 @@ int nes_init_cqp(struct nes_device *nesdev)
1007 /* Allocate a twice the number of CQP requests as the SQ size */ 1006 /* Allocate a twice the number of CQP requests as the SQ size */
1008 nesdev->nes_cqp_requests = kzalloc(sizeof(struct nes_cqp_request) * 1007 nesdev->nes_cqp_requests = kzalloc(sizeof(struct nes_cqp_request) *
1009 2 * NES_CQP_SQ_SIZE, GFP_KERNEL); 1008 2 * NES_CQP_SQ_SIZE, GFP_KERNEL);
1010 if (nesdev->nes_cqp_requests == NULL) { 1009 if (!nesdev->nes_cqp_requests) {
1011 nes_debug(NES_DBG_INIT, "Unable to allocate memory CQP request entries.\n");
1012 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size, nesdev->cqp.sq_vbase, 1010 pci_free_consistent(nesdev->pcidev, nesdev->cqp_mem_size, nesdev->cqp.sq_vbase,
1013 nesdev->cqp.sq_pbase); 1011 nesdev->cqp.sq_pbase);
1014 return -ENOMEM; 1012 return -ENOMEM;
diff --git a/drivers/infiniband/hw/nes/nes_mgt.c b/drivers/infiniband/hw/nes/nes_mgt.c
index 416645259b0f..33624f17c347 100644
--- a/drivers/infiniband/hw/nes/nes_mgt.c
+++ b/drivers/infiniband/hw/nes/nes_mgt.c
@@ -320,8 +320,7 @@ static int get_fpdu_info(struct nes_device *nesdev, struct nes_qp *nesqp,
320 320
321 /* Found one */ 321 /* Found one */
322 fpdu_info = kzalloc(sizeof(*fpdu_info), GFP_ATOMIC); 322 fpdu_info = kzalloc(sizeof(*fpdu_info), GFP_ATOMIC);
323 if (fpdu_info == NULL) { 323 if (!fpdu_info) {
324 nes_debug(NES_DBG_PAU, "Failed to alloc a fpdu_info.\n");
325 rc = -ENOMEM; 324 rc = -ENOMEM;
326 goto out; 325 goto out;
327 } 326 }
@@ -729,8 +728,7 @@ static int nes_change_quad_hash(struct nes_device *nesdev,
729 } 728 }
730 729
731 qh_chg = kmalloc(sizeof *qh_chg, GFP_ATOMIC); 730 qh_chg = kmalloc(sizeof *qh_chg, GFP_ATOMIC);
732 if (qh_chg == NULL) { 731 if (!qh_chg) {
733 nes_debug(NES_DBG_PAU, "Failed to get a cqp_request.\n");
734 ret = -ENOMEM; 732 ret = -ENOMEM;
735 goto chg_qh_err; 733 goto chg_qh_err;
736 } 734 }
@@ -880,10 +878,8 @@ int nes_init_mgt_qp(struct nes_device *nesdev, struct net_device *netdev, struct
880 878
881 /* Allocate space the all mgt QPs once */ 879 /* Allocate space the all mgt QPs once */
882 mgtvnic = kzalloc(NES_MGT_QP_COUNT * sizeof(struct nes_vnic_mgt), GFP_KERNEL); 880 mgtvnic = kzalloc(NES_MGT_QP_COUNT * sizeof(struct nes_vnic_mgt), GFP_KERNEL);
883 if (mgtvnic == NULL) { 881 if (!mgtvnic)
884 nes_debug(NES_DBG_INIT, "Unable to allocate memory for mgt structure\n");
885 return -ENOMEM; 882 return -ENOMEM;
886 }
887 883
888 /* Allocate fragment, RQ, and CQ; Reuse CEQ based on the PCI function */ 884 /* Allocate fragment, RQ, and CQ; Reuse CEQ based on the PCI function */
889 /* We are not sending from this NIC so sq is not allocated */ 885 /* We are not sending from this NIC so sq is not allocated */
diff --git a/drivers/infiniband/hw/nes/nes_nic.c b/drivers/infiniband/hw/nes/nes_nic.c
index 7f8597d6738b..5921ea3d50ae 100644
--- a/drivers/infiniband/hw/nes/nes_nic.c
+++ b/drivers/infiniband/hw/nes/nes_nic.c
@@ -662,10 +662,14 @@ tso_sq_no_longer_full:
662 nesnic->sq_head &= nesnic->sq_size-1; 662 nesnic->sq_head &= nesnic->sq_size-1;
663 } 663 }
664 } else { 664 } else {
665 nesvnic->linearized_skbs++;
666 hoffset = skb_transport_header(skb) - skb->data; 665 hoffset = skb_transport_header(skb) - skb->data;
667 nhoffset = skb_network_header(skb) - skb->data; 666 nhoffset = skb_network_header(skb) - skb->data;
668 skb_linearize(skb); 667 if (skb_linearize(skb)) {
668 nesvnic->tx_sw_dropped++;
669 kfree_skb(skb);
670 return NETDEV_TX_OK;
671 }
672 nesvnic->linearized_skbs++;
669 skb_set_transport_header(skb, hoffset); 673 skb_set_transport_header(skb, hoffset);
670 skb_set_network_header(skb, nhoffset); 674 skb_set_network_header(skb, nhoffset);
671 if (!nes_nic_send(skb, netdev)) 675 if (!nes_nic_send(skb, netdev))
@@ -1461,7 +1465,8 @@ static int nes_netdev_set_pauseparam(struct net_device *netdev,
1461/** 1465/**
1462 * nes_netdev_get_settings 1466 * nes_netdev_get_settings
1463 */ 1467 */
1464static int nes_netdev_get_settings(struct net_device *netdev, struct ethtool_cmd *et_cmd) 1468static int nes_netdev_get_link_ksettings(struct net_device *netdev,
1469 struct ethtool_link_ksettings *cmd)
1465{ 1470{
1466 struct nes_vnic *nesvnic = netdev_priv(netdev); 1471 struct nes_vnic *nesvnic = netdev_priv(netdev);
1467 struct nes_device *nesdev = nesvnic->nesdev; 1472 struct nes_device *nesdev = nesvnic->nesdev;
@@ -1470,54 +1475,59 @@ static int nes_netdev_get_settings(struct net_device *netdev, struct ethtool_cmd
1470 u8 phy_type = nesadapter->phy_type[mac_index]; 1475 u8 phy_type = nesadapter->phy_type[mac_index];
1471 u8 phy_index = nesadapter->phy_index[mac_index]; 1476 u8 phy_index = nesadapter->phy_index[mac_index];
1472 u16 phy_data; 1477 u16 phy_data;
1478 u32 supported, advertising;
1473 1479
1474 et_cmd->duplex = DUPLEX_FULL; 1480 cmd->base.duplex = DUPLEX_FULL;
1475 et_cmd->port = PORT_MII; 1481 cmd->base.port = PORT_MII;
1476 et_cmd->maxtxpkt = 511;
1477 et_cmd->maxrxpkt = 511;
1478 1482
1479 if (nesadapter->OneG_Mode) { 1483 if (nesadapter->OneG_Mode) {
1480 ethtool_cmd_speed_set(et_cmd, SPEED_1000); 1484 cmd->base.speed = SPEED_1000;
1481 if (phy_type == NES_PHY_TYPE_PUMA_1G) { 1485 if (phy_type == NES_PHY_TYPE_PUMA_1G) {
1482 et_cmd->supported = SUPPORTED_1000baseT_Full; 1486 supported = SUPPORTED_1000baseT_Full;
1483 et_cmd->advertising = ADVERTISED_1000baseT_Full; 1487 advertising = ADVERTISED_1000baseT_Full;
1484 et_cmd->autoneg = AUTONEG_DISABLE; 1488 cmd->base.autoneg = AUTONEG_DISABLE;
1485 et_cmd->transceiver = XCVR_INTERNAL; 1489 cmd->base.phy_address = mac_index;
1486 et_cmd->phy_address = mac_index;
1487 } else { 1490 } else {
1488 unsigned long flags; 1491 unsigned long flags;
1489 et_cmd->supported = SUPPORTED_1000baseT_Full 1492
1490 | SUPPORTED_Autoneg; 1493 supported = SUPPORTED_1000baseT_Full
1491 et_cmd->advertising = ADVERTISED_1000baseT_Full 1494 | SUPPORTED_Autoneg;
1492 | ADVERTISED_Autoneg; 1495 advertising = ADVERTISED_1000baseT_Full
1496 | ADVERTISED_Autoneg;
1493 spin_lock_irqsave(&nesadapter->phy_lock, flags); 1497 spin_lock_irqsave(&nesadapter->phy_lock, flags);
1494 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); 1498 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1495 spin_unlock_irqrestore(&nesadapter->phy_lock, flags); 1499 spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
1496 if (phy_data & 0x1000) 1500 if (phy_data & 0x1000)
1497 et_cmd->autoneg = AUTONEG_ENABLE; 1501 cmd->base.autoneg = AUTONEG_ENABLE;
1498 else 1502 else
1499 et_cmd->autoneg = AUTONEG_DISABLE; 1503 cmd->base.autoneg = AUTONEG_DISABLE;
1500 et_cmd->transceiver = XCVR_EXTERNAL; 1504 cmd->base.phy_address = phy_index;
1501 et_cmd->phy_address = phy_index;
1502 } 1505 }
1506 ethtool_convert_legacy_u32_to_link_mode(
1507 cmd->link_modes.supported, supported);
1508 ethtool_convert_legacy_u32_to_link_mode(
1509 cmd->link_modes.advertising, advertising);
1503 return 0; 1510 return 0;
1504 } 1511 }
1505 if ((phy_type == NES_PHY_TYPE_ARGUS) || 1512 if ((phy_type == NES_PHY_TYPE_ARGUS) ||
1506 (phy_type == NES_PHY_TYPE_SFP_D) || 1513 (phy_type == NES_PHY_TYPE_SFP_D) ||
1507 (phy_type == NES_PHY_TYPE_KR)) { 1514 (phy_type == NES_PHY_TYPE_KR)) {
1508 et_cmd->transceiver = XCVR_EXTERNAL; 1515 cmd->base.port = PORT_FIBRE;
1509 et_cmd->port = PORT_FIBRE; 1516 supported = SUPPORTED_FIBRE;
1510 et_cmd->supported = SUPPORTED_FIBRE; 1517 advertising = ADVERTISED_FIBRE;
1511 et_cmd->advertising = ADVERTISED_FIBRE; 1518 cmd->base.phy_address = phy_index;
1512 et_cmd->phy_address = phy_index;
1513 } else { 1519 } else {
1514 et_cmd->transceiver = XCVR_INTERNAL; 1520 supported = SUPPORTED_10000baseT_Full;
1515 et_cmd->supported = SUPPORTED_10000baseT_Full; 1521 advertising = ADVERTISED_10000baseT_Full;
1516 et_cmd->advertising = ADVERTISED_10000baseT_Full; 1522 cmd->base.phy_address = mac_index;
1517 et_cmd->phy_address = mac_index;
1518 } 1523 }
1519 ethtool_cmd_speed_set(et_cmd, SPEED_10000); 1524 cmd->base.speed = SPEED_10000;
1520 et_cmd->autoneg = AUTONEG_DISABLE; 1525 cmd->base.autoneg = AUTONEG_DISABLE;
1526 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1527 supported);
1528 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1529 advertising);
1530
1521 return 0; 1531 return 0;
1522} 1532}
1523 1533
@@ -1525,7 +1535,9 @@ static int nes_netdev_get_settings(struct net_device *netdev, struct ethtool_cmd
1525/** 1535/**
1526 * nes_netdev_set_settings 1536 * nes_netdev_set_settings
1527 */ 1537 */
1528static int nes_netdev_set_settings(struct net_device *netdev, struct ethtool_cmd *et_cmd) 1538static int
1539nes_netdev_set_link_ksettings(struct net_device *netdev,
1540 const struct ethtool_link_ksettings *cmd)
1529{ 1541{
1530 struct nes_vnic *nesvnic = netdev_priv(netdev); 1542 struct nes_vnic *nesvnic = netdev_priv(netdev);
1531 struct nes_device *nesdev = nesvnic->nesdev; 1543 struct nes_device *nesdev = nesvnic->nesdev;
@@ -1539,7 +1551,7 @@ static int nes_netdev_set_settings(struct net_device *netdev, struct ethtool_cmd
1539 1551
1540 spin_lock_irqsave(&nesadapter->phy_lock, flags); 1552 spin_lock_irqsave(&nesadapter->phy_lock, flags);
1541 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data); 1553 nes_read_1G_phy_reg(nesdev, 0, phy_index, &phy_data);
1542 if (et_cmd->autoneg) { 1554 if (cmd->base.autoneg) {
1543 /* Turn on Full duplex, Autoneg, and restart autonegotiation */ 1555 /* Turn on Full duplex, Autoneg, and restart autonegotiation */
1544 phy_data |= 0x1300; 1556 phy_data |= 0x1300;
1545 } else { 1557 } else {
@@ -1556,8 +1568,6 @@ static int nes_netdev_set_settings(struct net_device *netdev, struct ethtool_cmd
1556 1568
1557static const struct ethtool_ops nes_ethtool_ops = { 1569static const struct ethtool_ops nes_ethtool_ops = {
1558 .get_link = ethtool_op_get_link, 1570 .get_link = ethtool_op_get_link,
1559 .get_settings = nes_netdev_get_settings,
1560 .set_settings = nes_netdev_set_settings,
1561 .get_strings = nes_netdev_get_strings, 1571 .get_strings = nes_netdev_get_strings,
1562 .get_sset_count = nes_netdev_get_sset_count, 1572 .get_sset_count = nes_netdev_get_sset_count,
1563 .get_ethtool_stats = nes_netdev_get_ethtool_stats, 1573 .get_ethtool_stats = nes_netdev_get_ethtool_stats,
@@ -1566,6 +1576,8 @@ static const struct ethtool_ops nes_ethtool_ops = {
1566 .set_coalesce = nes_netdev_set_coalesce, 1576 .set_coalesce = nes_netdev_set_coalesce,
1567 .get_pauseparam = nes_netdev_get_pauseparam, 1577 .get_pauseparam = nes_netdev_get_pauseparam,
1568 .set_pauseparam = nes_netdev_set_pauseparam, 1578 .set_pauseparam = nes_netdev_set_pauseparam,
1579 .get_link_ksettings = nes_netdev_get_link_ksettings,
1580 .set_link_ksettings = nes_netdev_set_link_ksettings,
1569}; 1581};
1570 1582
1571static void nes_vlan_mode(struct net_device *netdev, struct nes_device *nesdev, netdev_features_t features) 1583static void nes_vlan_mode(struct net_device *netdev, struct nes_device *nesdev, netdev_features_t features)
diff --git a/drivers/infiniband/hw/nes/nes_verbs.c b/drivers/infiniband/hw/nes/nes_verbs.c
index bd69125731c1..aff9fb14768b 100644
--- a/drivers/infiniband/hw/nes/nes_verbs.c
+++ b/drivers/infiniband/hw/nes/nes_verbs.c
@@ -771,7 +771,8 @@ static int nes_dealloc_pd(struct ib_pd *ibpd)
771/** 771/**
772 * nes_create_ah 772 * nes_create_ah
773 */ 773 */
774static struct ib_ah *nes_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr) 774static struct ib_ah *nes_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr,
775 struct ib_udata *udata)
775{ 776{
776 return ERR_PTR(-ENOSYS); 777 return ERR_PTR(-ENOSYS);
777} 778}
@@ -1075,7 +1076,6 @@ static struct ib_qp *nes_create_qp(struct ib_pd *ibpd,
1075 mem = kzalloc(sizeof(*nesqp)+NES_SW_CONTEXT_ALIGN-1, GFP_KERNEL); 1076 mem = kzalloc(sizeof(*nesqp)+NES_SW_CONTEXT_ALIGN-1, GFP_KERNEL);
1076 if (!mem) { 1077 if (!mem) {
1077 nes_free_resource(nesadapter, nesadapter->allocated_qps, qp_num); 1078 nes_free_resource(nesadapter, nesadapter->allocated_qps, qp_num);
1078 nes_debug(NES_DBG_QP, "Unable to allocate QP\n");
1079 return ERR_PTR(-ENOMEM); 1079 return ERR_PTR(-ENOMEM);
1080 } 1080 }
1081 u64nesqp = (unsigned long)mem; 1081 u64nesqp = (unsigned long)mem;
@@ -1475,7 +1475,6 @@ static struct ib_cq *nes_create_cq(struct ib_device *ibdev,
1475 nescq = kzalloc(sizeof(struct nes_cq), GFP_KERNEL); 1475 nescq = kzalloc(sizeof(struct nes_cq), GFP_KERNEL);
1476 if (!nescq) { 1476 if (!nescq) {
1477 nes_free_resource(nesadapter, nesadapter->allocated_cqs, cq_num); 1477 nes_free_resource(nesadapter, nesadapter->allocated_cqs, cq_num);
1478 nes_debug(NES_DBG_CQ, "Unable to allocate nes_cq struct\n");
1479 return ERR_PTR(-ENOMEM); 1478 return ERR_PTR(-ENOMEM);
1480 } 1479 }
1481 1480
@@ -2408,7 +2407,6 @@ static struct ib_mr *nes_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
2408 } 2407 }
2409 nespbl = kzalloc(sizeof(*nespbl), GFP_KERNEL); 2408 nespbl = kzalloc(sizeof(*nespbl), GFP_KERNEL);
2410 if (!nespbl) { 2409 if (!nespbl) {
2411 nes_debug(NES_DBG_MR, "Unable to allocate PBL\n");
2412 ib_umem_release(region); 2410 ib_umem_release(region);
2413 return ERR_PTR(-ENOMEM); 2411 return ERR_PTR(-ENOMEM);
2414 } 2412 }
@@ -2416,7 +2414,6 @@ static struct ib_mr *nes_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
2416 if (!nesmr) { 2414 if (!nesmr) {
2417 ib_umem_release(region); 2415 ib_umem_release(region);
2418 kfree(nespbl); 2416 kfree(nespbl);
2419 nes_debug(NES_DBG_MR, "Unable to allocate nesmr\n");
2420 return ERR_PTR(-ENOMEM); 2417 return ERR_PTR(-ENOMEM);
2421 } 2418 }
2422 nesmr->region = region; 2419 nesmr->region = region;
diff --git a/drivers/infiniband/hw/ocrdma/ocrdma_ah.c b/drivers/infiniband/hw/ocrdma/ocrdma_ah.c
index 797362a297b2..14d33b0f3950 100644
--- a/drivers/infiniband/hw/ocrdma/ocrdma_ah.c
+++ b/drivers/infiniband/hw/ocrdma/ocrdma_ah.c
@@ -154,7 +154,8 @@ static inline int set_av_attr(struct ocrdma_dev *dev, struct ocrdma_ah *ah,
154 return status; 154 return status;
155} 155}
156 156
157struct ib_ah *ocrdma_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *attr) 157struct ib_ah *ocrdma_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *attr,
158 struct ib_udata *udata)
158{ 159{
159 u32 *ahid_addr; 160 u32 *ahid_addr;
160 int status; 161 int status;
diff --git a/drivers/infiniband/hw/ocrdma/ocrdma_ah.h b/drivers/infiniband/hw/ocrdma/ocrdma_ah.h
index 3856dd4c7e3d..0704a24b17c8 100644
--- a/drivers/infiniband/hw/ocrdma/ocrdma_ah.h
+++ b/drivers/infiniband/hw/ocrdma/ocrdma_ah.h
@@ -50,7 +50,9 @@ enum {
50 OCRDMA_AH_L3_TYPE_MASK = 0x03, 50 OCRDMA_AH_L3_TYPE_MASK = 0x03,
51 OCRDMA_AH_L3_TYPE_SHIFT = 0x1D /* 29 bits */ 51 OCRDMA_AH_L3_TYPE_SHIFT = 0x1D /* 29 bits */
52}; 52};
53struct ib_ah *ocrdma_create_ah(struct ib_pd *, struct ib_ah_attr *); 53
54struct ib_ah *ocrdma_create_ah(struct ib_pd *, struct ib_ah_attr *,
55 struct ib_udata *);
54int ocrdma_destroy_ah(struct ib_ah *); 56int ocrdma_destroy_ah(struct ib_ah *);
55int ocrdma_query_ah(struct ib_ah *, struct ib_ah_attr *); 57int ocrdma_query_ah(struct ib_ah *, struct ib_ah_attr *);
56int ocrdma_modify_ah(struct ib_ah *, struct ib_ah_attr *); 58int ocrdma_modify_ah(struct ib_ah *, struct ib_ah_attr *);
diff --git a/drivers/infiniband/hw/ocrdma/ocrdma_hw.c b/drivers/infiniband/hw/ocrdma/ocrdma_hw.c
index 67fc0b6857e1..9a305201545e 100644
--- a/drivers/infiniband/hw/ocrdma/ocrdma_hw.c
+++ b/drivers/infiniband/hw/ocrdma/ocrdma_hw.c
@@ -1596,10 +1596,9 @@ void ocrdma_alloc_pd_pool(struct ocrdma_dev *dev)
1596 1596
1597 dev->pd_mgr = kzalloc(sizeof(struct ocrdma_pd_resource_mgr), 1597 dev->pd_mgr = kzalloc(sizeof(struct ocrdma_pd_resource_mgr),
1598 GFP_KERNEL); 1598 GFP_KERNEL);
1599 if (!dev->pd_mgr) { 1599 if (!dev->pd_mgr)
1600 pr_err("%s(%d)Memory allocation failure.\n", __func__, dev->id);
1601 return; 1600 return;
1602 } 1601
1603 status = ocrdma_mbx_alloc_pd_range(dev); 1602 status = ocrdma_mbx_alloc_pd_range(dev);
1604 if (status) { 1603 if (status) {
1605 pr_err("%s(%d) Unable to initialize PD pool, using default.\n", 1604 pr_err("%s(%d) Unable to initialize PD pool, using default.\n",
@@ -1642,7 +1641,7 @@ static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1642static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev) 1641static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1643{ 1642{
1644 int i; 1643 int i;
1645 int status = 0; 1644 int status = -ENOMEM;
1646 int max_ah; 1645 int max_ah;
1647 struct ocrdma_create_ah_tbl *cmd; 1646 struct ocrdma_create_ah_tbl *cmd;
1648 struct ocrdma_create_ah_tbl_rsp *rsp; 1647 struct ocrdma_create_ah_tbl_rsp *rsp;
diff --git a/drivers/infiniband/hw/ocrdma/ocrdma_stats.c b/drivers/infiniband/hw/ocrdma/ocrdma_stats.c
index 8bef09a8c49f..f8e4b0a6486f 100644
--- a/drivers/infiniband/hw/ocrdma/ocrdma_stats.c
+++ b/drivers/infiniband/hw/ocrdma/ocrdma_stats.c
@@ -84,10 +84,8 @@ bool ocrdma_alloc_stats_resources(struct ocrdma_dev *dev)
84 84
85 /* Alloc debugfs mem */ 85 /* Alloc debugfs mem */
86 mem->debugfs_mem = kzalloc(OCRDMA_MAX_DBGFS_MEM, GFP_KERNEL); 86 mem->debugfs_mem = kzalloc(OCRDMA_MAX_DBGFS_MEM, GFP_KERNEL);
87 if (!mem->debugfs_mem) { 87 if (!mem->debugfs_mem)
88 pr_err("%s: stats debugfs mem allocation failed\n", __func__);
89 return false; 88 return false;
90 }
91 89
92 return true; 90 return true;
93} 91}
diff --git a/drivers/infiniband/hw/qedr/verbs.c b/drivers/infiniband/hw/qedr/verbs.c
index a61514296767..302fb05e6e6f 100644
--- a/drivers/infiniband/hw/qedr/verbs.c
+++ b/drivers/infiniband/hw/qedr/verbs.c
@@ -511,8 +511,10 @@ int qedr_dealloc_pd(struct ib_pd *ibpd)
511 struct qedr_dev *dev = get_qedr_dev(ibpd->device); 511 struct qedr_dev *dev = get_qedr_dev(ibpd->device);
512 struct qedr_pd *pd = get_qedr_pd(ibpd); 512 struct qedr_pd *pd = get_qedr_pd(ibpd);
513 513
514 if (!pd) 514 if (!pd) {
515 pr_err("Invalid PD received in dealloc_pd\n"); 515 pr_err("Invalid PD received in dealloc_pd\n");
516 return -EINVAL;
517 }
516 518
517 DP_DEBUG(dev, QEDR_MSG_INIT, "Deallocating PD %d\n", pd->pd_id); 519 DP_DEBUG(dev, QEDR_MSG_INIT, "Deallocating PD %d\n", pd->pd_id);
518 dev->ops->rdma_dealloc_pd(dev->rdma_ctx, pd->pd_id); 520 dev->ops->rdma_dealloc_pd(dev->rdma_ctx, pd->pd_id);
@@ -1477,6 +1479,7 @@ struct ib_qp *qedr_create_qp(struct ib_pd *ibpd,
1477 struct qedr_ucontext *ctx = NULL; 1479 struct qedr_ucontext *ctx = NULL;
1478 struct qedr_create_qp_ureq ureq; 1480 struct qedr_create_qp_ureq ureq;
1479 struct qedr_qp *qp; 1481 struct qedr_qp *qp;
1482 struct ib_qp *ibqp;
1480 int rc = 0; 1483 int rc = 0;
1481 1484
1482 DP_DEBUG(dev, QEDR_MSG_QP, "create qp: called from %s, pd=%p\n", 1485 DP_DEBUG(dev, QEDR_MSG_QP, "create qp: called from %s, pd=%p\n",
@@ -1486,13 +1489,13 @@ struct ib_qp *qedr_create_qp(struct ib_pd *ibpd,
1486 if (rc) 1489 if (rc)
1487 return ERR_PTR(rc); 1490 return ERR_PTR(rc);
1488 1491
1492 if (attrs->srq)
1493 return ERR_PTR(-EINVAL);
1494
1489 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1495 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1490 if (!qp) 1496 if (!qp)
1491 return ERR_PTR(-ENOMEM); 1497 return ERR_PTR(-ENOMEM);
1492 1498
1493 if (attrs->srq)
1494 return ERR_PTR(-EINVAL);
1495
1496 DP_DEBUG(dev, QEDR_MSG_QP, 1499 DP_DEBUG(dev, QEDR_MSG_QP,
1497 "create qp: sq_cq=%p, sq_icid=%d, rq_cq=%p, rq_icid=%d\n", 1500 "create qp: sq_cq=%p, sq_icid=%d, rq_cq=%p, rq_icid=%d\n",
1498 get_qedr_cq(attrs->send_cq), 1501 get_qedr_cq(attrs->send_cq),
@@ -1508,7 +1511,10 @@ struct ib_qp *qedr_create_qp(struct ib_pd *ibpd,
1508 "create qp: unexpected udata when creating GSI QP\n"); 1511 "create qp: unexpected udata when creating GSI QP\n");
1509 goto err0; 1512 goto err0;
1510 } 1513 }
1511 return qedr_create_gsi_qp(dev, attrs, qp); 1514 ibqp = qedr_create_gsi_qp(dev, attrs, qp);
1515 if (IS_ERR(ibqp))
1516 kfree(qp);
1517 return ibqp;
1512 } 1518 }
1513 1519
1514 memset(&in_params, 0, sizeof(in_params)); 1520 memset(&in_params, 0, sizeof(in_params));
@@ -2094,7 +2100,8 @@ int qedr_destroy_qp(struct ib_qp *ibqp)
2094 return rc; 2100 return rc;
2095} 2101}
2096 2102
2097struct ib_ah *qedr_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *attr) 2103struct ib_ah *qedr_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *attr,
2104 struct ib_udata *udata)
2098{ 2105{
2099 struct qedr_ah *ah; 2106 struct qedr_ah *ah;
2100 2107
@@ -2413,8 +2420,7 @@ static void handle_completed_mrs(struct qedr_dev *dev, struct mr_info *info)
2413 */ 2420 */
2414 pbl = list_first_entry(&info->inuse_pbl_list, 2421 pbl = list_first_entry(&info->inuse_pbl_list,
2415 struct qedr_pbl, list_entry); 2422 struct qedr_pbl, list_entry);
2416 list_del(&pbl->list_entry); 2423 list_move_tail(&pbl->list_entry, &info->free_pbl_list);
2417 list_add_tail(&pbl->list_entry, &info->free_pbl_list);
2418 info->completed_handled++; 2424 info->completed_handled++;
2419 } 2425 }
2420} 2426}
@@ -2981,11 +2987,6 @@ int qedr_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2981 return -EINVAL; 2987 return -EINVAL;
2982 } 2988 }
2983 2989
2984 if (!wr) {
2985 DP_ERR(dev, "Got an empty post send.\n");
2986 return -EINVAL;
2987 }
2988
2989 while (wr) { 2990 while (wr) {
2990 rc = __qedr_post_send(ibqp, wr, bad_wr); 2991 rc = __qedr_post_send(ibqp, wr, bad_wr);
2991 if (rc) 2992 if (rc)
diff --git a/drivers/infiniband/hw/qedr/verbs.h b/drivers/infiniband/hw/qedr/verbs.h
index a9b5e67bb81e..070677ca4d19 100644
--- a/drivers/infiniband/hw/qedr/verbs.h
+++ b/drivers/infiniband/hw/qedr/verbs.h
@@ -70,7 +70,8 @@ int qedr_query_qp(struct ib_qp *, struct ib_qp_attr *qp_attr,
70 int qp_attr_mask, struct ib_qp_init_attr *); 70 int qp_attr_mask, struct ib_qp_init_attr *);
71int qedr_destroy_qp(struct ib_qp *ibqp); 71int qedr_destroy_qp(struct ib_qp *ibqp);
72 72
73struct ib_ah *qedr_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *attr); 73struct ib_ah *qedr_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *attr,
74 struct ib_udata *udata);
74int qedr_destroy_ah(struct ib_ah *ibah); 75int qedr_destroy_ah(struct ib_ah *ibah);
75 76
76int qedr_dereg_mr(struct ib_mr *); 77int qedr_dereg_mr(struct ib_mr *);
diff --git a/drivers/infiniband/hw/qib/qib_diag.c b/drivers/infiniband/hw/qib/qib_diag.c
index 8c34b23e5bf6..775018b32b0d 100644
--- a/drivers/infiniband/hw/qib/qib_diag.c
+++ b/drivers/infiniband/hw/qib/qib_diag.c
@@ -609,8 +609,6 @@ static ssize_t qib_diagpkt_write(struct file *fp,
609 609
610 tmpbuf = vmalloc(plen); 610 tmpbuf = vmalloc(plen);
611 if (!tmpbuf) { 611 if (!tmpbuf) {
612 qib_devinfo(dd->pcidev,
613 "Unable to allocate tmp buffer, failing\n");
614 ret = -ENOMEM; 612 ret = -ENOMEM;
615 goto bail; 613 goto bail;
616 } 614 }
@@ -702,10 +700,8 @@ int qib_register_observer(struct qib_devdata *dd,
702 if (!dd || !op) 700 if (!dd || !op)
703 return -EINVAL; 701 return -EINVAL;
704 olp = vmalloc(sizeof(*olp)); 702 olp = vmalloc(sizeof(*olp));
705 if (!olp) { 703 if (!olp)
706 pr_err("vmalloc for observer failed\n");
707 return -ENOMEM; 704 return -ENOMEM;
708 }
709 705
710 spin_lock_irqsave(&dd->qib_diag_trans_lock, flags); 706 spin_lock_irqsave(&dd->qib_diag_trans_lock, flags);
711 olp->op = op; 707 olp->op = op;
diff --git a/drivers/infiniband/hw/qib/qib_driver.c b/drivers/infiniband/hw/qib/qib_driver.c
index 728e0a030d2e..2b5982f743ef 100644
--- a/drivers/infiniband/hw/qib/qib_driver.c
+++ b/drivers/infiniband/hw/qib/qib_driver.c
@@ -420,8 +420,7 @@ static u32 qib_rcv_hdrerr(struct qib_ctxtdata *rcd, struct qib_pportdata *ppd,
420 if (list_empty(&qp->rspwait)) { 420 if (list_empty(&qp->rspwait)) {
421 qp->r_flags |= 421 qp->r_flags |=
422 RVT_R_RSP_NAK; 422 RVT_R_RSP_NAK;
423 atomic_inc( 423 rvt_get_qp(qp);
424 &qp->refcount);
425 list_add_tail( 424 list_add_tail(
426 &qp->rspwait, 425 &qp->rspwait,
427 &rcd->qp_wait_list); 426 &rcd->qp_wait_list);
diff --git a/drivers/infiniband/hw/qib/qib_eeprom.c b/drivers/infiniband/hw/qib/qib_eeprom.c
index 311ee6c3dd5e..33a2e74c8495 100644
--- a/drivers/infiniband/hw/qib/qib_eeprom.c
+++ b/drivers/infiniband/hw/qib/qib_eeprom.c
@@ -182,12 +182,8 @@ void qib_get_eeprom_info(struct qib_devdata *dd)
182 * */ 182 * */
183 len = sizeof(struct qib_flash); 183 len = sizeof(struct qib_flash);
184 buf = vmalloc(len); 184 buf = vmalloc(len);
185 if (!buf) { 185 if (!buf)
186 qib_dev_err(dd,
187 "Couldn't allocate memory to read %u bytes from eeprom for GUID\n",
188 len);
189 goto bail; 186 goto bail;
190 }
191 187
192 /* 188 /*
193 * Use "public" eeprom read function, which does locking and 189 * Use "public" eeprom read function, which does locking and
diff --git a/drivers/infiniband/hw/qib/qib_file_ops.c b/drivers/infiniband/hw/qib/qib_file_ops.c
index 382466a90da7..2d1eacf1dfed 100644
--- a/drivers/infiniband/hw/qib/qib_file_ops.c
+++ b/drivers/infiniband/hw/qib/qib_file_ops.c
@@ -2066,8 +2066,11 @@ static ssize_t qib_write(struct file *fp, const char __user *data,
2066 ssize_t ret = 0; 2066 ssize_t ret = 0;
2067 void *dest; 2067 void *dest;
2068 2068
2069 if (WARN_ON_ONCE(!ib_safe_file_access(fp))) 2069 if (!ib_safe_file_access(fp)) {
2070 pr_err_once("qib_write: process %d (%s) changed security contexts after opening file descriptor, this is not allowed.\n",
2071 task_tgid_vnr(current), current->comm);
2070 return -EACCES; 2072 return -EACCES;
2073 }
2071 2074
2072 if (count < sizeof(cmd.type)) { 2075 if (count < sizeof(cmd.type)) {
2073 ret = -EINVAL; 2076 ret = -EINVAL;
diff --git a/drivers/infiniband/hw/qib/qib_iba6120.c b/drivers/infiniband/hw/qib/qib_iba6120.c
index a3733f25280f..92399d3ffd15 100644
--- a/drivers/infiniband/hw/qib/qib_iba6120.c
+++ b/drivers/infiniband/hw/qib/qib_iba6120.c
@@ -1759,9 +1759,7 @@ static void pe_boardname(struct qib_devdata *dd)
1759 } 1759 }
1760 namelen = strlen(n) + 1; 1760 namelen = strlen(n) + 1;
1761 dd->boardname = kmalloc(namelen, GFP_KERNEL); 1761 dd->boardname = kmalloc(namelen, GFP_KERNEL);
1762 if (!dd->boardname) 1762 if (dd->boardname)
1763 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
1764 else
1765 snprintf(dd->boardname, namelen, "%s", n); 1763 snprintf(dd->boardname, namelen, "%s", n);
1766 1764
1767 if (dd->majrev != 4 || !dd->minrev || dd->minrev > 2) 1765 if (dd->majrev != 4 || !dd->minrev || dd->minrev > 2)
@@ -2533,8 +2531,6 @@ static void init_6120_cntrnames(struct qib_devdata *dd)
2533 dd->cspec->cntrnamelen = 1 + s - cntr6120names; 2531 dd->cspec->cntrnamelen = 1 + s - cntr6120names;
2534 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs 2532 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
2535 * sizeof(u64), GFP_KERNEL); 2533 * sizeof(u64), GFP_KERNEL);
2536 if (!dd->cspec->cntrs)
2537 qib_dev_err(dd, "Failed allocation for counters\n");
2538 2534
2539 for (i = 0, s = (char *)portcntr6120names; s; i++) 2535 for (i = 0, s = (char *)portcntr6120names; s; i++)
2540 s = strchr(s + 1, '\n'); 2536 s = strchr(s + 1, '\n');
@@ -2542,8 +2538,6 @@ static void init_6120_cntrnames(struct qib_devdata *dd)
2542 dd->cspec->portcntrnamelen = sizeof(portcntr6120names) - 1; 2538 dd->cspec->portcntrnamelen = sizeof(portcntr6120names) - 1;
2543 dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs 2539 dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs
2544 * sizeof(u64), GFP_KERNEL); 2540 * sizeof(u64), GFP_KERNEL);
2545 if (!dd->cspec->portcntrs)
2546 qib_dev_err(dd, "Failed allocation for portcounters\n");
2547} 2541}
2548 2542
2549static u32 qib_read_6120cntrs(struct qib_devdata *dd, loff_t pos, char **namep, 2543static u32 qib_read_6120cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
diff --git a/drivers/infiniband/hw/qib/qib_iba7220.c b/drivers/infiniband/hw/qib/qib_iba7220.c
index 00b2af211157..e55e31a69195 100644
--- a/drivers/infiniband/hw/qib/qib_iba7220.c
+++ b/drivers/infiniband/hw/qib/qib_iba7220.c
@@ -2070,9 +2070,7 @@ static void qib_7220_boardname(struct qib_devdata *dd)
2070 2070
2071 namelen = strlen(n) + 1; 2071 namelen = strlen(n) + 1;
2072 dd->boardname = kmalloc(namelen, GFP_KERNEL); 2072 dd->boardname = kmalloc(namelen, GFP_KERNEL);
2073 if (!dd->boardname) 2073 if (dd->boardname)
2074 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
2075 else
2076 snprintf(dd->boardname, namelen, "%s", n); 2074 snprintf(dd->boardname, namelen, "%s", n);
2077 2075
2078 if (dd->majrev != 5 || !dd->minrev || dd->minrev > 2) 2076 if (dd->majrev != 5 || !dd->minrev || dd->minrev > 2)
@@ -3179,8 +3177,6 @@ static void init_7220_cntrnames(struct qib_devdata *dd)
3179 dd->cspec->cntrnamelen = 1 + s - cntr7220names; 3177 dd->cspec->cntrnamelen = 1 + s - cntr7220names;
3180 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs 3178 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
3181 * sizeof(u64), GFP_KERNEL); 3179 * sizeof(u64), GFP_KERNEL);
3182 if (!dd->cspec->cntrs)
3183 qib_dev_err(dd, "Failed allocation for counters\n");
3184 3180
3185 for (i = 0, s = (char *)portcntr7220names; s; i++) 3181 for (i = 0, s = (char *)portcntr7220names; s; i++)
3186 s = strchr(s + 1, '\n'); 3182 s = strchr(s + 1, '\n');
@@ -3188,8 +3184,6 @@ static void init_7220_cntrnames(struct qib_devdata *dd)
3188 dd->cspec->portcntrnamelen = sizeof(portcntr7220names) - 1; 3184 dd->cspec->portcntrnamelen = sizeof(portcntr7220names) - 1;
3189 dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs 3185 dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs
3190 * sizeof(u64), GFP_KERNEL); 3186 * sizeof(u64), GFP_KERNEL);
3191 if (!dd->cspec->portcntrs)
3192 qib_dev_err(dd, "Failed allocation for portcounters\n");
3193} 3187}
3194 3188
3195static u32 qib_read_7220cntrs(struct qib_devdata *dd, loff_t pos, char **namep, 3189static u32 qib_read_7220cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
diff --git a/drivers/infiniband/hw/qib/qib_iba7322.c b/drivers/infiniband/hw/qib/qib_iba7322.c
index ded27172320e..c4a3616062f1 100644
--- a/drivers/infiniband/hw/qib/qib_iba7322.c
+++ b/drivers/infiniband/hw/qib/qib_iba7322.c
@@ -3627,9 +3627,7 @@ static unsigned qib_7322_boardname(struct qib_devdata *dd)
3627 3627
3628 namelen = strlen(n) + 1; 3628 namelen = strlen(n) + 1;
3629 dd->boardname = kmalloc(namelen, GFP_KERNEL); 3629 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3630 if (!dd->boardname) 3630 if (dd->boardname)
3631 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3632 else
3633 snprintf(dd->boardname, namelen, "%s", n); 3631 snprintf(dd->boardname, namelen, "%s", n);
3634 3632
3635 snprintf(dd->boardversion, sizeof(dd->boardversion), 3633 snprintf(dd->boardversion, sizeof(dd->boardversion),
@@ -3656,7 +3654,7 @@ static unsigned qib_7322_boardname(struct qib_devdata *dd)
3656static int qib_do_7322_reset(struct qib_devdata *dd) 3654static int qib_do_7322_reset(struct qib_devdata *dd)
3657{ 3655{
3658 u64 val; 3656 u64 val;
3659 u64 *msix_vecsave; 3657 u64 *msix_vecsave = NULL;
3660 int i, msix_entries, ret = 1; 3658 int i, msix_entries, ret = 1;
3661 u16 cmdval; 3659 u16 cmdval;
3662 u8 int_line, clinesz; 3660 u8 int_line, clinesz;
@@ -3677,10 +3675,7 @@ static int qib_do_7322_reset(struct qib_devdata *dd)
3677 /* can be up to 512 bytes, too big for stack */ 3675 /* can be up to 512 bytes, too big for stack */
3678 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries * 3676 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3679 sizeof(u64), GFP_KERNEL); 3677 sizeof(u64), GFP_KERNEL);
3680 if (!msix_vecsave) 3678 }
3681 qib_dev_err(dd, "No mem to save MSIx data\n");
3682 } else
3683 msix_vecsave = NULL;
3684 3679
3685 /* 3680 /*
3686 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector 3681 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
@@ -5043,8 +5038,6 @@ static void init_7322_cntrnames(struct qib_devdata *dd)
5043 dd->cspec->cntrnamelen = 1 + s - cntr7322names; 5038 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
5044 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs 5039 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
5045 * sizeof(u64), GFP_KERNEL); 5040 * sizeof(u64), GFP_KERNEL);
5046 if (!dd->cspec->cntrs)
5047 qib_dev_err(dd, "Failed allocation for counters\n");
5048 5041
5049 for (i = 0, s = (char *)portcntr7322names; s; i++) 5042 for (i = 0, s = (char *)portcntr7322names; s; i++)
5050 s = strchr(s + 1, '\n'); 5043 s = strchr(s + 1, '\n');
@@ -5053,9 +5046,6 @@ static void init_7322_cntrnames(struct qib_devdata *dd)
5053 for (i = 0; i < dd->num_pports; ++i) { 5046 for (i = 0; i < dd->num_pports; ++i) {
5054 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs 5047 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
5055 * sizeof(u64), GFP_KERNEL); 5048 * sizeof(u64), GFP_KERNEL);
5056 if (!dd->pport[i].cpspec->portcntrs)
5057 qib_dev_err(dd,
5058 "Failed allocation for portcounters\n");
5059 } 5049 }
5060} 5050}
5061 5051
@@ -6461,7 +6451,6 @@ static int qib_init_7322_variables(struct qib_devdata *dd)
6461 sizeof(*dd->cspec->sendibchk), GFP_KERNEL); 6451 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
6462 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk || 6452 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6463 !dd->cspec->sendibchk) { 6453 !dd->cspec->sendibchk) {
6464 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
6465 ret = -ENOMEM; 6454 ret = -ENOMEM;
6466 goto bail; 6455 goto bail;
6467 } 6456 }
@@ -7338,10 +7327,9 @@ struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
7338 tabsize = actual_cnt; 7327 tabsize = actual_cnt;
7339 dd->cspec->msix_entries = kzalloc(tabsize * 7328 dd->cspec->msix_entries = kzalloc(tabsize *
7340 sizeof(struct qib_msix_entry), GFP_KERNEL); 7329 sizeof(struct qib_msix_entry), GFP_KERNEL);
7341 if (!dd->cspec->msix_entries) { 7330 if (!dd->cspec->msix_entries)
7342 qib_dev_err(dd, "No memory for MSIx table\n");
7343 tabsize = 0; 7331 tabsize = 0;
7344 } 7332
7345 for (i = 0; i < tabsize; i++) 7333 for (i = 0; i < tabsize; i++)
7346 dd->cspec->msix_entries[i].msix.entry = i; 7334 dd->cspec->msix_entries[i].msix.entry = i;
7347 7335
diff --git a/drivers/infiniband/hw/qib/qib_init.c b/drivers/infiniband/hw/qib/qib_init.c
index 1730aa839a47..b50240b1d5a4 100644
--- a/drivers/infiniband/hw/qib/qib_init.c
+++ b/drivers/infiniband/hw/qib/qib_init.c
@@ -133,11 +133,8 @@ int qib_create_ctxts(struct qib_devdata *dd)
133 * cleanup iterates across all possible ctxts. 133 * cleanup iterates across all possible ctxts.
134 */ 134 */
135 dd->rcd = kcalloc(dd->ctxtcnt, sizeof(*dd->rcd), GFP_KERNEL); 135 dd->rcd = kcalloc(dd->ctxtcnt, sizeof(*dd->rcd), GFP_KERNEL);
136 if (!dd->rcd) { 136 if (!dd->rcd)
137 qib_dev_err(dd,
138 "Unable to allocate ctxtdata array, failing\n");
139 return -ENOMEM; 137 return -ENOMEM;
140 }
141 138
142 /* create (one or more) kctxt */ 139 /* create (one or more) kctxt */
143 for (i = 0; i < dd->first_user_ctxt; ++i) { 140 for (i = 0; i < dd->first_user_ctxt; ++i) {
@@ -265,39 +262,23 @@ int qib_init_pportdata(struct qib_pportdata *ppd, struct qib_devdata *dd,
265 size = IB_CC_TABLE_CAP_DEFAULT * sizeof(struct ib_cc_table_entry) 262 size = IB_CC_TABLE_CAP_DEFAULT * sizeof(struct ib_cc_table_entry)
266 * IB_CCT_ENTRIES; 263 * IB_CCT_ENTRIES;
267 ppd->ccti_entries = kzalloc(size, GFP_KERNEL); 264 ppd->ccti_entries = kzalloc(size, GFP_KERNEL);
268 if (!ppd->ccti_entries) { 265 if (!ppd->ccti_entries)
269 qib_dev_err(dd,
270 "failed to allocate congestion control table for port %d!\n",
271 port);
272 goto bail; 266 goto bail;
273 }
274 267
275 size = IB_CC_CCS_ENTRIES * sizeof(struct ib_cc_congestion_entry); 268 size = IB_CC_CCS_ENTRIES * sizeof(struct ib_cc_congestion_entry);
276 ppd->congestion_entries = kzalloc(size, GFP_KERNEL); 269 ppd->congestion_entries = kzalloc(size, GFP_KERNEL);
277 if (!ppd->congestion_entries) { 270 if (!ppd->congestion_entries)
278 qib_dev_err(dd,
279 "failed to allocate congestion setting list for port %d!\n",
280 port);
281 goto bail_1; 271 goto bail_1;
282 }
283 272
284 size = sizeof(struct cc_table_shadow); 273 size = sizeof(struct cc_table_shadow);
285 ppd->ccti_entries_shadow = kzalloc(size, GFP_KERNEL); 274 ppd->ccti_entries_shadow = kzalloc(size, GFP_KERNEL);
286 if (!ppd->ccti_entries_shadow) { 275 if (!ppd->ccti_entries_shadow)
287 qib_dev_err(dd,
288 "failed to allocate shadow ccti list for port %d!\n",
289 port);
290 goto bail_2; 276 goto bail_2;
291 }
292 277
293 size = sizeof(struct ib_cc_congestion_setting_attr); 278 size = sizeof(struct ib_cc_congestion_setting_attr);
294 ppd->congestion_entries_shadow = kzalloc(size, GFP_KERNEL); 279 ppd->congestion_entries_shadow = kzalloc(size, GFP_KERNEL);
295 if (!ppd->congestion_entries_shadow) { 280 if (!ppd->congestion_entries_shadow)
296 qib_dev_err(dd,
297 "failed to allocate shadow congestion setting list for port %d!\n",
298 port);
299 goto bail_3; 281 goto bail_3;
300 }
301 282
302 return 0; 283 return 0;
303 284
@@ -391,18 +372,12 @@ static void init_shadow_tids(struct qib_devdata *dd)
391 dma_addr_t *addrs; 372 dma_addr_t *addrs;
392 373
393 pages = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(struct page *)); 374 pages = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(struct page *));
394 if (!pages) { 375 if (!pages)
395 qib_dev_err(dd,
396 "failed to allocate shadow page * array, no expected sends!\n");
397 goto bail; 376 goto bail;
398 }
399 377
400 addrs = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(dma_addr_t)); 378 addrs = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(dma_addr_t));
401 if (!addrs) { 379 if (!addrs)
402 qib_dev_err(dd,
403 "failed to allocate shadow dma handle array, no expected sends!\n");
404 goto bail_free; 380 goto bail_free;
405 }
406 381
407 dd->pageshadow = pages; 382 dd->pageshadow = pages;
408 dd->physshadow = addrs; 383 dd->physshadow = addrs;
@@ -1026,11 +1001,8 @@ static void qib_verify_pioperf(struct qib_devdata *dd)
1026 cnt = 1024; 1001 cnt = 1024;
1027 1002
1028 addr = vmalloc(cnt); 1003 addr = vmalloc(cnt);
1029 if (!addr) { 1004 if (!addr)
1030 qib_devinfo(dd->pcidev,
1031 "Couldn't get memory for checking PIO perf, skipping\n");
1032 goto done; 1005 goto done;
1033 }
1034 1006
1035 preempt_disable(); /* we want reasonably accurate elapsed time */ 1007 preempt_disable(); /* we want reasonably accurate elapsed time */
1036 msecs = 1 + jiffies_to_msecs(jiffies); 1008 msecs = 1 + jiffies_to_msecs(jiffies);
@@ -1172,9 +1144,6 @@ struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra)
1172 sizeof(long), GFP_KERNEL); 1144 sizeof(long), GFP_KERNEL);
1173 if (qib_cpulist) 1145 if (qib_cpulist)
1174 qib_cpulist_count = count; 1146 qib_cpulist_count = count;
1175 else
1176 qib_early_err(&pdev->dev,
1177 "Could not alloc cpulist info, cpu affinity might be wrong\n");
1178 } 1147 }
1179#ifdef CONFIG_DEBUG_FS 1148#ifdef CONFIG_DEBUG_FS
1180 qib_dbg_ibdev_init(&dd->verbs_dev); 1149 qib_dbg_ibdev_init(&dd->verbs_dev);
diff --git a/drivers/infiniband/hw/qib/qib_rc.c b/drivers/infiniband/hw/qib/qib_rc.c
index 2097512e75aa..031433cb7206 100644
--- a/drivers/infiniband/hw/qib/qib_rc.c
+++ b/drivers/infiniband/hw/qib/qib_rc.c
@@ -941,8 +941,6 @@ void qib_rc_send_complete(struct rvt_qp *qp, struct ib_header *hdr)
941{ 941{
942 struct ib_other_headers *ohdr; 942 struct ib_other_headers *ohdr;
943 struct rvt_swqe *wqe; 943 struct rvt_swqe *wqe;
944 struct ib_wc wc;
945 unsigned i;
946 u32 opcode; 944 u32 opcode;
947 u32 psn; 945 u32 psn;
948 946
@@ -988,22 +986,8 @@ void qib_rc_send_complete(struct rvt_qp *qp, struct ib_header *hdr)
988 qp->s_last = s_last; 986 qp->s_last = s_last;
989 /* see post_send() */ 987 /* see post_send() */
990 barrier(); 988 barrier();
991 for (i = 0; i < wqe->wr.num_sge; i++) { 989 rvt_put_swqe(wqe);
992 struct rvt_sge *sge = &wqe->sg_list[i]; 990 rvt_qp_swqe_complete(qp, wqe, IB_WC_SUCCESS);
993
994 rvt_put_mr(sge->mr);
995 }
996 /* Post a send completion queue entry if requested. */
997 if (!(qp->s_flags & RVT_S_SIGNAL_REQ_WR) ||
998 (wqe->wr.send_flags & IB_SEND_SIGNALED)) {
999 memset(&wc, 0, sizeof(wc));
1000 wc.wr_id = wqe->wr.wr_id;
1001 wc.status = IB_WC_SUCCESS;
1002 wc.opcode = ib_qib_wc_opcode[wqe->wr.opcode];
1003 wc.byte_len = wqe->length;
1004 wc.qp = &qp->ibqp;
1005 rvt_cq_enter(ibcq_to_rvtcq(qp->ibqp.send_cq), &wc, 0);
1006 }
1007 } 991 }
1008 /* 992 /*
1009 * If we were waiting for sends to complete before resending, 993 * If we were waiting for sends to complete before resending,
@@ -1032,9 +1016,6 @@ static struct rvt_swqe *do_rc_completion(struct rvt_qp *qp,
1032 struct rvt_swqe *wqe, 1016 struct rvt_swqe *wqe,
1033 struct qib_ibport *ibp) 1017 struct qib_ibport *ibp)
1034{ 1018{
1035 struct ib_wc wc;
1036 unsigned i;
1037
1038 /* 1019 /*
1039 * Don't decrement refcount and don't generate a 1020 * Don't decrement refcount and don't generate a
1040 * completion if the SWQE is being resent until the send 1021 * completion if the SWQE is being resent until the send
@@ -1044,28 +1025,14 @@ static struct rvt_swqe *do_rc_completion(struct rvt_qp *qp,
1044 qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) > 0) { 1025 qib_cmp24(qp->s_sending_psn, qp->s_sending_hpsn) > 0) {
1045 u32 s_last; 1026 u32 s_last;
1046 1027
1047 for (i = 0; i < wqe->wr.num_sge; i++) { 1028 rvt_put_swqe(wqe);
1048 struct rvt_sge *sge = &wqe->sg_list[i];
1049
1050 rvt_put_mr(sge->mr);
1051 }
1052 s_last = qp->s_last; 1029 s_last = qp->s_last;
1053 if (++s_last >= qp->s_size) 1030 if (++s_last >= qp->s_size)
1054 s_last = 0; 1031 s_last = 0;
1055 qp->s_last = s_last; 1032 qp->s_last = s_last;
1056 /* see post_send() */ 1033 /* see post_send() */
1057 barrier(); 1034 barrier();
1058 /* Post a send completion queue entry if requested. */ 1035 rvt_qp_swqe_complete(qp, wqe, IB_WC_SUCCESS);
1059 if (!(qp->s_flags & RVT_S_SIGNAL_REQ_WR) ||
1060 (wqe->wr.send_flags & IB_SEND_SIGNALED)) {
1061 memset(&wc, 0, sizeof(wc));
1062 wc.wr_id = wqe->wr.wr_id;
1063 wc.status = IB_WC_SUCCESS;
1064 wc.opcode = ib_qib_wc_opcode[wqe->wr.opcode];
1065 wc.byte_len = wqe->length;
1066 wc.qp = &qp->ibqp;
1067 rvt_cq_enter(ibcq_to_rvtcq(qp->ibqp.send_cq), &wc, 0);
1068 }
1069 } else 1036 } else
1070 this_cpu_inc(*ibp->rvp.rc_delayed_comp); 1037 this_cpu_inc(*ibp->rvp.rc_delayed_comp);
1071 1038
@@ -2112,8 +2079,7 @@ send_last:
2112 * Update the next expected PSN. We add 1 later 2079 * Update the next expected PSN. We add 1 later
2113 * below, so only add the remainder here. 2080 * below, so only add the remainder here.
2114 */ 2081 */
2115 if (len > pmtu) 2082 qp->r_psn += rvt_div_mtu(qp, len - 1);
2116 qp->r_psn += (len - 1) / pmtu;
2117 } else { 2083 } else {
2118 e->rdma_sge.mr = NULL; 2084 e->rdma_sge.mr = NULL;
2119 e->rdma_sge.vaddr = NULL; 2085 e->rdma_sge.vaddr = NULL;
diff --git a/drivers/infiniband/hw/qib/qib_ruc.c b/drivers/infiniband/hw/qib/qib_ruc.c
index de1bde5950f5..e54a2feeeb10 100644
--- a/drivers/infiniband/hw/qib/qib_ruc.c
+++ b/drivers/infiniband/hw/qib/qib_ruc.c
@@ -793,7 +793,6 @@ void qib_send_complete(struct rvt_qp *qp, struct rvt_swqe *wqe,
793 enum ib_wc_status status) 793 enum ib_wc_status status)
794{ 794{
795 u32 old_last, last; 795 u32 old_last, last;
796 unsigned i;
797 796
798 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_OR_FLUSH_SEND)) 797 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_OR_FLUSH_SEND))
799 return; 798 return;
@@ -805,32 +804,13 @@ void qib_send_complete(struct rvt_qp *qp, struct rvt_swqe *wqe,
805 qp->s_last = last; 804 qp->s_last = last;
806 /* See post_send() */ 805 /* See post_send() */
807 barrier(); 806 barrier();
808 for (i = 0; i < wqe->wr.num_sge; i++) { 807 rvt_put_swqe(wqe);
809 struct rvt_sge *sge = &wqe->sg_list[i];
810
811 rvt_put_mr(sge->mr);
812 }
813 if (qp->ibqp.qp_type == IB_QPT_UD || 808 if (qp->ibqp.qp_type == IB_QPT_UD ||
814 qp->ibqp.qp_type == IB_QPT_SMI || 809 qp->ibqp.qp_type == IB_QPT_SMI ||
815 qp->ibqp.qp_type == IB_QPT_GSI) 810 qp->ibqp.qp_type == IB_QPT_GSI)
816 atomic_dec(&ibah_to_rvtah(wqe->ud_wr.ah)->refcount); 811 atomic_dec(&ibah_to_rvtah(wqe->ud_wr.ah)->refcount);
817 812
818 /* See ch. 11.2.4.1 and 10.7.3.1 */ 813 rvt_qp_swqe_complete(qp, wqe, status);
819 if (!(qp->s_flags & RVT_S_SIGNAL_REQ_WR) ||
820 (wqe->wr.send_flags & IB_SEND_SIGNALED) ||
821 status != IB_WC_SUCCESS) {
822 struct ib_wc wc;
823
824 memset(&wc, 0, sizeof(wc));
825 wc.wr_id = wqe->wr.wr_id;
826 wc.status = status;
827 wc.opcode = ib_qib_wc_opcode[wqe->wr.opcode];
828 wc.qp = &qp->ibqp;
829 if (status == IB_WC_SUCCESS)
830 wc.byte_len = wqe->length;
831 rvt_cq_enter(ibcq_to_rvtcq(qp->ibqp.send_cq), &wc,
832 status != IB_WC_SUCCESS);
833 }
834 814
835 if (qp->s_acked == old_last) 815 if (qp->s_acked == old_last)
836 qp->s_acked = last; 816 qp->s_acked = last;
diff --git a/drivers/infiniband/hw/qib/qib_verbs.c b/drivers/infiniband/hw/qib/qib_verbs.c
index 954f15064514..4b54c0ddd08a 100644
--- a/drivers/infiniband/hw/qib/qib_verbs.c
+++ b/drivers/infiniband/hw/qib/qib_verbs.c
@@ -114,19 +114,6 @@ module_param_named(disable_sma, ib_qib_disable_sma, uint, S_IWUSR | S_IRUGO);
114MODULE_PARM_DESC(disable_sma, "Disable the SMA"); 114MODULE_PARM_DESC(disable_sma, "Disable the SMA");
115 115
116/* 116/*
117 * Translate ib_wr_opcode into ib_wc_opcode.
118 */
119const enum ib_wc_opcode ib_qib_wc_opcode[] = {
120 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
121 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
122 [IB_WR_SEND] = IB_WC_SEND,
123 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
124 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
125 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
126 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
127};
128
129/*
130 * System image GUID. 117 * System image GUID.
131 */ 118 */
132__be64 ib_qib_sys_image_guid; 119__be64 ib_qib_sys_image_guid;
@@ -464,7 +451,7 @@ static void mem_timer(unsigned long data)
464 priv = list_entry(list->next, struct qib_qp_priv, iowait); 451 priv = list_entry(list->next, struct qib_qp_priv, iowait);
465 qp = priv->owner; 452 qp = priv->owner;
466 list_del_init(&priv->iowait); 453 list_del_init(&priv->iowait);
467 atomic_inc(&qp->refcount); 454 rvt_get_qp(qp);
468 if (!list_empty(list)) 455 if (!list_empty(list))
469 mod_timer(&dev->mem_timer, jiffies + 1); 456 mod_timer(&dev->mem_timer, jiffies + 1);
470 } 457 }
@@ -477,8 +464,7 @@ static void mem_timer(unsigned long data)
477 qib_schedule_send(qp); 464 qib_schedule_send(qp);
478 } 465 }
479 spin_unlock_irqrestore(&qp->s_lock, flags); 466 spin_unlock_irqrestore(&qp->s_lock, flags);
480 if (atomic_dec_and_test(&qp->refcount)) 467 rvt_put_qp(qp);
481 wake_up(&qp->wait);
482 } 468 }
483} 469}
484 470
@@ -762,7 +748,7 @@ void qib_put_txreq(struct qib_verbs_txreq *tx)
762 iowait); 748 iowait);
763 qp = priv->owner; 749 qp = priv->owner;
764 list_del_init(&priv->iowait); 750 list_del_init(&priv->iowait);
765 atomic_inc(&qp->refcount); 751 rvt_get_qp(qp);
766 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags); 752 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
767 753
768 spin_lock_irqsave(&qp->s_lock, flags); 754 spin_lock_irqsave(&qp->s_lock, flags);
@@ -772,8 +758,7 @@ void qib_put_txreq(struct qib_verbs_txreq *tx)
772 } 758 }
773 spin_unlock_irqrestore(&qp->s_lock, flags); 759 spin_unlock_irqrestore(&qp->s_lock, flags);
774 760
775 if (atomic_dec_and_test(&qp->refcount)) 761 rvt_put_qp(qp);
776 wake_up(&qp->wait);
777 } else 762 } else
778 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags); 763 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
779} 764}
@@ -808,7 +793,7 @@ void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail)
808 break; 793 break;
809 avail -= qpp->s_tx->txreq.sg_count; 794 avail -= qpp->s_tx->txreq.sg_count;
810 list_del_init(&qpp->iowait); 795 list_del_init(&qpp->iowait);
811 atomic_inc(&qp->refcount); 796 rvt_get_qp(qp);
812 qps[n++] = qp; 797 qps[n++] = qp;
813 } 798 }
814 799
@@ -822,8 +807,7 @@ void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail)
822 qib_schedule_send(qp); 807 qib_schedule_send(qp);
823 } 808 }
824 spin_unlock(&qp->s_lock); 809 spin_unlock(&qp->s_lock);
825 if (atomic_dec_and_test(&qp->refcount)) 810 rvt_put_qp(qp);
826 wake_up(&qp->wait);
827 } 811 }
828} 812}
829 813
@@ -1288,7 +1272,7 @@ void qib_ib_piobufavail(struct qib_devdata *dd)
1288 priv = list_entry(list->next, struct qib_qp_priv, iowait); 1272 priv = list_entry(list->next, struct qib_qp_priv, iowait);
1289 qp = priv->owner; 1273 qp = priv->owner;
1290 list_del_init(&priv->iowait); 1274 list_del_init(&priv->iowait);
1291 atomic_inc(&qp->refcount); 1275 rvt_get_qp(qp);
1292 qps[n++] = qp; 1276 qps[n++] = qp;
1293 } 1277 }
1294 dd->f_wantpiobuf_intr(dd, 0); 1278 dd->f_wantpiobuf_intr(dd, 0);
@@ -1306,8 +1290,7 @@ full:
1306 spin_unlock_irqrestore(&qp->s_lock, flags); 1290 spin_unlock_irqrestore(&qp->s_lock, flags);
1307 1291
1308 /* Notify qib_destroy_qp() if it is waiting. */ 1292 /* Notify qib_destroy_qp() if it is waiting. */
1309 if (atomic_dec_and_test(&qp->refcount)) 1293 rvt_put_qp(qp);
1310 wake_up(&qp->wait);
1311 } 1294 }
1312} 1295}
1313 1296
diff --git a/drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c b/drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c
index 5b0248adf4ce..092d4e11a633 100644
--- a/drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c
+++ b/drivers/infiniband/hw/usnic/usnic_ib_qp_grp.c
@@ -117,10 +117,10 @@ static int enable_qp_grp(struct usnic_ib_qp_grp *qp_grp)
117 vnic_idx = usnic_vnic_get_index(qp_grp->vf->vnic); 117 vnic_idx = usnic_vnic_get_index(qp_grp->vf->vnic);
118 118
119 res_chunk = get_qp_res_chunk(qp_grp); 119 res_chunk = get_qp_res_chunk(qp_grp);
120 if (IS_ERR_OR_NULL(res_chunk)) { 120 if (IS_ERR(res_chunk)) {
121 usnic_err("Unable to get qp res with err %ld\n", 121 usnic_err("Unable to get qp res with err %ld\n",
122 PTR_ERR(res_chunk)); 122 PTR_ERR(res_chunk));
123 return res_chunk ? PTR_ERR(res_chunk) : -ENOMEM; 123 return PTR_ERR(res_chunk);
124 } 124 }
125 125
126 for (i = 0; i < res_chunk->cnt; i++) { 126 for (i = 0; i < res_chunk->cnt; i++) {
@@ -158,10 +158,10 @@ static int disable_qp_grp(struct usnic_ib_qp_grp *qp_grp)
158 vnic_idx = usnic_vnic_get_index(qp_grp->vf->vnic); 158 vnic_idx = usnic_vnic_get_index(qp_grp->vf->vnic);
159 159
160 res_chunk = get_qp_res_chunk(qp_grp); 160 res_chunk = get_qp_res_chunk(qp_grp);
161 if (IS_ERR_OR_NULL(res_chunk)) { 161 if (IS_ERR(res_chunk)) {
162 usnic_err("Unable to get qp res with err %ld\n", 162 usnic_err("Unable to get qp res with err %ld\n",
163 PTR_ERR(res_chunk)); 163 PTR_ERR(res_chunk));
164 return res_chunk ? PTR_ERR(res_chunk) : -ENOMEM; 164 return PTR_ERR(res_chunk);
165 } 165 }
166 166
167 for (i = 0; i < res_chunk->cnt; i++) { 167 for (i = 0; i < res_chunk->cnt; i++) {
@@ -186,11 +186,11 @@ static int init_filter_action(struct usnic_ib_qp_grp *qp_grp,
186 struct usnic_vnic_res_chunk *res_chunk; 186 struct usnic_vnic_res_chunk *res_chunk;
187 187
188 res_chunk = usnic_ib_qp_grp_get_chunk(qp_grp, USNIC_VNIC_RES_TYPE_RQ); 188 res_chunk = usnic_ib_qp_grp_get_chunk(qp_grp, USNIC_VNIC_RES_TYPE_RQ);
189 if (IS_ERR_OR_NULL(res_chunk)) { 189 if (IS_ERR(res_chunk)) {
190 usnic_err("Unable to get %s with err %ld\n", 190 usnic_err("Unable to get %s with err %ld\n",
191 usnic_vnic_res_type_to_str(USNIC_VNIC_RES_TYPE_RQ), 191 usnic_vnic_res_type_to_str(USNIC_VNIC_RES_TYPE_RQ),
192 PTR_ERR(res_chunk)); 192 PTR_ERR(res_chunk));
193 return res_chunk ? PTR_ERR(res_chunk) : -ENOMEM; 193 return PTR_ERR(res_chunk);
194 } 194 }
195 195
196 uaction->vnic_idx = usnic_vnic_get_index(qp_grp->vf->vnic); 196 uaction->vnic_idx = usnic_vnic_get_index(qp_grp->vf->vnic);
@@ -228,8 +228,6 @@ create_roce_custom_flow(struct usnic_ib_qp_grp *qp_grp,
228 228
229 flow = usnic_fwd_alloc_flow(qp_grp->ufdev, &filter, &uaction); 229 flow = usnic_fwd_alloc_flow(qp_grp->ufdev, &filter, &uaction);
230 if (IS_ERR_OR_NULL(flow)) { 230 if (IS_ERR_OR_NULL(flow)) {
231 usnic_err("Unable to alloc flow failed with err %ld\n",
232 PTR_ERR(flow));
233 err = flow ? PTR_ERR(flow) : -EFAULT; 231 err = flow ? PTR_ERR(flow) : -EFAULT;
234 goto out_unreserve_port; 232 goto out_unreserve_port;
235 } 233 }
@@ -303,8 +301,6 @@ create_udp_flow(struct usnic_ib_qp_grp *qp_grp,
303 301
304 flow = usnic_fwd_alloc_flow(qp_grp->ufdev, &filter, &uaction); 302 flow = usnic_fwd_alloc_flow(qp_grp->ufdev, &filter, &uaction);
305 if (IS_ERR_OR_NULL(flow)) { 303 if (IS_ERR_OR_NULL(flow)) {
306 usnic_err("Unable to alloc flow failed with err %ld\n",
307 PTR_ERR(flow));
308 err = flow ? PTR_ERR(flow) : -EFAULT; 304 err = flow ? PTR_ERR(flow) : -EFAULT;
309 goto out_put_sock; 305 goto out_put_sock;
310 } 306 }
@@ -694,18 +690,14 @@ usnic_ib_qp_grp_create(struct usnic_fwd_dev *ufdev, struct usnic_ib_vf *vf,
694 } 690 }
695 691
696 qp_grp = kzalloc(sizeof(*qp_grp), GFP_ATOMIC); 692 qp_grp = kzalloc(sizeof(*qp_grp), GFP_ATOMIC);
697 if (!qp_grp) { 693 if (!qp_grp)
698 usnic_err("Unable to alloc qp_grp - Out of memory\n");
699 return NULL; 694 return NULL;
700 }
701 695
702 qp_grp->res_chunk_list = alloc_res_chunk_list(vf->vnic, res_spec, 696 qp_grp->res_chunk_list = alloc_res_chunk_list(vf->vnic, res_spec,
703 qp_grp); 697 qp_grp);
704 if (IS_ERR_OR_NULL(qp_grp->res_chunk_list)) { 698 if (IS_ERR_OR_NULL(qp_grp->res_chunk_list)) {
705 err = qp_grp->res_chunk_list ? 699 err = qp_grp->res_chunk_list ?
706 PTR_ERR(qp_grp->res_chunk_list) : -ENOMEM; 700 PTR_ERR(qp_grp->res_chunk_list) : -ENOMEM;
707 usnic_err("Unable to alloc res for %d with err %d\n",
708 qp_grp->grp_id, err);
709 goto out_free_qp_grp; 701 goto out_free_qp_grp;
710 } 702 }
711 703
diff --git a/drivers/infiniband/hw/usnic/usnic_ib_verbs.c b/drivers/infiniband/hw/usnic/usnic_ib_verbs.c
index a5bfbba6bbac..74819a7951e2 100644
--- a/drivers/infiniband/hw/usnic/usnic_ib_verbs.c
+++ b/drivers/infiniband/hw/usnic/usnic_ib_verbs.c
@@ -87,12 +87,12 @@ static int usnic_ib_fill_create_qp_resp(struct usnic_ib_qp_grp *qp_grp,
87 resp.bar_len = bar->len; 87 resp.bar_len = bar->len;
88 88
89 chunk = usnic_ib_qp_grp_get_chunk(qp_grp, USNIC_VNIC_RES_TYPE_RQ); 89 chunk = usnic_ib_qp_grp_get_chunk(qp_grp, USNIC_VNIC_RES_TYPE_RQ);
90 if (IS_ERR_OR_NULL(chunk)) { 90 if (IS_ERR(chunk)) {
91 usnic_err("Failed to get chunk %s for qp_grp %d with err %ld\n", 91 usnic_err("Failed to get chunk %s for qp_grp %d with err %ld\n",
92 usnic_vnic_res_type_to_str(USNIC_VNIC_RES_TYPE_RQ), 92 usnic_vnic_res_type_to_str(USNIC_VNIC_RES_TYPE_RQ),
93 qp_grp->grp_id, 93 qp_grp->grp_id,
94 PTR_ERR(chunk)); 94 PTR_ERR(chunk));
95 return chunk ? PTR_ERR(chunk) : -ENOMEM; 95 return PTR_ERR(chunk);
96 } 96 }
97 97
98 WARN_ON(chunk->type != USNIC_VNIC_RES_TYPE_RQ); 98 WARN_ON(chunk->type != USNIC_VNIC_RES_TYPE_RQ);
@@ -101,12 +101,12 @@ static int usnic_ib_fill_create_qp_resp(struct usnic_ib_qp_grp *qp_grp,
101 resp.rq_idx[i] = chunk->res[i]->vnic_idx; 101 resp.rq_idx[i] = chunk->res[i]->vnic_idx;
102 102
103 chunk = usnic_ib_qp_grp_get_chunk(qp_grp, USNIC_VNIC_RES_TYPE_WQ); 103 chunk = usnic_ib_qp_grp_get_chunk(qp_grp, USNIC_VNIC_RES_TYPE_WQ);
104 if (IS_ERR_OR_NULL(chunk)) { 104 if (IS_ERR(chunk)) {
105 usnic_err("Failed to get chunk %s for qp_grp %d with err %ld\n", 105 usnic_err("Failed to get chunk %s for qp_grp %d with err %ld\n",
106 usnic_vnic_res_type_to_str(USNIC_VNIC_RES_TYPE_WQ), 106 usnic_vnic_res_type_to_str(USNIC_VNIC_RES_TYPE_WQ),
107 qp_grp->grp_id, 107 qp_grp->grp_id,
108 PTR_ERR(chunk)); 108 PTR_ERR(chunk));
109 return chunk ? PTR_ERR(chunk) : -ENOMEM; 109 return PTR_ERR(chunk);
110 } 110 }
111 111
112 WARN_ON(chunk->type != USNIC_VNIC_RES_TYPE_WQ); 112 WARN_ON(chunk->type != USNIC_VNIC_RES_TYPE_WQ);
@@ -115,12 +115,12 @@ static int usnic_ib_fill_create_qp_resp(struct usnic_ib_qp_grp *qp_grp,
115 resp.wq_idx[i] = chunk->res[i]->vnic_idx; 115 resp.wq_idx[i] = chunk->res[i]->vnic_idx;
116 116
117 chunk = usnic_ib_qp_grp_get_chunk(qp_grp, USNIC_VNIC_RES_TYPE_CQ); 117 chunk = usnic_ib_qp_grp_get_chunk(qp_grp, USNIC_VNIC_RES_TYPE_CQ);
118 if (IS_ERR_OR_NULL(chunk)) { 118 if (IS_ERR(chunk)) {
119 usnic_err("Failed to get chunk %s for qp_grp %d with err %ld\n", 119 usnic_err("Failed to get chunk %s for qp_grp %d with err %ld\n",
120 usnic_vnic_res_type_to_str(USNIC_VNIC_RES_TYPE_CQ), 120 usnic_vnic_res_type_to_str(USNIC_VNIC_RES_TYPE_CQ),
121 qp_grp->grp_id, 121 qp_grp->grp_id,
122 PTR_ERR(chunk)); 122 PTR_ERR(chunk));
123 return chunk ? PTR_ERR(chunk) : -ENOMEM; 123 return PTR_ERR(chunk);
124 } 124 }
125 125
126 WARN_ON(chunk->type != USNIC_VNIC_RES_TYPE_CQ); 126 WARN_ON(chunk->type != USNIC_VNIC_RES_TYPE_CQ);
@@ -738,7 +738,9 @@ int usnic_ib_mmap(struct ib_ucontext *context,
738 738
739/* In ib callbacks section - Start of stub funcs */ 739/* In ib callbacks section - Start of stub funcs */
740struct ib_ah *usnic_ib_create_ah(struct ib_pd *pd, 740struct ib_ah *usnic_ib_create_ah(struct ib_pd *pd,
741 struct ib_ah_attr *ah_attr) 741 struct ib_ah_attr *ah_attr,
742 struct ib_udata *udata)
743
742{ 744{
743 usnic_dbg("\n"); 745 usnic_dbg("\n");
744 return ERR_PTR(-EPERM); 746 return ERR_PTR(-EPERM);
diff --git a/drivers/infiniband/hw/usnic/usnic_ib_verbs.h b/drivers/infiniband/hw/usnic/usnic_ib_verbs.h
index 0d9d2e6a14d5..0ed8e072329e 100644
--- a/drivers/infiniband/hw/usnic/usnic_ib_verbs.h
+++ b/drivers/infiniband/hw/usnic/usnic_ib_verbs.h
@@ -75,7 +75,9 @@ int usnic_ib_dealloc_ucontext(struct ib_ucontext *ibcontext);
75int usnic_ib_mmap(struct ib_ucontext *context, 75int usnic_ib_mmap(struct ib_ucontext *context,
76 struct vm_area_struct *vma); 76 struct vm_area_struct *vma);
77struct ib_ah *usnic_ib_create_ah(struct ib_pd *pd, 77struct ib_ah *usnic_ib_create_ah(struct ib_pd *pd,
78 struct ib_ah_attr *ah_attr); 78 struct ib_ah_attr *ah_attr,
79 struct ib_udata *udata);
80
79int usnic_ib_destroy_ah(struct ib_ah *ah); 81int usnic_ib_destroy_ah(struct ib_ah *ah);
80int usnic_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, 82int usnic_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
81 struct ib_send_wr **bad_wr); 83 struct ib_send_wr **bad_wr);
diff --git a/drivers/infiniband/hw/usnic/usnic_vnic.c b/drivers/infiniband/hw/usnic/usnic_vnic.c
index 887510718690..e7b0030254da 100644
--- a/drivers/infiniband/hw/usnic/usnic_vnic.c
+++ b/drivers/infiniband/hw/usnic/usnic_vnic.c
@@ -241,17 +241,12 @@ usnic_vnic_get_resources(struct usnic_vnic *vnic, enum usnic_vnic_res_type type,
241 return ERR_PTR(-EINVAL); 241 return ERR_PTR(-EINVAL);
242 242
243 ret = kzalloc(sizeof(*ret), GFP_ATOMIC); 243 ret = kzalloc(sizeof(*ret), GFP_ATOMIC);
244 if (!ret) { 244 if (!ret)
245 usnic_err("Failed to allocate chunk for %s - Out of memory\n",
246 usnic_vnic_pci_name(vnic));
247 return ERR_PTR(-ENOMEM); 245 return ERR_PTR(-ENOMEM);
248 }
249 246
250 if (cnt > 0) { 247 if (cnt > 0) {
251 ret->res = kcalloc(cnt, sizeof(*(ret->res)), GFP_ATOMIC); 248 ret->res = kcalloc(cnt, sizeof(*(ret->res)), GFP_ATOMIC);
252 if (!ret->res) { 249 if (!ret->res) {
253 usnic_err("Failed to allocate resources for %s. Out of memory\n",
254 usnic_vnic_pci_name(vnic));
255 kfree(ret); 250 kfree(ret);
256 return ERR_PTR(-ENOMEM); 251 return ERR_PTR(-ENOMEM);
257 } 252 }
@@ -311,8 +306,10 @@ static int usnic_vnic_alloc_res_chunk(struct usnic_vnic *vnic,
311 struct usnic_vnic_res *res; 306 struct usnic_vnic_res *res;
312 307
313 cnt = vnic_dev_get_res_count(vnic->vdev, _to_vnic_res_type(type)); 308 cnt = vnic_dev_get_res_count(vnic->vdev, _to_vnic_res_type(type));
314 if (cnt < 1) 309 if (cnt < 1) {
310 usnic_err("Wrong res count with cnt %d\n", cnt);
315 return -EINVAL; 311 return -EINVAL;
312 }
316 313
317 chunk->cnt = chunk->free_cnt = cnt; 314 chunk->cnt = chunk->free_cnt = cnt;
318 chunk->res = kzalloc(sizeof(*(chunk->res))*cnt, GFP_KERNEL); 315 chunk->res = kzalloc(sizeof(*(chunk->res))*cnt, GFP_KERNEL);
@@ -384,12 +381,8 @@ static int usnic_vnic_discover_resources(struct pci_dev *pdev,
384 res_type < USNIC_VNIC_RES_TYPE_MAX; res_type++) { 381 res_type < USNIC_VNIC_RES_TYPE_MAX; res_type++) {
385 err = usnic_vnic_alloc_res_chunk(vnic, res_type, 382 err = usnic_vnic_alloc_res_chunk(vnic, res_type,
386 &vnic->chunks[res_type]); 383 &vnic->chunks[res_type]);
387 if (err) { 384 if (err)
388 usnic_err("Failed to alloc res %s with err %d\n",
389 usnic_vnic_res_type_to_str(res_type),
390 err);
391 goto out_clean_chunks; 385 goto out_clean_chunks;
392 }
393 } 386 }
394 387
395 return 0; 388 return 0;
@@ -454,11 +447,8 @@ struct usnic_vnic *usnic_vnic_alloc(struct pci_dev *pdev)
454 } 447 }
455 448
456 vnic = kzalloc(sizeof(*vnic), GFP_KERNEL); 449 vnic = kzalloc(sizeof(*vnic), GFP_KERNEL);
457 if (!vnic) { 450 if (!vnic)
458 usnic_err("Failed to alloc vnic for %s - out of memory\n",
459 pci_name(pdev));
460 return ERR_PTR(-ENOMEM); 451 return ERR_PTR(-ENOMEM);
461 }
462 452
463 spin_lock_init(&vnic->res_lock); 453 spin_lock_init(&vnic->res_lock);
464 454
diff --git a/drivers/infiniband/hw/vmw_pvrdma/Kconfig b/drivers/infiniband/hw/vmw_pvrdma/Kconfig
new file mode 100644
index 000000000000..5a9790ac0ede
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/Kconfig
@@ -0,0 +1,7 @@
1config INFINIBAND_VMWARE_PVRDMA
2 tristate "VMware Paravirtualized RDMA Driver"
3 depends on NETDEVICES && ETHERNET && PCI && INET && VMXNET3
4 ---help---
5 This driver provides low-level support for VMware Paravirtual
6 RDMA adapter. It interacts with the VMXNet3 driver to provide
7 Ethernet capabilities.
diff --git a/drivers/infiniband/hw/vmw_pvrdma/Makefile b/drivers/infiniband/hw/vmw_pvrdma/Makefile
new file mode 100644
index 000000000000..0194ed19f542
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_INFINIBAND_VMWARE_PVRDMA) += vmw_pvrdma.o
2
3vmw_pvrdma-y := pvrdma_cmd.o pvrdma_cq.o pvrdma_doorbell.o pvrdma_main.o pvrdma_misc.o pvrdma_mr.o pvrdma_qp.o pvrdma_verbs.o
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma.h b/drivers/infiniband/hw/vmw_pvrdma/pvrdma.h
new file mode 100644
index 000000000000..71e1d55d69d6
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma.h
@@ -0,0 +1,474 @@
1/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#ifndef __PVRDMA_H__
47#define __PVRDMA_H__
48
49#include <linux/compiler.h>
50#include <linux/interrupt.h>
51#include <linux/list.h>
52#include <linux/mutex.h>
53#include <linux/pci.h>
54#include <linux/semaphore.h>
55#include <linux/workqueue.h>
56#include <rdma/ib_umem.h>
57#include <rdma/ib_verbs.h>
58#include <rdma/vmw_pvrdma-abi.h>
59
60#include "pvrdma_ring.h"
61#include "pvrdma_dev_api.h"
62#include "pvrdma_verbs.h"
63
64/* NOT the same as BIT_MASK(). */
65#define PVRDMA_MASK(n) ((n << 1) - 1)
66
67/*
68 * VMware PVRDMA PCI device id.
69 */
70#define PCI_DEVICE_ID_VMWARE_PVRDMA 0x0820
71
72struct pvrdma_dev;
73
74struct pvrdma_page_dir {
75 dma_addr_t dir_dma;
76 u64 *dir;
77 int ntables;
78 u64 **tables;
79 u64 npages;
80 void **pages;
81};
82
83struct pvrdma_cq {
84 struct ib_cq ibcq;
85 int offset;
86 spinlock_t cq_lock; /* Poll lock. */
87 struct pvrdma_uar_map *uar;
88 struct ib_umem *umem;
89 struct pvrdma_ring_state *ring_state;
90 struct pvrdma_page_dir pdir;
91 u32 cq_handle;
92 bool is_kernel;
93 atomic_t refcnt;
94 wait_queue_head_t wait;
95};
96
97struct pvrdma_id_table {
98 u32 last;
99 u32 top;
100 u32 max;
101 u32 mask;
102 spinlock_t lock; /* Table lock. */
103 unsigned long *table;
104};
105
106struct pvrdma_uar_map {
107 unsigned long pfn;
108 void __iomem *map;
109 int index;
110};
111
112struct pvrdma_uar_table {
113 struct pvrdma_id_table tbl;
114 int size;
115};
116
117struct pvrdma_ucontext {
118 struct ib_ucontext ibucontext;
119 struct pvrdma_dev *dev;
120 struct pvrdma_uar_map uar;
121 u64 ctx_handle;
122};
123
124struct pvrdma_pd {
125 struct ib_pd ibpd;
126 u32 pdn;
127 u32 pd_handle;
128 int privileged;
129};
130
131struct pvrdma_mr {
132 u32 mr_handle;
133 u64 iova;
134 u64 size;
135};
136
137struct pvrdma_user_mr {
138 struct ib_mr ibmr;
139 struct ib_umem *umem;
140 struct pvrdma_mr mmr;
141 struct pvrdma_page_dir pdir;
142 u64 *pages;
143 u32 npages;
144 u32 max_pages;
145 u32 page_shift;
146};
147
148struct pvrdma_wq {
149 struct pvrdma_ring *ring;
150 spinlock_t lock; /* Work queue lock. */
151 int wqe_cnt;
152 int wqe_size;
153 int max_sg;
154 int offset;
155};
156
157struct pvrdma_ah {
158 struct ib_ah ibah;
159 struct pvrdma_av av;
160};
161
162struct pvrdma_qp {
163 struct ib_qp ibqp;
164 u32 qp_handle;
165 u32 qkey;
166 struct pvrdma_wq sq;
167 struct pvrdma_wq rq;
168 struct ib_umem *rumem;
169 struct ib_umem *sumem;
170 struct pvrdma_page_dir pdir;
171 int npages;
172 int npages_send;
173 int npages_recv;
174 u32 flags;
175 u8 port;
176 u8 state;
177 bool is_kernel;
178 struct mutex mutex; /* QP state mutex. */
179 atomic_t refcnt;
180 wait_queue_head_t wait;
181};
182
183struct pvrdma_dev {
184 /* PCI device-related information. */
185 struct ib_device ib_dev;
186 struct pci_dev *pdev;
187 void __iomem *regs;
188 struct pvrdma_device_shared_region *dsr; /* Shared region pointer */
189 dma_addr_t dsrbase; /* Shared region base address */
190 void *cmd_slot;
191 void *resp_slot;
192 unsigned long flags;
193 struct list_head device_link;
194
195 /* Locking and interrupt information. */
196 spinlock_t cmd_lock; /* Command lock. */
197 struct semaphore cmd_sema;
198 struct completion cmd_done;
199 struct {
200 enum pvrdma_intr_type type; /* Intr type */
201 struct msix_entry msix_entry[PVRDMA_MAX_INTERRUPTS];
202 irq_handler_t handler[PVRDMA_MAX_INTERRUPTS];
203 u8 enabled[PVRDMA_MAX_INTERRUPTS];
204 u8 size;
205 } intr;
206
207 /* RDMA-related device information. */
208 union ib_gid *sgid_tbl;
209 struct pvrdma_ring_state *async_ring_state;
210 struct pvrdma_page_dir async_pdir;
211 struct pvrdma_ring_state *cq_ring_state;
212 struct pvrdma_page_dir cq_pdir;
213 struct pvrdma_cq **cq_tbl;
214 spinlock_t cq_tbl_lock;
215 struct pvrdma_qp **qp_tbl;
216 spinlock_t qp_tbl_lock;
217 struct pvrdma_uar_table uar_table;
218 struct pvrdma_uar_map driver_uar;
219 __be64 sys_image_guid;
220 spinlock_t desc_lock; /* Device modification lock. */
221 u32 port_cap_mask;
222 struct mutex port_mutex; /* Port modification mutex. */
223 bool ib_active;
224 atomic_t num_qps;
225 atomic_t num_cqs;
226 atomic_t num_pds;
227 atomic_t num_ahs;
228
229 /* Network device information. */
230 struct net_device *netdev;
231 struct notifier_block nb_netdev;
232};
233
234struct pvrdma_netdevice_work {
235 struct work_struct work;
236 struct net_device *event_netdev;
237 unsigned long event;
238};
239
240static inline struct pvrdma_dev *to_vdev(struct ib_device *ibdev)
241{
242 return container_of(ibdev, struct pvrdma_dev, ib_dev);
243}
244
245static inline struct
246pvrdma_ucontext *to_vucontext(struct ib_ucontext *ibucontext)
247{
248 return container_of(ibucontext, struct pvrdma_ucontext, ibucontext);
249}
250
251static inline struct pvrdma_pd *to_vpd(struct ib_pd *ibpd)
252{
253 return container_of(ibpd, struct pvrdma_pd, ibpd);
254}
255
256static inline struct pvrdma_cq *to_vcq(struct ib_cq *ibcq)
257{
258 return container_of(ibcq, struct pvrdma_cq, ibcq);
259}
260
261static inline struct pvrdma_user_mr *to_vmr(struct ib_mr *ibmr)
262{
263 return container_of(ibmr, struct pvrdma_user_mr, ibmr);
264}
265
266static inline struct pvrdma_qp *to_vqp(struct ib_qp *ibqp)
267{
268 return container_of(ibqp, struct pvrdma_qp, ibqp);
269}
270
271static inline struct pvrdma_ah *to_vah(struct ib_ah *ibah)
272{
273 return container_of(ibah, struct pvrdma_ah, ibah);
274}
275
276static inline void pvrdma_write_reg(struct pvrdma_dev *dev, u32 reg, u32 val)
277{
278 writel(cpu_to_le32(val), dev->regs + reg);
279}
280
281static inline u32 pvrdma_read_reg(struct pvrdma_dev *dev, u32 reg)
282{
283 return le32_to_cpu(readl(dev->regs + reg));
284}
285
286static inline void pvrdma_write_uar_cq(struct pvrdma_dev *dev, u32 val)
287{
288 writel(cpu_to_le32(val), dev->driver_uar.map + PVRDMA_UAR_CQ_OFFSET);
289}
290
291static inline void pvrdma_write_uar_qp(struct pvrdma_dev *dev, u32 val)
292{
293 writel(cpu_to_le32(val), dev->driver_uar.map + PVRDMA_UAR_QP_OFFSET);
294}
295
296static inline void *pvrdma_page_dir_get_ptr(struct pvrdma_page_dir *pdir,
297 u64 offset)
298{
299 return pdir->pages[offset / PAGE_SIZE] + (offset % PAGE_SIZE);
300}
301
302static inline enum pvrdma_mtu ib_mtu_to_pvrdma(enum ib_mtu mtu)
303{
304 return (enum pvrdma_mtu)mtu;
305}
306
307static inline enum ib_mtu pvrdma_mtu_to_ib(enum pvrdma_mtu mtu)
308{
309 return (enum ib_mtu)mtu;
310}
311
312static inline enum pvrdma_port_state ib_port_state_to_pvrdma(
313 enum ib_port_state state)
314{
315 return (enum pvrdma_port_state)state;
316}
317
318static inline enum ib_port_state pvrdma_port_state_to_ib(
319 enum pvrdma_port_state state)
320{
321 return (enum ib_port_state)state;
322}
323
324static inline int ib_port_cap_flags_to_pvrdma(int flags)
325{
326 return flags & PVRDMA_MASK(PVRDMA_PORT_CAP_FLAGS_MAX);
327}
328
329static inline int pvrdma_port_cap_flags_to_ib(int flags)
330{
331 return flags;
332}
333
334static inline enum pvrdma_port_width ib_port_width_to_pvrdma(
335 enum ib_port_width width)
336{
337 return (enum pvrdma_port_width)width;
338}
339
340static inline enum ib_port_width pvrdma_port_width_to_ib(
341 enum pvrdma_port_width width)
342{
343 return (enum ib_port_width)width;
344}
345
346static inline enum pvrdma_port_speed ib_port_speed_to_pvrdma(
347 enum ib_port_speed speed)
348{
349 return (enum pvrdma_port_speed)speed;
350}
351
352static inline enum ib_port_speed pvrdma_port_speed_to_ib(
353 enum pvrdma_port_speed speed)
354{
355 return (enum ib_port_speed)speed;
356}
357
358static inline int pvrdma_qp_attr_mask_to_ib(int attr_mask)
359{
360 return attr_mask;
361}
362
363static inline int ib_qp_attr_mask_to_pvrdma(int attr_mask)
364{
365 return attr_mask & PVRDMA_MASK(PVRDMA_QP_ATTR_MASK_MAX);
366}
367
368static inline enum pvrdma_mig_state ib_mig_state_to_pvrdma(
369 enum ib_mig_state state)
370{
371 return (enum pvrdma_mig_state)state;
372}
373
374static inline enum ib_mig_state pvrdma_mig_state_to_ib(
375 enum pvrdma_mig_state state)
376{
377 return (enum ib_mig_state)state;
378}
379
380static inline int ib_access_flags_to_pvrdma(int flags)
381{
382 return flags;
383}
384
385static inline int pvrdma_access_flags_to_ib(int flags)
386{
387 return flags & PVRDMA_MASK(PVRDMA_ACCESS_FLAGS_MAX);
388}
389
390static inline enum pvrdma_qp_type ib_qp_type_to_pvrdma(enum ib_qp_type type)
391{
392 return (enum pvrdma_qp_type)type;
393}
394
395static inline enum ib_qp_type pvrdma_qp_type_to_ib(enum pvrdma_qp_type type)
396{
397 return (enum ib_qp_type)type;
398}
399
400static inline enum pvrdma_qp_state ib_qp_state_to_pvrdma(enum ib_qp_state state)
401{
402 return (enum pvrdma_qp_state)state;
403}
404
405static inline enum ib_qp_state pvrdma_qp_state_to_ib(enum pvrdma_qp_state state)
406{
407 return (enum ib_qp_state)state;
408}
409
410static inline enum pvrdma_wr_opcode ib_wr_opcode_to_pvrdma(enum ib_wr_opcode op)
411{
412 return (enum pvrdma_wr_opcode)op;
413}
414
415static inline enum ib_wc_status pvrdma_wc_status_to_ib(
416 enum pvrdma_wc_status status)
417{
418 return (enum ib_wc_status)status;
419}
420
421static inline int pvrdma_wc_opcode_to_ib(int opcode)
422{
423 return opcode;
424}
425
426static inline int pvrdma_wc_flags_to_ib(int flags)
427{
428 return flags;
429}
430
431static inline int ib_send_flags_to_pvrdma(int flags)
432{
433 return flags & PVRDMA_MASK(PVRDMA_SEND_FLAGS_MAX);
434}
435
436void pvrdma_qp_cap_to_ib(struct ib_qp_cap *dst,
437 const struct pvrdma_qp_cap *src);
438void ib_qp_cap_to_pvrdma(struct pvrdma_qp_cap *dst,
439 const struct ib_qp_cap *src);
440void pvrdma_gid_to_ib(union ib_gid *dst, const union pvrdma_gid *src);
441void ib_gid_to_pvrdma(union pvrdma_gid *dst, const union ib_gid *src);
442void pvrdma_global_route_to_ib(struct ib_global_route *dst,
443 const struct pvrdma_global_route *src);
444void ib_global_route_to_pvrdma(struct pvrdma_global_route *dst,
445 const struct ib_global_route *src);
446void pvrdma_ah_attr_to_ib(struct ib_ah_attr *dst,
447 const struct pvrdma_ah_attr *src);
448void ib_ah_attr_to_pvrdma(struct pvrdma_ah_attr *dst,
449 const struct ib_ah_attr *src);
450
451int pvrdma_uar_table_init(struct pvrdma_dev *dev);
452void pvrdma_uar_table_cleanup(struct pvrdma_dev *dev);
453
454int pvrdma_uar_alloc(struct pvrdma_dev *dev, struct pvrdma_uar_map *uar);
455void pvrdma_uar_free(struct pvrdma_dev *dev, struct pvrdma_uar_map *uar);
456
457void _pvrdma_flush_cqe(struct pvrdma_qp *qp, struct pvrdma_cq *cq);
458
459int pvrdma_page_dir_init(struct pvrdma_dev *dev, struct pvrdma_page_dir *pdir,
460 u64 npages, bool alloc_pages);
461void pvrdma_page_dir_cleanup(struct pvrdma_dev *dev,
462 struct pvrdma_page_dir *pdir);
463int pvrdma_page_dir_insert_dma(struct pvrdma_page_dir *pdir, u64 idx,
464 dma_addr_t daddr);
465int pvrdma_page_dir_insert_umem(struct pvrdma_page_dir *pdir,
466 struct ib_umem *umem, u64 offset);
467dma_addr_t pvrdma_page_dir_get_dma(struct pvrdma_page_dir *pdir, u64 idx);
468int pvrdma_page_dir_insert_page_list(struct pvrdma_page_dir *pdir,
469 u64 *page_list, int num_pages);
470
471int pvrdma_cmd_post(struct pvrdma_dev *dev, union pvrdma_cmd_req *req,
472 union pvrdma_cmd_resp *rsp, unsigned resp_code);
473
474#endif /* __PVRDMA_H__ */
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_cmd.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_cmd.c
new file mode 100644
index 000000000000..4a78c537d8a1
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_cmd.c
@@ -0,0 +1,119 @@
1/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#include <linux/list.h>
47
48#include "pvrdma.h"
49
50#define PVRDMA_CMD_TIMEOUT 10000 /* ms */
51
52static inline int pvrdma_cmd_recv(struct pvrdma_dev *dev,
53 union pvrdma_cmd_resp *resp,
54 unsigned resp_code)
55{
56 int err;
57
58 dev_dbg(&dev->pdev->dev, "receive response from device\n");
59
60 err = wait_for_completion_interruptible_timeout(&dev->cmd_done,
61 msecs_to_jiffies(PVRDMA_CMD_TIMEOUT));
62 if (err == 0 || err == -ERESTARTSYS) {
63 dev_warn(&dev->pdev->dev,
64 "completion timeout or interrupted\n");
65 return -ETIMEDOUT;
66 }
67
68 spin_lock(&dev->cmd_lock);
69 memcpy(resp, dev->resp_slot, sizeof(*resp));
70 spin_unlock(&dev->cmd_lock);
71
72 if (resp->hdr.ack != resp_code) {
73 dev_warn(&dev->pdev->dev,
74 "unknown response %#x expected %#x\n",
75 resp->hdr.ack, resp_code);
76 return -EFAULT;
77 }
78
79 return 0;
80}
81
82int
83pvrdma_cmd_post(struct pvrdma_dev *dev, union pvrdma_cmd_req *req,
84 union pvrdma_cmd_resp *resp, unsigned resp_code)
85{
86 int err;
87
88 dev_dbg(&dev->pdev->dev, "post request to device\n");
89
90 /* Serializiation */
91 down(&dev->cmd_sema);
92
93 BUILD_BUG_ON(sizeof(union pvrdma_cmd_req) !=
94 sizeof(struct pvrdma_cmd_modify_qp));
95
96 spin_lock(&dev->cmd_lock);
97 memcpy(dev->cmd_slot, req, sizeof(*req));
98 spin_unlock(&dev->cmd_lock);
99
100 init_completion(&dev->cmd_done);
101 pvrdma_write_reg(dev, PVRDMA_REG_REQUEST, 0);
102
103 /* Make sure the request is written before reading status. */
104 mb();
105
106 err = pvrdma_read_reg(dev, PVRDMA_REG_ERR);
107 if (err == 0) {
108 if (resp != NULL)
109 err = pvrdma_cmd_recv(dev, resp, resp_code);
110 } else {
111 dev_warn(&dev->pdev->dev,
112 "failed to write request error reg: %d\n", err);
113 err = -EFAULT;
114 }
115
116 up(&dev->cmd_sema);
117
118 return err;
119}
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c
new file mode 100644
index 000000000000..e429ca5b16aa
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_cq.c
@@ -0,0 +1,425 @@
1/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#include <asm/page.h>
47#include <linux/io.h>
48#include <linux/wait.h>
49#include <rdma/ib_addr.h>
50#include <rdma/ib_smi.h>
51#include <rdma/ib_user_verbs.h>
52
53#include "pvrdma.h"
54
55/**
56 * pvrdma_req_notify_cq - request notification for a completion queue
57 * @ibcq: the completion queue
58 * @notify_flags: notification flags
59 *
60 * @return: 0 for success.
61 */
62int pvrdma_req_notify_cq(struct ib_cq *ibcq,
63 enum ib_cq_notify_flags notify_flags)
64{
65 struct pvrdma_dev *dev = to_vdev(ibcq->device);
66 struct pvrdma_cq *cq = to_vcq(ibcq);
67 u32 val = cq->cq_handle;
68
69 val |= (notify_flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
70 PVRDMA_UAR_CQ_ARM_SOL : PVRDMA_UAR_CQ_ARM;
71
72 pvrdma_write_uar_cq(dev, val);
73
74 return 0;
75}
76
77/**
78 * pvrdma_create_cq - create completion queue
79 * @ibdev: the device
80 * @attr: completion queue attributes
81 * @context: user context
82 * @udata: user data
83 *
84 * @return: ib_cq completion queue pointer on success,
85 * otherwise returns negative errno.
86 */
87struct ib_cq *pvrdma_create_cq(struct ib_device *ibdev,
88 const struct ib_cq_init_attr *attr,
89 struct ib_ucontext *context,
90 struct ib_udata *udata)
91{
92 int entries = attr->cqe;
93 struct pvrdma_dev *dev = to_vdev(ibdev);
94 struct pvrdma_cq *cq;
95 int ret;
96 int npages;
97 unsigned long flags;
98 union pvrdma_cmd_req req;
99 union pvrdma_cmd_resp rsp;
100 struct pvrdma_cmd_create_cq *cmd = &req.create_cq;
101 struct pvrdma_cmd_create_cq_resp *resp = &rsp.create_cq_resp;
102 struct pvrdma_create_cq ucmd;
103
104 BUILD_BUG_ON(sizeof(struct pvrdma_cqe) != 64);
105
106 entries = roundup_pow_of_two(entries);
107 if (entries < 1 || entries > dev->dsr->caps.max_cqe)
108 return ERR_PTR(-EINVAL);
109
110 if (!atomic_add_unless(&dev->num_cqs, 1, dev->dsr->caps.max_cq))
111 return ERR_PTR(-ENOMEM);
112
113 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
114 if (!cq) {
115 atomic_dec(&dev->num_cqs);
116 return ERR_PTR(-ENOMEM);
117 }
118
119 cq->ibcq.cqe = entries;
120
121 if (context) {
122 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
123 ret = -EFAULT;
124 goto err_cq;
125 }
126
127 cq->umem = ib_umem_get(context, ucmd.buf_addr, ucmd.buf_size,
128 IB_ACCESS_LOCAL_WRITE, 1);
129 if (IS_ERR(cq->umem)) {
130 ret = PTR_ERR(cq->umem);
131 goto err_cq;
132 }
133
134 npages = ib_umem_page_count(cq->umem);
135 } else {
136 cq->is_kernel = true;
137
138 /* One extra page for shared ring state */
139 npages = 1 + (entries * sizeof(struct pvrdma_cqe) +
140 PAGE_SIZE - 1) / PAGE_SIZE;
141
142 /* Skip header page. */
143 cq->offset = PAGE_SIZE;
144 }
145
146 if (npages < 0 || npages > PVRDMA_PAGE_DIR_MAX_PAGES) {
147 dev_warn(&dev->pdev->dev,
148 "overflow pages in completion queue\n");
149 ret = -EINVAL;
150 goto err_umem;
151 }
152
153 ret = pvrdma_page_dir_init(dev, &cq->pdir, npages, cq->is_kernel);
154 if (ret) {
155 dev_warn(&dev->pdev->dev,
156 "could not allocate page directory\n");
157 goto err_umem;
158 }
159
160 /* Ring state is always the first page. Set in library for user cq. */
161 if (cq->is_kernel)
162 cq->ring_state = cq->pdir.pages[0];
163 else
164 pvrdma_page_dir_insert_umem(&cq->pdir, cq->umem, 0);
165
166 atomic_set(&cq->refcnt, 1);
167 init_waitqueue_head(&cq->wait);
168 spin_lock_init(&cq->cq_lock);
169
170 memset(cmd, 0, sizeof(*cmd));
171 cmd->hdr.cmd = PVRDMA_CMD_CREATE_CQ;
172 cmd->nchunks = npages;
173 cmd->ctx_handle = (context) ?
174 (u64)to_vucontext(context)->ctx_handle : 0;
175 cmd->cqe = entries;
176 cmd->pdir_dma = cq->pdir.dir_dma;
177 ret = pvrdma_cmd_post(dev, &req, &rsp, PVRDMA_CMD_CREATE_CQ_RESP);
178 if (ret < 0) {
179 dev_warn(&dev->pdev->dev,
180 "could not create completion queue, error: %d\n", ret);
181 goto err_page_dir;
182 }
183
184 cq->ibcq.cqe = resp->cqe;
185 cq->cq_handle = resp->cq_handle;
186 spin_lock_irqsave(&dev->cq_tbl_lock, flags);
187 dev->cq_tbl[cq->cq_handle % dev->dsr->caps.max_cq] = cq;
188 spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
189
190 if (context) {
191 cq->uar = &(to_vucontext(context)->uar);
192
193 /* Copy udata back. */
194 if (ib_copy_to_udata(udata, &cq->cq_handle, sizeof(__u32))) {
195 dev_warn(&dev->pdev->dev,
196 "failed to copy back udata\n");
197 pvrdma_destroy_cq(&cq->ibcq);
198 return ERR_PTR(-EINVAL);
199 }
200 }
201
202 return &cq->ibcq;
203
204err_page_dir:
205 pvrdma_page_dir_cleanup(dev, &cq->pdir);
206err_umem:
207 if (context)
208 ib_umem_release(cq->umem);
209err_cq:
210 atomic_dec(&dev->num_cqs);
211 kfree(cq);
212
213 return ERR_PTR(ret);
214}
215
216static void pvrdma_free_cq(struct pvrdma_dev *dev, struct pvrdma_cq *cq)
217{
218 atomic_dec(&cq->refcnt);
219 wait_event(cq->wait, !atomic_read(&cq->refcnt));
220
221 if (!cq->is_kernel)
222 ib_umem_release(cq->umem);
223
224 pvrdma_page_dir_cleanup(dev, &cq->pdir);
225 kfree(cq);
226}
227
228/**
229 * pvrdma_destroy_cq - destroy completion queue
230 * @cq: the completion queue to destroy.
231 *
232 * @return: 0 for success.
233 */
234int pvrdma_destroy_cq(struct ib_cq *cq)
235{
236 struct pvrdma_cq *vcq = to_vcq(cq);
237 union pvrdma_cmd_req req;
238 struct pvrdma_cmd_destroy_cq *cmd = &req.destroy_cq;
239 struct pvrdma_dev *dev = to_vdev(cq->device);
240 unsigned long flags;
241 int ret;
242
243 memset(cmd, 0, sizeof(*cmd));
244 cmd->hdr.cmd = PVRDMA_CMD_DESTROY_CQ;
245 cmd->cq_handle = vcq->cq_handle;
246
247 ret = pvrdma_cmd_post(dev, &req, NULL, 0);
248 if (ret < 0)
249 dev_warn(&dev->pdev->dev,
250 "could not destroy completion queue, error: %d\n",
251 ret);
252
253 /* free cq's resources */
254 spin_lock_irqsave(&dev->cq_tbl_lock, flags);
255 dev->cq_tbl[vcq->cq_handle] = NULL;
256 spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
257
258 pvrdma_free_cq(dev, vcq);
259 atomic_dec(&dev->num_cqs);
260
261 return ret;
262}
263
264/**
265 * pvrdma_modify_cq - modify the CQ moderation parameters
266 * @ibcq: the CQ to modify
267 * @cq_count: number of CQEs that will trigger an event
268 * @cq_period: max period of time in usec before triggering an event
269 *
270 * @return: -EOPNOTSUPP as CQ resize is not supported.
271 */
272int pvrdma_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
273{
274 return -EOPNOTSUPP;
275}
276
277static inline struct pvrdma_cqe *get_cqe(struct pvrdma_cq *cq, int i)
278{
279 return (struct pvrdma_cqe *)pvrdma_page_dir_get_ptr(
280 &cq->pdir,
281 cq->offset +
282 sizeof(struct pvrdma_cqe) * i);
283}
284
285void _pvrdma_flush_cqe(struct pvrdma_qp *qp, struct pvrdma_cq *cq)
286{
287 int head;
288 int has_data;
289
290 if (!cq->is_kernel)
291 return;
292
293 /* Lock held */
294 has_data = pvrdma_idx_ring_has_data(&cq->ring_state->rx,
295 cq->ibcq.cqe, &head);
296 if (unlikely(has_data > 0)) {
297 int items;
298 int curr;
299 int tail = pvrdma_idx(&cq->ring_state->rx.prod_tail,
300 cq->ibcq.cqe);
301 struct pvrdma_cqe *cqe;
302 struct pvrdma_cqe *curr_cqe;
303
304 items = (tail > head) ? (tail - head) :
305 (cq->ibcq.cqe - head + tail);
306 curr = --tail;
307 while (items-- > 0) {
308 if (curr < 0)
309 curr = cq->ibcq.cqe - 1;
310 if (tail < 0)
311 tail = cq->ibcq.cqe - 1;
312 curr_cqe = get_cqe(cq, curr);
313 if ((curr_cqe->qp & 0xFFFF) != qp->qp_handle) {
314 if (curr != tail) {
315 cqe = get_cqe(cq, tail);
316 *cqe = *curr_cqe;
317 }
318 tail--;
319 } else {
320 pvrdma_idx_ring_inc(
321 &cq->ring_state->rx.cons_head,
322 cq->ibcq.cqe);
323 }
324 curr--;
325 }
326 }
327}
328
329static int pvrdma_poll_one(struct pvrdma_cq *cq, struct pvrdma_qp **cur_qp,
330 struct ib_wc *wc)
331{
332 struct pvrdma_dev *dev = to_vdev(cq->ibcq.device);
333 int has_data;
334 unsigned int head;
335 bool tried = false;
336 struct pvrdma_cqe *cqe;
337
338retry:
339 has_data = pvrdma_idx_ring_has_data(&cq->ring_state->rx,
340 cq->ibcq.cqe, &head);
341 if (has_data == 0) {
342 if (tried)
343 return -EAGAIN;
344
345 pvrdma_write_uar_cq(dev, cq->cq_handle | PVRDMA_UAR_CQ_POLL);
346
347 tried = true;
348 goto retry;
349 } else if (has_data == PVRDMA_INVALID_IDX) {
350 dev_err(&dev->pdev->dev, "CQ ring state invalid\n");
351 return -EAGAIN;
352 }
353
354 cqe = get_cqe(cq, head);
355
356 /* Ensure cqe is valid. */
357 rmb();
358 if (dev->qp_tbl[cqe->qp & 0xffff])
359 *cur_qp = (struct pvrdma_qp *)dev->qp_tbl[cqe->qp & 0xffff];
360 else
361 return -EAGAIN;
362
363 wc->opcode = pvrdma_wc_opcode_to_ib(cqe->opcode);
364 wc->status = pvrdma_wc_status_to_ib(cqe->status);
365 wc->wr_id = cqe->wr_id;
366 wc->qp = &(*cur_qp)->ibqp;
367 wc->byte_len = cqe->byte_len;
368 wc->ex.imm_data = cqe->imm_data;
369 wc->src_qp = cqe->src_qp;
370 wc->wc_flags = pvrdma_wc_flags_to_ib(cqe->wc_flags);
371 wc->pkey_index = cqe->pkey_index;
372 wc->slid = cqe->slid;
373 wc->sl = cqe->sl;
374 wc->dlid_path_bits = cqe->dlid_path_bits;
375 wc->port_num = cqe->port_num;
376 wc->vendor_err = 0;
377
378 /* Update shared ring state */
379 pvrdma_idx_ring_inc(&cq->ring_state->rx.cons_head, cq->ibcq.cqe);
380
381 return 0;
382}
383
384/**
385 * pvrdma_poll_cq - poll for work completion queue entries
386 * @ibcq: completion queue
387 * @num_entries: the maximum number of entries
388 * @entry: pointer to work completion array
389 *
390 * @return: number of polled completion entries
391 */
392int pvrdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
393{
394 struct pvrdma_cq *cq = to_vcq(ibcq);
395 struct pvrdma_qp *cur_qp = NULL;
396 unsigned long flags;
397 int npolled;
398
399 if (num_entries < 1 || wc == NULL)
400 return 0;
401
402 spin_lock_irqsave(&cq->cq_lock, flags);
403 for (npolled = 0; npolled < num_entries; ++npolled) {
404 if (pvrdma_poll_one(cq, &cur_qp, wc + npolled))
405 break;
406 }
407
408 spin_unlock_irqrestore(&cq->cq_lock, flags);
409
410 /* Ensure we do not return errors from poll_cq */
411 return npolled;
412}
413
414/**
415 * pvrdma_resize_cq - resize CQ
416 * @ibcq: the completion queue
417 * @entries: CQ entries
418 * @udata: user data
419 *
420 * @return: -EOPNOTSUPP as CQ resize is not supported.
421 */
422int pvrdma_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
423{
424 return -EOPNOTSUPP;
425}
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h
new file mode 100644
index 000000000000..c06768635d65
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h
@@ -0,0 +1,586 @@
1/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#ifndef __PVRDMA_DEV_API_H__
47#define __PVRDMA_DEV_API_H__
48
49#include <linux/types.h>
50
51#include "pvrdma_verbs.h"
52
53#define PVRDMA_VERSION 17
54#define PVRDMA_BOARD_ID 1
55#define PVRDMA_REV_ID 1
56
57/*
58 * Masks and accessors for page directory, which is a two-level lookup:
59 * page directory -> page table -> page. Only one directory for now, but we
60 * could expand that easily. 9 bits for tables, 9 bits for pages, gives one
61 * gigabyte for memory regions and so forth.
62 */
63
64#define PVRDMA_PDIR_SHIFT 18
65#define PVRDMA_PTABLE_SHIFT 9
66#define PVRDMA_PAGE_DIR_DIR(x) (((x) >> PVRDMA_PDIR_SHIFT) & 0x1)
67#define PVRDMA_PAGE_DIR_TABLE(x) (((x) >> PVRDMA_PTABLE_SHIFT) & 0x1ff)
68#define PVRDMA_PAGE_DIR_PAGE(x) ((x) & 0x1ff)
69#define PVRDMA_PAGE_DIR_MAX_PAGES (1 * 512 * 512)
70#define PVRDMA_MAX_FAST_REG_PAGES 128
71
72/*
73 * Max MSI-X vectors.
74 */
75
76#define PVRDMA_MAX_INTERRUPTS 3
77
78/* Register offsets within PCI resource on BAR1. */
79#define PVRDMA_REG_VERSION 0x00 /* R: Version of device. */
80#define PVRDMA_REG_DSRLOW 0x04 /* W: Device shared region low PA. */
81#define PVRDMA_REG_DSRHIGH 0x08 /* W: Device shared region high PA. */
82#define PVRDMA_REG_CTL 0x0c /* W: PVRDMA_DEVICE_CTL */
83#define PVRDMA_REG_REQUEST 0x10 /* W: Indicate device request. */
84#define PVRDMA_REG_ERR 0x14 /* R: Device error. */
85#define PVRDMA_REG_ICR 0x18 /* R: Interrupt cause. */
86#define PVRDMA_REG_IMR 0x1c /* R/W: Interrupt mask. */
87#define PVRDMA_REG_MACL 0x20 /* R/W: MAC address low. */
88#define PVRDMA_REG_MACH 0x24 /* R/W: MAC address high. */
89
90/* Object flags. */
91#define PVRDMA_CQ_FLAG_ARMED_SOL BIT(0) /* Armed for solicited-only. */
92#define PVRDMA_CQ_FLAG_ARMED BIT(1) /* Armed. */
93#define PVRDMA_MR_FLAG_DMA BIT(0) /* DMA region. */
94#define PVRDMA_MR_FLAG_FRMR BIT(1) /* Fast reg memory region. */
95
96/*
97 * Atomic operation capability (masked versions are extended atomic
98 * operations.
99 */
100
101#define PVRDMA_ATOMIC_OP_COMP_SWAP BIT(0) /* Compare and swap. */
102#define PVRDMA_ATOMIC_OP_FETCH_ADD BIT(1) /* Fetch and add. */
103#define PVRDMA_ATOMIC_OP_MASK_COMP_SWAP BIT(2) /* Masked compare and swap. */
104#define PVRDMA_ATOMIC_OP_MASK_FETCH_ADD BIT(3) /* Masked fetch and add. */
105
106/*
107 * Base Memory Management Extension flags to support Fast Reg Memory Regions
108 * and Fast Reg Work Requests. Each flag represents a verb operation and we
109 * must support all of them to qualify for the BMME device cap.
110 */
111
112#define PVRDMA_BMME_FLAG_LOCAL_INV BIT(0) /* Local Invalidate. */
113#define PVRDMA_BMME_FLAG_REMOTE_INV BIT(1) /* Remote Invalidate. */
114#define PVRDMA_BMME_FLAG_FAST_REG_WR BIT(2) /* Fast Reg Work Request. */
115
116/*
117 * GID types. The interpretation of the gid_types bit field in the device
118 * capabilities will depend on the device mode. For now, the device only
119 * supports RoCE as mode, so only the different GID types for RoCE are
120 * defined.
121 */
122
123#define PVRDMA_GID_TYPE_FLAG_ROCE_V1 BIT(0)
124#define PVRDMA_GID_TYPE_FLAG_ROCE_V2 BIT(1)
125
126enum pvrdma_pci_resource {
127 PVRDMA_PCI_RESOURCE_MSIX, /* BAR0: MSI-X, MMIO. */
128 PVRDMA_PCI_RESOURCE_REG, /* BAR1: Registers, MMIO. */
129 PVRDMA_PCI_RESOURCE_UAR, /* BAR2: UAR pages, MMIO, 64-bit. */
130 PVRDMA_PCI_RESOURCE_LAST, /* Last. */
131};
132
133enum pvrdma_device_ctl {
134 PVRDMA_DEVICE_CTL_ACTIVATE, /* Activate device. */
135 PVRDMA_DEVICE_CTL_QUIESCE, /* Quiesce device. */
136 PVRDMA_DEVICE_CTL_RESET, /* Reset device. */
137};
138
139enum pvrdma_intr_vector {
140 PVRDMA_INTR_VECTOR_RESPONSE, /* Command response. */
141 PVRDMA_INTR_VECTOR_ASYNC, /* Async events. */
142 PVRDMA_INTR_VECTOR_CQ, /* CQ notification. */
143 /* Additional CQ notification vectors. */
144};
145
146enum pvrdma_intr_cause {
147 PVRDMA_INTR_CAUSE_RESPONSE = (1 << PVRDMA_INTR_VECTOR_RESPONSE),
148 PVRDMA_INTR_CAUSE_ASYNC = (1 << PVRDMA_INTR_VECTOR_ASYNC),
149 PVRDMA_INTR_CAUSE_CQ = (1 << PVRDMA_INTR_VECTOR_CQ),
150};
151
152enum pvrdma_intr_type {
153 PVRDMA_INTR_TYPE_INTX, /* Legacy. */
154 PVRDMA_INTR_TYPE_MSI, /* MSI. */
155 PVRDMA_INTR_TYPE_MSIX, /* MSI-X. */
156};
157
158enum pvrdma_gos_bits {
159 PVRDMA_GOS_BITS_UNK, /* Unknown. */
160 PVRDMA_GOS_BITS_32, /* 32-bit. */
161 PVRDMA_GOS_BITS_64, /* 64-bit. */
162};
163
164enum pvrdma_gos_type {
165 PVRDMA_GOS_TYPE_UNK, /* Unknown. */
166 PVRDMA_GOS_TYPE_LINUX, /* Linux. */
167};
168
169enum pvrdma_device_mode {
170 PVRDMA_DEVICE_MODE_ROCE, /* RoCE. */
171 PVRDMA_DEVICE_MODE_IWARP, /* iWarp. */
172 PVRDMA_DEVICE_MODE_IB, /* InfiniBand. */
173};
174
175struct pvrdma_gos_info {
176 u32 gos_bits:2; /* W: PVRDMA_GOS_BITS_ */
177 u32 gos_type:4; /* W: PVRDMA_GOS_TYPE_ */
178 u32 gos_ver:16; /* W: Guest OS version. */
179 u32 gos_misc:10; /* W: Other. */
180 u32 pad; /* Pad to 8-byte alignment. */
181};
182
183struct pvrdma_device_caps {
184 u64 fw_ver; /* R: Query device. */
185 __be64 node_guid;
186 __be64 sys_image_guid;
187 u64 max_mr_size;
188 u64 page_size_cap;
189 u64 atomic_arg_sizes; /* EX verbs. */
190 u32 ex_comp_mask; /* EX verbs. */
191 u32 device_cap_flags2; /* EX verbs. */
192 u32 max_fa_bit_boundary; /* EX verbs. */
193 u32 log_max_atomic_inline_arg; /* EX verbs. */
194 u32 vendor_id;
195 u32 vendor_part_id;
196 u32 hw_ver;
197 u32 max_qp;
198 u32 max_qp_wr;
199 u32 device_cap_flags;
200 u32 max_sge;
201 u32 max_sge_rd;
202 u32 max_cq;
203 u32 max_cqe;
204 u32 max_mr;
205 u32 max_pd;
206 u32 max_qp_rd_atom;
207 u32 max_ee_rd_atom;
208 u32 max_res_rd_atom;
209 u32 max_qp_init_rd_atom;
210 u32 max_ee_init_rd_atom;
211 u32 max_ee;
212 u32 max_rdd;
213 u32 max_mw;
214 u32 max_raw_ipv6_qp;
215 u32 max_raw_ethy_qp;
216 u32 max_mcast_grp;
217 u32 max_mcast_qp_attach;
218 u32 max_total_mcast_qp_attach;
219 u32 max_ah;
220 u32 max_fmr;
221 u32 max_map_per_fmr;
222 u32 max_srq;
223 u32 max_srq_wr;
224 u32 max_srq_sge;
225 u32 max_uar;
226 u32 gid_tbl_len;
227 u16 max_pkeys;
228 u8 local_ca_ack_delay;
229 u8 phys_port_cnt;
230 u8 mode; /* PVRDMA_DEVICE_MODE_ */
231 u8 atomic_ops; /* PVRDMA_ATOMIC_OP_* bits */
232 u8 bmme_flags; /* FRWR Mem Mgmt Extensions */
233 u8 gid_types; /* PVRDMA_GID_TYPE_FLAG_ */
234 u8 reserved[4];
235};
236
237struct pvrdma_ring_page_info {
238 u32 num_pages; /* Num pages incl. header. */
239 u32 reserved; /* Reserved. */
240 u64 pdir_dma; /* Page directory PA. */
241};
242
243#pragma pack(push, 1)
244
245struct pvrdma_device_shared_region {
246 u32 driver_version; /* W: Driver version. */
247 u32 pad; /* Pad to 8-byte align. */
248 struct pvrdma_gos_info gos_info; /* W: Guest OS information. */
249 u64 cmd_slot_dma; /* W: Command slot address. */
250 u64 resp_slot_dma; /* W: Response slot address. */
251 struct pvrdma_ring_page_info async_ring_pages;
252 /* W: Async ring page info. */
253 struct pvrdma_ring_page_info cq_ring_pages;
254 /* W: CQ ring page info. */
255 u32 uar_pfn; /* W: UAR pageframe. */
256 u32 pad2; /* Pad to 8-byte align. */
257 struct pvrdma_device_caps caps; /* R: Device capabilities. */
258};
259
260#pragma pack(pop)
261
262/* Event types. Currently a 1:1 mapping with enum ib_event. */
263enum pvrdma_eqe_type {
264 PVRDMA_EVENT_CQ_ERR,
265 PVRDMA_EVENT_QP_FATAL,
266 PVRDMA_EVENT_QP_REQ_ERR,
267 PVRDMA_EVENT_QP_ACCESS_ERR,
268 PVRDMA_EVENT_COMM_EST,
269 PVRDMA_EVENT_SQ_DRAINED,
270 PVRDMA_EVENT_PATH_MIG,
271 PVRDMA_EVENT_PATH_MIG_ERR,
272 PVRDMA_EVENT_DEVICE_FATAL,
273 PVRDMA_EVENT_PORT_ACTIVE,
274 PVRDMA_EVENT_PORT_ERR,
275 PVRDMA_EVENT_LID_CHANGE,
276 PVRDMA_EVENT_PKEY_CHANGE,
277 PVRDMA_EVENT_SM_CHANGE,
278 PVRDMA_EVENT_SRQ_ERR,
279 PVRDMA_EVENT_SRQ_LIMIT_REACHED,
280 PVRDMA_EVENT_QP_LAST_WQE_REACHED,
281 PVRDMA_EVENT_CLIENT_REREGISTER,
282 PVRDMA_EVENT_GID_CHANGE,
283};
284
285/* Event queue element. */
286struct pvrdma_eqe {
287 u32 type; /* Event type. */
288 u32 info; /* Handle, other. */
289};
290
291/* CQ notification queue element. */
292struct pvrdma_cqne {
293 u32 info; /* Handle */
294};
295
296enum {
297 PVRDMA_CMD_FIRST,
298 PVRDMA_CMD_QUERY_PORT = PVRDMA_CMD_FIRST,
299 PVRDMA_CMD_QUERY_PKEY,
300 PVRDMA_CMD_CREATE_PD,
301 PVRDMA_CMD_DESTROY_PD,
302 PVRDMA_CMD_CREATE_MR,
303 PVRDMA_CMD_DESTROY_MR,
304 PVRDMA_CMD_CREATE_CQ,
305 PVRDMA_CMD_RESIZE_CQ,
306 PVRDMA_CMD_DESTROY_CQ,
307 PVRDMA_CMD_CREATE_QP,
308 PVRDMA_CMD_MODIFY_QP,
309 PVRDMA_CMD_QUERY_QP,
310 PVRDMA_CMD_DESTROY_QP,
311 PVRDMA_CMD_CREATE_UC,
312 PVRDMA_CMD_DESTROY_UC,
313 PVRDMA_CMD_CREATE_BIND,
314 PVRDMA_CMD_DESTROY_BIND,
315 PVRDMA_CMD_MAX,
316};
317
318enum {
319 PVRDMA_CMD_FIRST_RESP = (1 << 31),
320 PVRDMA_CMD_QUERY_PORT_RESP = PVRDMA_CMD_FIRST_RESP,
321 PVRDMA_CMD_QUERY_PKEY_RESP,
322 PVRDMA_CMD_CREATE_PD_RESP,
323 PVRDMA_CMD_DESTROY_PD_RESP_NOOP,
324 PVRDMA_CMD_CREATE_MR_RESP,
325 PVRDMA_CMD_DESTROY_MR_RESP_NOOP,
326 PVRDMA_CMD_CREATE_CQ_RESP,
327 PVRDMA_CMD_RESIZE_CQ_RESP,
328 PVRDMA_CMD_DESTROY_CQ_RESP_NOOP,
329 PVRDMA_CMD_CREATE_QP_RESP,
330 PVRDMA_CMD_MODIFY_QP_RESP,
331 PVRDMA_CMD_QUERY_QP_RESP,
332 PVRDMA_CMD_DESTROY_QP_RESP,
333 PVRDMA_CMD_CREATE_UC_RESP,
334 PVRDMA_CMD_DESTROY_UC_RESP_NOOP,
335 PVRDMA_CMD_CREATE_BIND_RESP_NOOP,
336 PVRDMA_CMD_DESTROY_BIND_RESP_NOOP,
337 PVRDMA_CMD_MAX_RESP,
338};
339
340struct pvrdma_cmd_hdr {
341 u64 response; /* Key for response lookup. */
342 u32 cmd; /* PVRDMA_CMD_ */
343 u32 reserved; /* Reserved. */
344};
345
346struct pvrdma_cmd_resp_hdr {
347 u64 response; /* From cmd hdr. */
348 u32 ack; /* PVRDMA_CMD_XXX_RESP */
349 u8 err; /* Error. */
350 u8 reserved[3]; /* Reserved. */
351};
352
353struct pvrdma_cmd_query_port {
354 struct pvrdma_cmd_hdr hdr;
355 u8 port_num;
356 u8 reserved[7];
357};
358
359struct pvrdma_cmd_query_port_resp {
360 struct pvrdma_cmd_resp_hdr hdr;
361 struct pvrdma_port_attr attrs;
362};
363
364struct pvrdma_cmd_query_pkey {
365 struct pvrdma_cmd_hdr hdr;
366 u8 port_num;
367 u8 index;
368 u8 reserved[6];
369};
370
371struct pvrdma_cmd_query_pkey_resp {
372 struct pvrdma_cmd_resp_hdr hdr;
373 u16 pkey;
374 u8 reserved[6];
375};
376
377struct pvrdma_cmd_create_uc {
378 struct pvrdma_cmd_hdr hdr;
379 u32 pfn; /* UAR page frame number */
380 u8 reserved[4];
381};
382
383struct pvrdma_cmd_create_uc_resp {
384 struct pvrdma_cmd_resp_hdr hdr;
385 u32 ctx_handle;
386 u8 reserved[4];
387};
388
389struct pvrdma_cmd_destroy_uc {
390 struct pvrdma_cmd_hdr hdr;
391 u32 ctx_handle;
392 u8 reserved[4];
393};
394
395struct pvrdma_cmd_create_pd {
396 struct pvrdma_cmd_hdr hdr;
397 u32 ctx_handle;
398 u8 reserved[4];
399};
400
401struct pvrdma_cmd_create_pd_resp {
402 struct pvrdma_cmd_resp_hdr hdr;
403 u32 pd_handle;
404 u8 reserved[4];
405};
406
407struct pvrdma_cmd_destroy_pd {
408 struct pvrdma_cmd_hdr hdr;
409 u32 pd_handle;
410 u8 reserved[4];
411};
412
413struct pvrdma_cmd_create_mr {
414 struct pvrdma_cmd_hdr hdr;
415 u64 start;
416 u64 length;
417 u64 pdir_dma;
418 u32 pd_handle;
419 u32 access_flags;
420 u32 flags;
421 u32 nchunks;
422};
423
424struct pvrdma_cmd_create_mr_resp {
425 struct pvrdma_cmd_resp_hdr hdr;
426 u32 mr_handle;
427 u32 lkey;
428 u32 rkey;
429 u8 reserved[4];
430};
431
432struct pvrdma_cmd_destroy_mr {
433 struct pvrdma_cmd_hdr hdr;
434 u32 mr_handle;
435 u8 reserved[4];
436};
437
438struct pvrdma_cmd_create_cq {
439 struct pvrdma_cmd_hdr hdr;
440 u64 pdir_dma;
441 u32 ctx_handle;
442 u32 cqe;
443 u32 nchunks;
444 u8 reserved[4];
445};
446
447struct pvrdma_cmd_create_cq_resp {
448 struct pvrdma_cmd_resp_hdr hdr;
449 u32 cq_handle;
450 u32 cqe;
451};
452
453struct pvrdma_cmd_resize_cq {
454 struct pvrdma_cmd_hdr hdr;
455 u32 cq_handle;
456 u32 cqe;
457};
458
459struct pvrdma_cmd_resize_cq_resp {
460 struct pvrdma_cmd_resp_hdr hdr;
461 u32 cqe;
462 u8 reserved[4];
463};
464
465struct pvrdma_cmd_destroy_cq {
466 struct pvrdma_cmd_hdr hdr;
467 u32 cq_handle;
468 u8 reserved[4];
469};
470
471struct pvrdma_cmd_create_qp {
472 struct pvrdma_cmd_hdr hdr;
473 u64 pdir_dma;
474 u32 pd_handle;
475 u32 send_cq_handle;
476 u32 recv_cq_handle;
477 u32 srq_handle;
478 u32 max_send_wr;
479 u32 max_recv_wr;
480 u32 max_send_sge;
481 u32 max_recv_sge;
482 u32 max_inline_data;
483 u32 lkey;
484 u32 access_flags;
485 u16 total_chunks;
486 u16 send_chunks;
487 u16 max_atomic_arg;
488 u8 sq_sig_all;
489 u8 qp_type;
490 u8 is_srq;
491 u8 reserved[3];
492};
493
494struct pvrdma_cmd_create_qp_resp {
495 struct pvrdma_cmd_resp_hdr hdr;
496 u32 qpn;
497 u32 max_send_wr;
498 u32 max_recv_wr;
499 u32 max_send_sge;
500 u32 max_recv_sge;
501 u32 max_inline_data;
502};
503
504struct pvrdma_cmd_modify_qp {
505 struct pvrdma_cmd_hdr hdr;
506 u32 qp_handle;
507 u32 attr_mask;
508 struct pvrdma_qp_attr attrs;
509};
510
511struct pvrdma_cmd_query_qp {
512 struct pvrdma_cmd_hdr hdr;
513 u32 qp_handle;
514 u32 attr_mask;
515};
516
517struct pvrdma_cmd_query_qp_resp {
518 struct pvrdma_cmd_resp_hdr hdr;
519 struct pvrdma_qp_attr attrs;
520};
521
522struct pvrdma_cmd_destroy_qp {
523 struct pvrdma_cmd_hdr hdr;
524 u32 qp_handle;
525 u8 reserved[4];
526};
527
528struct pvrdma_cmd_destroy_qp_resp {
529 struct pvrdma_cmd_resp_hdr hdr;
530 u32 events_reported;
531 u8 reserved[4];
532};
533
534struct pvrdma_cmd_create_bind {
535 struct pvrdma_cmd_hdr hdr;
536 u32 mtu;
537 u32 vlan;
538 u32 index;
539 u8 new_gid[16];
540 u8 gid_type;
541 u8 reserved[3];
542};
543
544struct pvrdma_cmd_destroy_bind {
545 struct pvrdma_cmd_hdr hdr;
546 u32 index;
547 u8 dest_gid[16];
548 u8 reserved[4];
549};
550
551union pvrdma_cmd_req {
552 struct pvrdma_cmd_hdr hdr;
553 struct pvrdma_cmd_query_port query_port;
554 struct pvrdma_cmd_query_pkey query_pkey;
555 struct pvrdma_cmd_create_uc create_uc;
556 struct pvrdma_cmd_destroy_uc destroy_uc;
557 struct pvrdma_cmd_create_pd create_pd;
558 struct pvrdma_cmd_destroy_pd destroy_pd;
559 struct pvrdma_cmd_create_mr create_mr;
560 struct pvrdma_cmd_destroy_mr destroy_mr;
561 struct pvrdma_cmd_create_cq create_cq;
562 struct pvrdma_cmd_resize_cq resize_cq;
563 struct pvrdma_cmd_destroy_cq destroy_cq;
564 struct pvrdma_cmd_create_qp create_qp;
565 struct pvrdma_cmd_modify_qp modify_qp;
566 struct pvrdma_cmd_query_qp query_qp;
567 struct pvrdma_cmd_destroy_qp destroy_qp;
568 struct pvrdma_cmd_create_bind create_bind;
569 struct pvrdma_cmd_destroy_bind destroy_bind;
570};
571
572union pvrdma_cmd_resp {
573 struct pvrdma_cmd_resp_hdr hdr;
574 struct pvrdma_cmd_query_port_resp query_port_resp;
575 struct pvrdma_cmd_query_pkey_resp query_pkey_resp;
576 struct pvrdma_cmd_create_uc_resp create_uc_resp;
577 struct pvrdma_cmd_create_pd_resp create_pd_resp;
578 struct pvrdma_cmd_create_mr_resp create_mr_resp;
579 struct pvrdma_cmd_create_cq_resp create_cq_resp;
580 struct pvrdma_cmd_resize_cq_resp resize_cq_resp;
581 struct pvrdma_cmd_create_qp_resp create_qp_resp;
582 struct pvrdma_cmd_query_qp_resp query_qp_resp;
583 struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp;
584};
585
586#endif /* __PVRDMA_DEV_API_H__ */
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_doorbell.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_doorbell.c
new file mode 100644
index 000000000000..bf51357ea3aa
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_doorbell.c
@@ -0,0 +1,127 @@
1/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#include <linux/bitmap.h>
47#include <linux/errno.h>
48#include <linux/slab.h>
49
50#include "pvrdma.h"
51
52int pvrdma_uar_table_init(struct pvrdma_dev *dev)
53{
54 u32 num = dev->dsr->caps.max_uar;
55 u32 mask = num - 1;
56 struct pvrdma_id_table *tbl = &dev->uar_table.tbl;
57
58 if (!is_power_of_2(num))
59 return -EINVAL;
60
61 tbl->last = 0;
62 tbl->top = 0;
63 tbl->max = num;
64 tbl->mask = mask;
65 spin_lock_init(&tbl->lock);
66 tbl->table = kcalloc(BITS_TO_LONGS(num), sizeof(long), GFP_KERNEL);
67 if (!tbl->table)
68 return -ENOMEM;
69
70 /* 0th UAR is taken by the device. */
71 set_bit(0, tbl->table);
72
73 return 0;
74}
75
76void pvrdma_uar_table_cleanup(struct pvrdma_dev *dev)
77{
78 struct pvrdma_id_table *tbl = &dev->uar_table.tbl;
79
80 kfree(tbl->table);
81}
82
83int pvrdma_uar_alloc(struct pvrdma_dev *dev, struct pvrdma_uar_map *uar)
84{
85 struct pvrdma_id_table *tbl;
86 unsigned long flags;
87 u32 obj;
88
89 tbl = &dev->uar_table.tbl;
90
91 spin_lock_irqsave(&tbl->lock, flags);
92 obj = find_next_zero_bit(tbl->table, tbl->max, tbl->last);
93 if (obj >= tbl->max) {
94 tbl->top = (tbl->top + tbl->max) & tbl->mask;
95 obj = find_first_zero_bit(tbl->table, tbl->max);
96 }
97
98 if (obj >= tbl->max) {
99 spin_unlock_irqrestore(&tbl->lock, flags);
100 return -ENOMEM;
101 }
102
103 set_bit(obj, tbl->table);
104 obj |= tbl->top;
105
106 spin_unlock_irqrestore(&tbl->lock, flags);
107
108 uar->index = obj;
109 uar->pfn = (pci_resource_start(dev->pdev, PVRDMA_PCI_RESOURCE_UAR) >>
110 PAGE_SHIFT) + uar->index;
111
112 return 0;
113}
114
115void pvrdma_uar_free(struct pvrdma_dev *dev, struct pvrdma_uar_map *uar)
116{
117 struct pvrdma_id_table *tbl = &dev->uar_table.tbl;
118 unsigned long flags;
119 u32 obj;
120
121 obj = uar->index & (tbl->max - 1);
122 spin_lock_irqsave(&tbl->lock, flags);
123 clear_bit(obj, tbl->table);
124 tbl->last = min(tbl->last, obj);
125 tbl->top = (tbl->top + tbl->max) & tbl->mask;
126 spin_unlock_irqrestore(&tbl->lock, flags);
127}
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c
new file mode 100644
index 000000000000..231a1ce1f4be
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c
@@ -0,0 +1,1211 @@
1/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#include <linux/errno.h>
47#include <linux/inetdevice.h>
48#include <linux/init.h>
49#include <linux/module.h>
50#include <linux/slab.h>
51#include <rdma/ib_addr.h>
52#include <rdma/ib_smi.h>
53#include <rdma/ib_user_verbs.h>
54#include <net/addrconf.h>
55
56#include "pvrdma.h"
57
58#define DRV_NAME "vmw_pvrdma"
59#define DRV_VERSION "1.0.0.0-k"
60
61static DEFINE_MUTEX(pvrdma_device_list_lock);
62static LIST_HEAD(pvrdma_device_list);
63static struct workqueue_struct *event_wq;
64
65static int pvrdma_add_gid(struct ib_device *ibdev,
66 u8 port_num,
67 unsigned int index,
68 const union ib_gid *gid,
69 const struct ib_gid_attr *attr,
70 void **context);
71static int pvrdma_del_gid(struct ib_device *ibdev,
72 u8 port_num,
73 unsigned int index,
74 void **context);
75
76
77static ssize_t show_hca(struct device *device, struct device_attribute *attr,
78 char *buf)
79{
80 return sprintf(buf, "VMW_PVRDMA-%s\n", DRV_VERSION);
81}
82
83static ssize_t show_rev(struct device *device, struct device_attribute *attr,
84 char *buf)
85{
86 return sprintf(buf, "%d\n", PVRDMA_REV_ID);
87}
88
89static ssize_t show_board(struct device *device, struct device_attribute *attr,
90 char *buf)
91{
92 return sprintf(buf, "%d\n", PVRDMA_BOARD_ID);
93}
94
95static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
96static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
97static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
98
99static struct device_attribute *pvrdma_class_attributes[] = {
100 &dev_attr_hw_rev,
101 &dev_attr_hca_type,
102 &dev_attr_board_id
103};
104
105static void pvrdma_get_fw_ver_str(struct ib_device *device, char *str,
106 size_t str_len)
107{
108 struct pvrdma_dev *dev =
109 container_of(device, struct pvrdma_dev, ib_dev);
110 snprintf(str, str_len, "%d.%d.%d\n",
111 (int) (dev->dsr->caps.fw_ver >> 32),
112 (int) (dev->dsr->caps.fw_ver >> 16) & 0xffff,
113 (int) dev->dsr->caps.fw_ver & 0xffff);
114}
115
116static int pvrdma_init_device(struct pvrdma_dev *dev)
117{
118 /* Initialize some device related stuff */
119 spin_lock_init(&dev->cmd_lock);
120 sema_init(&dev->cmd_sema, 1);
121 atomic_set(&dev->num_qps, 0);
122 atomic_set(&dev->num_cqs, 0);
123 atomic_set(&dev->num_pds, 0);
124 atomic_set(&dev->num_ahs, 0);
125
126 return 0;
127}
128
129static int pvrdma_port_immutable(struct ib_device *ibdev, u8 port_num,
130 struct ib_port_immutable *immutable)
131{
132 struct ib_port_attr attr;
133 int err;
134
135 err = pvrdma_query_port(ibdev, port_num, &attr);
136 if (err)
137 return err;
138
139 immutable->pkey_tbl_len = attr.pkey_tbl_len;
140 immutable->gid_tbl_len = attr.gid_tbl_len;
141 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
142 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
143 return 0;
144}
145
146static struct net_device *pvrdma_get_netdev(struct ib_device *ibdev,
147 u8 port_num)
148{
149 struct net_device *netdev;
150 struct pvrdma_dev *dev = to_vdev(ibdev);
151
152 if (port_num != 1)
153 return NULL;
154
155 rcu_read_lock();
156 netdev = dev->netdev;
157 if (netdev)
158 dev_hold(netdev);
159 rcu_read_unlock();
160
161 return netdev;
162}
163
164static int pvrdma_register_device(struct pvrdma_dev *dev)
165{
166 int ret = -1;
167 int i = 0;
168
169 strlcpy(dev->ib_dev.name, "vmw_pvrdma%d", IB_DEVICE_NAME_MAX);
170 dev->ib_dev.node_guid = dev->dsr->caps.node_guid;
171 dev->sys_image_guid = dev->dsr->caps.sys_image_guid;
172 dev->flags = 0;
173 dev->ib_dev.owner = THIS_MODULE;
174 dev->ib_dev.num_comp_vectors = 1;
175 dev->ib_dev.dma_device = &dev->pdev->dev;
176 dev->ib_dev.uverbs_abi_ver = PVRDMA_UVERBS_ABI_VERSION;
177 dev->ib_dev.uverbs_cmd_mask =
178 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
179 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
180 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
181 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
182 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
183 (1ull << IB_USER_VERBS_CMD_REG_MR) |
184 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
185 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
186 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
187 (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
188 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
189 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
190 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
191 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
192 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
193 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
194 (1ull << IB_USER_VERBS_CMD_POST_SEND) |
195 (1ull << IB_USER_VERBS_CMD_POST_RECV) |
196 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
197 (1ull << IB_USER_VERBS_CMD_DESTROY_AH);
198
199 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
200 dev->ib_dev.phys_port_cnt = dev->dsr->caps.phys_port_cnt;
201
202 dev->ib_dev.query_device = pvrdma_query_device;
203 dev->ib_dev.query_port = pvrdma_query_port;
204 dev->ib_dev.query_gid = pvrdma_query_gid;
205 dev->ib_dev.query_pkey = pvrdma_query_pkey;
206 dev->ib_dev.modify_port = pvrdma_modify_port;
207 dev->ib_dev.alloc_ucontext = pvrdma_alloc_ucontext;
208 dev->ib_dev.dealloc_ucontext = pvrdma_dealloc_ucontext;
209 dev->ib_dev.mmap = pvrdma_mmap;
210 dev->ib_dev.alloc_pd = pvrdma_alloc_pd;
211 dev->ib_dev.dealloc_pd = pvrdma_dealloc_pd;
212 dev->ib_dev.create_ah = pvrdma_create_ah;
213 dev->ib_dev.destroy_ah = pvrdma_destroy_ah;
214 dev->ib_dev.create_qp = pvrdma_create_qp;
215 dev->ib_dev.modify_qp = pvrdma_modify_qp;
216 dev->ib_dev.query_qp = pvrdma_query_qp;
217 dev->ib_dev.destroy_qp = pvrdma_destroy_qp;
218 dev->ib_dev.post_send = pvrdma_post_send;
219 dev->ib_dev.post_recv = pvrdma_post_recv;
220 dev->ib_dev.create_cq = pvrdma_create_cq;
221 dev->ib_dev.modify_cq = pvrdma_modify_cq;
222 dev->ib_dev.resize_cq = pvrdma_resize_cq;
223 dev->ib_dev.destroy_cq = pvrdma_destroy_cq;
224 dev->ib_dev.poll_cq = pvrdma_poll_cq;
225 dev->ib_dev.req_notify_cq = pvrdma_req_notify_cq;
226 dev->ib_dev.get_dma_mr = pvrdma_get_dma_mr;
227 dev->ib_dev.reg_user_mr = pvrdma_reg_user_mr;
228 dev->ib_dev.dereg_mr = pvrdma_dereg_mr;
229 dev->ib_dev.alloc_mr = pvrdma_alloc_mr;
230 dev->ib_dev.map_mr_sg = pvrdma_map_mr_sg;
231 dev->ib_dev.add_gid = pvrdma_add_gid;
232 dev->ib_dev.del_gid = pvrdma_del_gid;
233 dev->ib_dev.get_netdev = pvrdma_get_netdev;
234 dev->ib_dev.get_port_immutable = pvrdma_port_immutable;
235 dev->ib_dev.get_link_layer = pvrdma_port_link_layer;
236 dev->ib_dev.get_dev_fw_str = pvrdma_get_fw_ver_str;
237
238 mutex_init(&dev->port_mutex);
239 spin_lock_init(&dev->desc_lock);
240
241 dev->cq_tbl = kcalloc(dev->dsr->caps.max_cq, sizeof(void *),
242 GFP_KERNEL);
243 if (!dev->cq_tbl)
244 return ret;
245 spin_lock_init(&dev->cq_tbl_lock);
246
247 dev->qp_tbl = kcalloc(dev->dsr->caps.max_qp, sizeof(void *),
248 GFP_KERNEL);
249 if (!dev->qp_tbl)
250 goto err_cq_free;
251 spin_lock_init(&dev->qp_tbl_lock);
252
253 ret = ib_register_device(&dev->ib_dev, NULL);
254 if (ret)
255 goto err_qp_free;
256
257 for (i = 0; i < ARRAY_SIZE(pvrdma_class_attributes); ++i) {
258 ret = device_create_file(&dev->ib_dev.dev,
259 pvrdma_class_attributes[i]);
260 if (ret)
261 goto err_class;
262 }
263
264 dev->ib_active = true;
265
266 return 0;
267
268err_class:
269 ib_unregister_device(&dev->ib_dev);
270err_qp_free:
271 kfree(dev->qp_tbl);
272err_cq_free:
273 kfree(dev->cq_tbl);
274
275 return ret;
276}
277
278static irqreturn_t pvrdma_intr0_handler(int irq, void *dev_id)
279{
280 u32 icr = PVRDMA_INTR_CAUSE_RESPONSE;
281 struct pvrdma_dev *dev = dev_id;
282
283 dev_dbg(&dev->pdev->dev, "interrupt 0 (response) handler\n");
284
285 if (dev->intr.type != PVRDMA_INTR_TYPE_MSIX) {
286 /* Legacy intr */
287 icr = pvrdma_read_reg(dev, PVRDMA_REG_ICR);
288 if (icr == 0)
289 return IRQ_NONE;
290 }
291
292 if (icr == PVRDMA_INTR_CAUSE_RESPONSE)
293 complete(&dev->cmd_done);
294
295 return IRQ_HANDLED;
296}
297
298static void pvrdma_qp_event(struct pvrdma_dev *dev, u32 qpn, int type)
299{
300 struct pvrdma_qp *qp;
301 unsigned long flags;
302
303 spin_lock_irqsave(&dev->qp_tbl_lock, flags);
304 qp = dev->qp_tbl[qpn % dev->dsr->caps.max_qp];
305 if (qp)
306 atomic_inc(&qp->refcnt);
307 spin_unlock_irqrestore(&dev->qp_tbl_lock, flags);
308
309 if (qp && qp->ibqp.event_handler) {
310 struct ib_qp *ibqp = &qp->ibqp;
311 struct ib_event e;
312
313 e.device = ibqp->device;
314 e.element.qp = ibqp;
315 e.event = type; /* 1:1 mapping for now. */
316 ibqp->event_handler(&e, ibqp->qp_context);
317 }
318 if (qp) {
319 atomic_dec(&qp->refcnt);
320 if (atomic_read(&qp->refcnt) == 0)
321 wake_up(&qp->wait);
322 }
323}
324
325static void pvrdma_cq_event(struct pvrdma_dev *dev, u32 cqn, int type)
326{
327 struct pvrdma_cq *cq;
328 unsigned long flags;
329
330 spin_lock_irqsave(&dev->cq_tbl_lock, flags);
331 cq = dev->cq_tbl[cqn % dev->dsr->caps.max_cq];
332 if (cq)
333 atomic_inc(&cq->refcnt);
334 spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
335
336 if (cq && cq->ibcq.event_handler) {
337 struct ib_cq *ibcq = &cq->ibcq;
338 struct ib_event e;
339
340 e.device = ibcq->device;
341 e.element.cq = ibcq;
342 e.event = type; /* 1:1 mapping for now. */
343 ibcq->event_handler(&e, ibcq->cq_context);
344 }
345 if (cq) {
346 atomic_dec(&cq->refcnt);
347 if (atomic_read(&cq->refcnt) == 0)
348 wake_up(&cq->wait);
349 }
350}
351
352static void pvrdma_dispatch_event(struct pvrdma_dev *dev, int port,
353 enum ib_event_type event)
354{
355 struct ib_event ib_event;
356
357 memset(&ib_event, 0, sizeof(ib_event));
358 ib_event.device = &dev->ib_dev;
359 ib_event.element.port_num = port;
360 ib_event.event = event;
361 ib_dispatch_event(&ib_event);
362}
363
364static void pvrdma_dev_event(struct pvrdma_dev *dev, u8 port, int type)
365{
366 if (port < 1 || port > dev->dsr->caps.phys_port_cnt) {
367 dev_warn(&dev->pdev->dev, "event on port %d\n", port);
368 return;
369 }
370
371 pvrdma_dispatch_event(dev, port, type);
372}
373
374static inline struct pvrdma_eqe *get_eqe(struct pvrdma_dev *dev, unsigned int i)
375{
376 return (struct pvrdma_eqe *)pvrdma_page_dir_get_ptr(
377 &dev->async_pdir,
378 PAGE_SIZE +
379 sizeof(struct pvrdma_eqe) * i);
380}
381
382static irqreturn_t pvrdma_intr1_handler(int irq, void *dev_id)
383{
384 struct pvrdma_dev *dev = dev_id;
385 struct pvrdma_ring *ring = &dev->async_ring_state->rx;
386 int ring_slots = (dev->dsr->async_ring_pages.num_pages - 1) *
387 PAGE_SIZE / sizeof(struct pvrdma_eqe);
388 unsigned int head;
389
390 dev_dbg(&dev->pdev->dev, "interrupt 1 (async event) handler\n");
391
392 /*
393 * Don't process events until the IB device is registered. Otherwise
394 * we'll try to ib_dispatch_event() on an invalid device.
395 */
396 if (!dev->ib_active)
397 return IRQ_HANDLED;
398
399 while (pvrdma_idx_ring_has_data(ring, ring_slots, &head) > 0) {
400 struct pvrdma_eqe *eqe;
401
402 eqe = get_eqe(dev, head);
403
404 switch (eqe->type) {
405 case PVRDMA_EVENT_QP_FATAL:
406 case PVRDMA_EVENT_QP_REQ_ERR:
407 case PVRDMA_EVENT_QP_ACCESS_ERR:
408 case PVRDMA_EVENT_COMM_EST:
409 case PVRDMA_EVENT_SQ_DRAINED:
410 case PVRDMA_EVENT_PATH_MIG:
411 case PVRDMA_EVENT_PATH_MIG_ERR:
412 case PVRDMA_EVENT_QP_LAST_WQE_REACHED:
413 pvrdma_qp_event(dev, eqe->info, eqe->type);
414 break;
415
416 case PVRDMA_EVENT_CQ_ERR:
417 pvrdma_cq_event(dev, eqe->info, eqe->type);
418 break;
419
420 case PVRDMA_EVENT_SRQ_ERR:
421 case PVRDMA_EVENT_SRQ_LIMIT_REACHED:
422 break;
423
424 case PVRDMA_EVENT_PORT_ACTIVE:
425 case PVRDMA_EVENT_PORT_ERR:
426 case PVRDMA_EVENT_LID_CHANGE:
427 case PVRDMA_EVENT_PKEY_CHANGE:
428 case PVRDMA_EVENT_SM_CHANGE:
429 case PVRDMA_EVENT_CLIENT_REREGISTER:
430 case PVRDMA_EVENT_GID_CHANGE:
431 pvrdma_dev_event(dev, eqe->info, eqe->type);
432 break;
433
434 case PVRDMA_EVENT_DEVICE_FATAL:
435 pvrdma_dev_event(dev, 1, eqe->type);
436 break;
437
438 default:
439 break;
440 }
441
442 pvrdma_idx_ring_inc(&ring->cons_head, ring_slots);
443 }
444
445 return IRQ_HANDLED;
446}
447
448static inline struct pvrdma_cqne *get_cqne(struct pvrdma_dev *dev,
449 unsigned int i)
450{
451 return (struct pvrdma_cqne *)pvrdma_page_dir_get_ptr(
452 &dev->cq_pdir,
453 PAGE_SIZE +
454 sizeof(struct pvrdma_cqne) * i);
455}
456
457static irqreturn_t pvrdma_intrx_handler(int irq, void *dev_id)
458{
459 struct pvrdma_dev *dev = dev_id;
460 struct pvrdma_ring *ring = &dev->cq_ring_state->rx;
461 int ring_slots = (dev->dsr->cq_ring_pages.num_pages - 1) * PAGE_SIZE /
462 sizeof(struct pvrdma_cqne);
463 unsigned int head;
464 unsigned long flags;
465
466 dev_dbg(&dev->pdev->dev, "interrupt x (completion) handler\n");
467
468 while (pvrdma_idx_ring_has_data(ring, ring_slots, &head) > 0) {
469 struct pvrdma_cqne *cqne;
470 struct pvrdma_cq *cq;
471
472 cqne = get_cqne(dev, head);
473 spin_lock_irqsave(&dev->cq_tbl_lock, flags);
474 cq = dev->cq_tbl[cqne->info % dev->dsr->caps.max_cq];
475 if (cq)
476 atomic_inc(&cq->refcnt);
477 spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
478
479 if (cq && cq->ibcq.comp_handler)
480 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
481 if (cq) {
482 atomic_dec(&cq->refcnt);
483 if (atomic_read(&cq->refcnt))
484 wake_up(&cq->wait);
485 }
486 pvrdma_idx_ring_inc(&ring->cons_head, ring_slots);
487 }
488
489 return IRQ_HANDLED;
490}
491
492static void pvrdma_disable_msi_all(struct pvrdma_dev *dev)
493{
494 if (dev->intr.type == PVRDMA_INTR_TYPE_MSIX)
495 pci_disable_msix(dev->pdev);
496 else if (dev->intr.type == PVRDMA_INTR_TYPE_MSI)
497 pci_disable_msi(dev->pdev);
498}
499
500static void pvrdma_free_irq(struct pvrdma_dev *dev)
501{
502 int i;
503
504 dev_dbg(&dev->pdev->dev, "freeing interrupts\n");
505
506 if (dev->intr.type == PVRDMA_INTR_TYPE_MSIX) {
507 for (i = 0; i < dev->intr.size; i++) {
508 if (dev->intr.enabled[i]) {
509 free_irq(dev->intr.msix_entry[i].vector, dev);
510 dev->intr.enabled[i] = 0;
511 }
512 }
513 } else if (dev->intr.type == PVRDMA_INTR_TYPE_INTX ||
514 dev->intr.type == PVRDMA_INTR_TYPE_MSI) {
515 free_irq(dev->pdev->irq, dev);
516 }
517}
518
519static void pvrdma_enable_intrs(struct pvrdma_dev *dev)
520{
521 dev_dbg(&dev->pdev->dev, "enable interrupts\n");
522 pvrdma_write_reg(dev, PVRDMA_REG_IMR, 0);
523}
524
525static void pvrdma_disable_intrs(struct pvrdma_dev *dev)
526{
527 dev_dbg(&dev->pdev->dev, "disable interrupts\n");
528 pvrdma_write_reg(dev, PVRDMA_REG_IMR, ~0);
529}
530
531static int pvrdma_enable_msix(struct pci_dev *pdev, struct pvrdma_dev *dev)
532{
533 int i;
534 int ret;
535
536 for (i = 0; i < PVRDMA_MAX_INTERRUPTS; i++) {
537 dev->intr.msix_entry[i].entry = i;
538 dev->intr.msix_entry[i].vector = i;
539
540 switch (i) {
541 case 0:
542 /* CMD ring handler */
543 dev->intr.handler[i] = pvrdma_intr0_handler;
544 break;
545 case 1:
546 /* Async event ring handler */
547 dev->intr.handler[i] = pvrdma_intr1_handler;
548 break;
549 default:
550 /* Completion queue handler */
551 dev->intr.handler[i] = pvrdma_intrx_handler;
552 break;
553 }
554 }
555
556 ret = pci_enable_msix(pdev, dev->intr.msix_entry,
557 PVRDMA_MAX_INTERRUPTS);
558 if (!ret) {
559 dev->intr.type = PVRDMA_INTR_TYPE_MSIX;
560 dev->intr.size = PVRDMA_MAX_INTERRUPTS;
561 } else if (ret > 0) {
562 ret = pci_enable_msix(pdev, dev->intr.msix_entry, ret);
563 if (!ret) {
564 dev->intr.type = PVRDMA_INTR_TYPE_MSIX;
565 dev->intr.size = ret;
566 } else {
567 dev->intr.size = 0;
568 }
569 }
570
571 dev_dbg(&pdev->dev, "using interrupt type %d, size %d\n",
572 dev->intr.type, dev->intr.size);
573
574 return ret;
575}
576
577static int pvrdma_alloc_intrs(struct pvrdma_dev *dev)
578{
579 int ret = 0;
580 int i;
581
582 if (pci_find_capability(dev->pdev, PCI_CAP_ID_MSIX) &&
583 pvrdma_enable_msix(dev->pdev, dev)) {
584 /* Try MSI */
585 ret = pci_enable_msi(dev->pdev);
586 if (!ret) {
587 dev->intr.type = PVRDMA_INTR_TYPE_MSI;
588 } else {
589 /* Legacy INTR */
590 dev->intr.type = PVRDMA_INTR_TYPE_INTX;
591 }
592 }
593
594 /* Request First IRQ */
595 switch (dev->intr.type) {
596 case PVRDMA_INTR_TYPE_INTX:
597 case PVRDMA_INTR_TYPE_MSI:
598 ret = request_irq(dev->pdev->irq, pvrdma_intr0_handler,
599 IRQF_SHARED, DRV_NAME, dev);
600 if (ret) {
601 dev_err(&dev->pdev->dev,
602 "failed to request interrupt\n");
603 goto disable_msi;
604 }
605 break;
606 case PVRDMA_INTR_TYPE_MSIX:
607 ret = request_irq(dev->intr.msix_entry[0].vector,
608 pvrdma_intr0_handler, 0, DRV_NAME, dev);
609 if (ret) {
610 dev_err(&dev->pdev->dev,
611 "failed to request interrupt 0\n");
612 goto disable_msi;
613 }
614 dev->intr.enabled[0] = 1;
615 break;
616 default:
617 /* Not reached */
618 break;
619 }
620
621 /* For MSIX: request intr for each vector */
622 if (dev->intr.size > 1) {
623 ret = request_irq(dev->intr.msix_entry[1].vector,
624 pvrdma_intr1_handler, 0, DRV_NAME, dev);
625 if (ret) {
626 dev_err(&dev->pdev->dev,
627 "failed to request interrupt 1\n");
628 goto free_irq;
629 }
630 dev->intr.enabled[1] = 1;
631
632 for (i = 2; i < dev->intr.size; i++) {
633 ret = request_irq(dev->intr.msix_entry[i].vector,
634 pvrdma_intrx_handler, 0,
635 DRV_NAME, dev);
636 if (ret) {
637 dev_err(&dev->pdev->dev,
638 "failed to request interrupt %d\n", i);
639 goto free_irq;
640 }
641 dev->intr.enabled[i] = 1;
642 }
643 }
644
645 return 0;
646
647free_irq:
648 pvrdma_free_irq(dev);
649disable_msi:
650 pvrdma_disable_msi_all(dev);
651 return ret;
652}
653
654static void pvrdma_free_slots(struct pvrdma_dev *dev)
655{
656 struct pci_dev *pdev = dev->pdev;
657
658 if (dev->resp_slot)
659 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->resp_slot,
660 dev->dsr->resp_slot_dma);
661 if (dev->cmd_slot)
662 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->cmd_slot,
663 dev->dsr->cmd_slot_dma);
664}
665
666static int pvrdma_add_gid_at_index(struct pvrdma_dev *dev,
667 const union ib_gid *gid,
668 int index)
669{
670 int ret;
671 union pvrdma_cmd_req req;
672 struct pvrdma_cmd_create_bind *cmd_bind = &req.create_bind;
673
674 if (!dev->sgid_tbl) {
675 dev_warn(&dev->pdev->dev, "sgid table not initialized\n");
676 return -EINVAL;
677 }
678
679 memset(cmd_bind, 0, sizeof(*cmd_bind));
680 cmd_bind->hdr.cmd = PVRDMA_CMD_CREATE_BIND;
681 memcpy(cmd_bind->new_gid, gid->raw, 16);
682 cmd_bind->mtu = ib_mtu_enum_to_int(IB_MTU_1024);
683 cmd_bind->vlan = 0xfff;
684 cmd_bind->index = index;
685 cmd_bind->gid_type = PVRDMA_GID_TYPE_FLAG_ROCE_V1;
686
687 ret = pvrdma_cmd_post(dev, &req, NULL, 0);
688 if (ret < 0) {
689 dev_warn(&dev->pdev->dev,
690 "could not create binding, error: %d\n", ret);
691 return -EFAULT;
692 }
693 memcpy(&dev->sgid_tbl[index], gid, sizeof(*gid));
694 return 0;
695}
696
697static int pvrdma_add_gid(struct ib_device *ibdev,
698 u8 port_num,
699 unsigned int index,
700 const union ib_gid *gid,
701 const struct ib_gid_attr *attr,
702 void **context)
703{
704 struct pvrdma_dev *dev = to_vdev(ibdev);
705
706 return pvrdma_add_gid_at_index(dev, gid, index);
707}
708
709static int pvrdma_del_gid_at_index(struct pvrdma_dev *dev, int index)
710{
711 int ret;
712 union pvrdma_cmd_req req;
713 struct pvrdma_cmd_destroy_bind *cmd_dest = &req.destroy_bind;
714
715 /* Update sgid table. */
716 if (!dev->sgid_tbl) {
717 dev_warn(&dev->pdev->dev, "sgid table not initialized\n");
718 return -EINVAL;
719 }
720
721 memset(cmd_dest, 0, sizeof(*cmd_dest));
722 cmd_dest->hdr.cmd = PVRDMA_CMD_DESTROY_BIND;
723 memcpy(cmd_dest->dest_gid, &dev->sgid_tbl[index], 16);
724 cmd_dest->index = index;
725
726 ret = pvrdma_cmd_post(dev, &req, NULL, 0);
727 if (ret < 0) {
728 dev_warn(&dev->pdev->dev,
729 "could not destroy binding, error: %d\n", ret);
730 return ret;
731 }
732 memset(&dev->sgid_tbl[index], 0, 16);
733 return 0;
734}
735
736static int pvrdma_del_gid(struct ib_device *ibdev,
737 u8 port_num,
738 unsigned int index,
739 void **context)
740{
741 struct pvrdma_dev *dev = to_vdev(ibdev);
742
743 dev_dbg(&dev->pdev->dev, "removing gid at index %u from %s",
744 index, dev->netdev->name);
745
746 return pvrdma_del_gid_at_index(dev, index);
747}
748
749static void pvrdma_netdevice_event_handle(struct pvrdma_dev *dev,
750 unsigned long event)
751{
752 switch (event) {
753 case NETDEV_REBOOT:
754 case NETDEV_DOWN:
755 pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
756 break;
757 case NETDEV_UP:
758 pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
759 break;
760 default:
761 dev_dbg(&dev->pdev->dev, "ignore netdevice event %ld on %s\n",
762 event, dev->ib_dev.name);
763 break;
764 }
765}
766
767static void pvrdma_netdevice_event_work(struct work_struct *work)
768{
769 struct pvrdma_netdevice_work *netdev_work;
770 struct pvrdma_dev *dev;
771
772 netdev_work = container_of(work, struct pvrdma_netdevice_work, work);
773
774 mutex_lock(&pvrdma_device_list_lock);
775 list_for_each_entry(dev, &pvrdma_device_list, device_link) {
776 if (dev->netdev == netdev_work->event_netdev) {
777 pvrdma_netdevice_event_handle(dev, netdev_work->event);
778 break;
779 }
780 }
781 mutex_unlock(&pvrdma_device_list_lock);
782
783 kfree(netdev_work);
784}
785
786static int pvrdma_netdevice_event(struct notifier_block *this,
787 unsigned long event, void *ptr)
788{
789 struct net_device *event_netdev = netdev_notifier_info_to_dev(ptr);
790 struct pvrdma_netdevice_work *netdev_work;
791
792 netdev_work = kmalloc(sizeof(*netdev_work), GFP_ATOMIC);
793 if (!netdev_work)
794 return NOTIFY_BAD;
795
796 INIT_WORK(&netdev_work->work, pvrdma_netdevice_event_work);
797 netdev_work->event_netdev = event_netdev;
798 netdev_work->event = event;
799 queue_work(event_wq, &netdev_work->work);
800
801 return NOTIFY_DONE;
802}
803
804static int pvrdma_pci_probe(struct pci_dev *pdev,
805 const struct pci_device_id *id)
806{
807 struct pci_dev *pdev_net;
808 struct pvrdma_dev *dev;
809 int ret;
810 unsigned long start;
811 unsigned long len;
812 unsigned int version;
813 dma_addr_t slot_dma = 0;
814
815 dev_dbg(&pdev->dev, "initializing driver %s\n", pci_name(pdev));
816
817 /* Allocate zero-out device */
818 dev = (struct pvrdma_dev *)ib_alloc_device(sizeof(*dev));
819 if (!dev) {
820 dev_err(&pdev->dev, "failed to allocate IB device\n");
821 return -ENOMEM;
822 }
823
824 mutex_lock(&pvrdma_device_list_lock);
825 list_add(&dev->device_link, &pvrdma_device_list);
826 mutex_unlock(&pvrdma_device_list_lock);
827
828 ret = pvrdma_init_device(dev);
829 if (ret)
830 goto err_free_device;
831
832 dev->pdev = pdev;
833 pci_set_drvdata(pdev, dev);
834
835 ret = pci_enable_device(pdev);
836 if (ret) {
837 dev_err(&pdev->dev, "cannot enable PCI device\n");
838 goto err_free_device;
839 }
840
841 dev_dbg(&pdev->dev, "PCI resource flags BAR0 %#lx\n",
842 pci_resource_flags(pdev, 0));
843 dev_dbg(&pdev->dev, "PCI resource len %#llx\n",
844 (unsigned long long)pci_resource_len(pdev, 0));
845 dev_dbg(&pdev->dev, "PCI resource start %#llx\n",
846 (unsigned long long)pci_resource_start(pdev, 0));
847 dev_dbg(&pdev->dev, "PCI resource flags BAR1 %#lx\n",
848 pci_resource_flags(pdev, 1));
849 dev_dbg(&pdev->dev, "PCI resource len %#llx\n",
850 (unsigned long long)pci_resource_len(pdev, 1));
851 dev_dbg(&pdev->dev, "PCI resource start %#llx\n",
852 (unsigned long long)pci_resource_start(pdev, 1));
853
854 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
855 !(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
856 dev_err(&pdev->dev, "PCI BAR region not MMIO\n");
857 ret = -ENOMEM;
858 goto err_free_device;
859 }
860
861 ret = pci_request_regions(pdev, DRV_NAME);
862 if (ret) {
863 dev_err(&pdev->dev, "cannot request PCI resources\n");
864 goto err_disable_pdev;
865 }
866
867 /* Enable 64-Bit DMA */
868 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
869 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
870 if (ret != 0) {
871 dev_err(&pdev->dev,
872 "pci_set_consistent_dma_mask failed\n");
873 goto err_free_resource;
874 }
875 } else {
876 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
877 if (ret != 0) {
878 dev_err(&pdev->dev,
879 "pci_set_dma_mask failed\n");
880 goto err_free_resource;
881 }
882 }
883
884 pci_set_master(pdev);
885
886 /* Map register space */
887 start = pci_resource_start(dev->pdev, PVRDMA_PCI_RESOURCE_REG);
888 len = pci_resource_len(dev->pdev, PVRDMA_PCI_RESOURCE_REG);
889 dev->regs = ioremap(start, len);
890 if (!dev->regs) {
891 dev_err(&pdev->dev, "register mapping failed\n");
892 ret = -ENOMEM;
893 goto err_free_resource;
894 }
895
896 /* Setup per-device UAR. */
897 dev->driver_uar.index = 0;
898 dev->driver_uar.pfn =
899 pci_resource_start(dev->pdev, PVRDMA_PCI_RESOURCE_UAR) >>
900 PAGE_SHIFT;
901 dev->driver_uar.map =
902 ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
903 if (!dev->driver_uar.map) {
904 dev_err(&pdev->dev, "failed to remap UAR pages\n");
905 ret = -ENOMEM;
906 goto err_unmap_regs;
907 }
908
909 version = pvrdma_read_reg(dev, PVRDMA_REG_VERSION);
910 dev_info(&pdev->dev, "device version %d, driver version %d\n",
911 version, PVRDMA_VERSION);
912 if (version < PVRDMA_VERSION) {
913 dev_err(&pdev->dev, "incompatible device version\n");
914 goto err_uar_unmap;
915 }
916
917 dev->dsr = dma_alloc_coherent(&pdev->dev, sizeof(*dev->dsr),
918 &dev->dsrbase, GFP_KERNEL);
919 if (!dev->dsr) {
920 dev_err(&pdev->dev, "failed to allocate shared region\n");
921 ret = -ENOMEM;
922 goto err_uar_unmap;
923 }
924
925 /* Setup the shared region */
926 memset(dev->dsr, 0, sizeof(*dev->dsr));
927 dev->dsr->driver_version = PVRDMA_VERSION;
928 dev->dsr->gos_info.gos_bits = sizeof(void *) == 4 ?
929 PVRDMA_GOS_BITS_32 :
930 PVRDMA_GOS_BITS_64;
931 dev->dsr->gos_info.gos_type = PVRDMA_GOS_TYPE_LINUX;
932 dev->dsr->gos_info.gos_ver = 1;
933 dev->dsr->uar_pfn = dev->driver_uar.pfn;
934
935 /* Command slot. */
936 dev->cmd_slot = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
937 &slot_dma, GFP_KERNEL);
938 if (!dev->cmd_slot) {
939 ret = -ENOMEM;
940 goto err_free_dsr;
941 }
942
943 dev->dsr->cmd_slot_dma = (u64)slot_dma;
944
945 /* Response slot. */
946 dev->resp_slot = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
947 &slot_dma, GFP_KERNEL);
948 if (!dev->resp_slot) {
949 ret = -ENOMEM;
950 goto err_free_slots;
951 }
952
953 dev->dsr->resp_slot_dma = (u64)slot_dma;
954
955 /* Async event ring */
956 dev->dsr->async_ring_pages.num_pages = 4;
957 ret = pvrdma_page_dir_init(dev, &dev->async_pdir,
958 dev->dsr->async_ring_pages.num_pages, true);
959 if (ret)
960 goto err_free_slots;
961 dev->async_ring_state = dev->async_pdir.pages[0];
962 dev->dsr->async_ring_pages.pdir_dma = dev->async_pdir.dir_dma;
963
964 /* CQ notification ring */
965 dev->dsr->cq_ring_pages.num_pages = 4;
966 ret = pvrdma_page_dir_init(dev, &dev->cq_pdir,
967 dev->dsr->cq_ring_pages.num_pages, true);
968 if (ret)
969 goto err_free_async_ring;
970 dev->cq_ring_state = dev->cq_pdir.pages[0];
971 dev->dsr->cq_ring_pages.pdir_dma = dev->cq_pdir.dir_dma;
972
973 /*
974 * Write the PA of the shared region to the device. The writes must be
975 * ordered such that the high bits are written last. When the writes
976 * complete, the device will have filled out the capabilities.
977 */
978
979 pvrdma_write_reg(dev, PVRDMA_REG_DSRLOW, (u32)dev->dsrbase);
980 pvrdma_write_reg(dev, PVRDMA_REG_DSRHIGH,
981 (u32)((u64)(dev->dsrbase) >> 32));
982
983 /* Make sure the write is complete before reading status. */
984 mb();
985
986 /* Currently, the driver only supports RoCE mode. */
987 if (dev->dsr->caps.mode != PVRDMA_DEVICE_MODE_ROCE) {
988 dev_err(&pdev->dev, "unsupported transport %d\n",
989 dev->dsr->caps.mode);
990 ret = -EFAULT;
991 goto err_free_cq_ring;
992 }
993
994 /* Currently, the driver only supports RoCE V1. */
995 if (!(dev->dsr->caps.gid_types & PVRDMA_GID_TYPE_FLAG_ROCE_V1)) {
996 dev_err(&pdev->dev, "driver needs RoCE v1 support\n");
997 ret = -EFAULT;
998 goto err_free_cq_ring;
999 }
1000
1001 /* Paired vmxnet3 will have same bus, slot. But func will be 0 */
1002 pdev_net = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1003 if (!pdev_net) {
1004 dev_err(&pdev->dev, "failed to find paired net device\n");
1005 ret = -ENODEV;
1006 goto err_free_cq_ring;
1007 }
1008
1009 if (pdev_net->vendor != PCI_VENDOR_ID_VMWARE ||
1010 pdev_net->device != PCI_DEVICE_ID_VMWARE_VMXNET3) {
1011 dev_err(&pdev->dev, "failed to find paired vmxnet3 device\n");
1012 pci_dev_put(pdev_net);
1013 ret = -ENODEV;
1014 goto err_free_cq_ring;
1015 }
1016
1017 dev->netdev = pci_get_drvdata(pdev_net);
1018 pci_dev_put(pdev_net);
1019 if (!dev->netdev) {
1020 dev_err(&pdev->dev, "failed to get vmxnet3 device\n");
1021 ret = -ENODEV;
1022 goto err_free_cq_ring;
1023 }
1024
1025 dev_info(&pdev->dev, "paired device to %s\n", dev->netdev->name);
1026
1027 /* Interrupt setup */
1028 ret = pvrdma_alloc_intrs(dev);
1029 if (ret) {
1030 dev_err(&pdev->dev, "failed to allocate interrupts\n");
1031 ret = -ENOMEM;
1032 goto err_netdevice;
1033 }
1034
1035 /* Allocate UAR table. */
1036 ret = pvrdma_uar_table_init(dev);
1037 if (ret) {
1038 dev_err(&pdev->dev, "failed to allocate UAR table\n");
1039 ret = -ENOMEM;
1040 goto err_free_intrs;
1041 }
1042
1043 /* Allocate GID table */
1044 dev->sgid_tbl = kcalloc(dev->dsr->caps.gid_tbl_len,
1045 sizeof(union ib_gid), GFP_KERNEL);
1046 if (!dev->sgid_tbl) {
1047 ret = -ENOMEM;
1048 goto err_free_uar_table;
1049 }
1050 dev_dbg(&pdev->dev, "gid table len %d\n", dev->dsr->caps.gid_tbl_len);
1051
1052 pvrdma_enable_intrs(dev);
1053
1054 /* Activate pvrdma device */
1055 pvrdma_write_reg(dev, PVRDMA_REG_CTL, PVRDMA_DEVICE_CTL_ACTIVATE);
1056
1057 /* Make sure the write is complete before reading status. */
1058 mb();
1059
1060 /* Check if device was successfully activated */
1061 ret = pvrdma_read_reg(dev, PVRDMA_REG_ERR);
1062 if (ret != 0) {
1063 dev_err(&pdev->dev, "failed to activate device\n");
1064 ret = -EFAULT;
1065 goto err_disable_intr;
1066 }
1067
1068 /* Register IB device */
1069 ret = pvrdma_register_device(dev);
1070 if (ret) {
1071 dev_err(&pdev->dev, "failed to register IB device\n");
1072 goto err_disable_intr;
1073 }
1074
1075 dev->nb_netdev.notifier_call = pvrdma_netdevice_event;
1076 ret = register_netdevice_notifier(&dev->nb_netdev);
1077 if (ret) {
1078 dev_err(&pdev->dev, "failed to register netdevice events\n");
1079 goto err_unreg_ibdev;
1080 }
1081
1082 dev_info(&pdev->dev, "attached to device\n");
1083 return 0;
1084
1085err_unreg_ibdev:
1086 ib_unregister_device(&dev->ib_dev);
1087err_disable_intr:
1088 pvrdma_disable_intrs(dev);
1089 kfree(dev->sgid_tbl);
1090err_free_uar_table:
1091 pvrdma_uar_table_cleanup(dev);
1092err_free_intrs:
1093 pvrdma_free_irq(dev);
1094 pvrdma_disable_msi_all(dev);
1095err_netdevice:
1096 unregister_netdevice_notifier(&dev->nb_netdev);
1097err_free_cq_ring:
1098 pvrdma_page_dir_cleanup(dev, &dev->cq_pdir);
1099err_free_async_ring:
1100 pvrdma_page_dir_cleanup(dev, &dev->async_pdir);
1101err_free_slots:
1102 pvrdma_free_slots(dev);
1103err_free_dsr:
1104 dma_free_coherent(&pdev->dev, sizeof(*dev->dsr), dev->dsr,
1105 dev->dsrbase);
1106err_uar_unmap:
1107 iounmap(dev->driver_uar.map);
1108err_unmap_regs:
1109 iounmap(dev->regs);
1110err_free_resource:
1111 pci_release_regions(pdev);
1112err_disable_pdev:
1113 pci_disable_device(pdev);
1114 pci_set_drvdata(pdev, NULL);
1115err_free_device:
1116 mutex_lock(&pvrdma_device_list_lock);
1117 list_del(&dev->device_link);
1118 mutex_unlock(&pvrdma_device_list_lock);
1119 ib_dealloc_device(&dev->ib_dev);
1120 return ret;
1121}
1122
1123static void pvrdma_pci_remove(struct pci_dev *pdev)
1124{
1125 struct pvrdma_dev *dev = pci_get_drvdata(pdev);
1126
1127 if (!dev)
1128 return;
1129
1130 dev_info(&pdev->dev, "detaching from device\n");
1131
1132 unregister_netdevice_notifier(&dev->nb_netdev);
1133 dev->nb_netdev.notifier_call = NULL;
1134
1135 flush_workqueue(event_wq);
1136
1137 /* Unregister ib device */
1138 ib_unregister_device(&dev->ib_dev);
1139
1140 mutex_lock(&pvrdma_device_list_lock);
1141 list_del(&dev->device_link);
1142 mutex_unlock(&pvrdma_device_list_lock);
1143
1144 pvrdma_disable_intrs(dev);
1145 pvrdma_free_irq(dev);
1146 pvrdma_disable_msi_all(dev);
1147
1148 /* Deactivate pvrdma device */
1149 pvrdma_write_reg(dev, PVRDMA_REG_CTL, PVRDMA_DEVICE_CTL_RESET);
1150 pvrdma_page_dir_cleanup(dev, &dev->cq_pdir);
1151 pvrdma_page_dir_cleanup(dev, &dev->async_pdir);
1152 pvrdma_free_slots(dev);
1153
1154 iounmap(dev->regs);
1155 kfree(dev->sgid_tbl);
1156 kfree(dev->cq_tbl);
1157 kfree(dev->qp_tbl);
1158 pvrdma_uar_table_cleanup(dev);
1159 iounmap(dev->driver_uar.map);
1160
1161 ib_dealloc_device(&dev->ib_dev);
1162
1163 /* Free pci resources */
1164 pci_release_regions(pdev);
1165 pci_disable_device(pdev);
1166 pci_set_drvdata(pdev, NULL);
1167}
1168
1169static struct pci_device_id pvrdma_pci_table[] = {
1170 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, PCI_DEVICE_ID_VMWARE_PVRDMA), },
1171 { 0 },
1172};
1173
1174MODULE_DEVICE_TABLE(pci, pvrdma_pci_table);
1175
1176static struct pci_driver pvrdma_driver = {
1177 .name = DRV_NAME,
1178 .id_table = pvrdma_pci_table,
1179 .probe = pvrdma_pci_probe,
1180 .remove = pvrdma_pci_remove,
1181};
1182
1183static int __init pvrdma_init(void)
1184{
1185 int err;
1186
1187 event_wq = alloc_ordered_workqueue("pvrdma_event_wq", WQ_MEM_RECLAIM);
1188 if (!event_wq)
1189 return -ENOMEM;
1190
1191 err = pci_register_driver(&pvrdma_driver);
1192 if (err)
1193 destroy_workqueue(event_wq);
1194
1195 return err;
1196}
1197
1198static void __exit pvrdma_cleanup(void)
1199{
1200 pci_unregister_driver(&pvrdma_driver);
1201
1202 destroy_workqueue(event_wq);
1203}
1204
1205module_init(pvrdma_init);
1206module_exit(pvrdma_cleanup);
1207
1208MODULE_AUTHOR("VMware, Inc");
1209MODULE_DESCRIPTION("VMware Paravirtual RDMA driver");
1210MODULE_VERSION(DRV_VERSION);
1211MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_misc.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_misc.c
new file mode 100644
index 000000000000..948b5ccd2a70
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_misc.c
@@ -0,0 +1,304 @@
1/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#include <linux/errno.h>
47#include <linux/slab.h>
48#include <linux/bitmap.h>
49
50#include "pvrdma.h"
51
52int pvrdma_page_dir_init(struct pvrdma_dev *dev, struct pvrdma_page_dir *pdir,
53 u64 npages, bool alloc_pages)
54{
55 u64 i;
56
57 if (npages > PVRDMA_PAGE_DIR_MAX_PAGES)
58 return -EINVAL;
59
60 memset(pdir, 0, sizeof(*pdir));
61
62 pdir->dir = dma_alloc_coherent(&dev->pdev->dev, PAGE_SIZE,
63 &pdir->dir_dma, GFP_KERNEL);
64 if (!pdir->dir)
65 goto err;
66
67 pdir->ntables = PVRDMA_PAGE_DIR_TABLE(npages - 1) + 1;
68 pdir->tables = kcalloc(pdir->ntables, sizeof(*pdir->tables),
69 GFP_KERNEL);
70 if (!pdir->tables)
71 goto err;
72
73 for (i = 0; i < pdir->ntables; i++) {
74 pdir->tables[i] = dma_alloc_coherent(&dev->pdev->dev, PAGE_SIZE,
75 (dma_addr_t *)&pdir->dir[i],
76 GFP_KERNEL);
77 if (!pdir->tables[i])
78 goto err;
79 }
80
81 pdir->npages = npages;
82
83 if (alloc_pages) {
84 pdir->pages = kcalloc(npages, sizeof(*pdir->pages),
85 GFP_KERNEL);
86 if (!pdir->pages)
87 goto err;
88
89 for (i = 0; i < pdir->npages; i++) {
90 dma_addr_t page_dma;
91
92 pdir->pages[i] = dma_alloc_coherent(&dev->pdev->dev,
93 PAGE_SIZE,
94 &page_dma,
95 GFP_KERNEL);
96 if (!pdir->pages[i])
97 goto err;
98
99 pvrdma_page_dir_insert_dma(pdir, i, page_dma);
100 }
101 }
102
103 return 0;
104
105err:
106 pvrdma_page_dir_cleanup(dev, pdir);
107
108 return -ENOMEM;
109}
110
111static u64 *pvrdma_page_dir_table(struct pvrdma_page_dir *pdir, u64 idx)
112{
113 return pdir->tables[PVRDMA_PAGE_DIR_TABLE(idx)];
114}
115
116dma_addr_t pvrdma_page_dir_get_dma(struct pvrdma_page_dir *pdir, u64 idx)
117{
118 return pvrdma_page_dir_table(pdir, idx)[PVRDMA_PAGE_DIR_PAGE(idx)];
119}
120
121static void pvrdma_page_dir_cleanup_pages(struct pvrdma_dev *dev,
122 struct pvrdma_page_dir *pdir)
123{
124 if (pdir->pages) {
125 u64 i;
126
127 for (i = 0; i < pdir->npages && pdir->pages[i]; i++) {
128 dma_addr_t page_dma = pvrdma_page_dir_get_dma(pdir, i);
129
130 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
131 pdir->pages[i], page_dma);
132 }
133
134 kfree(pdir->pages);
135 }
136}
137
138static void pvrdma_page_dir_cleanup_tables(struct pvrdma_dev *dev,
139 struct pvrdma_page_dir *pdir)
140{
141 if (pdir->tables) {
142 int i;
143
144 pvrdma_page_dir_cleanup_pages(dev, pdir);
145
146 for (i = 0; i < pdir->ntables; i++) {
147 u64 *table = pdir->tables[i];
148
149 if (table)
150 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
151 table, pdir->dir[i]);
152 }
153
154 kfree(pdir->tables);
155 }
156}
157
158void pvrdma_page_dir_cleanup(struct pvrdma_dev *dev,
159 struct pvrdma_page_dir *pdir)
160{
161 if (pdir->dir) {
162 pvrdma_page_dir_cleanup_tables(dev, pdir);
163 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
164 pdir->dir, pdir->dir_dma);
165 }
166}
167
168int pvrdma_page_dir_insert_dma(struct pvrdma_page_dir *pdir, u64 idx,
169 dma_addr_t daddr)
170{
171 u64 *table;
172
173 if (idx >= pdir->npages)
174 return -EINVAL;
175
176 table = pvrdma_page_dir_table(pdir, idx);
177 table[PVRDMA_PAGE_DIR_PAGE(idx)] = daddr;
178
179 return 0;
180}
181
182int pvrdma_page_dir_insert_umem(struct pvrdma_page_dir *pdir,
183 struct ib_umem *umem, u64 offset)
184{
185 u64 i = offset;
186 int j, entry;
187 int ret = 0, len = 0;
188 struct scatterlist *sg;
189
190 if (offset >= pdir->npages)
191 return -EINVAL;
192
193 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
194 len = sg_dma_len(sg) >> PAGE_SHIFT;
195 for (j = 0; j < len; j++) {
196 dma_addr_t addr = sg_dma_address(sg) +
197 umem->page_size * j;
198
199 ret = pvrdma_page_dir_insert_dma(pdir, i, addr);
200 if (ret)
201 goto exit;
202
203 i++;
204 }
205 }
206
207exit:
208 return ret;
209}
210
211int pvrdma_page_dir_insert_page_list(struct pvrdma_page_dir *pdir,
212 u64 *page_list,
213 int num_pages)
214{
215 int i;
216 int ret;
217
218 if (num_pages > pdir->npages)
219 return -EINVAL;
220
221 for (i = 0; i < num_pages; i++) {
222 ret = pvrdma_page_dir_insert_dma(pdir, i, page_list[i]);
223 if (ret)
224 return ret;
225 }
226
227 return 0;
228}
229
230void pvrdma_qp_cap_to_ib(struct ib_qp_cap *dst, const struct pvrdma_qp_cap *src)
231{
232 dst->max_send_wr = src->max_send_wr;
233 dst->max_recv_wr = src->max_recv_wr;
234 dst->max_send_sge = src->max_send_sge;
235 dst->max_recv_sge = src->max_recv_sge;
236 dst->max_inline_data = src->max_inline_data;
237}
238
239void ib_qp_cap_to_pvrdma(struct pvrdma_qp_cap *dst, const struct ib_qp_cap *src)
240{
241 dst->max_send_wr = src->max_send_wr;
242 dst->max_recv_wr = src->max_recv_wr;
243 dst->max_send_sge = src->max_send_sge;
244 dst->max_recv_sge = src->max_recv_sge;
245 dst->max_inline_data = src->max_inline_data;
246}
247
248void pvrdma_gid_to_ib(union ib_gid *dst, const union pvrdma_gid *src)
249{
250 BUILD_BUG_ON(sizeof(union pvrdma_gid) != sizeof(union ib_gid));
251 memcpy(dst, src, sizeof(*src));
252}
253
254void ib_gid_to_pvrdma(union pvrdma_gid *dst, const union ib_gid *src)
255{
256 BUILD_BUG_ON(sizeof(union pvrdma_gid) != sizeof(union ib_gid));
257 memcpy(dst, src, sizeof(*src));
258}
259
260void pvrdma_global_route_to_ib(struct ib_global_route *dst,
261 const struct pvrdma_global_route *src)
262{
263 pvrdma_gid_to_ib(&dst->dgid, &src->dgid);
264 dst->flow_label = src->flow_label;
265 dst->sgid_index = src->sgid_index;
266 dst->hop_limit = src->hop_limit;
267 dst->traffic_class = src->traffic_class;
268}
269
270void ib_global_route_to_pvrdma(struct pvrdma_global_route *dst,
271 const struct ib_global_route *src)
272{
273 ib_gid_to_pvrdma(&dst->dgid, &src->dgid);
274 dst->flow_label = src->flow_label;
275 dst->sgid_index = src->sgid_index;
276 dst->hop_limit = src->hop_limit;
277 dst->traffic_class = src->traffic_class;
278}
279
280void pvrdma_ah_attr_to_ib(struct ib_ah_attr *dst,
281 const struct pvrdma_ah_attr *src)
282{
283 pvrdma_global_route_to_ib(&dst->grh, &src->grh);
284 dst->dlid = src->dlid;
285 dst->sl = src->sl;
286 dst->src_path_bits = src->src_path_bits;
287 dst->static_rate = src->static_rate;
288 dst->ah_flags = src->ah_flags;
289 dst->port_num = src->port_num;
290 memcpy(&dst->dmac, &src->dmac, sizeof(dst->dmac));
291}
292
293void ib_ah_attr_to_pvrdma(struct pvrdma_ah_attr *dst,
294 const struct ib_ah_attr *src)
295{
296 ib_global_route_to_pvrdma(&dst->grh, &src->grh);
297 dst->dlid = src->dlid;
298 dst->sl = src->sl;
299 dst->src_path_bits = src->src_path_bits;
300 dst->static_rate = src->static_rate;
301 dst->ah_flags = src->ah_flags;
302 dst->port_num = src->port_num;
303 memcpy(&dst->dmac, &src->dmac, sizeof(dst->dmac));
304}
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_mr.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_mr.c
new file mode 100644
index 000000000000..8519f3212e52
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_mr.c
@@ -0,0 +1,334 @@
1/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#include <linux/list.h>
47#include <linux/slab.h>
48
49#include "pvrdma.h"
50
51/**
52 * pvrdma_get_dma_mr - get a DMA memory region
53 * @pd: protection domain
54 * @acc: access flags
55 *
56 * @return: ib_mr pointer on success, otherwise returns an errno.
57 */
58struct ib_mr *pvrdma_get_dma_mr(struct ib_pd *pd, int acc)
59{
60 struct pvrdma_dev *dev = to_vdev(pd->device);
61 struct pvrdma_user_mr *mr;
62 union pvrdma_cmd_req req;
63 union pvrdma_cmd_resp rsp;
64 struct pvrdma_cmd_create_mr *cmd = &req.create_mr;
65 struct pvrdma_cmd_create_mr_resp *resp = &rsp.create_mr_resp;
66 int ret;
67
68 /* Support only LOCAL_WRITE flag for DMA MRs */
69 if (acc & ~IB_ACCESS_LOCAL_WRITE) {
70 dev_warn(&dev->pdev->dev,
71 "unsupported dma mr access flags %#x\n", acc);
72 return ERR_PTR(-EOPNOTSUPP);
73 }
74
75 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
76 if (!mr)
77 return ERR_PTR(-ENOMEM);
78
79 memset(cmd, 0, sizeof(*cmd));
80 cmd->hdr.cmd = PVRDMA_CMD_CREATE_MR;
81 cmd->pd_handle = to_vpd(pd)->pd_handle;
82 cmd->access_flags = acc;
83 cmd->flags = PVRDMA_MR_FLAG_DMA;
84
85 ret = pvrdma_cmd_post(dev, &req, &rsp, PVRDMA_CMD_CREATE_MR_RESP);
86 if (ret < 0) {
87 dev_warn(&dev->pdev->dev,
88 "could not get DMA mem region, error: %d\n", ret);
89 kfree(mr);
90 return ERR_PTR(ret);
91 }
92
93 mr->mmr.mr_handle = resp->mr_handle;
94 mr->ibmr.lkey = resp->lkey;
95 mr->ibmr.rkey = resp->rkey;
96
97 return &mr->ibmr;
98}
99
100/**
101 * pvrdma_reg_user_mr - register a userspace memory region
102 * @pd: protection domain
103 * @start: starting address
104 * @length: length of region
105 * @virt_addr: I/O virtual address
106 * @access_flags: access flags for memory region
107 * @udata: user data
108 *
109 * @return: ib_mr pointer on success, otherwise returns an errno.
110 */
111struct ib_mr *pvrdma_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
112 u64 virt_addr, int access_flags,
113 struct ib_udata *udata)
114{
115 struct pvrdma_dev *dev = to_vdev(pd->device);
116 struct pvrdma_user_mr *mr = NULL;
117 struct ib_umem *umem;
118 union pvrdma_cmd_req req;
119 union pvrdma_cmd_resp rsp;
120 struct pvrdma_cmd_create_mr *cmd = &req.create_mr;
121 struct pvrdma_cmd_create_mr_resp *resp = &rsp.create_mr_resp;
122 int nchunks;
123 int ret;
124 int entry;
125 struct scatterlist *sg;
126
127 if (length == 0 || length > dev->dsr->caps.max_mr_size) {
128 dev_warn(&dev->pdev->dev, "invalid mem region length\n");
129 return ERR_PTR(-EINVAL);
130 }
131
132 umem = ib_umem_get(pd->uobject->context, start,
133 length, access_flags, 0);
134 if (IS_ERR(umem)) {
135 dev_warn(&dev->pdev->dev,
136 "could not get umem for mem region\n");
137 return ERR_CAST(umem);
138 }
139
140 nchunks = 0;
141 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry)
142 nchunks += sg_dma_len(sg) >> PAGE_SHIFT;
143
144 if (nchunks < 0 || nchunks > PVRDMA_PAGE_DIR_MAX_PAGES) {
145 dev_warn(&dev->pdev->dev, "overflow %d pages in mem region\n",
146 nchunks);
147 ret = -EINVAL;
148 goto err_umem;
149 }
150
151 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
152 if (!mr) {
153 ret = -ENOMEM;
154 goto err_umem;
155 }
156
157 mr->mmr.iova = virt_addr;
158 mr->mmr.size = length;
159 mr->umem = umem;
160
161 ret = pvrdma_page_dir_init(dev, &mr->pdir, nchunks, false);
162 if (ret) {
163 dev_warn(&dev->pdev->dev,
164 "could not allocate page directory\n");
165 goto err_umem;
166 }
167
168 ret = pvrdma_page_dir_insert_umem(&mr->pdir, mr->umem, 0);
169 if (ret)
170 goto err_pdir;
171
172 memset(cmd, 0, sizeof(*cmd));
173 cmd->hdr.cmd = PVRDMA_CMD_CREATE_MR;
174 cmd->start = start;
175 cmd->length = length;
176 cmd->pd_handle = to_vpd(pd)->pd_handle;
177 cmd->access_flags = access_flags;
178 cmd->nchunks = nchunks;
179 cmd->pdir_dma = mr->pdir.dir_dma;
180
181 ret = pvrdma_cmd_post(dev, &req, &rsp, PVRDMA_CMD_CREATE_MR_RESP);
182 if (ret < 0) {
183 dev_warn(&dev->pdev->dev,
184 "could not register mem region, error: %d\n", ret);
185 goto err_pdir;
186 }
187
188 mr->mmr.mr_handle = resp->mr_handle;
189 mr->ibmr.lkey = resp->lkey;
190 mr->ibmr.rkey = resp->rkey;
191
192 return &mr->ibmr;
193
194err_pdir:
195 pvrdma_page_dir_cleanup(dev, &mr->pdir);
196err_umem:
197 ib_umem_release(umem);
198 kfree(mr);
199
200 return ERR_PTR(ret);
201}
202
203/**
204 * pvrdma_alloc_mr - allocate a memory region
205 * @pd: protection domain
206 * @mr_type: type of memory region
207 * @max_num_sg: maximum number of pages
208 *
209 * @return: ib_mr pointer on success, otherwise returns an errno.
210 */
211struct ib_mr *pvrdma_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
212 u32 max_num_sg)
213{
214 struct pvrdma_dev *dev = to_vdev(pd->device);
215 struct pvrdma_user_mr *mr;
216 union pvrdma_cmd_req req;
217 union pvrdma_cmd_resp rsp;
218 struct pvrdma_cmd_create_mr *cmd = &req.create_mr;
219 struct pvrdma_cmd_create_mr_resp *resp = &rsp.create_mr_resp;
220 int size = max_num_sg * sizeof(u64);
221 int ret;
222
223 if (mr_type != IB_MR_TYPE_MEM_REG ||
224 max_num_sg > PVRDMA_MAX_FAST_REG_PAGES)
225 return ERR_PTR(-EINVAL);
226
227 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
228 if (!mr)
229 return ERR_PTR(-ENOMEM);
230
231 mr->pages = kzalloc(size, GFP_KERNEL);
232 if (!mr->pages) {
233 ret = -ENOMEM;
234 goto freemr;
235 }
236
237 ret = pvrdma_page_dir_init(dev, &mr->pdir, max_num_sg, false);
238 if (ret) {
239 dev_warn(&dev->pdev->dev,
240 "failed to allocate page dir for mr\n");
241 ret = -ENOMEM;
242 goto freepages;
243 }
244
245 memset(cmd, 0, sizeof(*cmd));
246 cmd->hdr.cmd = PVRDMA_CMD_CREATE_MR;
247 cmd->pd_handle = to_vpd(pd)->pd_handle;
248 cmd->access_flags = 0;
249 cmd->flags = PVRDMA_MR_FLAG_FRMR;
250 cmd->nchunks = max_num_sg;
251
252 ret = pvrdma_cmd_post(dev, &req, &rsp, PVRDMA_CMD_CREATE_MR_RESP);
253 if (ret < 0) {
254 dev_warn(&dev->pdev->dev,
255 "could not create FR mem region, error: %d\n", ret);
256 goto freepdir;
257 }
258
259 mr->max_pages = max_num_sg;
260 mr->mmr.mr_handle = resp->mr_handle;
261 mr->ibmr.lkey = resp->lkey;
262 mr->ibmr.rkey = resp->rkey;
263 mr->page_shift = PAGE_SHIFT;
264 mr->umem = NULL;
265
266 return &mr->ibmr;
267
268freepdir:
269 pvrdma_page_dir_cleanup(dev, &mr->pdir);
270freepages:
271 kfree(mr->pages);
272freemr:
273 kfree(mr);
274 return ERR_PTR(ret);
275}
276
277/**
278 * pvrdma_dereg_mr - deregister a memory region
279 * @ibmr: memory region
280 *
281 * @return: 0 on success.
282 */
283int pvrdma_dereg_mr(struct ib_mr *ibmr)
284{
285 struct pvrdma_user_mr *mr = to_vmr(ibmr);
286 struct pvrdma_dev *dev = to_vdev(ibmr->device);
287 union pvrdma_cmd_req req;
288 struct pvrdma_cmd_destroy_mr *cmd = &req.destroy_mr;
289 int ret;
290
291 memset(cmd, 0, sizeof(*cmd));
292 cmd->hdr.cmd = PVRDMA_CMD_DESTROY_MR;
293 cmd->mr_handle = mr->mmr.mr_handle;
294 ret = pvrdma_cmd_post(dev, &req, NULL, 0);
295 if (ret < 0)
296 dev_warn(&dev->pdev->dev,
297 "could not deregister mem region, error: %d\n", ret);
298
299 pvrdma_page_dir_cleanup(dev, &mr->pdir);
300 if (mr->umem)
301 ib_umem_release(mr->umem);
302
303 kfree(mr->pages);
304 kfree(mr);
305
306 return 0;
307}
308
309static int pvrdma_set_page(struct ib_mr *ibmr, u64 addr)
310{
311 struct pvrdma_user_mr *mr = to_vmr(ibmr);
312
313 if (mr->npages == mr->max_pages)
314 return -ENOMEM;
315
316 mr->pages[mr->npages++] = addr;
317 return 0;
318}
319
320int pvrdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
321 unsigned int *sg_offset)
322{
323 struct pvrdma_user_mr *mr = to_vmr(ibmr);
324 struct pvrdma_dev *dev = to_vdev(ibmr->device);
325 int ret;
326
327 mr->npages = 0;
328
329 ret = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, pvrdma_set_page);
330 if (ret < 0)
331 dev_warn(&dev->pdev->dev, "could not map sg to pages\n");
332
333 return ret;
334}
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c
new file mode 100644
index 000000000000..c8c01e558125
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c
@@ -0,0 +1,972 @@
1/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#include <asm/page.h>
47#include <linux/io.h>
48#include <linux/wait.h>
49#include <rdma/ib_addr.h>
50#include <rdma/ib_smi.h>
51#include <rdma/ib_user_verbs.h>
52
53#include "pvrdma.h"
54
55static inline void get_cqs(struct pvrdma_qp *qp, struct pvrdma_cq **send_cq,
56 struct pvrdma_cq **recv_cq)
57{
58 *send_cq = to_vcq(qp->ibqp.send_cq);
59 *recv_cq = to_vcq(qp->ibqp.recv_cq);
60}
61
62static void pvrdma_lock_cqs(struct pvrdma_cq *scq, struct pvrdma_cq *rcq,
63 unsigned long *scq_flags,
64 unsigned long *rcq_flags)
65 __acquires(scq->cq_lock) __acquires(rcq->cq_lock)
66{
67 if (scq == rcq) {
68 spin_lock_irqsave(&scq->cq_lock, *scq_flags);
69 __acquire(rcq->cq_lock);
70 } else if (scq->cq_handle < rcq->cq_handle) {
71 spin_lock_irqsave(&scq->cq_lock, *scq_flags);
72 spin_lock_irqsave_nested(&rcq->cq_lock, *rcq_flags,
73 SINGLE_DEPTH_NESTING);
74 } else {
75 spin_lock_irqsave(&rcq->cq_lock, *rcq_flags);
76 spin_lock_irqsave_nested(&scq->cq_lock, *scq_flags,
77 SINGLE_DEPTH_NESTING);
78 }
79}
80
81static void pvrdma_unlock_cqs(struct pvrdma_cq *scq, struct pvrdma_cq *rcq,
82 unsigned long *scq_flags,
83 unsigned long *rcq_flags)
84 __releases(scq->cq_lock) __releases(rcq->cq_lock)
85{
86 if (scq == rcq) {
87 __release(rcq->cq_lock);
88 spin_unlock_irqrestore(&scq->cq_lock, *scq_flags);
89 } else if (scq->cq_handle < rcq->cq_handle) {
90 spin_unlock_irqrestore(&rcq->cq_lock, *rcq_flags);
91 spin_unlock_irqrestore(&scq->cq_lock, *scq_flags);
92 } else {
93 spin_unlock_irqrestore(&scq->cq_lock, *scq_flags);
94 spin_unlock_irqrestore(&rcq->cq_lock, *rcq_flags);
95 }
96}
97
98static void pvrdma_reset_qp(struct pvrdma_qp *qp)
99{
100 struct pvrdma_cq *scq, *rcq;
101 unsigned long scq_flags, rcq_flags;
102
103 /* Clean up cqes */
104 get_cqs(qp, &scq, &rcq);
105 pvrdma_lock_cqs(scq, rcq, &scq_flags, &rcq_flags);
106
107 _pvrdma_flush_cqe(qp, scq);
108 if (scq != rcq)
109 _pvrdma_flush_cqe(qp, rcq);
110
111 pvrdma_unlock_cqs(scq, rcq, &scq_flags, &rcq_flags);
112
113 /*
114 * Reset queuepair. The checks are because usermode queuepairs won't
115 * have kernel ringstates.
116 */
117 if (qp->rq.ring) {
118 atomic_set(&qp->rq.ring->cons_head, 0);
119 atomic_set(&qp->rq.ring->prod_tail, 0);
120 }
121 if (qp->sq.ring) {
122 atomic_set(&qp->sq.ring->cons_head, 0);
123 atomic_set(&qp->sq.ring->prod_tail, 0);
124 }
125}
126
127static int pvrdma_set_rq_size(struct pvrdma_dev *dev,
128 struct ib_qp_cap *req_cap,
129 struct pvrdma_qp *qp)
130{
131 if (req_cap->max_recv_wr > dev->dsr->caps.max_qp_wr ||
132 req_cap->max_recv_sge > dev->dsr->caps.max_sge) {
133 dev_warn(&dev->pdev->dev, "recv queue size invalid\n");
134 return -EINVAL;
135 }
136
137 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, req_cap->max_recv_wr));
138 qp->rq.max_sg = roundup_pow_of_two(max(1U, req_cap->max_recv_sge));
139
140 /* Write back */
141 req_cap->max_recv_wr = qp->rq.wqe_cnt;
142 req_cap->max_recv_sge = qp->rq.max_sg;
143
144 qp->rq.wqe_size = roundup_pow_of_two(sizeof(struct pvrdma_rq_wqe_hdr) +
145 sizeof(struct pvrdma_sge) *
146 qp->rq.max_sg);
147 qp->npages_recv = (qp->rq.wqe_cnt * qp->rq.wqe_size + PAGE_SIZE - 1) /
148 PAGE_SIZE;
149
150 return 0;
151}
152
153static int pvrdma_set_sq_size(struct pvrdma_dev *dev, struct ib_qp_cap *req_cap,
154 enum ib_qp_type type, struct pvrdma_qp *qp)
155{
156 if (req_cap->max_send_wr > dev->dsr->caps.max_qp_wr ||
157 req_cap->max_send_sge > dev->dsr->caps.max_sge) {
158 dev_warn(&dev->pdev->dev, "send queue size invalid\n");
159 return -EINVAL;
160 }
161
162 qp->sq.wqe_cnt = roundup_pow_of_two(max(1U, req_cap->max_send_wr));
163 qp->sq.max_sg = roundup_pow_of_two(max(1U, req_cap->max_send_sge));
164
165 /* Write back */
166 req_cap->max_send_wr = qp->sq.wqe_cnt;
167 req_cap->max_send_sge = qp->sq.max_sg;
168
169 qp->sq.wqe_size = roundup_pow_of_two(sizeof(struct pvrdma_sq_wqe_hdr) +
170 sizeof(struct pvrdma_sge) *
171 qp->sq.max_sg);
172 /* Note: one extra page for the header. */
173 qp->npages_send = 1 + (qp->sq.wqe_cnt * qp->sq.wqe_size +
174 PAGE_SIZE - 1) / PAGE_SIZE;
175
176 return 0;
177}
178
179/**
180 * pvrdma_create_qp - create queue pair
181 * @pd: protection domain
182 * @init_attr: queue pair attributes
183 * @udata: user data
184 *
185 * @return: the ib_qp pointer on success, otherwise returns an errno.
186 */
187struct ib_qp *pvrdma_create_qp(struct ib_pd *pd,
188 struct ib_qp_init_attr *init_attr,
189 struct ib_udata *udata)
190{
191 struct pvrdma_qp *qp = NULL;
192 struct pvrdma_dev *dev = to_vdev(pd->device);
193 union pvrdma_cmd_req req;
194 union pvrdma_cmd_resp rsp;
195 struct pvrdma_cmd_create_qp *cmd = &req.create_qp;
196 struct pvrdma_cmd_create_qp_resp *resp = &rsp.create_qp_resp;
197 struct pvrdma_create_qp ucmd;
198 unsigned long flags;
199 int ret;
200
201 if (init_attr->create_flags) {
202 dev_warn(&dev->pdev->dev,
203 "invalid create queuepair flags %#x\n",
204 init_attr->create_flags);
205 return ERR_PTR(-EINVAL);
206 }
207
208 if (init_attr->qp_type != IB_QPT_RC &&
209 init_attr->qp_type != IB_QPT_UD &&
210 init_attr->qp_type != IB_QPT_GSI) {
211 dev_warn(&dev->pdev->dev, "queuepair type %d not supported\n",
212 init_attr->qp_type);
213 return ERR_PTR(-EINVAL);
214 }
215
216 if (!atomic_add_unless(&dev->num_qps, 1, dev->dsr->caps.max_qp))
217 return ERR_PTR(-ENOMEM);
218
219 switch (init_attr->qp_type) {
220 case IB_QPT_GSI:
221 if (init_attr->port_num == 0 ||
222 init_attr->port_num > pd->device->phys_port_cnt ||
223 udata) {
224 dev_warn(&dev->pdev->dev, "invalid queuepair attrs\n");
225 ret = -EINVAL;
226 goto err_qp;
227 }
228 /* fall through */
229 case IB_QPT_RC:
230 case IB_QPT_UD:
231 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
232 if (!qp) {
233 ret = -ENOMEM;
234 goto err_qp;
235 }
236
237 spin_lock_init(&qp->sq.lock);
238 spin_lock_init(&qp->rq.lock);
239 mutex_init(&qp->mutex);
240 atomic_set(&qp->refcnt, 1);
241 init_waitqueue_head(&qp->wait);
242
243 qp->state = IB_QPS_RESET;
244
245 if (pd->uobject && udata) {
246 dev_dbg(&dev->pdev->dev,
247 "create queuepair from user space\n");
248
249 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
250 ret = -EFAULT;
251 goto err_qp;
252 }
253
254 /* set qp->sq.wqe_cnt, shift, buf_size.. */
255 qp->rumem = ib_umem_get(pd->uobject->context,
256 ucmd.rbuf_addr,
257 ucmd.rbuf_size, 0, 0);
258 if (IS_ERR(qp->rumem)) {
259 ret = PTR_ERR(qp->rumem);
260 goto err_qp;
261 }
262
263 qp->sumem = ib_umem_get(pd->uobject->context,
264 ucmd.sbuf_addr,
265 ucmd.sbuf_size, 0, 0);
266 if (IS_ERR(qp->sumem)) {
267 ib_umem_release(qp->rumem);
268 ret = PTR_ERR(qp->sumem);
269 goto err_qp;
270 }
271
272 qp->npages_send = ib_umem_page_count(qp->sumem);
273 qp->npages_recv = ib_umem_page_count(qp->rumem);
274 qp->npages = qp->npages_send + qp->npages_recv;
275 } else {
276 qp->is_kernel = true;
277
278 ret = pvrdma_set_sq_size(to_vdev(pd->device),
279 &init_attr->cap,
280 init_attr->qp_type, qp);
281 if (ret)
282 goto err_qp;
283
284 ret = pvrdma_set_rq_size(to_vdev(pd->device),
285 &init_attr->cap, qp);
286 if (ret)
287 goto err_qp;
288
289 qp->npages = qp->npages_send + qp->npages_recv;
290
291 /* Skip header page. */
292 qp->sq.offset = PAGE_SIZE;
293
294 /* Recv queue pages are after send pages. */
295 qp->rq.offset = qp->npages_send * PAGE_SIZE;
296 }
297
298 if (qp->npages < 0 || qp->npages > PVRDMA_PAGE_DIR_MAX_PAGES) {
299 dev_warn(&dev->pdev->dev,
300 "overflow pages in queuepair\n");
301 ret = -EINVAL;
302 goto err_umem;
303 }
304
305 ret = pvrdma_page_dir_init(dev, &qp->pdir, qp->npages,
306 qp->is_kernel);
307 if (ret) {
308 dev_warn(&dev->pdev->dev,
309 "could not allocate page directory\n");
310 goto err_umem;
311 }
312
313 if (!qp->is_kernel) {
314 pvrdma_page_dir_insert_umem(&qp->pdir, qp->sumem, 0);
315 pvrdma_page_dir_insert_umem(&qp->pdir, qp->rumem,
316 qp->npages_send);
317 } else {
318 /* Ring state is always the first page. */
319 qp->sq.ring = qp->pdir.pages[0];
320 qp->rq.ring = &qp->sq.ring[1];
321 }
322 break;
323 default:
324 ret = -EINVAL;
325 goto err_qp;
326 }
327
328 /* Not supported */
329 init_attr->cap.max_inline_data = 0;
330
331 memset(cmd, 0, sizeof(*cmd));
332 cmd->hdr.cmd = PVRDMA_CMD_CREATE_QP;
333 cmd->pd_handle = to_vpd(pd)->pd_handle;
334 cmd->send_cq_handle = to_vcq(init_attr->send_cq)->cq_handle;
335 cmd->recv_cq_handle = to_vcq(init_attr->recv_cq)->cq_handle;
336 cmd->max_send_wr = init_attr->cap.max_send_wr;
337 cmd->max_recv_wr = init_attr->cap.max_recv_wr;
338 cmd->max_send_sge = init_attr->cap.max_send_sge;
339 cmd->max_recv_sge = init_attr->cap.max_recv_sge;
340 cmd->max_inline_data = init_attr->cap.max_inline_data;
341 cmd->sq_sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0;
342 cmd->qp_type = ib_qp_type_to_pvrdma(init_attr->qp_type);
343 cmd->access_flags = IB_ACCESS_LOCAL_WRITE;
344 cmd->total_chunks = qp->npages;
345 cmd->send_chunks = qp->npages_send - 1;
346 cmd->pdir_dma = qp->pdir.dir_dma;
347
348 dev_dbg(&dev->pdev->dev, "create queuepair with %d, %d, %d, %d\n",
349 cmd->max_send_wr, cmd->max_recv_wr, cmd->max_send_sge,
350 cmd->max_recv_sge);
351
352 ret = pvrdma_cmd_post(dev, &req, &rsp, PVRDMA_CMD_CREATE_QP_RESP);
353 if (ret < 0) {
354 dev_warn(&dev->pdev->dev,
355 "could not create queuepair, error: %d\n", ret);
356 goto err_pdir;
357 }
358
359 /* max_send_wr/_recv_wr/_send_sge/_recv_sge/_inline_data */
360 qp->qp_handle = resp->qpn;
361 qp->port = init_attr->port_num;
362 qp->ibqp.qp_num = resp->qpn;
363 spin_lock_irqsave(&dev->qp_tbl_lock, flags);
364 dev->qp_tbl[qp->qp_handle % dev->dsr->caps.max_qp] = qp;
365 spin_unlock_irqrestore(&dev->qp_tbl_lock, flags);
366
367 return &qp->ibqp;
368
369err_pdir:
370 pvrdma_page_dir_cleanup(dev, &qp->pdir);
371err_umem:
372 if (pd->uobject && udata) {
373 if (qp->rumem)
374 ib_umem_release(qp->rumem);
375 if (qp->sumem)
376 ib_umem_release(qp->sumem);
377 }
378err_qp:
379 kfree(qp);
380 atomic_dec(&dev->num_qps);
381
382 return ERR_PTR(ret);
383}
384
385static void pvrdma_free_qp(struct pvrdma_qp *qp)
386{
387 struct pvrdma_dev *dev = to_vdev(qp->ibqp.device);
388 struct pvrdma_cq *scq;
389 struct pvrdma_cq *rcq;
390 unsigned long flags, scq_flags, rcq_flags;
391
392 /* In case cq is polling */
393 get_cqs(qp, &scq, &rcq);
394 pvrdma_lock_cqs(scq, rcq, &scq_flags, &rcq_flags);
395
396 _pvrdma_flush_cqe(qp, scq);
397 if (scq != rcq)
398 _pvrdma_flush_cqe(qp, rcq);
399
400 spin_lock_irqsave(&dev->qp_tbl_lock, flags);
401 dev->qp_tbl[qp->qp_handle] = NULL;
402 spin_unlock_irqrestore(&dev->qp_tbl_lock, flags);
403
404 pvrdma_unlock_cqs(scq, rcq, &scq_flags, &rcq_flags);
405
406 atomic_dec(&qp->refcnt);
407 wait_event(qp->wait, !atomic_read(&qp->refcnt));
408
409 pvrdma_page_dir_cleanup(dev, &qp->pdir);
410
411 kfree(qp);
412
413 atomic_dec(&dev->num_qps);
414}
415
416/**
417 * pvrdma_destroy_qp - destroy a queue pair
418 * @qp: the queue pair to destroy
419 *
420 * @return: 0 on success.
421 */
422int pvrdma_destroy_qp(struct ib_qp *qp)
423{
424 struct pvrdma_qp *vqp = to_vqp(qp);
425 union pvrdma_cmd_req req;
426 struct pvrdma_cmd_destroy_qp *cmd = &req.destroy_qp;
427 int ret;
428
429 memset(cmd, 0, sizeof(*cmd));
430 cmd->hdr.cmd = PVRDMA_CMD_DESTROY_QP;
431 cmd->qp_handle = vqp->qp_handle;
432
433 ret = pvrdma_cmd_post(to_vdev(qp->device), &req, NULL, 0);
434 if (ret < 0)
435 dev_warn(&to_vdev(qp->device)->pdev->dev,
436 "destroy queuepair failed, error: %d\n", ret);
437
438 pvrdma_free_qp(vqp);
439
440 return 0;
441}
442
443/**
444 * pvrdma_modify_qp - modify queue pair attributes
445 * @ibqp: the queue pair
446 * @attr: the new queue pair's attributes
447 * @attr_mask: attributes mask
448 * @udata: user data
449 *
450 * @returns 0 on success, otherwise returns an errno.
451 */
452int pvrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
453 int attr_mask, struct ib_udata *udata)
454{
455 struct pvrdma_dev *dev = to_vdev(ibqp->device);
456 struct pvrdma_qp *qp = to_vqp(ibqp);
457 union pvrdma_cmd_req req;
458 union pvrdma_cmd_resp rsp;
459 struct pvrdma_cmd_modify_qp *cmd = &req.modify_qp;
460 int cur_state, next_state;
461 int ret;
462
463 /* Sanity checking. Should need lock here */
464 mutex_lock(&qp->mutex);
465 cur_state = (attr_mask & IB_QP_CUR_STATE) ? attr->cur_qp_state :
466 qp->state;
467 next_state = (attr_mask & IB_QP_STATE) ? attr->qp_state : cur_state;
468
469 if (!ib_modify_qp_is_ok(cur_state, next_state, ibqp->qp_type,
470 attr_mask, IB_LINK_LAYER_ETHERNET)) {
471 ret = -EINVAL;
472 goto out;
473 }
474
475 if (attr_mask & IB_QP_PORT) {
476 if (attr->port_num == 0 ||
477 attr->port_num > ibqp->device->phys_port_cnt) {
478 ret = -EINVAL;
479 goto out;
480 }
481 }
482
483 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
484 if (attr->min_rnr_timer > 31) {
485 ret = -EINVAL;
486 goto out;
487 }
488 }
489
490 if (attr_mask & IB_QP_PKEY_INDEX) {
491 if (attr->pkey_index >= dev->dsr->caps.max_pkeys) {
492 ret = -EINVAL;
493 goto out;
494 }
495 }
496
497 if (attr_mask & IB_QP_QKEY)
498 qp->qkey = attr->qkey;
499
500 if (cur_state == next_state && cur_state == IB_QPS_RESET) {
501 ret = 0;
502 goto out;
503 }
504
505 qp->state = next_state;
506 memset(cmd, 0, sizeof(*cmd));
507 cmd->hdr.cmd = PVRDMA_CMD_MODIFY_QP;
508 cmd->qp_handle = qp->qp_handle;
509 cmd->attr_mask = ib_qp_attr_mask_to_pvrdma(attr_mask);
510 cmd->attrs.qp_state = ib_qp_state_to_pvrdma(attr->qp_state);
511 cmd->attrs.cur_qp_state =
512 ib_qp_state_to_pvrdma(attr->cur_qp_state);
513 cmd->attrs.path_mtu = ib_mtu_to_pvrdma(attr->path_mtu);
514 cmd->attrs.path_mig_state =
515 ib_mig_state_to_pvrdma(attr->path_mig_state);
516 cmd->attrs.qkey = attr->qkey;
517 cmd->attrs.rq_psn = attr->rq_psn;
518 cmd->attrs.sq_psn = attr->sq_psn;
519 cmd->attrs.dest_qp_num = attr->dest_qp_num;
520 cmd->attrs.qp_access_flags =
521 ib_access_flags_to_pvrdma(attr->qp_access_flags);
522 cmd->attrs.pkey_index = attr->pkey_index;
523 cmd->attrs.alt_pkey_index = attr->alt_pkey_index;
524 cmd->attrs.en_sqd_async_notify = attr->en_sqd_async_notify;
525 cmd->attrs.sq_draining = attr->sq_draining;
526 cmd->attrs.max_rd_atomic = attr->max_rd_atomic;
527 cmd->attrs.max_dest_rd_atomic = attr->max_dest_rd_atomic;
528 cmd->attrs.min_rnr_timer = attr->min_rnr_timer;
529 cmd->attrs.port_num = attr->port_num;
530 cmd->attrs.timeout = attr->timeout;
531 cmd->attrs.retry_cnt = attr->retry_cnt;
532 cmd->attrs.rnr_retry = attr->rnr_retry;
533 cmd->attrs.alt_port_num = attr->alt_port_num;
534 cmd->attrs.alt_timeout = attr->alt_timeout;
535 ib_qp_cap_to_pvrdma(&cmd->attrs.cap, &attr->cap);
536 ib_ah_attr_to_pvrdma(&cmd->attrs.ah_attr, &attr->ah_attr);
537 ib_ah_attr_to_pvrdma(&cmd->attrs.alt_ah_attr, &attr->alt_ah_attr);
538
539 ret = pvrdma_cmd_post(dev, &req, &rsp, PVRDMA_CMD_MODIFY_QP_RESP);
540 if (ret < 0) {
541 dev_warn(&dev->pdev->dev,
542 "could not modify queuepair, error: %d\n", ret);
543 } else if (rsp.hdr.err > 0) {
544 dev_warn(&dev->pdev->dev,
545 "cannot modify queuepair, error: %d\n", rsp.hdr.err);
546 ret = -EINVAL;
547 }
548
549 if (ret == 0 && next_state == IB_QPS_RESET)
550 pvrdma_reset_qp(qp);
551
552out:
553 mutex_unlock(&qp->mutex);
554
555 return ret;
556}
557
558static inline void *get_sq_wqe(struct pvrdma_qp *qp, int n)
559{
560 return pvrdma_page_dir_get_ptr(&qp->pdir,
561 qp->sq.offset + n * qp->sq.wqe_size);
562}
563
564static inline void *get_rq_wqe(struct pvrdma_qp *qp, int n)
565{
566 return pvrdma_page_dir_get_ptr(&qp->pdir,
567 qp->rq.offset + n * qp->rq.wqe_size);
568}
569
570static int set_reg_seg(struct pvrdma_sq_wqe_hdr *wqe_hdr, struct ib_reg_wr *wr)
571{
572 struct pvrdma_user_mr *mr = to_vmr(wr->mr);
573
574 wqe_hdr->wr.fast_reg.iova_start = mr->ibmr.iova;
575 wqe_hdr->wr.fast_reg.pl_pdir_dma = mr->pdir.dir_dma;
576 wqe_hdr->wr.fast_reg.page_shift = mr->page_shift;
577 wqe_hdr->wr.fast_reg.page_list_len = mr->npages;
578 wqe_hdr->wr.fast_reg.length = mr->ibmr.length;
579 wqe_hdr->wr.fast_reg.access_flags = wr->access;
580 wqe_hdr->wr.fast_reg.rkey = wr->key;
581
582 return pvrdma_page_dir_insert_page_list(&mr->pdir, mr->pages,
583 mr->npages);
584}
585
586/**
587 * pvrdma_post_send - post send work request entries on a QP
588 * @ibqp: the QP
589 * @wr: work request list to post
590 * @bad_wr: the first bad WR returned
591 *
592 * @return: 0 on success, otherwise errno returned.
593 */
594int pvrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
595 struct ib_send_wr **bad_wr)
596{
597 struct pvrdma_qp *qp = to_vqp(ibqp);
598 struct pvrdma_dev *dev = to_vdev(ibqp->device);
599 unsigned long flags;
600 struct pvrdma_sq_wqe_hdr *wqe_hdr;
601 struct pvrdma_sge *sge;
602 int i, index;
603 int nreq;
604 int ret;
605
606 /*
607 * In states lower than RTS, we can fail immediately. In other states,
608 * just post and let the device figure it out.
609 */
610 if (qp->state < IB_QPS_RTS) {
611 *bad_wr = wr;
612 return -EINVAL;
613 }
614
615 spin_lock_irqsave(&qp->sq.lock, flags);
616
617 index = pvrdma_idx(&qp->sq.ring->prod_tail, qp->sq.wqe_cnt);
618 for (nreq = 0; wr; nreq++, wr = wr->next) {
619 unsigned int tail;
620
621 if (unlikely(!pvrdma_idx_ring_has_space(
622 qp->sq.ring, qp->sq.wqe_cnt, &tail))) {
623 dev_warn_ratelimited(&dev->pdev->dev,
624 "send queue is full\n");
625 *bad_wr = wr;
626 ret = -ENOMEM;
627 goto out;
628 }
629
630 if (unlikely(wr->num_sge > qp->sq.max_sg || wr->num_sge < 0)) {
631 dev_warn_ratelimited(&dev->pdev->dev,
632 "send SGE overflow\n");
633 *bad_wr = wr;
634 ret = -EINVAL;
635 goto out;
636 }
637
638 if (unlikely(wr->opcode < 0)) {
639 dev_warn_ratelimited(&dev->pdev->dev,
640 "invalid send opcode\n");
641 *bad_wr = wr;
642 ret = -EINVAL;
643 goto out;
644 }
645
646 /*
647 * Only support UD, RC.
648 * Need to check opcode table for thorough checking.
649 * opcode _UD _UC _RC
650 * _SEND x x x
651 * _SEND_WITH_IMM x x x
652 * _RDMA_WRITE x x
653 * _RDMA_WRITE_WITH_IMM x x
654 * _LOCAL_INV x x
655 * _SEND_WITH_INV x x
656 * _RDMA_READ x
657 * _ATOMIC_CMP_AND_SWP x
658 * _ATOMIC_FETCH_AND_ADD x
659 * _MASK_ATOMIC_CMP_AND_SWP x
660 * _MASK_ATOMIC_FETCH_AND_ADD x
661 * _REG_MR x
662 *
663 */
664 if (qp->ibqp.qp_type != IB_QPT_UD &&
665 qp->ibqp.qp_type != IB_QPT_RC &&
666 wr->opcode != IB_WR_SEND) {
667 dev_warn_ratelimited(&dev->pdev->dev,
668 "unsupported queuepair type\n");
669 *bad_wr = wr;
670 ret = -EINVAL;
671 goto out;
672 } else if (qp->ibqp.qp_type == IB_QPT_UD ||
673 qp->ibqp.qp_type == IB_QPT_GSI) {
674 if (wr->opcode != IB_WR_SEND &&
675 wr->opcode != IB_WR_SEND_WITH_IMM) {
676 dev_warn_ratelimited(&dev->pdev->dev,
677 "invalid send opcode\n");
678 *bad_wr = wr;
679 ret = -EINVAL;
680 goto out;
681 }
682 }
683
684 wqe_hdr = (struct pvrdma_sq_wqe_hdr *)get_sq_wqe(qp, index);
685 memset(wqe_hdr, 0, sizeof(*wqe_hdr));
686 wqe_hdr->wr_id = wr->wr_id;
687 wqe_hdr->num_sge = wr->num_sge;
688 wqe_hdr->opcode = ib_wr_opcode_to_pvrdma(wr->opcode);
689 wqe_hdr->send_flags = ib_send_flags_to_pvrdma(wr->send_flags);
690 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
691 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
692 wqe_hdr->ex.imm_data = wr->ex.imm_data;
693
694 switch (qp->ibqp.qp_type) {
695 case IB_QPT_GSI:
696 case IB_QPT_UD:
697 if (unlikely(!ud_wr(wr)->ah)) {
698 dev_warn_ratelimited(&dev->pdev->dev,
699 "invalid address handle\n");
700 *bad_wr = wr;
701 ret = -EINVAL;
702 goto out;
703 }
704
705 /*
706 * Use qkey from qp context if high order bit set,
707 * otherwise from work request.
708 */
709 wqe_hdr->wr.ud.remote_qpn = ud_wr(wr)->remote_qpn;
710 wqe_hdr->wr.ud.remote_qkey =
711 ud_wr(wr)->remote_qkey & 0x80000000 ?
712 qp->qkey : ud_wr(wr)->remote_qkey;
713 wqe_hdr->wr.ud.av = to_vah(ud_wr(wr)->ah)->av;
714
715 break;
716 case IB_QPT_RC:
717 switch (wr->opcode) {
718 case IB_WR_RDMA_READ:
719 case IB_WR_RDMA_WRITE:
720 case IB_WR_RDMA_WRITE_WITH_IMM:
721 wqe_hdr->wr.rdma.remote_addr =
722 rdma_wr(wr)->remote_addr;
723 wqe_hdr->wr.rdma.rkey = rdma_wr(wr)->rkey;
724 break;
725 case IB_WR_LOCAL_INV:
726 case IB_WR_SEND_WITH_INV:
727 wqe_hdr->ex.invalidate_rkey =
728 wr->ex.invalidate_rkey;
729 break;
730 case IB_WR_ATOMIC_CMP_AND_SWP:
731 case IB_WR_ATOMIC_FETCH_AND_ADD:
732 wqe_hdr->wr.atomic.remote_addr =
733 atomic_wr(wr)->remote_addr;
734 wqe_hdr->wr.atomic.rkey = atomic_wr(wr)->rkey;
735 wqe_hdr->wr.atomic.compare_add =
736 atomic_wr(wr)->compare_add;
737 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP)
738 wqe_hdr->wr.atomic.swap =
739 atomic_wr(wr)->swap;
740 break;
741 case IB_WR_REG_MR:
742 ret = set_reg_seg(wqe_hdr, reg_wr(wr));
743 if (ret < 0) {
744 dev_warn_ratelimited(&dev->pdev->dev,
745 "Failed to set fast register work request\n");
746 *bad_wr = wr;
747 goto out;
748 }
749 break;
750 default:
751 break;
752 }
753
754 break;
755 default:
756 dev_warn_ratelimited(&dev->pdev->dev,
757 "invalid queuepair type\n");
758 ret = -EINVAL;
759 *bad_wr = wr;
760 goto out;
761 }
762
763 sge = (struct pvrdma_sge *)(wqe_hdr + 1);
764 for (i = 0; i < wr->num_sge; i++) {
765 /* Need to check wqe_size 0 or max size */
766 sge->addr = wr->sg_list[i].addr;
767 sge->length = wr->sg_list[i].length;
768 sge->lkey = wr->sg_list[i].lkey;
769 sge++;
770 }
771
772 /* Make sure wqe is written before index update */
773 smp_wmb();
774
775 index++;
776 if (unlikely(index >= qp->sq.wqe_cnt))
777 index = 0;
778 /* Update shared sq ring */
779 pvrdma_idx_ring_inc(&qp->sq.ring->prod_tail,
780 qp->sq.wqe_cnt);
781 }
782
783 ret = 0;
784
785out:
786 spin_unlock_irqrestore(&qp->sq.lock, flags);
787
788 if (!ret)
789 pvrdma_write_uar_qp(dev, PVRDMA_UAR_QP_SEND | qp->qp_handle);
790
791 return ret;
792}
793
794/**
795 * pvrdma_post_receive - post receive work request entries on a QP
796 * @ibqp: the QP
797 * @wr: the work request list to post
798 * @bad_wr: the first bad WR returned
799 *
800 * @return: 0 on success, otherwise errno returned.
801 */
802int pvrdma_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
803 struct ib_recv_wr **bad_wr)
804{
805 struct pvrdma_dev *dev = to_vdev(ibqp->device);
806 unsigned long flags;
807 struct pvrdma_qp *qp = to_vqp(ibqp);
808 struct pvrdma_rq_wqe_hdr *wqe_hdr;
809 struct pvrdma_sge *sge;
810 int index, nreq;
811 int ret = 0;
812 int i;
813
814 /*
815 * In the RESET state, we can fail immediately. For other states,
816 * just post and let the device figure it out.
817 */
818 if (qp->state == IB_QPS_RESET) {
819 *bad_wr = wr;
820 return -EINVAL;
821 }
822
823 spin_lock_irqsave(&qp->rq.lock, flags);
824
825 index = pvrdma_idx(&qp->rq.ring->prod_tail, qp->rq.wqe_cnt);
826 for (nreq = 0; wr; nreq++, wr = wr->next) {
827 unsigned int tail;
828
829 if (unlikely(wr->num_sge > qp->rq.max_sg ||
830 wr->num_sge < 0)) {
831 ret = -EINVAL;
832 *bad_wr = wr;
833 dev_warn_ratelimited(&dev->pdev->dev,
834 "recv SGE overflow\n");
835 goto out;
836 }
837
838 if (unlikely(!pvrdma_idx_ring_has_space(
839 qp->rq.ring, qp->rq.wqe_cnt, &tail))) {
840 ret = -ENOMEM;
841 *bad_wr = wr;
842 dev_warn_ratelimited(&dev->pdev->dev,
843 "recv queue full\n");
844 goto out;
845 }
846
847 wqe_hdr = (struct pvrdma_rq_wqe_hdr *)get_rq_wqe(qp, index);
848 wqe_hdr->wr_id = wr->wr_id;
849 wqe_hdr->num_sge = wr->num_sge;
850 wqe_hdr->total_len = 0;
851
852 sge = (struct pvrdma_sge *)(wqe_hdr + 1);
853 for (i = 0; i < wr->num_sge; i++) {
854 sge->addr = wr->sg_list[i].addr;
855 sge->length = wr->sg_list[i].length;
856 sge->lkey = wr->sg_list[i].lkey;
857 sge++;
858 }
859
860 /* Make sure wqe is written before index update */
861 smp_wmb();
862
863 index++;
864 if (unlikely(index >= qp->rq.wqe_cnt))
865 index = 0;
866 /* Update shared rq ring */
867 pvrdma_idx_ring_inc(&qp->rq.ring->prod_tail,
868 qp->rq.wqe_cnt);
869 }
870
871 spin_unlock_irqrestore(&qp->rq.lock, flags);
872
873 pvrdma_write_uar_qp(dev, PVRDMA_UAR_QP_RECV | qp->qp_handle);
874
875 return ret;
876
877out:
878 spin_unlock_irqrestore(&qp->rq.lock, flags);
879
880 return ret;
881}
882
883/**
884 * pvrdma_query_qp - query a queue pair's attributes
885 * @ibqp: the queue pair to query
886 * @attr: the queue pair's attributes
887 * @attr_mask: attributes mask
888 * @init_attr: initial queue pair attributes
889 *
890 * @returns 0 on success, otherwise returns an errno.
891 */
892int pvrdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
893 int attr_mask, struct ib_qp_init_attr *init_attr)
894{
895 struct pvrdma_dev *dev = to_vdev(ibqp->device);
896 struct pvrdma_qp *qp = to_vqp(ibqp);
897 union pvrdma_cmd_req req;
898 union pvrdma_cmd_resp rsp;
899 struct pvrdma_cmd_query_qp *cmd = &req.query_qp;
900 struct pvrdma_cmd_query_qp_resp *resp = &rsp.query_qp_resp;
901 int ret = 0;
902
903 mutex_lock(&qp->mutex);
904
905 if (qp->state == IB_QPS_RESET) {
906 attr->qp_state = IB_QPS_RESET;
907 goto out;
908 }
909
910 memset(cmd, 0, sizeof(*cmd));
911 cmd->hdr.cmd = PVRDMA_CMD_QUERY_QP;
912 cmd->qp_handle = qp->qp_handle;
913 cmd->attr_mask = ib_qp_attr_mask_to_pvrdma(attr_mask);
914
915 ret = pvrdma_cmd_post(dev, &req, &rsp, PVRDMA_CMD_QUERY_QP_RESP);
916 if (ret < 0) {
917 dev_warn(&dev->pdev->dev,
918 "could not query queuepair, error: %d\n", ret);
919 goto out;
920 }
921
922 attr->qp_state = pvrdma_qp_state_to_ib(resp->attrs.qp_state);
923 attr->cur_qp_state =
924 pvrdma_qp_state_to_ib(resp->attrs.cur_qp_state);
925 attr->path_mtu = pvrdma_mtu_to_ib(resp->attrs.path_mtu);
926 attr->path_mig_state =
927 pvrdma_mig_state_to_ib(resp->attrs.path_mig_state);
928 attr->qkey = resp->attrs.qkey;
929 attr->rq_psn = resp->attrs.rq_psn;
930 attr->sq_psn = resp->attrs.sq_psn;
931 attr->dest_qp_num = resp->attrs.dest_qp_num;
932 attr->qp_access_flags =
933 pvrdma_access_flags_to_ib(resp->attrs.qp_access_flags);
934 attr->pkey_index = resp->attrs.pkey_index;
935 attr->alt_pkey_index = resp->attrs.alt_pkey_index;
936 attr->en_sqd_async_notify = resp->attrs.en_sqd_async_notify;
937 attr->sq_draining = resp->attrs.sq_draining;
938 attr->max_rd_atomic = resp->attrs.max_rd_atomic;
939 attr->max_dest_rd_atomic = resp->attrs.max_dest_rd_atomic;
940 attr->min_rnr_timer = resp->attrs.min_rnr_timer;
941 attr->port_num = resp->attrs.port_num;
942 attr->timeout = resp->attrs.timeout;
943 attr->retry_cnt = resp->attrs.retry_cnt;
944 attr->rnr_retry = resp->attrs.rnr_retry;
945 attr->alt_port_num = resp->attrs.alt_port_num;
946 attr->alt_timeout = resp->attrs.alt_timeout;
947 pvrdma_qp_cap_to_ib(&attr->cap, &resp->attrs.cap);
948 pvrdma_ah_attr_to_ib(&attr->ah_attr, &resp->attrs.ah_attr);
949 pvrdma_ah_attr_to_ib(&attr->alt_ah_attr, &resp->attrs.alt_ah_attr);
950
951 qp->state = attr->qp_state;
952
953 ret = 0;
954
955out:
956 attr->cur_qp_state = attr->qp_state;
957
958 init_attr->event_handler = qp->ibqp.event_handler;
959 init_attr->qp_context = qp->ibqp.qp_context;
960 init_attr->send_cq = qp->ibqp.send_cq;
961 init_attr->recv_cq = qp->ibqp.recv_cq;
962 init_attr->srq = qp->ibqp.srq;
963 init_attr->xrcd = NULL;
964 init_attr->cap = attr->cap;
965 init_attr->sq_sig_type = 0;
966 init_attr->qp_type = qp->ibqp.qp_type;
967 init_attr->create_flags = 0;
968 init_attr->port_num = qp->port;
969
970 mutex_unlock(&qp->mutex);
971 return ret;
972}
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_ring.h b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_ring.h
new file mode 100644
index 000000000000..ed9022a91a1d
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_ring.h
@@ -0,0 +1,131 @@
1/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#ifndef __PVRDMA_RING_H__
47#define __PVRDMA_RING_H__
48
49#include <linux/types.h>
50
51#define PVRDMA_INVALID_IDX -1 /* Invalid index. */
52
53struct pvrdma_ring {
54 atomic_t prod_tail; /* Producer tail. */
55 atomic_t cons_head; /* Consumer head. */
56};
57
58struct pvrdma_ring_state {
59 struct pvrdma_ring tx; /* Tx ring. */
60 struct pvrdma_ring rx; /* Rx ring. */
61};
62
63static inline int pvrdma_idx_valid(__u32 idx, __u32 max_elems)
64{
65 /* Generates fewer instructions than a less-than. */
66 return (idx & ~((max_elems << 1) - 1)) == 0;
67}
68
69static inline __s32 pvrdma_idx(atomic_t *var, __u32 max_elems)
70{
71 const unsigned int idx = atomic_read(var);
72
73 if (pvrdma_idx_valid(idx, max_elems))
74 return idx & (max_elems - 1);
75 return PVRDMA_INVALID_IDX;
76}
77
78static inline void pvrdma_idx_ring_inc(atomic_t *var, __u32 max_elems)
79{
80 __u32 idx = atomic_read(var) + 1; /* Increment. */
81
82 idx &= (max_elems << 1) - 1; /* Modulo size, flip gen. */
83 atomic_set(var, idx);
84}
85
86static inline __s32 pvrdma_idx_ring_has_space(const struct pvrdma_ring *r,
87 __u32 max_elems, __u32 *out_tail)
88{
89 const __u32 tail = atomic_read(&r->prod_tail);
90 const __u32 head = atomic_read(&r->cons_head);
91
92 if (pvrdma_idx_valid(tail, max_elems) &&
93 pvrdma_idx_valid(head, max_elems)) {
94 *out_tail = tail & (max_elems - 1);
95 return tail != (head ^ max_elems);
96 }
97 return PVRDMA_INVALID_IDX;
98}
99
100static inline __s32 pvrdma_idx_ring_has_data(const struct pvrdma_ring *r,
101 __u32 max_elems, __u32 *out_head)
102{
103 const __u32 tail = atomic_read(&r->prod_tail);
104 const __u32 head = atomic_read(&r->cons_head);
105
106 if (pvrdma_idx_valid(tail, max_elems) &&
107 pvrdma_idx_valid(head, max_elems)) {
108 *out_head = head & (max_elems - 1);
109 return tail != head;
110 }
111 return PVRDMA_INVALID_IDX;
112}
113
114static inline bool pvrdma_idx_ring_is_valid_idx(const struct pvrdma_ring *r,
115 __u32 max_elems, __u32 *idx)
116{
117 const __u32 tail = atomic_read(&r->prod_tail);
118 const __u32 head = atomic_read(&r->cons_head);
119
120 if (pvrdma_idx_valid(tail, max_elems) &&
121 pvrdma_idx_valid(head, max_elems) &&
122 pvrdma_idx_valid(*idx, max_elems)) {
123 if (tail > head && (*idx < tail && *idx >= head))
124 return true;
125 else if (head > tail && (*idx >= head || *idx < tail))
126 return true;
127 }
128 return false;
129}
130
131#endif /* __PVRDMA_RING_H__ */
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c
new file mode 100644
index 000000000000..54891370d18a
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.c
@@ -0,0 +1,579 @@
1/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#include <asm/page.h>
47#include <linux/inet.h>
48#include <linux/io.h>
49#include <rdma/ib_addr.h>
50#include <rdma/ib_smi.h>
51#include <rdma/ib_user_verbs.h>
52#include <rdma/vmw_pvrdma-abi.h>
53
54#include "pvrdma.h"
55
56/**
57 * pvrdma_query_device - query device
58 * @ibdev: the device to query
59 * @props: the device properties
60 * @uhw: user data
61 *
62 * @return: 0 on success, otherwise negative errno
63 */
64int pvrdma_query_device(struct ib_device *ibdev,
65 struct ib_device_attr *props,
66 struct ib_udata *uhw)
67{
68 struct pvrdma_dev *dev = to_vdev(ibdev);
69
70 if (uhw->inlen || uhw->outlen)
71 return -EINVAL;
72
73 memset(props, 0, sizeof(*props));
74
75 props->fw_ver = dev->dsr->caps.fw_ver;
76 props->sys_image_guid = dev->dsr->caps.sys_image_guid;
77 props->max_mr_size = dev->dsr->caps.max_mr_size;
78 props->page_size_cap = dev->dsr->caps.page_size_cap;
79 props->vendor_id = dev->dsr->caps.vendor_id;
80 props->vendor_part_id = dev->pdev->device;
81 props->hw_ver = dev->dsr->caps.hw_ver;
82 props->max_qp = dev->dsr->caps.max_qp;
83 props->max_qp_wr = dev->dsr->caps.max_qp_wr;
84 props->device_cap_flags = dev->dsr->caps.device_cap_flags;
85 props->max_sge = dev->dsr->caps.max_sge;
86 props->max_cq = dev->dsr->caps.max_cq;
87 props->max_cqe = dev->dsr->caps.max_cqe;
88 props->max_mr = dev->dsr->caps.max_mr;
89 props->max_pd = dev->dsr->caps.max_pd;
90 props->max_qp_rd_atom = dev->dsr->caps.max_qp_rd_atom;
91 props->max_qp_init_rd_atom = dev->dsr->caps.max_qp_init_rd_atom;
92 props->atomic_cap =
93 dev->dsr->caps.atomic_ops &
94 (PVRDMA_ATOMIC_OP_COMP_SWAP | PVRDMA_ATOMIC_OP_FETCH_ADD) ?
95 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
96 props->masked_atomic_cap = props->atomic_cap;
97 props->max_ah = dev->dsr->caps.max_ah;
98 props->max_pkeys = dev->dsr->caps.max_pkeys;
99 props->local_ca_ack_delay = dev->dsr->caps.local_ca_ack_delay;
100 if ((dev->dsr->caps.bmme_flags & PVRDMA_BMME_FLAG_LOCAL_INV) &&
101 (dev->dsr->caps.bmme_flags & PVRDMA_BMME_FLAG_REMOTE_INV) &&
102 (dev->dsr->caps.bmme_flags & PVRDMA_BMME_FLAG_FAST_REG_WR)) {
103 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
104 }
105
106 return 0;
107}
108
109/**
110 * pvrdma_query_port - query device port attributes
111 * @ibdev: the device to query
112 * @port: the port number
113 * @props: the device properties
114 *
115 * @return: 0 on success, otherwise negative errno
116 */
117int pvrdma_query_port(struct ib_device *ibdev, u8 port,
118 struct ib_port_attr *props)
119{
120 struct pvrdma_dev *dev = to_vdev(ibdev);
121 union pvrdma_cmd_req req;
122 union pvrdma_cmd_resp rsp;
123 struct pvrdma_cmd_query_port *cmd = &req.query_port;
124 struct pvrdma_cmd_query_port_resp *resp = &rsp.query_port_resp;
125 int err;
126
127 memset(cmd, 0, sizeof(*cmd));
128 cmd->hdr.cmd = PVRDMA_CMD_QUERY_PORT;
129 cmd->port_num = port;
130
131 err = pvrdma_cmd_post(dev, &req, &rsp, PVRDMA_CMD_QUERY_PORT_RESP);
132 if (err < 0) {
133 dev_warn(&dev->pdev->dev,
134 "could not query port, error: %d\n", err);
135 return err;
136 }
137
138 memset(props, 0, sizeof(*props));
139
140 props->state = pvrdma_port_state_to_ib(resp->attrs.state);
141 props->max_mtu = pvrdma_mtu_to_ib(resp->attrs.max_mtu);
142 props->active_mtu = pvrdma_mtu_to_ib(resp->attrs.active_mtu);
143 props->gid_tbl_len = resp->attrs.gid_tbl_len;
144 props->port_cap_flags =
145 pvrdma_port_cap_flags_to_ib(resp->attrs.port_cap_flags);
146 props->max_msg_sz = resp->attrs.max_msg_sz;
147 props->bad_pkey_cntr = resp->attrs.bad_pkey_cntr;
148 props->qkey_viol_cntr = resp->attrs.qkey_viol_cntr;
149 props->pkey_tbl_len = resp->attrs.pkey_tbl_len;
150 props->lid = resp->attrs.lid;
151 props->sm_lid = resp->attrs.sm_lid;
152 props->lmc = resp->attrs.lmc;
153 props->max_vl_num = resp->attrs.max_vl_num;
154 props->sm_sl = resp->attrs.sm_sl;
155 props->subnet_timeout = resp->attrs.subnet_timeout;
156 props->init_type_reply = resp->attrs.init_type_reply;
157 props->active_width = pvrdma_port_width_to_ib(resp->attrs.active_width);
158 props->active_speed = pvrdma_port_speed_to_ib(resp->attrs.active_speed);
159 props->phys_state = resp->attrs.phys_state;
160
161 return 0;
162}
163
164/**
165 * pvrdma_query_gid - query device gid
166 * @ibdev: the device to query
167 * @port: the port number
168 * @index: the index
169 * @gid: the device gid value
170 *
171 * @return: 0 on success, otherwise negative errno
172 */
173int pvrdma_query_gid(struct ib_device *ibdev, u8 port, int index,
174 union ib_gid *gid)
175{
176 struct pvrdma_dev *dev = to_vdev(ibdev);
177
178 if (index >= dev->dsr->caps.gid_tbl_len)
179 return -EINVAL;
180
181 memcpy(gid, &dev->sgid_tbl[index], sizeof(union ib_gid));
182
183 return 0;
184}
185
186/**
187 * pvrdma_query_pkey - query device port's P_Key table
188 * @ibdev: the device to query
189 * @port: the port number
190 * @index: the index
191 * @pkey: the device P_Key value
192 *
193 * @return: 0 on success, otherwise negative errno
194 */
195int pvrdma_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
196 u16 *pkey)
197{
198 int err = 0;
199 union pvrdma_cmd_req req;
200 union pvrdma_cmd_resp rsp;
201 struct pvrdma_cmd_query_pkey *cmd = &req.query_pkey;
202
203 memset(cmd, 0, sizeof(*cmd));
204 cmd->hdr.cmd = PVRDMA_CMD_QUERY_PKEY;
205 cmd->port_num = port;
206 cmd->index = index;
207
208 err = pvrdma_cmd_post(to_vdev(ibdev), &req, &rsp,
209 PVRDMA_CMD_QUERY_PKEY_RESP);
210 if (err < 0) {
211 dev_warn(&to_vdev(ibdev)->pdev->dev,
212 "could not query pkey, error: %d\n", err);
213 return err;
214 }
215
216 *pkey = rsp.query_pkey_resp.pkey;
217
218 return 0;
219}
220
221enum rdma_link_layer pvrdma_port_link_layer(struct ib_device *ibdev,
222 u8 port)
223{
224 return IB_LINK_LAYER_ETHERNET;
225}
226
227int pvrdma_modify_device(struct ib_device *ibdev, int mask,
228 struct ib_device_modify *props)
229{
230 unsigned long flags;
231
232 if (mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
233 IB_DEVICE_MODIFY_NODE_DESC)) {
234 dev_warn(&to_vdev(ibdev)->pdev->dev,
235 "unsupported device modify mask %#x\n", mask);
236 return -EOPNOTSUPP;
237 }
238
239 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
240 spin_lock_irqsave(&to_vdev(ibdev)->desc_lock, flags);
241 memcpy(ibdev->node_desc, props->node_desc, 64);
242 spin_unlock_irqrestore(&to_vdev(ibdev)->desc_lock, flags);
243 }
244
245 if (mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
246 mutex_lock(&to_vdev(ibdev)->port_mutex);
247 to_vdev(ibdev)->sys_image_guid =
248 cpu_to_be64(props->sys_image_guid);
249 mutex_unlock(&to_vdev(ibdev)->port_mutex);
250 }
251
252 return 0;
253}
254
255/**
256 * pvrdma_modify_port - modify device port attributes
257 * @ibdev: the device to modify
258 * @port: the port number
259 * @mask: attributes to modify
260 * @props: the device properties
261 *
262 * @return: 0 on success, otherwise negative errno
263 */
264int pvrdma_modify_port(struct ib_device *ibdev, u8 port, int mask,
265 struct ib_port_modify *props)
266{
267 struct ib_port_attr attr;
268 struct pvrdma_dev *vdev = to_vdev(ibdev);
269 int ret;
270
271 if (mask & ~IB_PORT_SHUTDOWN) {
272 dev_warn(&vdev->pdev->dev,
273 "unsupported port modify mask %#x\n", mask);
274 return -EOPNOTSUPP;
275 }
276
277 mutex_lock(&vdev->port_mutex);
278 ret = pvrdma_query_port(ibdev, port, &attr);
279 if (ret)
280 goto out;
281
282 vdev->port_cap_mask |= props->set_port_cap_mask;
283 vdev->port_cap_mask &= ~props->clr_port_cap_mask;
284
285 if (mask & IB_PORT_SHUTDOWN)
286 vdev->ib_active = false;
287
288out:
289 mutex_unlock(&vdev->port_mutex);
290 return ret;
291}
292
293/**
294 * pvrdma_alloc_ucontext - allocate ucontext
295 * @ibdev: the IB device
296 * @udata: user data
297 *
298 * @return: the ib_ucontext pointer on success, otherwise errno.
299 */
300struct ib_ucontext *pvrdma_alloc_ucontext(struct ib_device *ibdev,
301 struct ib_udata *udata)
302{
303 struct pvrdma_dev *vdev = to_vdev(ibdev);
304 struct pvrdma_ucontext *context;
305 union pvrdma_cmd_req req;
306 union pvrdma_cmd_resp rsp;
307 struct pvrdma_cmd_create_uc *cmd = &req.create_uc;
308 struct pvrdma_cmd_create_uc_resp *resp = &rsp.create_uc_resp;
309 struct pvrdma_alloc_ucontext_resp uresp;
310 int ret;
311 void *ptr;
312
313 if (!vdev->ib_active)
314 return ERR_PTR(-EAGAIN);
315
316 context = kmalloc(sizeof(*context), GFP_KERNEL);
317 if (!context)
318 return ERR_PTR(-ENOMEM);
319
320 context->dev = vdev;
321 ret = pvrdma_uar_alloc(vdev, &context->uar);
322 if (ret) {
323 kfree(context);
324 return ERR_PTR(-ENOMEM);
325 }
326
327 /* get ctx_handle from host */
328 memset(cmd, 0, sizeof(*cmd));
329 cmd->pfn = context->uar.pfn;
330 cmd->hdr.cmd = PVRDMA_CMD_CREATE_UC;
331 ret = pvrdma_cmd_post(vdev, &req, &rsp, PVRDMA_CMD_CREATE_UC_RESP);
332 if (ret < 0) {
333 dev_warn(&vdev->pdev->dev,
334 "could not create ucontext, error: %d\n", ret);
335 ptr = ERR_PTR(ret);
336 goto err;
337 }
338
339 context->ctx_handle = resp->ctx_handle;
340
341 /* copy back to user */
342 uresp.qp_tab_size = vdev->dsr->caps.max_qp;
343 ret = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
344 if (ret) {
345 pvrdma_uar_free(vdev, &context->uar);
346 context->ibucontext.device = ibdev;
347 pvrdma_dealloc_ucontext(&context->ibucontext);
348 return ERR_PTR(-EFAULT);
349 }
350
351 return &context->ibucontext;
352
353err:
354 pvrdma_uar_free(vdev, &context->uar);
355 kfree(context);
356 return ptr;
357}
358
359/**
360 * pvrdma_dealloc_ucontext - deallocate ucontext
361 * @ibcontext: the ucontext
362 *
363 * @return: 0 on success, otherwise errno.
364 */
365int pvrdma_dealloc_ucontext(struct ib_ucontext *ibcontext)
366{
367 struct pvrdma_ucontext *context = to_vucontext(ibcontext);
368 union pvrdma_cmd_req req;
369 struct pvrdma_cmd_destroy_uc *cmd = &req.destroy_uc;
370 int ret;
371
372 memset(cmd, 0, sizeof(*cmd));
373 cmd->hdr.cmd = PVRDMA_CMD_DESTROY_UC;
374 cmd->ctx_handle = context->ctx_handle;
375
376 ret = pvrdma_cmd_post(context->dev, &req, NULL, 0);
377 if (ret < 0)
378 dev_warn(&context->dev->pdev->dev,
379 "destroy ucontext failed, error: %d\n", ret);
380
381 /* Free the UAR even if the device command failed */
382 pvrdma_uar_free(to_vdev(ibcontext->device), &context->uar);
383 kfree(context);
384
385 return ret;
386}
387
388/**
389 * pvrdma_mmap - create mmap region
390 * @ibcontext: the user context
391 * @vma: the VMA
392 *
393 * @return: 0 on success, otherwise errno.
394 */
395int pvrdma_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
396{
397 struct pvrdma_ucontext *context = to_vucontext(ibcontext);
398 unsigned long start = vma->vm_start;
399 unsigned long size = vma->vm_end - vma->vm_start;
400 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
401
402 dev_dbg(&context->dev->pdev->dev, "create mmap region\n");
403
404 if ((size != PAGE_SIZE) || (offset & ~PAGE_MASK)) {
405 dev_warn(&context->dev->pdev->dev,
406 "invalid params for mmap region\n");
407 return -EINVAL;
408 }
409
410 /* Map UAR to kernel space, VM_LOCKED? */
411 vma->vm_flags |= VM_DONTCOPY | VM_DONTEXPAND;
412 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
413 if (io_remap_pfn_range(vma, start, context->uar.pfn, size,
414 vma->vm_page_prot))
415 return -EAGAIN;
416
417 return 0;
418}
419
420/**
421 * pvrdma_alloc_pd - allocate protection domain
422 * @ibdev: the IB device
423 * @context: user context
424 * @udata: user data
425 *
426 * @return: the ib_pd protection domain pointer on success, otherwise errno.
427 */
428struct ib_pd *pvrdma_alloc_pd(struct ib_device *ibdev,
429 struct ib_ucontext *context,
430 struct ib_udata *udata)
431{
432 struct pvrdma_pd *pd;
433 struct pvrdma_dev *dev = to_vdev(ibdev);
434 union pvrdma_cmd_req req;
435 union pvrdma_cmd_resp rsp;
436 struct pvrdma_cmd_create_pd *cmd = &req.create_pd;
437 struct pvrdma_cmd_create_pd_resp *resp = &rsp.create_pd_resp;
438 int ret;
439 void *ptr;
440
441 /* Check allowed max pds */
442 if (!atomic_add_unless(&dev->num_pds, 1, dev->dsr->caps.max_pd))
443 return ERR_PTR(-ENOMEM);
444
445 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
446 if (!pd) {
447 ptr = ERR_PTR(-ENOMEM);
448 goto err;
449 }
450
451 memset(cmd, 0, sizeof(*cmd));
452 cmd->hdr.cmd = PVRDMA_CMD_CREATE_PD;
453 cmd->ctx_handle = (context) ? to_vucontext(context)->ctx_handle : 0;
454 ret = pvrdma_cmd_post(dev, &req, &rsp, PVRDMA_CMD_CREATE_PD_RESP);
455 if (ret < 0) {
456 dev_warn(&dev->pdev->dev,
457 "failed to allocate protection domain, error: %d\n",
458 ret);
459 ptr = ERR_PTR(ret);
460 goto freepd;
461 }
462
463 pd->privileged = !context;
464 pd->pd_handle = resp->pd_handle;
465 pd->pdn = resp->pd_handle;
466
467 if (context) {
468 if (ib_copy_to_udata(udata, &pd->pdn, sizeof(__u32))) {
469 dev_warn(&dev->pdev->dev,
470 "failed to copy back protection domain\n");
471 pvrdma_dealloc_pd(&pd->ibpd);
472 return ERR_PTR(-EFAULT);
473 }
474 }
475
476 /* u32 pd handle */
477 return &pd->ibpd;
478
479freepd:
480 kfree(pd);
481err:
482 atomic_dec(&dev->num_pds);
483 return ptr;
484}
485
486/**
487 * pvrdma_dealloc_pd - deallocate protection domain
488 * @pd: the protection domain to be released
489 *
490 * @return: 0 on success, otherwise errno.
491 */
492int pvrdma_dealloc_pd(struct ib_pd *pd)
493{
494 struct pvrdma_dev *dev = to_vdev(pd->device);
495 union pvrdma_cmd_req req;
496 struct pvrdma_cmd_destroy_pd *cmd = &req.destroy_pd;
497 int ret;
498
499 memset(cmd, 0, sizeof(*cmd));
500 cmd->hdr.cmd = PVRDMA_CMD_DESTROY_PD;
501 cmd->pd_handle = to_vpd(pd)->pd_handle;
502
503 ret = pvrdma_cmd_post(dev, &req, NULL, 0);
504 if (ret)
505 dev_warn(&dev->pdev->dev,
506 "could not dealloc protection domain, error: %d\n",
507 ret);
508
509 kfree(to_vpd(pd));
510 atomic_dec(&dev->num_pds);
511
512 return 0;
513}
514
515/**
516 * pvrdma_create_ah - create an address handle
517 * @pd: the protection domain
518 * @ah_attr: the attributes of the AH
519 * @udata: user data blob
520 *
521 * @return: the ib_ah pointer on success, otherwise errno.
522 */
523struct ib_ah *pvrdma_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr,
524 struct ib_udata *udata)
525{
526 struct pvrdma_dev *dev = to_vdev(pd->device);
527 struct pvrdma_ah *ah;
528 enum rdma_link_layer ll;
529
530 if (!(ah_attr->ah_flags & IB_AH_GRH))
531 return ERR_PTR(-EINVAL);
532
533 ll = rdma_port_get_link_layer(pd->device, ah_attr->port_num);
534
535 if (ll != IB_LINK_LAYER_ETHERNET ||
536 rdma_is_multicast_addr((struct in6_addr *)ah_attr->grh.dgid.raw))
537 return ERR_PTR(-EINVAL);
538
539 if (!atomic_add_unless(&dev->num_ahs, 1, dev->dsr->caps.max_ah))
540 return ERR_PTR(-ENOMEM);
541
542 ah = kzalloc(sizeof(*ah), GFP_KERNEL);
543 if (!ah) {
544 atomic_dec(&dev->num_ahs);
545 return ERR_PTR(-ENOMEM);
546 }
547
548 ah->av.port_pd = to_vpd(pd)->pd_handle | (ah_attr->port_num << 24);
549 ah->av.src_path_bits = ah_attr->src_path_bits;
550 ah->av.src_path_bits |= 0x80;
551 ah->av.gid_index = ah_attr->grh.sgid_index;
552 ah->av.hop_limit = ah_attr->grh.hop_limit;
553 ah->av.sl_tclass_flowlabel = (ah_attr->grh.traffic_class << 20) |
554 ah_attr->grh.flow_label;
555 memcpy(ah->av.dgid, ah_attr->grh.dgid.raw, 16);
556 memcpy(ah->av.dmac, ah_attr->dmac, 6);
557
558 ah->ibah.device = pd->device;
559 ah->ibah.pd = pd;
560 ah->ibah.uobject = NULL;
561
562 return &ah->ibah;
563}
564
565/**
566 * pvrdma_destroy_ah - destroy an address handle
567 * @ah: the address handle to destroyed
568 *
569 * @return: 0 on success.
570 */
571int pvrdma_destroy_ah(struct ib_ah *ah)
572{
573 struct pvrdma_dev *dev = to_vdev(ah->device);
574
575 kfree(to_vah(ah));
576 atomic_dec(&dev->num_ahs);
577
578 return 0;
579}
diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h
new file mode 100644
index 000000000000..bfbe96b56255
--- /dev/null
+++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_verbs.h
@@ -0,0 +1,436 @@
1/*
2 * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of EITHER the GNU General Public License
6 * version 2 as published by the Free Software Foundation or the BSD
7 * 2-Clause License. This program is distributed in the hope that it
8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10 * See the GNU General Public License version 2 for more details at
11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program available in the file COPYING in the main
15 * directory of this source tree.
16 *
17 * The BSD 2-Clause License
18 *
19 * Redistribution and use in source and binary forms, with or
20 * without modification, are permitted provided that the following
21 * conditions are met:
22 *
23 * - Redistributions of source code must retain the above
24 * copyright notice, this list of conditions and the following
25 * disclaimer.
26 *
27 * - Redistributions in binary form must reproduce the above
28 * copyright notice, this list of conditions and the following
29 * disclaimer in the documentation and/or other materials
30 * provided with the distribution.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46#ifndef __PVRDMA_VERBS_H__
47#define __PVRDMA_VERBS_H__
48
49#include <linux/types.h>
50
51union pvrdma_gid {
52 u8 raw[16];
53 struct {
54 __be64 subnet_prefix;
55 __be64 interface_id;
56 } global;
57};
58
59enum pvrdma_link_layer {
60 PVRDMA_LINK_LAYER_UNSPECIFIED,
61 PVRDMA_LINK_LAYER_INFINIBAND,
62 PVRDMA_LINK_LAYER_ETHERNET,
63};
64
65enum pvrdma_mtu {
66 PVRDMA_MTU_256 = 1,
67 PVRDMA_MTU_512 = 2,
68 PVRDMA_MTU_1024 = 3,
69 PVRDMA_MTU_2048 = 4,
70 PVRDMA_MTU_4096 = 5,
71};
72
73static inline int pvrdma_mtu_enum_to_int(enum pvrdma_mtu mtu)
74{
75 switch (mtu) {
76 case PVRDMA_MTU_256: return 256;
77 case PVRDMA_MTU_512: return 512;
78 case PVRDMA_MTU_1024: return 1024;
79 case PVRDMA_MTU_2048: return 2048;
80 case PVRDMA_MTU_4096: return 4096;
81 default: return -1;
82 }
83}
84
85static inline enum pvrdma_mtu pvrdma_mtu_int_to_enum(int mtu)
86{
87 switch (mtu) {
88 case 256: return PVRDMA_MTU_256;
89 case 512: return PVRDMA_MTU_512;
90 case 1024: return PVRDMA_MTU_1024;
91 case 2048: return PVRDMA_MTU_2048;
92 case 4096:
93 default: return PVRDMA_MTU_4096;
94 }
95}
96
97enum pvrdma_port_state {
98 PVRDMA_PORT_NOP = 0,
99 PVRDMA_PORT_DOWN = 1,
100 PVRDMA_PORT_INIT = 2,
101 PVRDMA_PORT_ARMED = 3,
102 PVRDMA_PORT_ACTIVE = 4,
103 PVRDMA_PORT_ACTIVE_DEFER = 5,
104};
105
106enum pvrdma_port_cap_flags {
107 PVRDMA_PORT_SM = 1 << 1,
108 PVRDMA_PORT_NOTICE_SUP = 1 << 2,
109 PVRDMA_PORT_TRAP_SUP = 1 << 3,
110 PVRDMA_PORT_OPT_IPD_SUP = 1 << 4,
111 PVRDMA_PORT_AUTO_MIGR_SUP = 1 << 5,
112 PVRDMA_PORT_SL_MAP_SUP = 1 << 6,
113 PVRDMA_PORT_MKEY_NVRAM = 1 << 7,
114 PVRDMA_PORT_PKEY_NVRAM = 1 << 8,
115 PVRDMA_PORT_LED_INFO_SUP = 1 << 9,
116 PVRDMA_PORT_SM_DISABLED = 1 << 10,
117 PVRDMA_PORT_SYS_IMAGE_GUID_SUP = 1 << 11,
118 PVRDMA_PORT_PKEY_SW_EXT_PORT_TRAP_SUP = 1 << 12,
119 PVRDMA_PORT_EXTENDED_SPEEDS_SUP = 1 << 14,
120 PVRDMA_PORT_CM_SUP = 1 << 16,
121 PVRDMA_PORT_SNMP_TUNNEL_SUP = 1 << 17,
122 PVRDMA_PORT_REINIT_SUP = 1 << 18,
123 PVRDMA_PORT_DEVICE_MGMT_SUP = 1 << 19,
124 PVRDMA_PORT_VENDOR_CLASS_SUP = 1 << 20,
125 PVRDMA_PORT_DR_NOTICE_SUP = 1 << 21,
126 PVRDMA_PORT_CAP_MASK_NOTICE_SUP = 1 << 22,
127 PVRDMA_PORT_BOOT_MGMT_SUP = 1 << 23,
128 PVRDMA_PORT_LINK_LATENCY_SUP = 1 << 24,
129 PVRDMA_PORT_CLIENT_REG_SUP = 1 << 25,
130 PVRDMA_PORT_IP_BASED_GIDS = 1 << 26,
131 PVRDMA_PORT_CAP_FLAGS_MAX = PVRDMA_PORT_IP_BASED_GIDS,
132};
133
134enum pvrdma_port_width {
135 PVRDMA_WIDTH_1X = 1,
136 PVRDMA_WIDTH_4X = 2,
137 PVRDMA_WIDTH_8X = 4,
138 PVRDMA_WIDTH_12X = 8,
139};
140
141static inline int pvrdma_width_enum_to_int(enum pvrdma_port_width width)
142{
143 switch (width) {
144 case PVRDMA_WIDTH_1X: return 1;
145 case PVRDMA_WIDTH_4X: return 4;
146 case PVRDMA_WIDTH_8X: return 8;
147 case PVRDMA_WIDTH_12X: return 12;
148 default: return -1;
149 }
150}
151
152enum pvrdma_port_speed {
153 PVRDMA_SPEED_SDR = 1,
154 PVRDMA_SPEED_DDR = 2,
155 PVRDMA_SPEED_QDR = 4,
156 PVRDMA_SPEED_FDR10 = 8,
157 PVRDMA_SPEED_FDR = 16,
158 PVRDMA_SPEED_EDR = 32,
159};
160
161struct pvrdma_port_attr {
162 enum pvrdma_port_state state;
163 enum pvrdma_mtu max_mtu;
164 enum pvrdma_mtu active_mtu;
165 u32 gid_tbl_len;
166 u32 port_cap_flags;
167 u32 max_msg_sz;
168 u32 bad_pkey_cntr;
169 u32 qkey_viol_cntr;
170 u16 pkey_tbl_len;
171 u16 lid;
172 u16 sm_lid;
173 u8 lmc;
174 u8 max_vl_num;
175 u8 sm_sl;
176 u8 subnet_timeout;
177 u8 init_type_reply;
178 u8 active_width;
179 u8 active_speed;
180 u8 phys_state;
181 u8 reserved[2];
182};
183
184struct pvrdma_global_route {
185 union pvrdma_gid dgid;
186 u32 flow_label;
187 u8 sgid_index;
188 u8 hop_limit;
189 u8 traffic_class;
190 u8 reserved;
191};
192
193struct pvrdma_grh {
194 __be32 version_tclass_flow;
195 __be16 paylen;
196 u8 next_hdr;
197 u8 hop_limit;
198 union pvrdma_gid sgid;
199 union pvrdma_gid dgid;
200};
201
202enum pvrdma_ah_flags {
203 PVRDMA_AH_GRH = 1,
204};
205
206enum pvrdma_rate {
207 PVRDMA_RATE_PORT_CURRENT = 0,
208 PVRDMA_RATE_2_5_GBPS = 2,
209 PVRDMA_RATE_5_GBPS = 5,
210 PVRDMA_RATE_10_GBPS = 3,
211 PVRDMA_RATE_20_GBPS = 6,
212 PVRDMA_RATE_30_GBPS = 4,
213 PVRDMA_RATE_40_GBPS = 7,
214 PVRDMA_RATE_60_GBPS = 8,
215 PVRDMA_RATE_80_GBPS = 9,
216 PVRDMA_RATE_120_GBPS = 10,
217 PVRDMA_RATE_14_GBPS = 11,
218 PVRDMA_RATE_56_GBPS = 12,
219 PVRDMA_RATE_112_GBPS = 13,
220 PVRDMA_RATE_168_GBPS = 14,
221 PVRDMA_RATE_25_GBPS = 15,
222 PVRDMA_RATE_100_GBPS = 16,
223 PVRDMA_RATE_200_GBPS = 17,
224 PVRDMA_RATE_300_GBPS = 18,
225};
226
227struct pvrdma_ah_attr {
228 struct pvrdma_global_route grh;
229 u16 dlid;
230 u16 vlan_id;
231 u8 sl;
232 u8 src_path_bits;
233 u8 static_rate;
234 u8 ah_flags;
235 u8 port_num;
236 u8 dmac[6];
237 u8 reserved;
238};
239
240enum pvrdma_cq_notify_flags {
241 PVRDMA_CQ_SOLICITED = 1 << 0,
242 PVRDMA_CQ_NEXT_COMP = 1 << 1,
243 PVRDMA_CQ_SOLICITED_MASK = PVRDMA_CQ_SOLICITED |
244 PVRDMA_CQ_NEXT_COMP,
245 PVRDMA_CQ_REPORT_MISSED_EVENTS = 1 << 2,
246};
247
248struct pvrdma_qp_cap {
249 u32 max_send_wr;
250 u32 max_recv_wr;
251 u32 max_send_sge;
252 u32 max_recv_sge;
253 u32 max_inline_data;
254 u32 reserved;
255};
256
257enum pvrdma_sig_type {
258 PVRDMA_SIGNAL_ALL_WR,
259 PVRDMA_SIGNAL_REQ_WR,
260};
261
262enum pvrdma_qp_type {
263 PVRDMA_QPT_SMI,
264 PVRDMA_QPT_GSI,
265 PVRDMA_QPT_RC,
266 PVRDMA_QPT_UC,
267 PVRDMA_QPT_UD,
268 PVRDMA_QPT_RAW_IPV6,
269 PVRDMA_QPT_RAW_ETHERTYPE,
270 PVRDMA_QPT_RAW_PACKET = 8,
271 PVRDMA_QPT_XRC_INI = 9,
272 PVRDMA_QPT_XRC_TGT,
273 PVRDMA_QPT_MAX,
274};
275
276enum pvrdma_qp_create_flags {
277 PVRDMA_QP_CREATE_IPOPVRDMA_UD_LSO = 1 << 0,
278 PVRDMA_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 1 << 1,
279};
280
281enum pvrdma_qp_attr_mask {
282 PVRDMA_QP_STATE = 1 << 0,
283 PVRDMA_QP_CUR_STATE = 1 << 1,
284 PVRDMA_QP_EN_SQD_ASYNC_NOTIFY = 1 << 2,
285 PVRDMA_QP_ACCESS_FLAGS = 1 << 3,
286 PVRDMA_QP_PKEY_INDEX = 1 << 4,
287 PVRDMA_QP_PORT = 1 << 5,
288 PVRDMA_QP_QKEY = 1 << 6,
289 PVRDMA_QP_AV = 1 << 7,
290 PVRDMA_QP_PATH_MTU = 1 << 8,
291 PVRDMA_QP_TIMEOUT = 1 << 9,
292 PVRDMA_QP_RETRY_CNT = 1 << 10,
293 PVRDMA_QP_RNR_RETRY = 1 << 11,
294 PVRDMA_QP_RQ_PSN = 1 << 12,
295 PVRDMA_QP_MAX_QP_RD_ATOMIC = 1 << 13,
296 PVRDMA_QP_ALT_PATH = 1 << 14,
297 PVRDMA_QP_MIN_RNR_TIMER = 1 << 15,
298 PVRDMA_QP_SQ_PSN = 1 << 16,
299 PVRDMA_QP_MAX_DEST_RD_ATOMIC = 1 << 17,
300 PVRDMA_QP_PATH_MIG_STATE = 1 << 18,
301 PVRDMA_QP_CAP = 1 << 19,
302 PVRDMA_QP_DEST_QPN = 1 << 20,
303 PVRDMA_QP_ATTR_MASK_MAX = PVRDMA_QP_DEST_QPN,
304};
305
306enum pvrdma_qp_state {
307 PVRDMA_QPS_RESET,
308 PVRDMA_QPS_INIT,
309 PVRDMA_QPS_RTR,
310 PVRDMA_QPS_RTS,
311 PVRDMA_QPS_SQD,
312 PVRDMA_QPS_SQE,
313 PVRDMA_QPS_ERR,
314};
315
316enum pvrdma_mig_state {
317 PVRDMA_MIG_MIGRATED,
318 PVRDMA_MIG_REARM,
319 PVRDMA_MIG_ARMED,
320};
321
322enum pvrdma_mw_type {
323 PVRDMA_MW_TYPE_1 = 1,
324 PVRDMA_MW_TYPE_2 = 2,
325};
326
327struct pvrdma_qp_attr {
328 enum pvrdma_qp_state qp_state;
329 enum pvrdma_qp_state cur_qp_state;
330 enum pvrdma_mtu path_mtu;
331 enum pvrdma_mig_state path_mig_state;
332 u32 qkey;
333 u32 rq_psn;
334 u32 sq_psn;
335 u32 dest_qp_num;
336 u32 qp_access_flags;
337 u16 pkey_index;
338 u16 alt_pkey_index;
339 u8 en_sqd_async_notify;
340 u8 sq_draining;
341 u8 max_rd_atomic;
342 u8 max_dest_rd_atomic;
343 u8 min_rnr_timer;
344 u8 port_num;
345 u8 timeout;
346 u8 retry_cnt;
347 u8 rnr_retry;
348 u8 alt_port_num;
349 u8 alt_timeout;
350 u8 reserved[5];
351 struct pvrdma_qp_cap cap;
352 struct pvrdma_ah_attr ah_attr;
353 struct pvrdma_ah_attr alt_ah_attr;
354};
355
356enum pvrdma_send_flags {
357 PVRDMA_SEND_FENCE = 1 << 0,
358 PVRDMA_SEND_SIGNALED = 1 << 1,
359 PVRDMA_SEND_SOLICITED = 1 << 2,
360 PVRDMA_SEND_INLINE = 1 << 3,
361 PVRDMA_SEND_IP_CSUM = 1 << 4,
362 PVRDMA_SEND_FLAGS_MAX = PVRDMA_SEND_IP_CSUM,
363};
364
365enum pvrdma_access_flags {
366 PVRDMA_ACCESS_LOCAL_WRITE = 1 << 0,
367 PVRDMA_ACCESS_REMOTE_WRITE = 1 << 1,
368 PVRDMA_ACCESS_REMOTE_READ = 1 << 2,
369 PVRDMA_ACCESS_REMOTE_ATOMIC = 1 << 3,
370 PVRDMA_ACCESS_MW_BIND = 1 << 4,
371 PVRDMA_ZERO_BASED = 1 << 5,
372 PVRDMA_ACCESS_ON_DEMAND = 1 << 6,
373 PVRDMA_ACCESS_FLAGS_MAX = PVRDMA_ACCESS_ON_DEMAND,
374};
375
376int pvrdma_query_device(struct ib_device *ibdev,
377 struct ib_device_attr *props,
378 struct ib_udata *udata);
379int pvrdma_query_port(struct ib_device *ibdev, u8 port,
380 struct ib_port_attr *props);
381int pvrdma_query_gid(struct ib_device *ibdev, u8 port,
382 int index, union ib_gid *gid);
383int pvrdma_query_pkey(struct ib_device *ibdev, u8 port,
384 u16 index, u16 *pkey);
385enum rdma_link_layer pvrdma_port_link_layer(struct ib_device *ibdev,
386 u8 port);
387int pvrdma_modify_device(struct ib_device *ibdev, int mask,
388 struct ib_device_modify *props);
389int pvrdma_modify_port(struct ib_device *ibdev, u8 port,
390 int mask, struct ib_port_modify *props);
391int pvrdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma);
392struct ib_ucontext *pvrdma_alloc_ucontext(struct ib_device *ibdev,
393 struct ib_udata *udata);
394int pvrdma_dealloc_ucontext(struct ib_ucontext *context);
395struct ib_pd *pvrdma_alloc_pd(struct ib_device *ibdev,
396 struct ib_ucontext *context,
397 struct ib_udata *udata);
398int pvrdma_dealloc_pd(struct ib_pd *ibpd);
399struct ib_mr *pvrdma_get_dma_mr(struct ib_pd *pd, int acc);
400struct ib_mr *pvrdma_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
401 u64 virt_addr, int access_flags,
402 struct ib_udata *udata);
403int pvrdma_dereg_mr(struct ib_mr *mr);
404struct ib_mr *pvrdma_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
405 u32 max_num_sg);
406int pvrdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
407 int sg_nents, unsigned int *sg_offset);
408int pvrdma_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
409int pvrdma_resize_cq(struct ib_cq *ibcq, int entries,
410 struct ib_udata *udata);
411struct ib_cq *pvrdma_create_cq(struct ib_device *ibdev,
412 const struct ib_cq_init_attr *attr,
413 struct ib_ucontext *context,
414 struct ib_udata *udata);
415int pvrdma_resize_cq(struct ib_cq *ibcq, int entries,
416 struct ib_udata *udata);
417int pvrdma_destroy_cq(struct ib_cq *cq);
418int pvrdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
419int pvrdma_req_notify_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
420struct ib_ah *pvrdma_create_ah(struct ib_pd *pd, struct ib_ah_attr *ah_attr,
421 struct ib_udata *udata);
422int pvrdma_destroy_ah(struct ib_ah *ah);
423struct ib_qp *pvrdma_create_qp(struct ib_pd *pd,
424 struct ib_qp_init_attr *init_attr,
425 struct ib_udata *udata);
426int pvrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
427 int attr_mask, struct ib_udata *udata);
428int pvrdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
429 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
430int pvrdma_destroy_qp(struct ib_qp *qp);
431int pvrdma_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
432 struct ib_send_wr **bad_wr);
433int pvrdma_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
434 struct ib_recv_wr **bad_wr);
435
436#endif /* __PVRDMA_VERBS_H__ */
diff --git a/drivers/infiniband/sw/rdmavt/cq.c b/drivers/infiniband/sw/rdmavt/cq.c
index 6d9904a4a0ab..4d0b6992e847 100644
--- a/drivers/infiniband/sw/rdmavt/cq.c
+++ b/drivers/infiniband/sw/rdmavt/cq.c
@@ -119,18 +119,17 @@ void rvt_cq_enter(struct rvt_cq *cq, struct ib_wc *entry, bool solicited)
119 if (cq->notify == IB_CQ_NEXT_COMP || 119 if (cq->notify == IB_CQ_NEXT_COMP ||
120 (cq->notify == IB_CQ_SOLICITED && 120 (cq->notify == IB_CQ_SOLICITED &&
121 (solicited || entry->status != IB_WC_SUCCESS))) { 121 (solicited || entry->status != IB_WC_SUCCESS))) {
122 struct kthread_worker *worker;
123 /* 122 /*
124 * This will cause send_complete() to be called in 123 * This will cause send_complete() to be called in
125 * another thread. 124 * another thread.
126 */ 125 */
127 smp_read_barrier_depends(); /* see rvt_cq_exit */ 126 spin_lock(&cq->rdi->n_cqs_lock);
128 worker = cq->rdi->worker; 127 if (likely(cq->rdi->worker)) {
129 if (likely(worker)) {
130 cq->notify = RVT_CQ_NONE; 128 cq->notify = RVT_CQ_NONE;
131 cq->triggered++; 129 cq->triggered++;
132 kthread_queue_work(worker, &cq->comptask); 130 kthread_queue_work(cq->rdi->worker, &cq->comptask);
133 } 131 }
132 spin_unlock(&cq->rdi->n_cqs_lock);
134 } 133 }
135 134
136 spin_unlock_irqrestore(&cq->lock, flags); 135 spin_unlock_irqrestore(&cq->lock, flags);
@@ -240,15 +239,15 @@ struct ib_cq *rvt_create_cq(struct ib_device *ibdev,
240 } 239 }
241 } 240 }
242 241
243 spin_lock(&rdi->n_cqs_lock); 242 spin_lock_irq(&rdi->n_cqs_lock);
244 if (rdi->n_cqs_allocated == rdi->dparms.props.max_cq) { 243 if (rdi->n_cqs_allocated == rdi->dparms.props.max_cq) {
245 spin_unlock(&rdi->n_cqs_lock); 244 spin_unlock_irq(&rdi->n_cqs_lock);
246 ret = ERR_PTR(-ENOMEM); 245 ret = ERR_PTR(-ENOMEM);
247 goto bail_ip; 246 goto bail_ip;
248 } 247 }
249 248
250 rdi->n_cqs_allocated++; 249 rdi->n_cqs_allocated++;
251 spin_unlock(&rdi->n_cqs_lock); 250 spin_unlock_irq(&rdi->n_cqs_lock);
252 251
253 if (cq->ip) { 252 if (cq->ip) {
254 spin_lock_irq(&rdi->pending_lock); 253 spin_lock_irq(&rdi->pending_lock);
@@ -296,9 +295,9 @@ int rvt_destroy_cq(struct ib_cq *ibcq)
296 struct rvt_dev_info *rdi = cq->rdi; 295 struct rvt_dev_info *rdi = cq->rdi;
297 296
298 kthread_flush_work(&cq->comptask); 297 kthread_flush_work(&cq->comptask);
299 spin_lock(&rdi->n_cqs_lock); 298 spin_lock_irq(&rdi->n_cqs_lock);
300 rdi->n_cqs_allocated--; 299 rdi->n_cqs_allocated--;
301 spin_unlock(&rdi->n_cqs_lock); 300 spin_unlock_irq(&rdi->n_cqs_lock);
302 if (cq->ip) 301 if (cq->ip)
303 kref_put(&cq->ip->ref, rvt_release_mmap_info); 302 kref_put(&cq->ip->ref, rvt_release_mmap_info);
304 else 303 else
@@ -504,33 +503,23 @@ int rvt_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *entry)
504 */ 503 */
505int rvt_driver_cq_init(struct rvt_dev_info *rdi) 504int rvt_driver_cq_init(struct rvt_dev_info *rdi)
506{ 505{
507 int ret = 0;
508 int cpu; 506 int cpu;
509 struct task_struct *task; 507 struct kthread_worker *worker;
510 508
511 if (rdi->worker) 509 if (rdi->worker)
512 return 0; 510 return 0;
511
513 spin_lock_init(&rdi->n_cqs_lock); 512 spin_lock_init(&rdi->n_cqs_lock);
514 rdi->worker = kzalloc(sizeof(*rdi->worker), GFP_KERNEL);
515 if (!rdi->worker)
516 return -ENOMEM;
517 kthread_init_worker(rdi->worker);
518 task = kthread_create_on_node(
519 kthread_worker_fn,
520 rdi->worker,
521 rdi->dparms.node,
522 "%s", rdi->dparms.cq_name);
523 if (IS_ERR(task)) {
524 kfree(rdi->worker);
525 rdi->worker = NULL;
526 return PTR_ERR(task);
527 }
528 513
529 set_user_nice(task, MIN_NICE);
530 cpu = cpumask_first(cpumask_of_node(rdi->dparms.node)); 514 cpu = cpumask_first(cpumask_of_node(rdi->dparms.node));
531 kthread_bind(task, cpu); 515 worker = kthread_create_worker_on_cpu(cpu, 0,
532 wake_up_process(task); 516 "%s", rdi->dparms.cq_name);
533 return ret; 517 if (IS_ERR(worker))
518 return PTR_ERR(worker);
519
520 set_user_nice(worker->task, MIN_NICE);
521 rdi->worker = worker;
522 return 0;
534} 523}
535 524
536/** 525/**
@@ -541,13 +530,14 @@ void rvt_cq_exit(struct rvt_dev_info *rdi)
541{ 530{
542 struct kthread_worker *worker; 531 struct kthread_worker *worker;
543 532
544 worker = rdi->worker; 533 /* block future queuing from send_complete() */
545 if (!worker) 534 spin_lock_irq(&rdi->n_cqs_lock);
535 if (!rdi->worker) {
536 spin_unlock_irq(&rdi->n_cqs_lock);
546 return; 537 return;
547 /* blocks future queuing from send_complete() */ 538 }
548 rdi->worker = NULL; 539 rdi->worker = NULL;
549 smp_wmb(); /* See rdi_cq_enter */ 540 spin_unlock_irq(&rdi->n_cqs_lock);
550 kthread_flush_worker(worker); 541
551 kthread_stop(worker->task); 542 kthread_destroy_worker(worker);
552 kfree(worker);
553} 543}
diff --git a/drivers/infiniband/sw/rdmavt/mcast.c b/drivers/infiniband/sw/rdmavt/mcast.c
index 983d319ac976..05c8c2afb0e3 100644
--- a/drivers/infiniband/sw/rdmavt/mcast.c
+++ b/drivers/infiniband/sw/rdmavt/mcast.c
@@ -81,7 +81,7 @@ static struct rvt_mcast_qp *rvt_mcast_qp_alloc(struct rvt_qp *qp)
81 goto bail; 81 goto bail;
82 82
83 mqp->qp = qp; 83 mqp->qp = qp;
84 atomic_inc(&qp->refcount); 84 rvt_get_qp(qp);
85 85
86bail: 86bail:
87 return mqp; 87 return mqp;
@@ -92,8 +92,7 @@ static void rvt_mcast_qp_free(struct rvt_mcast_qp *mqp)
92 struct rvt_qp *qp = mqp->qp; 92 struct rvt_qp *qp = mqp->qp;
93 93
94 /* Notify hfi1_destroy_qp() if it is waiting. */ 94 /* Notify hfi1_destroy_qp() if it is waiting. */
95 if (atomic_dec_and_test(&qp->refcount)) 95 rvt_put_qp(qp);
96 wake_up(&qp->wait);
97 96
98 kfree(mqp); 97 kfree(mqp);
99} 98}
diff --git a/drivers/infiniband/sw/rdmavt/mr.c b/drivers/infiniband/sw/rdmavt/mr.c
index 46b64970058e..52fd15276ee6 100644
--- a/drivers/infiniband/sw/rdmavt/mr.c
+++ b/drivers/infiniband/sw/rdmavt/mr.c
@@ -51,6 +51,7 @@
51#include <rdma/rdma_vt.h> 51#include <rdma/rdma_vt.h>
52#include "vt.h" 52#include "vt.h"
53#include "mr.h" 53#include "mr.h"
54#include "trace.h"
54 55
55/** 56/**
56 * rvt_driver_mr_init - Init MR resources per driver 57 * rvt_driver_mr_init - Init MR resources per driver
@@ -84,6 +85,7 @@ int rvt_driver_mr_init(struct rvt_dev_info *rdi)
84 lkey_table_size = rdi->dparms.lkey_table_size; 85 lkey_table_size = rdi->dparms.lkey_table_size;
85 } 86 }
86 rdi->lkey_table.max = 1 << lkey_table_size; 87 rdi->lkey_table.max = 1 << lkey_table_size;
88 rdi->lkey_table.shift = 32 - lkey_table_size;
87 lk_tab_size = rdi->lkey_table.max * sizeof(*rdi->lkey_table.table); 89 lk_tab_size = rdi->lkey_table.max * sizeof(*rdi->lkey_table.table);
88 rdi->lkey_table.table = (struct rvt_mregion __rcu **) 90 rdi->lkey_table.table = (struct rvt_mregion __rcu **)
89 vmalloc_node(lk_tab_size, rdi->dparms.node); 91 vmalloc_node(lk_tab_size, rdi->dparms.node);
@@ -402,6 +404,7 @@ struct ib_mr *rvt_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
402 } 404 }
403 mr->mr.map[m]->segs[n].vaddr = vaddr; 405 mr->mr.map[m]->segs[n].vaddr = vaddr;
404 mr->mr.map[m]->segs[n].length = umem->page_size; 406 mr->mr.map[m]->segs[n].length = umem->page_size;
407 trace_rvt_mr_user_seg(&mr->mr, m, n, vaddr, umem->page_size);
405 n++; 408 n++;
406 if (n == RVT_SEGSZ) { 409 if (n == RVT_SEGSZ) {
407 m++; 410 m++;
@@ -506,6 +509,7 @@ static int rvt_set_page(struct ib_mr *ibmr, u64 addr)
506 n = mapped_segs % RVT_SEGSZ; 509 n = mapped_segs % RVT_SEGSZ;
507 mr->mr.map[m]->segs[n].vaddr = (void *)addr; 510 mr->mr.map[m]->segs[n].vaddr = (void *)addr;
508 mr->mr.map[m]->segs[n].length = ps; 511 mr->mr.map[m]->segs[n].length = ps;
512 trace_rvt_mr_page_seg(&mr->mr, m, n, (void *)addr, ps);
509 mr->mr.length += ps; 513 mr->mr.length += ps;
510 514
511 return 0; 515 return 0;
@@ -692,6 +696,7 @@ int rvt_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
692 for (i = 0; i < list_len; i++) { 696 for (i = 0; i < list_len; i++) {
693 fmr->mr.map[m]->segs[n].vaddr = (void *)page_list[i]; 697 fmr->mr.map[m]->segs[n].vaddr = (void *)page_list[i];
694 fmr->mr.map[m]->segs[n].length = ps; 698 fmr->mr.map[m]->segs[n].length = ps;
699 trace_rvt_mr_fmr_seg(&fmr->mr, m, n, (void *)page_list[i], ps);
695 if (++n == RVT_SEGSZ) { 700 if (++n == RVT_SEGSZ) {
696 m++; 701 m++;
697 n = 0; 702 n = 0;
@@ -774,7 +779,6 @@ int rvt_lkey_ok(struct rvt_lkey_table *rkt, struct rvt_pd *pd,
774 struct rvt_mregion *mr; 779 struct rvt_mregion *mr;
775 unsigned n, m; 780 unsigned n, m;
776 size_t off; 781 size_t off;
777 struct rvt_dev_info *dev = ib_to_rvt(pd->ibpd.device);
778 782
779 /* 783 /*
780 * We use LKEY == zero for kernel virtual addresses 784 * We use LKEY == zero for kernel virtual addresses
@@ -782,12 +786,14 @@ int rvt_lkey_ok(struct rvt_lkey_table *rkt, struct rvt_pd *pd,
782 */ 786 */
783 rcu_read_lock(); 787 rcu_read_lock();
784 if (sge->lkey == 0) { 788 if (sge->lkey == 0) {
789 struct rvt_dev_info *dev = ib_to_rvt(pd->ibpd.device);
790
785 if (pd->user) 791 if (pd->user)
786 goto bail; 792 goto bail;
787 mr = rcu_dereference(dev->dma_mr); 793 mr = rcu_dereference(dev->dma_mr);
788 if (!mr) 794 if (!mr)
789 goto bail; 795 goto bail;
790 atomic_inc(&mr->refcount); 796 rvt_get_mr(mr);
791 rcu_read_unlock(); 797 rcu_read_unlock();
792 798
793 isge->mr = mr; 799 isge->mr = mr;
@@ -798,8 +804,7 @@ int rvt_lkey_ok(struct rvt_lkey_table *rkt, struct rvt_pd *pd,
798 isge->n = 0; 804 isge->n = 0;
799 goto ok; 805 goto ok;
800 } 806 }
801 mr = rcu_dereference( 807 mr = rcu_dereference(rkt->table[sge->lkey >> rkt->shift]);
802 rkt->table[(sge->lkey >> (32 - dev->dparms.lkey_table_size))]);
803 if (unlikely(!mr || atomic_read(&mr->lkey_invalid) || 808 if (unlikely(!mr || atomic_read(&mr->lkey_invalid) ||
804 mr->lkey != sge->lkey || mr->pd != &pd->ibpd)) 809 mr->lkey != sge->lkey || mr->pd != &pd->ibpd))
805 goto bail; 810 goto bail;
@@ -809,7 +814,7 @@ int rvt_lkey_ok(struct rvt_lkey_table *rkt, struct rvt_pd *pd,
809 off + sge->length > mr->length || 814 off + sge->length > mr->length ||
810 (mr->access_flags & acc) != acc)) 815 (mr->access_flags & acc) != acc))
811 goto bail; 816 goto bail;
812 atomic_inc(&mr->refcount); 817 rvt_get_mr(mr);
813 rcu_read_unlock(); 818 rcu_read_unlock();
814 819
815 off += mr->offset; 820 off += mr->offset;
@@ -887,7 +892,7 @@ int rvt_rkey_ok(struct rvt_qp *qp, struct rvt_sge *sge,
887 mr = rcu_dereference(rdi->dma_mr); 892 mr = rcu_dereference(rdi->dma_mr);
888 if (!mr) 893 if (!mr)
889 goto bail; 894 goto bail;
890 atomic_inc(&mr->refcount); 895 rvt_get_mr(mr);
891 rcu_read_unlock(); 896 rcu_read_unlock();
892 897
893 sge->mr = mr; 898 sge->mr = mr;
@@ -899,8 +904,7 @@ int rvt_rkey_ok(struct rvt_qp *qp, struct rvt_sge *sge,
899 goto ok; 904 goto ok;
900 } 905 }
901 906
902 mr = rcu_dereference( 907 mr = rcu_dereference(rkt->table[rkey >> rkt->shift]);
903 rkt->table[(rkey >> (32 - dev->dparms.lkey_table_size))]);
904 if (unlikely(!mr || atomic_read(&mr->lkey_invalid) || 908 if (unlikely(!mr || atomic_read(&mr->lkey_invalid) ||
905 mr->lkey != rkey || qp->ibqp.pd != mr->pd)) 909 mr->lkey != rkey || qp->ibqp.pd != mr->pd))
906 goto bail; 910 goto bail;
@@ -909,7 +913,7 @@ int rvt_rkey_ok(struct rvt_qp *qp, struct rvt_sge *sge,
909 if (unlikely(vaddr < mr->iova || off + len > mr->length || 913 if (unlikely(vaddr < mr->iova || off + len > mr->length ||
910 (mr->access_flags & acc) == 0)) 914 (mr->access_flags & acc) == 0))
911 goto bail; 915 goto bail;
912 atomic_inc(&mr->refcount); 916 rvt_get_mr(mr);
913 rcu_read_unlock(); 917 rcu_read_unlock();
914 918
915 off += mr->offset; 919 off += mr->offset;
diff --git a/drivers/infiniband/sw/rdmavt/qp.c b/drivers/infiniband/sw/rdmavt/qp.c
index 6500c3b5a89c..2a13ac660f2b 100644
--- a/drivers/infiniband/sw/rdmavt/qp.c
+++ b/drivers/infiniband/sw/rdmavt/qp.c
@@ -76,6 +76,23 @@ const int ib_rvt_state_ops[IB_QPS_ERR + 1] = {
76}; 76};
77EXPORT_SYMBOL(ib_rvt_state_ops); 77EXPORT_SYMBOL(ib_rvt_state_ops);
78 78
79/*
80 * Translate ib_wr_opcode into ib_wc_opcode.
81 */
82const enum ib_wc_opcode ib_rvt_wc_opcode[] = {
83 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
84 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
85 [IB_WR_SEND] = IB_WC_SEND,
86 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
87 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
88 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
89 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD,
90 [IB_WR_SEND_WITH_INV] = IB_WC_SEND,
91 [IB_WR_LOCAL_INV] = IB_WC_LOCAL_INV,
92 [IB_WR_REG_MR] = IB_WC_REG_MR
93};
94EXPORT_SYMBOL(ib_rvt_wc_opcode);
95
79static void get_map_page(struct rvt_qpn_table *qpt, 96static void get_map_page(struct rvt_qpn_table *qpt,
80 struct rvt_qpn_map *map, 97 struct rvt_qpn_map *map,
81 gfp_t gfp) 98 gfp_t gfp)
@@ -884,7 +901,8 @@ struct ib_qp *rvt_create_qp(struct ib_pd *ibpd,
884 return ret; 901 return ret;
885 902
886bail_ip: 903bail_ip:
887 kref_put(&qp->ip->ref, rvt_release_mmap_info); 904 if (qp->ip)
905 kref_put(&qp->ip->ref, rvt_release_mmap_info);
888 906
889bail_qpn: 907bail_qpn:
890 free_qpn(&rdi->qp_dev->qpn_table, qp->ibqp.qp_num); 908 free_qpn(&rdi->qp_dev->qpn_table, qp->ibqp.qp_num);
diff --git a/drivers/infiniband/sw/rdmavt/trace.h b/drivers/infiniband/sw/rdmavt/trace.h
index 6c0457db5499..e2d23acb6a7d 100644
--- a/drivers/infiniband/sw/rdmavt/trace.h
+++ b/drivers/infiniband/sw/rdmavt/trace.h
@@ -45,143 +45,10 @@
45 * 45 *
46 */ 46 */
47 47
48#undef TRACE_SYSTEM_VAR
49#define TRACE_SYSTEM_VAR rdmavt
50
51#if !defined(__RDMAVT_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
52#define __RDMAVT_TRACE_H
53
54#include <linux/tracepoint.h>
55#include <linux/trace_seq.h>
56
57#include <rdma/ib_verbs.h>
58#include <rdma/rdma_vt.h>
59
60#define RDI_DEV_ENTRY(rdi) __string(dev, rdi->driver_f.get_card_name(rdi)) 48#define RDI_DEV_ENTRY(rdi) __string(dev, rdi->driver_f.get_card_name(rdi))
61#define RDI_DEV_ASSIGN(rdi) __assign_str(dev, rdi->driver_f.get_card_name(rdi)) 49#define RDI_DEV_ASSIGN(rdi) __assign_str(dev, rdi->driver_f.get_card_name(rdi))
62 50
63#undef TRACE_SYSTEM 51#include "trace_rvt.h"
64#define TRACE_SYSTEM rdmavt 52#include "trace_qp.h"
65 53#include "trace_tx.h"
66TRACE_EVENT(rvt_dbg, 54#include "trace_mr.h"
67 TP_PROTO(struct rvt_dev_info *rdi,
68 const char *msg),
69 TP_ARGS(rdi, msg),
70 TP_STRUCT__entry(
71 RDI_DEV_ENTRY(rdi)
72 __string(msg, msg)
73 ),
74 TP_fast_assign(
75 RDI_DEV_ASSIGN(rdi);
76 __assign_str(msg, msg);
77 ),
78 TP_printk("[%s]: %s", __get_str(dev), __get_str(msg))
79);
80
81#undef TRACE_SYSTEM
82#define TRACE_SYSTEM rvt_qphash
83DECLARE_EVENT_CLASS(rvt_qphash_template,
84 TP_PROTO(struct rvt_qp *qp, u32 bucket),
85 TP_ARGS(qp, bucket),
86 TP_STRUCT__entry(
87 RDI_DEV_ENTRY(ib_to_rvt(qp->ibqp.device))
88 __field(u32, qpn)
89 __field(u32, bucket)
90 ),
91 TP_fast_assign(
92 RDI_DEV_ASSIGN(ib_to_rvt(qp->ibqp.device))
93 __entry->qpn = qp->ibqp.qp_num;
94 __entry->bucket = bucket;
95 ),
96 TP_printk(
97 "[%s] qpn 0x%x bucket %u",
98 __get_str(dev),
99 __entry->qpn,
100 __entry->bucket
101 )
102);
103
104DEFINE_EVENT(rvt_qphash_template, rvt_qpinsert,
105 TP_PROTO(struct rvt_qp *qp, u32 bucket),
106 TP_ARGS(qp, bucket));
107
108DEFINE_EVENT(rvt_qphash_template, rvt_qpremove,
109 TP_PROTO(struct rvt_qp *qp, u32 bucket),
110 TP_ARGS(qp, bucket));
111
112#undef TRACE_SYSTEM
113#define TRACE_SYSTEM rvt_tx
114
115#define wr_opcode_name(opcode) { IB_WR_##opcode, #opcode }
116#define show_wr_opcode(opcode) \
117__print_symbolic(opcode, \
118 wr_opcode_name(RDMA_WRITE), \
119 wr_opcode_name(RDMA_WRITE_WITH_IMM), \
120 wr_opcode_name(SEND), \
121 wr_opcode_name(SEND_WITH_IMM), \
122 wr_opcode_name(RDMA_READ), \
123 wr_opcode_name(ATOMIC_CMP_AND_SWP), \
124 wr_opcode_name(ATOMIC_FETCH_AND_ADD), \
125 wr_opcode_name(LSO), \
126 wr_opcode_name(SEND_WITH_INV), \
127 wr_opcode_name(RDMA_READ_WITH_INV), \
128 wr_opcode_name(LOCAL_INV), \
129 wr_opcode_name(MASKED_ATOMIC_CMP_AND_SWP), \
130 wr_opcode_name(MASKED_ATOMIC_FETCH_AND_ADD))
131
132#define POS_PRN \
133"[%s] wr_id %llx qpn %x psn 0x%x lpsn 0x%x length %u opcode 0x%.2x,%s size %u avail %u head %u last %u"
134
135TRACE_EVENT(
136 rvt_post_one_wr,
137 TP_PROTO(struct rvt_qp *qp, struct rvt_swqe *wqe),
138 TP_ARGS(qp, wqe),
139 TP_STRUCT__entry(
140 RDI_DEV_ENTRY(ib_to_rvt(qp->ibqp.device))
141 __field(u64, wr_id)
142 __field(u32, qpn)
143 __field(u32, psn)
144 __field(u32, lpsn)
145 __field(u32, length)
146 __field(u32, opcode)
147 __field(u32, size)
148 __field(u32, avail)
149 __field(u32, head)
150 __field(u32, last)
151 ),
152 TP_fast_assign(
153 RDI_DEV_ASSIGN(ib_to_rvt(qp->ibqp.device))
154 __entry->wr_id = wqe->wr.wr_id;
155 __entry->qpn = qp->ibqp.qp_num;
156 __entry->psn = wqe->psn;
157 __entry->lpsn = wqe->lpsn;
158 __entry->length = wqe->length;
159 __entry->opcode = wqe->wr.opcode;
160 __entry->size = qp->s_size;
161 __entry->avail = qp->s_avail;
162 __entry->head = qp->s_head;
163 __entry->last = qp->s_last;
164 ),
165 TP_printk(
166 POS_PRN,
167 __get_str(dev),
168 __entry->wr_id,
169 __entry->qpn,
170 __entry->psn,
171 __entry->lpsn,
172 __entry->length,
173 __entry->opcode, show_wr_opcode(__entry->opcode),
174 __entry->size,
175 __entry->avail,
176 __entry->head,
177 __entry->last
178 )
179);
180
181#endif /* __RDMAVT_TRACE_H */
182
183#undef TRACE_INCLUDE_PATH
184#undef TRACE_INCLUDE_FILE
185#define TRACE_INCLUDE_PATH .
186#define TRACE_INCLUDE_FILE trace
187#include <trace/define_trace.h>
diff --git a/drivers/infiniband/sw/rdmavt/trace_mr.h b/drivers/infiniband/sw/rdmavt/trace_mr.h
new file mode 100644
index 000000000000..3318a6c36373
--- /dev/null
+++ b/drivers/infiniband/sw/rdmavt/trace_mr.h
@@ -0,0 +1,112 @@
1/*
2 * Copyright(c) 2016 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47#if !defined(__RVT_TRACE_MR_H) || defined(TRACE_HEADER_MULTI_READ)
48#define __RVT_TRACE_MR_H
49
50#include <linux/tracepoint.h>
51#include <linux/trace_seq.h>
52
53#include <rdma/ib_verbs.h>
54#include <rdma/rdma_vt.h>
55#include <rdma/rdmavt_mr.h>
56
57#undef TRACE_SYSTEM
58#define TRACE_SYSTEM rvt_mr
59DECLARE_EVENT_CLASS(
60 rvt_mr_template,
61 TP_PROTO(struct rvt_mregion *mr, u16 m, u16 n, void *v, size_t len),
62 TP_ARGS(mr, m, n, v, len),
63 TP_STRUCT__entry(
64 RDI_DEV_ENTRY(ib_to_rvt(mr->pd->device))
65 __field(void *, vaddr)
66 __field(struct page *, page)
67 __field(size_t, len)
68 __field(u32, lkey)
69 __field(u16, m)
70 __field(u16, n)
71 ),
72 TP_fast_assign(
73 RDI_DEV_ASSIGN(ib_to_rvt(mr->pd->device));
74 __entry->vaddr = v;
75 __entry->page = virt_to_page(v);
76 __entry->m = m;
77 __entry->n = n;
78 __entry->len = len;
79 ),
80 TP_printk(
81 "[%s] vaddr %p page %p m %u n %u len %ld",
82 __get_str(dev),
83 __entry->vaddr,
84 __entry->page,
85 __entry->m,
86 __entry->n,
87 __entry->len
88 )
89);
90
91DEFINE_EVENT(
92 rvt_mr_template, rvt_mr_page_seg,
93 TP_PROTO(struct rvt_mregion *mr, u16 m, u16 n, void *v, size_t len),
94 TP_ARGS(mr, m, n, v, len));
95
96DEFINE_EVENT(
97 rvt_mr_template, rvt_mr_fmr_seg,
98 TP_PROTO(struct rvt_mregion *mr, u16 m, u16 n, void *v, size_t len),
99 TP_ARGS(mr, m, n, v, len));
100
101DEFINE_EVENT(
102 rvt_mr_template, rvt_mr_user_seg,
103 TP_PROTO(struct rvt_mregion *mr, u16 m, u16 n, void *v, size_t len),
104 TP_ARGS(mr, m, n, v, len));
105
106#endif /* __RVT_TRACE_MR_H */
107
108#undef TRACE_INCLUDE_PATH
109#undef TRACE_INCLUDE_FILE
110#define TRACE_INCLUDE_PATH .
111#define TRACE_INCLUDE_FILE trace_mr
112#include <trace/define_trace.h>
diff --git a/drivers/infiniband/sw/rdmavt/trace_qp.h b/drivers/infiniband/sw/rdmavt/trace_qp.h
new file mode 100644
index 000000000000..4c77a3119bda
--- /dev/null
+++ b/drivers/infiniband/sw/rdmavt/trace_qp.h
@@ -0,0 +1,96 @@
1/*
2 * Copyright(c) 2016 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47#if !defined(__RVT_TRACE_QP_H) || defined(TRACE_HEADER_MULTI_READ)
48#define __RVT_TRACE_QP_H
49
50#include <linux/tracepoint.h>
51#include <linux/trace_seq.h>
52
53#include <rdma/ib_verbs.h>
54#include <rdma/rdma_vt.h>
55
56#undef TRACE_SYSTEM
57#define TRACE_SYSTEM rvt_qp
58
59DECLARE_EVENT_CLASS(rvt_qphash_template,
60 TP_PROTO(struct rvt_qp *qp, u32 bucket),
61 TP_ARGS(qp, bucket),
62 TP_STRUCT__entry(
63 RDI_DEV_ENTRY(ib_to_rvt(qp->ibqp.device))
64 __field(u32, qpn)
65 __field(u32, bucket)
66 ),
67 TP_fast_assign(
68 RDI_DEV_ASSIGN(ib_to_rvt(qp->ibqp.device))
69 __entry->qpn = qp->ibqp.qp_num;
70 __entry->bucket = bucket;
71 ),
72 TP_printk(
73 "[%s] qpn 0x%x bucket %u",
74 __get_str(dev),
75 __entry->qpn,
76 __entry->bucket
77 )
78);
79
80DEFINE_EVENT(rvt_qphash_template, rvt_qpinsert,
81 TP_PROTO(struct rvt_qp *qp, u32 bucket),
82 TP_ARGS(qp, bucket));
83
84DEFINE_EVENT(rvt_qphash_template, rvt_qpremove,
85 TP_PROTO(struct rvt_qp *qp, u32 bucket),
86 TP_ARGS(qp, bucket));
87
88
89#endif /* __RVT_TRACE_QP_H */
90
91#undef TRACE_INCLUDE_PATH
92#undef TRACE_INCLUDE_FILE
93#define TRACE_INCLUDE_PATH .
94#define TRACE_INCLUDE_FILE trace_qp
95#include <trace/define_trace.h>
96
diff --git a/drivers/infiniband/sw/rdmavt/trace_rvt.h b/drivers/infiniband/sw/rdmavt/trace_rvt.h
new file mode 100644
index 000000000000..746f33461d9a
--- /dev/null
+++ b/drivers/infiniband/sw/rdmavt/trace_rvt.h
@@ -0,0 +1,81 @@
1/*
2 * Copyright(c) 2016 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47#if !defined(__RVT_TRACE_RVT_H) || defined(TRACE_HEADER_MULTI_READ)
48#define __RVT_TRACE_RVT_H
49
50#include <linux/tracepoint.h>
51#include <linux/trace_seq.h>
52
53#include <rdma/ib_verbs.h>
54#include <rdma/rdma_vt.h>
55
56#undef TRACE_SYSTEM
57#define TRACE_SYSTEM rvt
58
59TRACE_EVENT(rvt_dbg,
60 TP_PROTO(struct rvt_dev_info *rdi,
61 const char *msg),
62 TP_ARGS(rdi, msg),
63 TP_STRUCT__entry(
64 RDI_DEV_ENTRY(rdi)
65 __string(msg, msg)
66 ),
67 TP_fast_assign(
68 RDI_DEV_ASSIGN(rdi);
69 __assign_str(msg, msg);
70 ),
71 TP_printk("[%s]: %s", __get_str(dev), __get_str(msg))
72);
73
74#endif /* __RVT_TRACE_MISC_H */
75
76#undef TRACE_INCLUDE_PATH
77#undef TRACE_INCLUDE_FILE
78#define TRACE_INCLUDE_PATH .
79#define TRACE_INCLUDE_FILE trace_rvt
80#include <trace/define_trace.h>
81
diff --git a/drivers/infiniband/sw/rdmavt/trace_tx.h b/drivers/infiniband/sw/rdmavt/trace_tx.h
new file mode 100644
index 000000000000..0e03173662d8
--- /dev/null
+++ b/drivers/infiniband/sw/rdmavt/trace_tx.h
@@ -0,0 +1,132 @@
1/*
2 * Copyright(c) 2016 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47#if !defined(__RVT_TRACE_TX_H) || defined(TRACE_HEADER_MULTI_READ)
48#define __RVT_TRACE_TX_H
49
50#include <linux/tracepoint.h>
51#include <linux/trace_seq.h>
52
53#include <rdma/ib_verbs.h>
54#include <rdma/rdma_vt.h>
55
56#undef TRACE_SYSTEM
57#define TRACE_SYSTEM rvt_tx
58
59#define wr_opcode_name(opcode) { IB_WR_##opcode, #opcode }
60#define show_wr_opcode(opcode) \
61__print_symbolic(opcode, \
62 wr_opcode_name(RDMA_WRITE), \
63 wr_opcode_name(RDMA_WRITE_WITH_IMM), \
64 wr_opcode_name(SEND), \
65 wr_opcode_name(SEND_WITH_IMM), \
66 wr_opcode_name(RDMA_READ), \
67 wr_opcode_name(ATOMIC_CMP_AND_SWP), \
68 wr_opcode_name(ATOMIC_FETCH_AND_ADD), \
69 wr_opcode_name(LSO), \
70 wr_opcode_name(SEND_WITH_INV), \
71 wr_opcode_name(RDMA_READ_WITH_INV), \
72 wr_opcode_name(LOCAL_INV), \
73 wr_opcode_name(MASKED_ATOMIC_CMP_AND_SWP), \
74 wr_opcode_name(MASKED_ATOMIC_FETCH_AND_ADD))
75
76#define POS_PRN \
77"[%s] wr_id %llx qpn %x psn 0x%x lpsn 0x%x length %u opcode 0x%.2x,%s size %u avail %u head %u last %u"
78
79TRACE_EVENT(
80 rvt_post_one_wr,
81 TP_PROTO(struct rvt_qp *qp, struct rvt_swqe *wqe),
82 TP_ARGS(qp, wqe),
83 TP_STRUCT__entry(
84 RDI_DEV_ENTRY(ib_to_rvt(qp->ibqp.device))
85 __field(u64, wr_id)
86 __field(u32, qpn)
87 __field(u32, psn)
88 __field(u32, lpsn)
89 __field(u32, length)
90 __field(u32, opcode)
91 __field(u32, size)
92 __field(u32, avail)
93 __field(u32, head)
94 __field(u32, last)
95 ),
96 TP_fast_assign(
97 RDI_DEV_ASSIGN(ib_to_rvt(qp->ibqp.device))
98 __entry->wr_id = wqe->wr.wr_id;
99 __entry->qpn = qp->ibqp.qp_num;
100 __entry->psn = wqe->psn;
101 __entry->lpsn = wqe->lpsn;
102 __entry->length = wqe->length;
103 __entry->opcode = wqe->wr.opcode;
104 __entry->size = qp->s_size;
105 __entry->avail = qp->s_avail;
106 __entry->head = qp->s_head;
107 __entry->last = qp->s_last;
108 ),
109 TP_printk(
110 POS_PRN,
111 __get_str(dev),
112 __entry->wr_id,
113 __entry->qpn,
114 __entry->psn,
115 __entry->lpsn,
116 __entry->length,
117 __entry->opcode, show_wr_opcode(__entry->opcode),
118 __entry->size,
119 __entry->avail,
120 __entry->head,
121 __entry->last
122 )
123);
124
125#endif /* __RVT_TRACE_TX_H */
126
127#undef TRACE_INCLUDE_PATH
128#undef TRACE_INCLUDE_FILE
129#define TRACE_INCLUDE_PATH .
130#define TRACE_INCLUDE_FILE trace_tx
131#include <trace/define_trace.h>
132
diff --git a/drivers/infiniband/sw/rxe/rxe_comp.c b/drivers/infiniband/sw/rxe/rxe_comp.c
index 6c5e29db88e3..cd27cbde7652 100644
--- a/drivers/infiniband/sw/rxe/rxe_comp.c
+++ b/drivers/infiniband/sw/rxe/rxe_comp.c
@@ -420,11 +420,12 @@ static void do_complete(struct rxe_qp *qp, struct rxe_send_wqe *wqe)
420 (wqe->wr.send_flags & IB_SEND_SIGNALED) || 420 (wqe->wr.send_flags & IB_SEND_SIGNALED) ||
421 (qp->req.state == QP_STATE_ERROR)) { 421 (qp->req.state == QP_STATE_ERROR)) {
422 make_send_cqe(qp, wqe, &cqe); 422 make_send_cqe(qp, wqe, &cqe);
423 advance_consumer(qp->sq.queue);
423 rxe_cq_post(qp->scq, &cqe, 0); 424 rxe_cq_post(qp->scq, &cqe, 0);
425 } else {
426 advance_consumer(qp->sq.queue);
424 } 427 }
425 428
426 advance_consumer(qp->sq.queue);
427
428 /* 429 /*
429 * we completed something so let req run again 430 * we completed something so let req run again
430 * if it is trying to fence 431 * if it is trying to fence
@@ -510,6 +511,8 @@ int rxe_completer(void *arg)
510 struct rxe_pkt_info *pkt = NULL; 511 struct rxe_pkt_info *pkt = NULL;
511 enum comp_state state; 512 enum comp_state state;
512 513
514 rxe_add_ref(qp);
515
513 if (!qp->valid) { 516 if (!qp->valid) {
514 while ((skb = skb_dequeue(&qp->resp_pkts))) { 517 while ((skb = skb_dequeue(&qp->resp_pkts))) {
515 rxe_drop_ref(qp); 518 rxe_drop_ref(qp);
@@ -739,11 +742,13 @@ exit:
739 /* we come here if we are done with processing and want the task to 742 /* we come here if we are done with processing and want the task to
740 * exit from the loop calling us 743 * exit from the loop calling us
741 */ 744 */
745 rxe_drop_ref(qp);
742 return -EAGAIN; 746 return -EAGAIN;
743 747
744done: 748done:
745 /* we come here if we have processed a packet we want the task to call 749 /* we come here if we have processed a packet we want the task to call
746 * us again to see if there is anything else to do 750 * us again to see if there is anything else to do
747 */ 751 */
752 rxe_drop_ref(qp);
748 return 0; 753 return 0;
749} 754}
diff --git a/drivers/infiniband/sw/rxe/rxe_loc.h b/drivers/infiniband/sw/rxe/rxe_loc.h
index 73849a5a91b3..efe4c6a35442 100644
--- a/drivers/infiniband/sw/rxe/rxe_loc.h
+++ b/drivers/infiniband/sw/rxe/rxe_loc.h
@@ -266,8 +266,6 @@ static inline int rxe_xmit_packet(struct rxe_dev *rxe, struct rxe_qp *qp,
266 return err; 266 return err;
267 } 267 }
268 268
269 atomic_inc(&qp->skb_out);
270
271 if ((qp_type(qp) != IB_QPT_RC) && 269 if ((qp_type(qp) != IB_QPT_RC) &&
272 (pkt->mask & RXE_END_MASK)) { 270 (pkt->mask & RXE_END_MASK)) {
273 pkt->wqe->state = wqe_state_done; 271 pkt->wqe->state = wqe_state_done;
diff --git a/drivers/infiniband/sw/rxe/rxe_mr.c b/drivers/infiniband/sw/rxe/rxe_mr.c
index 1869152f1d23..d0faca294006 100644
--- a/drivers/infiniband/sw/rxe/rxe_mr.c
+++ b/drivers/infiniband/sw/rxe/rxe_mr.c
@@ -355,6 +355,9 @@ int rxe_mem_copy(struct rxe_mem *mem, u64 iova, void *addr, int length,
355 size_t offset; 355 size_t offset;
356 u32 crc = crcp ? (*crcp) : 0; 356 u32 crc = crcp ? (*crcp) : 0;
357 357
358 if (length == 0)
359 return 0;
360
358 if (mem->type == RXE_MEM_TYPE_DMA) { 361 if (mem->type == RXE_MEM_TYPE_DMA) {
359 u8 *src, *dest; 362 u8 *src, *dest;
360 363
diff --git a/drivers/infiniband/sw/rxe/rxe_net.c b/drivers/infiniband/sw/rxe/rxe_net.c
index ffff5a54cb34..16967cdb45df 100644
--- a/drivers/infiniband/sw/rxe/rxe_net.c
+++ b/drivers/infiniband/sw/rxe/rxe_net.c
@@ -46,7 +46,7 @@
46#include "rxe_loc.h" 46#include "rxe_loc.h"
47 47
48static LIST_HEAD(rxe_dev_list); 48static LIST_HEAD(rxe_dev_list);
49static spinlock_t dev_list_lock; /* spinlock for device list */ 49static DEFINE_SPINLOCK(dev_list_lock); /* spinlock for device list */
50 50
51struct rxe_dev *net_to_rxe(struct net_device *ndev) 51struct rxe_dev *net_to_rxe(struct net_device *ndev)
52{ 52{
@@ -455,6 +455,8 @@ static int send(struct rxe_dev *rxe, struct rxe_pkt_info *pkt,
455 return -EAGAIN; 455 return -EAGAIN;
456 } 456 }
457 457
458 if (pkt->qp)
459 atomic_inc(&pkt->qp->skb_out);
458 kfree_skb(skb); 460 kfree_skb(skb);
459 461
460 return 0; 462 return 0;
@@ -659,8 +661,6 @@ struct notifier_block rxe_net_notifier = {
659 661
660int rxe_net_ipv4_init(void) 662int rxe_net_ipv4_init(void)
661{ 663{
662 spin_lock_init(&dev_list_lock);
663
664 recv_sockets.sk4 = rxe_setup_udp_tunnel(&init_net, 664 recv_sockets.sk4 = rxe_setup_udp_tunnel(&init_net,
665 htons(ROCE_V2_UDP_DPORT), false); 665 htons(ROCE_V2_UDP_DPORT), false);
666 if (IS_ERR(recv_sockets.sk4)) { 666 if (IS_ERR(recv_sockets.sk4)) {
@@ -676,8 +676,6 @@ int rxe_net_ipv6_init(void)
676{ 676{
677#if IS_ENABLED(CONFIG_IPV6) 677#if IS_ENABLED(CONFIG_IPV6)
678 678
679 spin_lock_init(&dev_list_lock);
680
681 recv_sockets.sk6 = rxe_setup_udp_tunnel(&init_net, 679 recv_sockets.sk6 = rxe_setup_udp_tunnel(&init_net,
682 htons(ROCE_V2_UDP_DPORT), true); 680 htons(ROCE_V2_UDP_DPORT), true);
683 if (IS_ERR(recv_sockets.sk6)) { 681 if (IS_ERR(recv_sockets.sk6)) {
diff --git a/drivers/infiniband/sw/rxe/rxe_param.h b/drivers/infiniband/sw/rxe/rxe_param.h
index f459c43a77c8..13ed2cc6eaa2 100644
--- a/drivers/infiniband/sw/rxe/rxe_param.h
+++ b/drivers/infiniband/sw/rxe/rxe_param.h
@@ -82,7 +82,7 @@ enum rxe_device_param {
82 RXE_MAX_SGE = 32, 82 RXE_MAX_SGE = 32,
83 RXE_MAX_SGE_RD = 32, 83 RXE_MAX_SGE_RD = 32,
84 RXE_MAX_CQ = 16384, 84 RXE_MAX_CQ = 16384,
85 RXE_MAX_LOG_CQE = 13, 85 RXE_MAX_LOG_CQE = 15,
86 RXE_MAX_MR = 2 * 1024, 86 RXE_MAX_MR = 2 * 1024,
87 RXE_MAX_PD = 0x7ffc, 87 RXE_MAX_PD = 0x7ffc,
88 RXE_MAX_QP_RD_ATOM = 128, 88 RXE_MAX_QP_RD_ATOM = 128,
diff --git a/drivers/infiniband/sw/rxe/rxe_pool.c b/drivers/infiniband/sw/rxe/rxe_pool.c
index 6bac0717c540..d723947a8542 100644
--- a/drivers/infiniband/sw/rxe/rxe_pool.c
+++ b/drivers/infiniband/sw/rxe/rxe_pool.c
@@ -180,7 +180,6 @@ static int rxe_pool_init_index(struct rxe_pool *pool, u32 max, u32 min)
180 size = BITS_TO_LONGS(max - min + 1) * sizeof(long); 180 size = BITS_TO_LONGS(max - min + 1) * sizeof(long);
181 pool->table = kmalloc(size, GFP_KERNEL); 181 pool->table = kmalloc(size, GFP_KERNEL);
182 if (!pool->table) { 182 if (!pool->table) {
183 pr_warn("no memory for bit table\n");
184 err = -ENOMEM; 183 err = -ENOMEM;
185 goto out; 184 goto out;
186 } 185 }
diff --git a/drivers/infiniband/sw/rxe/rxe_recv.c b/drivers/infiniband/sw/rxe/rxe_recv.c
index 46f062842a9a..252b4d637d45 100644
--- a/drivers/infiniband/sw/rxe/rxe_recv.c
+++ b/drivers/infiniband/sw/rxe/rxe_recv.c
@@ -391,16 +391,15 @@ int rxe_rcv(struct sk_buff *skb)
391 payload_size(pkt)); 391 payload_size(pkt));
392 calc_icrc = cpu_to_be32(~calc_icrc); 392 calc_icrc = cpu_to_be32(~calc_icrc);
393 if (unlikely(calc_icrc != pack_icrc)) { 393 if (unlikely(calc_icrc != pack_icrc)) {
394 char saddr[sizeof(struct in6_addr)];
395
396 if (skb->protocol == htons(ETH_P_IPV6)) 394 if (skb->protocol == htons(ETH_P_IPV6))
397 sprintf(saddr, "%pI6", &ipv6_hdr(skb)->saddr); 395 pr_warn_ratelimited("bad ICRC from %pI6c\n",
396 &ipv6_hdr(skb)->saddr);
398 else if (skb->protocol == htons(ETH_P_IP)) 397 else if (skb->protocol == htons(ETH_P_IP))
399 sprintf(saddr, "%pI4", &ip_hdr(skb)->saddr); 398 pr_warn_ratelimited("bad ICRC from %pI4\n",
399 &ip_hdr(skb)->saddr);
400 else 400 else
401 sprintf(saddr, "unknown"); 401 pr_warn_ratelimited("bad ICRC from unknown\n");
402 402
403 pr_warn_ratelimited("bad ICRC from %s\n", saddr);
404 goto drop; 403 goto drop;
405 } 404 }
406 405
diff --git a/drivers/infiniband/sw/rxe/rxe_req.c b/drivers/infiniband/sw/rxe/rxe_req.c
index 22bd9630dcd9..73d4a97603a1 100644
--- a/drivers/infiniband/sw/rxe/rxe_req.c
+++ b/drivers/infiniband/sw/rxe/rxe_req.c
@@ -548,23 +548,23 @@ static void update_wqe_psn(struct rxe_qp *qp,
548static void save_state(struct rxe_send_wqe *wqe, 548static void save_state(struct rxe_send_wqe *wqe,
549 struct rxe_qp *qp, 549 struct rxe_qp *qp,
550 struct rxe_send_wqe *rollback_wqe, 550 struct rxe_send_wqe *rollback_wqe,
551 struct rxe_qp *rollback_qp) 551 u32 *rollback_psn)
552{ 552{
553 rollback_wqe->state = wqe->state; 553 rollback_wqe->state = wqe->state;
554 rollback_wqe->first_psn = wqe->first_psn; 554 rollback_wqe->first_psn = wqe->first_psn;
555 rollback_wqe->last_psn = wqe->last_psn; 555 rollback_wqe->last_psn = wqe->last_psn;
556 rollback_qp->req.psn = qp->req.psn; 556 *rollback_psn = qp->req.psn;
557} 557}
558 558
559static void rollback_state(struct rxe_send_wqe *wqe, 559static void rollback_state(struct rxe_send_wqe *wqe,
560 struct rxe_qp *qp, 560 struct rxe_qp *qp,
561 struct rxe_send_wqe *rollback_wqe, 561 struct rxe_send_wqe *rollback_wqe,
562 struct rxe_qp *rollback_qp) 562 u32 rollback_psn)
563{ 563{
564 wqe->state = rollback_wqe->state; 564 wqe->state = rollback_wqe->state;
565 wqe->first_psn = rollback_wqe->first_psn; 565 wqe->first_psn = rollback_wqe->first_psn;
566 wqe->last_psn = rollback_wqe->last_psn; 566 wqe->last_psn = rollback_wqe->last_psn;
567 qp->req.psn = rollback_qp->req.psn; 567 qp->req.psn = rollback_psn;
568} 568}
569 569
570static void update_state(struct rxe_qp *qp, struct rxe_send_wqe *wqe, 570static void update_state(struct rxe_qp *qp, struct rxe_send_wqe *wqe,
@@ -593,8 +593,10 @@ int rxe_requester(void *arg)
593 int mtu; 593 int mtu;
594 int opcode; 594 int opcode;
595 int ret; 595 int ret;
596 struct rxe_qp rollback_qp;
597 struct rxe_send_wqe rollback_wqe; 596 struct rxe_send_wqe rollback_wqe;
597 u32 rollback_psn;
598
599 rxe_add_ref(qp);
598 600
599next_wqe: 601next_wqe:
600 if (unlikely(!qp->valid || qp->req.state == QP_STATE_ERROR)) 602 if (unlikely(!qp->valid || qp->req.state == QP_STATE_ERROR))
@@ -697,6 +699,7 @@ next_wqe:
697 wqe->state = wqe_state_done; 699 wqe->state = wqe_state_done;
698 wqe->status = IB_WC_SUCCESS; 700 wqe->status = IB_WC_SUCCESS;
699 __rxe_do_task(&qp->comp.task); 701 __rxe_do_task(&qp->comp.task);
702 rxe_drop_ref(qp);
700 return 0; 703 return 0;
701 } 704 }
702 payload = mtu; 705 payload = mtu;
@@ -719,7 +722,7 @@ next_wqe:
719 * rxe_xmit_packet(). 722 * rxe_xmit_packet().
720 * Otherwise, completer might initiate an unjustified retry flow. 723 * Otherwise, completer might initiate an unjustified retry flow.
721 */ 724 */
722 save_state(wqe, qp, &rollback_wqe, &rollback_qp); 725 save_state(wqe, qp, &rollback_wqe, &rollback_psn);
723 update_wqe_state(qp, wqe, &pkt); 726 update_wqe_state(qp, wqe, &pkt);
724 update_wqe_psn(qp, wqe, &pkt, payload); 727 update_wqe_psn(qp, wqe, &pkt, payload);
725 ret = rxe_xmit_packet(to_rdev(qp->ibqp.device), qp, &pkt, skb); 728 ret = rxe_xmit_packet(to_rdev(qp->ibqp.device), qp, &pkt, skb);
@@ -727,7 +730,7 @@ next_wqe:
727 qp->need_req_skb = 1; 730 qp->need_req_skb = 1;
728 kfree_skb(skb); 731 kfree_skb(skb);
729 732
730 rollback_state(wqe, qp, &rollback_wqe, &rollback_qp); 733 rollback_state(wqe, qp, &rollback_wqe, rollback_psn);
731 734
732 if (ret == -EAGAIN) { 735 if (ret == -EAGAIN) {
733 rxe_run_task(&qp->req.task, 1); 736 rxe_run_task(&qp->req.task, 1);
@@ -756,8 +759,7 @@ err:
756 */ 759 */
757 wqe->wr.send_flags |= IB_SEND_SIGNALED; 760 wqe->wr.send_flags |= IB_SEND_SIGNALED;
758 __rxe_do_task(&qp->comp.task); 761 __rxe_do_task(&qp->comp.task);
759 return -EAGAIN;
760
761exit: 762exit:
763 rxe_drop_ref(qp);
762 return -EAGAIN; 764 return -EAGAIN;
763} 765}
diff --git a/drivers/infiniband/sw/rxe/rxe_resp.c b/drivers/infiniband/sw/rxe/rxe_resp.c
index dd3d88adc003..7a36ec9dbc0c 100644
--- a/drivers/infiniband/sw/rxe/rxe_resp.c
+++ b/drivers/infiniband/sw/rxe/rxe_resp.c
@@ -444,6 +444,13 @@ static enum resp_states check_rkey(struct rxe_qp *qp,
444 return RESPST_EXECUTE; 444 return RESPST_EXECUTE;
445 } 445 }
446 446
447 /* A zero-byte op is not required to set an addr or rkey. */
448 if ((pkt->mask & (RXE_READ_MASK | RXE_WRITE_OR_SEND)) &&
449 (pkt->mask & RXE_RETH_MASK) &&
450 reth_len(pkt) == 0) {
451 return RESPST_EXECUTE;
452 }
453
447 va = qp->resp.va; 454 va = qp->resp.va;
448 rkey = qp->resp.rkey; 455 rkey = qp->resp.rkey;
449 resid = qp->resp.resid; 456 resid = qp->resp.resid;
@@ -680,9 +687,14 @@ static enum resp_states read_reply(struct rxe_qp *qp,
680 res->read.va_org = qp->resp.va; 687 res->read.va_org = qp->resp.va;
681 688
682 res->first_psn = req_pkt->psn; 689 res->first_psn = req_pkt->psn;
683 res->last_psn = req_pkt->psn + 690
684 (reth_len(req_pkt) + mtu - 1) / 691 if (reth_len(req_pkt)) {
685 mtu - 1; 692 res->last_psn = (req_pkt->psn +
693 (reth_len(req_pkt) + mtu - 1) /
694 mtu - 1) & BTH_PSN_MASK;
695 } else {
696 res->last_psn = res->first_psn;
697 }
686 res->cur_psn = req_pkt->psn; 698 res->cur_psn = req_pkt->psn;
687 699
688 res->read.resid = qp->resp.resid; 700 res->read.resid = qp->resp.resid;
@@ -742,7 +754,8 @@ static enum resp_states read_reply(struct rxe_qp *qp,
742 } else { 754 } else {
743 qp->resp.res = NULL; 755 qp->resp.res = NULL;
744 qp->resp.opcode = -1; 756 qp->resp.opcode = -1;
745 qp->resp.psn = res->cur_psn; 757 if (psn_compare(res->cur_psn, qp->resp.psn) >= 0)
758 qp->resp.psn = res->cur_psn;
746 state = RESPST_CLEANUP; 759 state = RESPST_CLEANUP;
747 } 760 }
748 761
@@ -1132,6 +1145,7 @@ static enum resp_states duplicate_request(struct rxe_qp *qp,
1132 pkt, skb_copy); 1145 pkt, skb_copy);
1133 if (rc) { 1146 if (rc) {
1134 pr_err("Failed resending result. This flow is not handled - skb ignored\n"); 1147 pr_err("Failed resending result. This flow is not handled - skb ignored\n");
1148 rxe_drop_ref(qp);
1135 kfree_skb(skb_copy); 1149 kfree_skb(skb_copy);
1136 rc = RESPST_CLEANUP; 1150 rc = RESPST_CLEANUP;
1137 goto out; 1151 goto out;
@@ -1198,6 +1212,8 @@ int rxe_responder(void *arg)
1198 struct rxe_pkt_info *pkt = NULL; 1212 struct rxe_pkt_info *pkt = NULL;
1199 int ret = 0; 1213 int ret = 0;
1200 1214
1215 rxe_add_ref(qp);
1216
1201 qp->resp.aeth_syndrome = AETH_ACK_UNLIMITED; 1217 qp->resp.aeth_syndrome = AETH_ACK_UNLIMITED;
1202 1218
1203 if (!qp->valid) { 1219 if (!qp->valid) {
@@ -1386,5 +1402,6 @@ int rxe_responder(void *arg)
1386exit: 1402exit:
1387 ret = -EAGAIN; 1403 ret = -EAGAIN;
1388done: 1404done:
1405 rxe_drop_ref(qp);
1389 return ret; 1406 return ret;
1390} 1407}
diff --git a/drivers/infiniband/sw/rxe/rxe_srq.c b/drivers/infiniband/sw/rxe/rxe_srq.c
index 2a6e3cd2d4e8..efc832a2d7c6 100644
--- a/drivers/infiniband/sw/rxe/rxe_srq.c
+++ b/drivers/infiniband/sw/rxe/rxe_srq.c
@@ -169,7 +169,7 @@ int rxe_srq_from_attr(struct rxe_dev *rxe, struct rxe_srq *srq,
169 } 169 }
170 } 170 }
171 171
172 err = rxe_queue_resize(q, (unsigned int *)&attr->max_wr, 172 err = rxe_queue_resize(q, &attr->max_wr,
173 rcv_wqe_size(srq->rq.max_sge), 173 rcv_wqe_size(srq->rq.max_sge),
174 srq->rq.queue->ip ? 174 srq->rq.queue->ip ?
175 srq->rq.queue->ip->context : 175 srq->rq.queue->ip->context :
diff --git a/drivers/infiniband/sw/rxe/rxe_task.c b/drivers/infiniband/sw/rxe/rxe_task.c
index 1e19bf828a6e..d2a14a1bdc7f 100644
--- a/drivers/infiniband/sw/rxe/rxe_task.c
+++ b/drivers/infiniband/sw/rxe/rxe_task.c
@@ -121,6 +121,7 @@ int rxe_init_task(void *obj, struct rxe_task *task,
121 task->arg = arg; 121 task->arg = arg;
122 task->func = func; 122 task->func = func;
123 snprintf(task->name, sizeof(task->name), "%s", name); 123 snprintf(task->name, sizeof(task->name), "%s", name);
124 task->destroyed = false;
124 125
125 tasklet_init(&task->tasklet, rxe_do_task, (unsigned long)task); 126 tasklet_init(&task->tasklet, rxe_do_task, (unsigned long)task);
126 127
@@ -132,11 +133,29 @@ int rxe_init_task(void *obj, struct rxe_task *task,
132 133
133void rxe_cleanup_task(struct rxe_task *task) 134void rxe_cleanup_task(struct rxe_task *task)
134{ 135{
136 unsigned long flags;
137 bool idle;
138
139 /*
140 * Mark the task, then wait for it to finish. It might be
141 * running in a non-tasklet (direct call) context.
142 */
143 task->destroyed = true;
144
145 do {
146 spin_lock_irqsave(&task->state_lock, flags);
147 idle = (task->state == TASK_STATE_START);
148 spin_unlock_irqrestore(&task->state_lock, flags);
149 } while (!idle);
150
135 tasklet_kill(&task->tasklet); 151 tasklet_kill(&task->tasklet);
136} 152}
137 153
138void rxe_run_task(struct rxe_task *task, int sched) 154void rxe_run_task(struct rxe_task *task, int sched)
139{ 155{
156 if (task->destroyed)
157 return;
158
140 if (sched) 159 if (sched)
141 tasklet_schedule(&task->tasklet); 160 tasklet_schedule(&task->tasklet);
142 else 161 else
diff --git a/drivers/infiniband/sw/rxe/rxe_task.h b/drivers/infiniband/sw/rxe/rxe_task.h
index d14aa6daed05..08ff42d451c6 100644
--- a/drivers/infiniband/sw/rxe/rxe_task.h
+++ b/drivers/infiniband/sw/rxe/rxe_task.h
@@ -54,6 +54,7 @@ struct rxe_task {
54 int (*func)(void *arg); 54 int (*func)(void *arg);
55 int ret; 55 int ret;
56 char name[16]; 56 char name[16];
57 bool destroyed;
57}; 58};
58 59
59/* 60/*
diff --git a/drivers/infiniband/sw/rxe/rxe_verbs.c b/drivers/infiniband/sw/rxe/rxe_verbs.c
index 19841c863daf..beb7021ff18a 100644
--- a/drivers/infiniband/sw/rxe/rxe_verbs.c
+++ b/drivers/infiniband/sw/rxe/rxe_verbs.c
@@ -316,7 +316,9 @@ static int rxe_init_av(struct rxe_dev *rxe, struct ib_ah_attr *attr,
316 return err; 316 return err;
317} 317}
318 318
319static struct ib_ah *rxe_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *attr) 319static struct ib_ah *rxe_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *attr,
320 struct ib_udata *udata)
321
320{ 322{
321 int err; 323 int err;
322 struct rxe_dev *rxe = to_rdev(ibpd->device); 324 struct rxe_dev *rxe = to_rdev(ibpd->device);
@@ -564,7 +566,7 @@ static struct ib_qp *rxe_create_qp(struct ib_pd *ibpd,
564 if (udata) { 566 if (udata) {
565 if (udata->inlen) { 567 if (udata->inlen) {
566 err = -EINVAL; 568 err = -EINVAL;
567 goto err1; 569 goto err2;
568 } 570 }
569 qp->is_user = 1; 571 qp->is_user = 1;
570 } 572 }
@@ -573,12 +575,13 @@ static struct ib_qp *rxe_create_qp(struct ib_pd *ibpd,
573 575
574 err = rxe_qp_from_init(rxe, qp, pd, init, udata, ibpd); 576 err = rxe_qp_from_init(rxe, qp, pd, init, udata, ibpd);
575 if (err) 577 if (err)
576 goto err2; 578 goto err3;
577 579
578 return &qp->ibqp; 580 return &qp->ibqp;
579 581
580err2: 582err3:
581 rxe_drop_index(qp); 583 rxe_drop_index(qp);
584err2:
582 rxe_drop_ref(qp); 585 rxe_drop_ref(qp);
583err1: 586err1:
584 return ERR_PTR(err); 587 return ERR_PTR(err);
@@ -1007,11 +1010,19 @@ static int rxe_peek_cq(struct ib_cq *ibcq, int wc_cnt)
1007static int rxe_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) 1010static int rxe_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
1008{ 1011{
1009 struct rxe_cq *cq = to_rcq(ibcq); 1012 struct rxe_cq *cq = to_rcq(ibcq);
1013 unsigned long irq_flags;
1014 int ret = 0;
1010 1015
1016 spin_lock_irqsave(&cq->cq_lock, irq_flags);
1011 if (cq->notify != IB_CQ_NEXT_COMP) 1017 if (cq->notify != IB_CQ_NEXT_COMP)
1012 cq->notify = flags & IB_CQ_SOLICITED_MASK; 1018 cq->notify = flags & IB_CQ_SOLICITED_MASK;
1013 1019
1014 return 0; 1020 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !queue_empty(cq->queue))
1021 ret = 1;
1022
1023 spin_unlock_irqrestore(&cq->cq_lock, irq_flags);
1024
1025 return ret;
1015} 1026}
1016 1027
1017static struct ib_mr *rxe_get_dma_mr(struct ib_pd *ibpd, int access) 1028static struct ib_mr *rxe_get_dma_mr(struct ib_pd *ibpd, int access)
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_cm.c b/drivers/infiniband/ulp/ipoib/ipoib_cm.c
index 339a1eecdfe3..096c4f6fbd65 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_cm.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_cm.c
@@ -357,11 +357,8 @@ static int ipoib_cm_nonsrq_init_rx(struct net_device *dev, struct ib_cm_id *cm_i
357 int i; 357 int i;
358 358
359 rx->rx_ring = vzalloc(ipoib_recvq_size * sizeof *rx->rx_ring); 359 rx->rx_ring = vzalloc(ipoib_recvq_size * sizeof *rx->rx_ring);
360 if (!rx->rx_ring) { 360 if (!rx->rx_ring)
361 printk(KERN_WARNING "%s: failed to allocate CM non-SRQ ring (%d entries)\n",
362 priv->ca->name, ipoib_recvq_size);
363 return -ENOMEM; 361 return -ENOMEM;
364 }
365 362
366 t = kmalloc(sizeof *t, GFP_KERNEL); 363 t = kmalloc(sizeof *t, GFP_KERNEL);
367 if (!t) { 364 if (!t) {
@@ -1054,8 +1051,6 @@ static struct ib_qp *ipoib_cm_create_tx_qp(struct net_device *dev, struct ipoib_
1054 1051
1055 tx_qp = ib_create_qp(priv->pd, &attr); 1052 tx_qp = ib_create_qp(priv->pd, &attr);
1056 if (PTR_ERR(tx_qp) == -EINVAL) { 1053 if (PTR_ERR(tx_qp) == -EINVAL) {
1057 ipoib_warn(priv, "can't use GFP_NOIO for QPs on device %s, using GFP_KERNEL\n",
1058 priv->ca->name);
1059 attr.create_flags &= ~IB_QP_CREATE_USE_GFP_NOIO; 1054 attr.create_flags &= ~IB_QP_CREATE_USE_GFP_NOIO;
1060 tx_qp = ib_create_qp(priv->pd, &attr); 1055 tx_qp = ib_create_qp(priv->pd, &attr);
1061 } 1056 }
@@ -1134,7 +1129,6 @@ static int ipoib_cm_tx_init(struct ipoib_cm_tx *p, u32 qpn,
1134 p->tx_ring = __vmalloc(ipoib_sendq_size * sizeof *p->tx_ring, 1129 p->tx_ring = __vmalloc(ipoib_sendq_size * sizeof *p->tx_ring,
1135 GFP_NOIO, PAGE_KERNEL); 1130 GFP_NOIO, PAGE_KERNEL);
1136 if (!p->tx_ring) { 1131 if (!p->tx_ring) {
1137 ipoib_warn(priv, "failed to allocate tx ring\n");
1138 ret = -ENOMEM; 1132 ret = -ENOMEM;
1139 goto err_tx; 1133 goto err_tx;
1140 } 1134 }
@@ -1550,8 +1544,6 @@ static void ipoib_cm_create_srq(struct net_device *dev, int max_sge)
1550 1544
1551 priv->cm.srq_ring = vzalloc(ipoib_recvq_size * sizeof *priv->cm.srq_ring); 1545 priv->cm.srq_ring = vzalloc(ipoib_recvq_size * sizeof *priv->cm.srq_ring);
1552 if (!priv->cm.srq_ring) { 1546 if (!priv->cm.srq_ring) {
1553 printk(KERN_WARNING "%s: failed to allocate CM SRQ ring (%d entries)\n",
1554 priv->ca->name, ipoib_recvq_size);
1555 ib_destroy_srq(priv->cm.srq); 1547 ib_destroy_srq(priv->cm.srq);
1556 priv->cm.srq = NULL; 1548 priv->cm.srq = NULL;
1557 return; 1549 return;
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_ib.c b/drivers/infiniband/ulp/ipoib/ipoib_ib.c
index 830fecb6934c..5038f9d2d753 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_ib.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_ib.c
@@ -416,11 +416,8 @@ static void ipoib_ib_handle_tx_wc(struct net_device *dev, struct ib_wc *wc)
416 "(status=%d, wrid=%d vend_err %x)\n", 416 "(status=%d, wrid=%d vend_err %x)\n",
417 wc->status, wr_id, wc->vendor_err); 417 wc->status, wr_id, wc->vendor_err);
418 qp_work = kzalloc(sizeof(*qp_work), GFP_ATOMIC); 418 qp_work = kzalloc(sizeof(*qp_work), GFP_ATOMIC);
419 if (!qp_work) { 419 if (!qp_work)
420 ipoib_warn(priv, "%s Failed alloc ipoib_qp_state_validate for qp: 0x%x\n",
421 __func__, priv->qp->qp_num);
422 return; 420 return;
423 }
424 421
425 INIT_WORK(&qp_work->work, ipoib_qp_state_validate_work); 422 INIT_WORK(&qp_work->work, ipoib_qp_state_validate_work);
426 qp_work->priv = priv; 423 qp_work->priv = priv;
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_main.c b/drivers/infiniband/ulp/ipoib/ipoib_main.c
index c50794fb92db..3ce0765a05ab 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_main.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_main.c
@@ -1619,11 +1619,8 @@ int ipoib_dev_init(struct net_device *dev, struct ib_device *ca, int port)
1619 /* Allocate RX/TX "rings" to hold queued skbs */ 1619 /* Allocate RX/TX "rings" to hold queued skbs */
1620 priv->rx_ring = kzalloc(ipoib_recvq_size * sizeof *priv->rx_ring, 1620 priv->rx_ring = kzalloc(ipoib_recvq_size * sizeof *priv->rx_ring,
1621 GFP_KERNEL); 1621 GFP_KERNEL);
1622 if (!priv->rx_ring) { 1622 if (!priv->rx_ring)
1623 printk(KERN_WARNING "%s: failed to allocate RX ring (%d entries)\n",
1624 ca->name, ipoib_recvq_size);
1625 goto out; 1623 goto out;
1626 }
1627 1624
1628 priv->tx_ring = vzalloc(ipoib_sendq_size * sizeof *priv->tx_ring); 1625 priv->tx_ring = vzalloc(ipoib_sendq_size * sizeof *priv->tx_ring);
1629 if (!priv->tx_ring) { 1626 if (!priv->tx_ring) {
diff --git a/drivers/infiniband/ulp/ipoib/ipoib_multicast.c b/drivers/infiniband/ulp/ipoib/ipoib_multicast.c
index 1909dd252c94..fddff403d5d2 100644
--- a/drivers/infiniband/ulp/ipoib/ipoib_multicast.c
+++ b/drivers/infiniband/ulp/ipoib/ipoib_multicast.c
@@ -575,8 +575,11 @@ void ipoib_mcast_join_task(struct work_struct *work)
575 if (!test_bit(IPOIB_FLAG_OPER_UP, &priv->flags)) 575 if (!test_bit(IPOIB_FLAG_OPER_UP, &priv->flags))
576 return; 576 return;
577 577
578 if (ib_query_port(priv->ca, priv->port, &port_attr) || 578 if (ib_query_port(priv->ca, priv->port, &port_attr)) {
579 port_attr.state != IB_PORT_ACTIVE) { 579 ipoib_dbg(priv, "ib_query_port() failed\n");
580 return;
581 }
582 if (port_attr.state != IB_PORT_ACTIVE) {
580 ipoib_dbg(priv, "port state is not ACTIVE (state = %d) suspending join task\n", 583 ipoib_dbg(priv, "port state is not ACTIVE (state = %d) suspending join task\n",
581 port_attr.state); 584 port_attr.state);
582 return; 585 return;
diff --git a/drivers/infiniband/ulp/iser/iser_verbs.c b/drivers/infiniband/ulp/iser/iser_verbs.c
index a4b791dfaa1d..8ae7a3beddb7 100644
--- a/drivers/infiniband/ulp/iser/iser_verbs.c
+++ b/drivers/infiniband/ulp/iser/iser_verbs.c
@@ -890,11 +890,14 @@ static int iser_cma_handler(struct rdma_cm_id *cma_id, struct rdma_cm_event *eve
890 case RDMA_CM_EVENT_ESTABLISHED: 890 case RDMA_CM_EVENT_ESTABLISHED:
891 iser_connected_handler(cma_id, event->param.conn.private_data); 891 iser_connected_handler(cma_id, event->param.conn.private_data);
892 break; 892 break;
893 case RDMA_CM_EVENT_REJECTED:
894 iser_info("Connection rejected: %s\n",
895 rdma_reject_msg(cma_id, event->status));
896 /* FALLTHROUGH */
893 case RDMA_CM_EVENT_ADDR_ERROR: 897 case RDMA_CM_EVENT_ADDR_ERROR:
894 case RDMA_CM_EVENT_ROUTE_ERROR: 898 case RDMA_CM_EVENT_ROUTE_ERROR:
895 case RDMA_CM_EVENT_CONNECT_ERROR: 899 case RDMA_CM_EVENT_CONNECT_ERROR:
896 case RDMA_CM_EVENT_UNREACHABLE: 900 case RDMA_CM_EVENT_UNREACHABLE:
897 case RDMA_CM_EVENT_REJECTED:
898 iser_connect_error(cma_id); 901 iser_connect_error(cma_id);
899 break; 902 break;
900 case RDMA_CM_EVENT_DISCONNECTED: 903 case RDMA_CM_EVENT_DISCONNECTED:
diff --git a/drivers/infiniband/ulp/isert/ib_isert.c b/drivers/infiniband/ulp/isert/ib_isert.c
index 6dd43f63238e..314e95516068 100644
--- a/drivers/infiniband/ulp/isert/ib_isert.c
+++ b/drivers/infiniband/ulp/isert/ib_isert.c
@@ -184,7 +184,7 @@ isert_alloc_rx_descriptors(struct isert_conn *isert_conn)
184 isert_conn->rx_descs = kzalloc(ISERT_QP_MAX_RECV_DTOS * 184 isert_conn->rx_descs = kzalloc(ISERT_QP_MAX_RECV_DTOS *
185 sizeof(struct iser_rx_desc), GFP_KERNEL); 185 sizeof(struct iser_rx_desc), GFP_KERNEL);
186 if (!isert_conn->rx_descs) 186 if (!isert_conn->rx_descs)
187 goto fail; 187 return -ENOMEM;
188 188
189 rx_desc = isert_conn->rx_descs; 189 rx_desc = isert_conn->rx_descs;
190 190
@@ -213,9 +213,7 @@ dma_map_fail:
213 } 213 }
214 kfree(isert_conn->rx_descs); 214 kfree(isert_conn->rx_descs);
215 isert_conn->rx_descs = NULL; 215 isert_conn->rx_descs = NULL;
216fail:
217 isert_err("conn %p failed to allocate rx descriptors\n", isert_conn); 216 isert_err("conn %p failed to allocate rx descriptors\n", isert_conn);
218
219 return -ENOMEM; 217 return -ENOMEM;
220} 218}
221 219
@@ -269,10 +267,8 @@ isert_alloc_comps(struct isert_device *device)
269 267
270 device->comps = kcalloc(device->comps_used, sizeof(struct isert_comp), 268 device->comps = kcalloc(device->comps_used, sizeof(struct isert_comp),
271 GFP_KERNEL); 269 GFP_KERNEL);
272 if (!device->comps) { 270 if (!device->comps)
273 isert_err("Unable to allocate completion contexts\n");
274 return -ENOMEM; 271 return -ENOMEM;
275 }
276 272
277 max_cqe = min(ISER_MAX_CQ_LEN, device->ib_device->attrs.max_cqe); 273 max_cqe = min(ISER_MAX_CQ_LEN, device->ib_device->attrs.max_cqe);
278 274
@@ -432,10 +428,8 @@ isert_alloc_login_buf(struct isert_conn *isert_conn,
432 428
433 isert_conn->login_req_buf = kzalloc(sizeof(*isert_conn->login_req_buf), 429 isert_conn->login_req_buf = kzalloc(sizeof(*isert_conn->login_req_buf),
434 GFP_KERNEL); 430 GFP_KERNEL);
435 if (!isert_conn->login_req_buf) { 431 if (!isert_conn->login_req_buf)
436 isert_err("Unable to allocate isert_conn->login_buf\n");
437 return -ENOMEM; 432 return -ENOMEM;
438 }
439 433
440 isert_conn->login_req_dma = ib_dma_map_single(ib_dev, 434 isert_conn->login_req_dma = ib_dma_map_single(ib_dev,
441 isert_conn->login_req_buf, 435 isert_conn->login_req_buf,
@@ -795,6 +789,8 @@ isert_cma_handler(struct rdma_cm_id *cma_id, struct rdma_cm_event *event)
795 */ 789 */
796 return 1; 790 return 1;
797 case RDMA_CM_EVENT_REJECTED: /* FALLTHRU */ 791 case RDMA_CM_EVENT_REJECTED: /* FALLTHRU */
792 isert_info("Connection rejected: %s\n",
793 rdma_reject_msg(cma_id, event->status));
798 case RDMA_CM_EVENT_UNREACHABLE: /* FALLTHRU */ 794 case RDMA_CM_EVENT_UNREACHABLE: /* FALLTHRU */
799 case RDMA_CM_EVENT_CONNECT_ERROR: 795 case RDMA_CM_EVENT_CONNECT_ERROR:
800 ret = isert_connect_error(cma_id); 796 ret = isert_connect_error(cma_id);
@@ -1276,11 +1272,8 @@ isert_handle_text_cmd(struct isert_conn *isert_conn, struct isert_cmd *isert_cmd
1276 1272
1277 if (payload_length) { 1273 if (payload_length) {
1278 text_in = kzalloc(payload_length, GFP_KERNEL); 1274 text_in = kzalloc(payload_length, GFP_KERNEL);
1279 if (!text_in) { 1275 if (!text_in)
1280 isert_err("Unable to allocate text_in of payload_length: %u\n",
1281 payload_length);
1282 return -ENOMEM; 1276 return -ENOMEM;
1283 }
1284 } 1277 }
1285 cmd->text_in_ptr = text_in; 1278 cmd->text_in_ptr = text_in;
1286 1279
@@ -1851,6 +1844,8 @@ isert_put_response(struct iscsi_conn *conn, struct iscsi_cmd *cmd)
1851 isert_cmd->pdu_buf_dma = ib_dma_map_single(ib_dev, 1844 isert_cmd->pdu_buf_dma = ib_dma_map_single(ib_dev,
1852 (void *)cmd->sense_buffer, pdu_len, 1845 (void *)cmd->sense_buffer, pdu_len,
1853 DMA_TO_DEVICE); 1846 DMA_TO_DEVICE);
1847 if (ib_dma_mapping_error(ib_dev, isert_cmd->pdu_buf_dma))
1848 return -ENOMEM;
1854 1849
1855 isert_cmd->pdu_buf_len = pdu_len; 1850 isert_cmd->pdu_buf_len = pdu_len;
1856 tx_dsg->addr = isert_cmd->pdu_buf_dma; 1851 tx_dsg->addr = isert_cmd->pdu_buf_dma;
@@ -1978,6 +1973,8 @@ isert_put_reject(struct iscsi_cmd *cmd, struct iscsi_conn *conn)
1978 isert_cmd->pdu_buf_dma = ib_dma_map_single(ib_dev, 1973 isert_cmd->pdu_buf_dma = ib_dma_map_single(ib_dev,
1979 (void *)cmd->buf_ptr, ISCSI_HDR_LEN, 1974 (void *)cmd->buf_ptr, ISCSI_HDR_LEN,
1980 DMA_TO_DEVICE); 1975 DMA_TO_DEVICE);
1976 if (ib_dma_mapping_error(ib_dev, isert_cmd->pdu_buf_dma))
1977 return -ENOMEM;
1981 isert_cmd->pdu_buf_len = ISCSI_HDR_LEN; 1978 isert_cmd->pdu_buf_len = ISCSI_HDR_LEN;
1982 tx_dsg->addr = isert_cmd->pdu_buf_dma; 1979 tx_dsg->addr = isert_cmd->pdu_buf_dma;
1983 tx_dsg->length = ISCSI_HDR_LEN; 1980 tx_dsg->length = ISCSI_HDR_LEN;
@@ -2018,6 +2015,8 @@ isert_put_text_rsp(struct iscsi_cmd *cmd, struct iscsi_conn *conn)
2018 2015
2019 isert_cmd->pdu_buf_dma = ib_dma_map_single(ib_dev, 2016 isert_cmd->pdu_buf_dma = ib_dma_map_single(ib_dev,
2020 txt_rsp_buf, txt_rsp_len, DMA_TO_DEVICE); 2017 txt_rsp_buf, txt_rsp_len, DMA_TO_DEVICE);
2018 if (ib_dma_mapping_error(ib_dev, isert_cmd->pdu_buf_dma))
2019 return -ENOMEM;
2021 2020
2022 isert_cmd->pdu_buf_len = txt_rsp_len; 2021 isert_cmd->pdu_buf_len = txt_rsp_len;
2023 tx_dsg->addr = isert_cmd->pdu_buf_dma; 2022 tx_dsg->addr = isert_cmd->pdu_buf_dma;
@@ -2307,10 +2306,9 @@ isert_setup_np(struct iscsi_np *np,
2307 int ret; 2306 int ret;
2308 2307
2309 isert_np = kzalloc(sizeof(struct isert_np), GFP_KERNEL); 2308 isert_np = kzalloc(sizeof(struct isert_np), GFP_KERNEL);
2310 if (!isert_np) { 2309 if (!isert_np)
2311 isert_err("Unable to allocate struct isert_np\n");
2312 return -ENOMEM; 2310 return -ENOMEM;
2313 } 2311
2314 sema_init(&isert_np->sem, 0); 2312 sema_init(&isert_np->sem, 0);
2315 mutex_init(&isert_np->mutex); 2313 mutex_init(&isert_np->mutex);
2316 INIT_LIST_HEAD(&isert_np->accepted); 2314 INIT_LIST_HEAD(&isert_np->accepted);
@@ -2651,7 +2649,6 @@ static int __init isert_init(void)
2651 WQ_UNBOUND | WQ_HIGHPRI, 0); 2649 WQ_UNBOUND | WQ_HIGHPRI, 0);
2652 if (!isert_comp_wq) { 2650 if (!isert_comp_wq) {
2653 isert_err("Unable to allocate isert_comp_wq\n"); 2651 isert_err("Unable to allocate isert_comp_wq\n");
2654 ret = -ENOMEM;
2655 return -ENOMEM; 2652 return -ENOMEM;
2656 } 2653 }
2657 2654
diff --git a/drivers/infiniband/ulp/srp/ib_srp.c b/drivers/infiniband/ulp/srp/ib_srp.c
index d980fb458ad4..8ddc07123193 100644
--- a/drivers/infiniband/ulp/srp/ib_srp.c
+++ b/drivers/infiniband/ulp/srp/ib_srp.c
@@ -64,6 +64,11 @@ MODULE_LICENSE("Dual BSD/GPL");
64MODULE_VERSION(DRV_VERSION); 64MODULE_VERSION(DRV_VERSION);
65MODULE_INFO(release_date, DRV_RELDATE); 65MODULE_INFO(release_date, DRV_RELDATE);
66 66
67#if !defined(CONFIG_DYNAMIC_DEBUG)
68#define DEFINE_DYNAMIC_DEBUG_METADATA(name, fmt)
69#define DYNAMIC_DEBUG_BRANCH(descriptor) false
70#endif
71
67static unsigned int srp_sg_tablesize; 72static unsigned int srp_sg_tablesize;
68static unsigned int cmd_sg_entries; 73static unsigned int cmd_sg_entries;
69static unsigned int indirect_sg_entries; 74static unsigned int indirect_sg_entries;
@@ -384,6 +389,9 @@ static struct srp_fr_pool *srp_create_fr_pool(struct ib_device *device,
384 max_page_list_len); 389 max_page_list_len);
385 if (IS_ERR(mr)) { 390 if (IS_ERR(mr)) {
386 ret = PTR_ERR(mr); 391 ret = PTR_ERR(mr);
392 if (ret == -ENOMEM)
393 pr_info("%s: ib_alloc_mr() failed. Try to reduce max_cmd_per_lun, max_sect or ch_count\n",
394 dev_name(&device->dev));
387 goto destroy_pool; 395 goto destroy_pool;
388 } 396 }
389 d->mr = mr; 397 d->mr = mr;
@@ -1266,8 +1274,12 @@ static int srp_map_finish_fmr(struct srp_map_state *state,
1266 struct ib_pool_fmr *fmr; 1274 struct ib_pool_fmr *fmr;
1267 u64 io_addr = 0; 1275 u64 io_addr = 0;
1268 1276
1269 if (state->fmr.next >= state->fmr.end) 1277 if (state->fmr.next >= state->fmr.end) {
1278 shost_printk(KERN_ERR, ch->target->scsi_host,
1279 PFX "Out of MRs (mr_per_cmd = %d)\n",
1280 ch->target->mr_per_cmd);
1270 return -ENOMEM; 1281 return -ENOMEM;
1282 }
1271 1283
1272 WARN_ON_ONCE(!dev->use_fmr); 1284 WARN_ON_ONCE(!dev->use_fmr);
1273 1285
@@ -1323,8 +1335,12 @@ static int srp_map_finish_fr(struct srp_map_state *state,
1323 u32 rkey; 1335 u32 rkey;
1324 int n, err; 1336 int n, err;
1325 1337
1326 if (state->fr.next >= state->fr.end) 1338 if (state->fr.next >= state->fr.end) {
1339 shost_printk(KERN_ERR, ch->target->scsi_host,
1340 PFX "Out of MRs (mr_per_cmd = %d)\n",
1341 ch->target->mr_per_cmd);
1327 return -ENOMEM; 1342 return -ENOMEM;
1343 }
1328 1344
1329 WARN_ON_ONCE(!dev->use_fast_reg); 1345 WARN_ON_ONCE(!dev->use_fast_reg);
1330 1346
@@ -1556,7 +1572,6 @@ static int srp_map_idb(struct srp_rdma_ch *ch, struct srp_request *req,
1556 return 0; 1572 return 0;
1557} 1573}
1558 1574
1559#if defined(DYNAMIC_DATA_DEBUG)
1560static void srp_check_mapping(struct srp_map_state *state, 1575static void srp_check_mapping(struct srp_map_state *state,
1561 struct srp_rdma_ch *ch, struct srp_request *req, 1576 struct srp_rdma_ch *ch, struct srp_request *req,
1562 struct scatterlist *scat, int count) 1577 struct scatterlist *scat, int count)
@@ -1580,7 +1595,6 @@ static void srp_check_mapping(struct srp_map_state *state,
1580 scsi_bufflen(req->scmnd), desc_len, mr_len, 1595 scsi_bufflen(req->scmnd), desc_len, mr_len,
1581 state->ndesc, state->nmdesc); 1596 state->ndesc, state->nmdesc);
1582} 1597}
1583#endif
1584 1598
1585/** 1599/**
1586 * srp_map_data() - map SCSI data buffer onto an SRP request 1600 * srp_map_data() - map SCSI data buffer onto an SRP request
@@ -1669,14 +1683,12 @@ static int srp_map_data(struct scsi_cmnd *scmnd, struct srp_rdma_ch *ch,
1669 if (ret < 0) 1683 if (ret < 0)
1670 goto unmap; 1684 goto unmap;
1671 1685
1672#if defined(DYNAMIC_DEBUG)
1673 { 1686 {
1674 DEFINE_DYNAMIC_DEBUG_METADATA(ddm, 1687 DEFINE_DYNAMIC_DEBUG_METADATA(ddm,
1675 "Memory mapping consistency check"); 1688 "Memory mapping consistency check");
1676 if (unlikely(ddm.flags & _DPRINTK_FLAGS_PRINT)) 1689 if (DYNAMIC_DEBUG_BRANCH(ddm))
1677 srp_check_mapping(&state, ch, req, scat, count); 1690 srp_check_mapping(&state, ch, req, scat, count);
1678 } 1691 }
1679#endif
1680 1692
1681 /* We've mapped the request, now pull as much of the indirect 1693 /* We've mapped the request, now pull as much of the indirect
1682 * descriptor table as we can into the command buffer. If this 1694 * descriptor table as we can into the command buffer. If this
@@ -3287,7 +3299,9 @@ static ssize_t srp_create_target(struct device *dev,
3287 */ 3299 */
3288 scsi_host_get(target->scsi_host); 3300 scsi_host_get(target->scsi_host);
3289 3301
3290 mutex_lock(&host->add_target_mutex); 3302 ret = mutex_lock_interruptible(&host->add_target_mutex);
3303 if (ret < 0)
3304 goto put;
3291 3305
3292 ret = srp_parse_options(buf, target); 3306 ret = srp_parse_options(buf, target);
3293 if (ret) 3307 if (ret)
@@ -3443,6 +3457,7 @@ connected:
3443out: 3457out:
3444 mutex_unlock(&host->add_target_mutex); 3458 mutex_unlock(&host->add_target_mutex);
3445 3459
3460put:
3446 scsi_host_put(target->scsi_host); 3461 scsi_host_put(target->scsi_host);
3447 if (ret < 0) 3462 if (ret < 0)
3448 scsi_host_put(target->scsi_host); 3463 scsi_host_put(target->scsi_host);
@@ -3526,6 +3541,7 @@ free_host:
3526static void srp_add_one(struct ib_device *device) 3541static void srp_add_one(struct ib_device *device)
3527{ 3542{
3528 struct srp_device *srp_dev; 3543 struct srp_device *srp_dev;
3544 struct ib_device_attr *attr = &device->attrs;
3529 struct srp_host *host; 3545 struct srp_host *host;
3530 int mr_page_shift, p; 3546 int mr_page_shift, p;
3531 u64 max_pages_per_mr; 3547 u64 max_pages_per_mr;
@@ -3540,25 +3556,25 @@ static void srp_add_one(struct ib_device *device)
3540 * minimum of 4096 bytes. We're unlikely to build large sglists 3556 * minimum of 4096 bytes. We're unlikely to build large sglists
3541 * out of smaller entries. 3557 * out of smaller entries.
3542 */ 3558 */
3543 mr_page_shift = max(12, ffs(device->attrs.page_size_cap) - 1); 3559 mr_page_shift = max(12, ffs(attr->page_size_cap) - 1);
3544 srp_dev->mr_page_size = 1 << mr_page_shift; 3560 srp_dev->mr_page_size = 1 << mr_page_shift;
3545 srp_dev->mr_page_mask = ~((u64) srp_dev->mr_page_size - 1); 3561 srp_dev->mr_page_mask = ~((u64) srp_dev->mr_page_size - 1);
3546 max_pages_per_mr = device->attrs.max_mr_size; 3562 max_pages_per_mr = attr->max_mr_size;
3547 do_div(max_pages_per_mr, srp_dev->mr_page_size); 3563 do_div(max_pages_per_mr, srp_dev->mr_page_size);
3548 pr_debug("%s: %llu / %u = %llu <> %u\n", __func__, 3564 pr_debug("%s: %llu / %u = %llu <> %u\n", __func__,
3549 device->attrs.max_mr_size, srp_dev->mr_page_size, 3565 attr->max_mr_size, srp_dev->mr_page_size,
3550 max_pages_per_mr, SRP_MAX_PAGES_PER_MR); 3566 max_pages_per_mr, SRP_MAX_PAGES_PER_MR);
3551 srp_dev->max_pages_per_mr = min_t(u64, SRP_MAX_PAGES_PER_MR, 3567 srp_dev->max_pages_per_mr = min_t(u64, SRP_MAX_PAGES_PER_MR,
3552 max_pages_per_mr); 3568 max_pages_per_mr);
3553 3569
3554 srp_dev->has_fmr = (device->alloc_fmr && device->dealloc_fmr && 3570 srp_dev->has_fmr = (device->alloc_fmr && device->dealloc_fmr &&
3555 device->map_phys_fmr && device->unmap_fmr); 3571 device->map_phys_fmr && device->unmap_fmr);
3556 srp_dev->has_fr = (device->attrs.device_cap_flags & 3572 srp_dev->has_fr = (attr->device_cap_flags &
3557 IB_DEVICE_MEM_MGT_EXTENSIONS); 3573 IB_DEVICE_MEM_MGT_EXTENSIONS);
3558 if (!never_register && !srp_dev->has_fmr && !srp_dev->has_fr) { 3574 if (!never_register && !srp_dev->has_fmr && !srp_dev->has_fr) {
3559 dev_warn(&device->dev, "neither FMR nor FR is supported\n"); 3575 dev_warn(&device->dev, "neither FMR nor FR is supported\n");
3560 } else if (!never_register && 3576 } else if (!never_register &&
3561 device->attrs.max_mr_size >= 2 * srp_dev->mr_page_size) { 3577 attr->max_mr_size >= 2 * srp_dev->mr_page_size) {
3562 srp_dev->use_fast_reg = (srp_dev->has_fr && 3578 srp_dev->use_fast_reg = (srp_dev->has_fr &&
3563 (!srp_dev->has_fmr || prefer_fr)); 3579 (!srp_dev->has_fmr || prefer_fr));
3564 srp_dev->use_fmr = !srp_dev->use_fast_reg && srp_dev->has_fmr; 3580 srp_dev->use_fmr = !srp_dev->use_fast_reg && srp_dev->has_fmr;
@@ -3571,13 +3587,13 @@ static void srp_add_one(struct ib_device *device)
3571 if (srp_dev->use_fast_reg) { 3587 if (srp_dev->use_fast_reg) {
3572 srp_dev->max_pages_per_mr = 3588 srp_dev->max_pages_per_mr =
3573 min_t(u32, srp_dev->max_pages_per_mr, 3589 min_t(u32, srp_dev->max_pages_per_mr,
3574 device->attrs.max_fast_reg_page_list_len); 3590 attr->max_fast_reg_page_list_len);
3575 } 3591 }
3576 srp_dev->mr_max_size = srp_dev->mr_page_size * 3592 srp_dev->mr_max_size = srp_dev->mr_page_size *
3577 srp_dev->max_pages_per_mr; 3593 srp_dev->max_pages_per_mr;
3578 pr_debug("%s: mr_page_shift = %d, device->max_mr_size = %#llx, device->max_fast_reg_page_list_len = %u, max_pages_per_mr = %d, mr_max_size = %#x\n", 3594 pr_debug("%s: mr_page_shift = %d, device->max_mr_size = %#llx, device->max_fast_reg_page_list_len = %u, max_pages_per_mr = %d, mr_max_size = %#x\n",
3579 device->name, mr_page_shift, device->attrs.max_mr_size, 3595 device->name, mr_page_shift, attr->max_mr_size,
3580 device->attrs.max_fast_reg_page_list_len, 3596 attr->max_fast_reg_page_list_len,
3581 srp_dev->max_pages_per_mr, srp_dev->mr_max_size); 3597 srp_dev->max_pages_per_mr, srp_dev->mr_max_size);
3582 3598
3583 INIT_LIST_HEAD(&srp_dev->dev_list); 3599 INIT_LIST_HEAD(&srp_dev->dev_list);
diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c
index 0b1f69ed2e92..d21ba9d857c3 100644
--- a/drivers/infiniband/ulp/srpt/ib_srpt.c
+++ b/drivers/infiniband/ulp/srpt/ib_srpt.c
@@ -1840,7 +1840,6 @@ static int srpt_cm_req_recv(struct ib_cm_id *cm_id,
1840 struct srpt_rdma_ch *ch, *tmp_ch; 1840 struct srpt_rdma_ch *ch, *tmp_ch;
1841 u32 it_iu_len; 1841 u32 it_iu_len;
1842 int i, ret = 0; 1842 int i, ret = 0;
1843 unsigned char *p;
1844 1843
1845 WARN_ON_ONCE(irqs_disabled()); 1844 WARN_ON_ONCE(irqs_disabled());
1846 1845
@@ -1994,21 +1993,18 @@ static int srpt_cm_req_recv(struct ib_cm_id *cm_id,
1994 be64_to_cpu(*(__be64 *)(ch->i_port_id + 8))); 1993 be64_to_cpu(*(__be64 *)(ch->i_port_id + 8)));
1995 1994
1996 pr_debug("registering session %s\n", ch->sess_name); 1995 pr_debug("registering session %s\n", ch->sess_name);
1997 p = &ch->sess_name[0];
1998 1996
1999try_again:
2000 ch->sess = target_alloc_session(&sport->port_tpg_1, 0, 0, 1997 ch->sess = target_alloc_session(&sport->port_tpg_1, 0, 0,
2001 TARGET_PROT_NORMAL, p, ch, NULL); 1998 TARGET_PROT_NORMAL, ch->sess_name, ch,
1999 NULL);
2000 /* Retry without leading "0x" */
2001 if (IS_ERR(ch->sess))
2002 ch->sess = target_alloc_session(&sport->port_tpg_1, 0, 0,
2003 TARGET_PROT_NORMAL,
2004 ch->sess_name + 2, ch, NULL);
2002 if (IS_ERR(ch->sess)) { 2005 if (IS_ERR(ch->sess)) {
2003 pr_info("Rejected login because no ACL has been" 2006 pr_info("Rejected login because no ACL has been configured yet for initiator %s.\n",
2004 " configured yet for initiator %s.\n", p); 2007 ch->sess_name);
2005 /*
2006 * XXX: Hack to retry of ch->i_port_id without leading '0x'
2007 */
2008 if (p == &ch->sess_name[0]) {
2009 p += 2;
2010 goto try_again;
2011 }
2012 rej->reason = cpu_to_be32((PTR_ERR(ch->sess) == -ENOMEM) ? 2008 rej->reason = cpu_to_be32((PTR_ERR(ch->sess) == -ENOMEM) ?
2013 SRP_LOGIN_REJ_INSUFFICIENT_RESOURCES : 2009 SRP_LOGIN_REJ_INSUFFICIENT_RESOURCES :
2014 SRP_LOGIN_REJ_CHANNEL_LIMIT_REACHED); 2010 SRP_LOGIN_REJ_CHANNEL_LIMIT_REACHED);
diff --git a/drivers/net/ethernet/qlogic/qede/qede_roce.c b/drivers/net/ethernet/qlogic/qede/qede_roce.c
index 9867f960b063..49272716a7c4 100644
--- a/drivers/net/ethernet/qlogic/qede/qede_roce.c
+++ b/drivers/net/ethernet/qlogic/qede/qede_roce.c
@@ -191,8 +191,8 @@ int qede_roce_register_driver(struct qedr_driver *drv)
191 } 191 }
192 mutex_unlock(&qedr_dev_list_lock); 192 mutex_unlock(&qedr_dev_list_lock);
193 193
194 DP_INFO(edev, "qedr: discovered and registered %d RoCE funcs\n", 194 pr_notice("qedr: discovered and registered %d RoCE funcs\n",
195 qedr_counter); 195 qedr_counter);
196 196
197 return 0; 197 return 0;
198} 198}
diff --git a/drivers/net/vmxnet3/vmxnet3_int.h b/drivers/net/vmxnet3/vmxnet3_int.h
index 7dc37a090549..59e077be8829 100644
--- a/drivers/net/vmxnet3/vmxnet3_int.h
+++ b/drivers/net/vmxnet3/vmxnet3_int.h
@@ -119,9 +119,8 @@ enum {
119}; 119};
120 120
121/* 121/*
122 * PCI vendor and device IDs. 122 * Maximum devices supported.
123 */ 123 */
124#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
125#define MAX_ETHERNET_CARDS 10 124#define MAX_ETHERNET_CARDS 10
126#define MAX_PCI_PASSTHRU_DEVICE 6 125#define MAX_PCI_PASSTHRU_DEVICE 6
127 126
diff --git a/drivers/nvme/host/rdma.c b/drivers/nvme/host/rdma.c
index f42ab70ffa38..f587af345889 100644
--- a/drivers/nvme/host/rdma.c
+++ b/drivers/nvme/host/rdma.c
@@ -42,6 +42,28 @@
42 42
43#define NVME_RDMA_MAX_INLINE_SEGMENTS 1 43#define NVME_RDMA_MAX_INLINE_SEGMENTS 1
44 44
45static const char *const nvme_rdma_cm_status_strs[] = {
46 [NVME_RDMA_CM_INVALID_LEN] = "invalid length",
47 [NVME_RDMA_CM_INVALID_RECFMT] = "invalid record format",
48 [NVME_RDMA_CM_INVALID_QID] = "invalid queue ID",
49 [NVME_RDMA_CM_INVALID_HSQSIZE] = "invalid host SQ size",
50 [NVME_RDMA_CM_INVALID_HRQSIZE] = "invalid host RQ size",
51 [NVME_RDMA_CM_NO_RSC] = "resource not found",
52 [NVME_RDMA_CM_INVALID_IRD] = "invalid IRD",
53 [NVME_RDMA_CM_INVALID_ORD] = "Invalid ORD",
54};
55
56static const char *nvme_rdma_cm_msg(enum nvme_rdma_cm_status status)
57{
58 size_t index = status;
59
60 if (index < ARRAY_SIZE(nvme_rdma_cm_status_strs) &&
61 nvme_rdma_cm_status_strs[index])
62 return nvme_rdma_cm_status_strs[index];
63 else
64 return "unrecognized reason";
65};
66
45/* 67/*
46 * We handle AEN commands ourselves and don't even let the 68 * We handle AEN commands ourselves and don't even let the
47 * block layer know about them. 69 * block layer know about them.
@@ -1214,16 +1236,24 @@ out_destroy_queue_ib:
1214static int nvme_rdma_conn_rejected(struct nvme_rdma_queue *queue, 1236static int nvme_rdma_conn_rejected(struct nvme_rdma_queue *queue,
1215 struct rdma_cm_event *ev) 1237 struct rdma_cm_event *ev)
1216{ 1238{
1217 if (ev->param.conn.private_data_len) { 1239 struct rdma_cm_id *cm_id = queue->cm_id;
1218 struct nvme_rdma_cm_rej *rej = 1240 int status = ev->status;
1219 (struct nvme_rdma_cm_rej *)ev->param.conn.private_data; 1241 const char *rej_msg;
1242 const struct nvme_rdma_cm_rej *rej_data;
1243 u8 rej_data_len;
1244
1245 rej_msg = rdma_reject_msg(cm_id, status);
1246 rej_data = rdma_consumer_reject_data(cm_id, ev, &rej_data_len);
1247
1248 if (rej_data && rej_data_len >= sizeof(u16)) {
1249 u16 sts = le16_to_cpu(rej_data->sts);
1220 1250
1221 dev_err(queue->ctrl->ctrl.device, 1251 dev_err(queue->ctrl->ctrl.device,
1222 "Connect rejected, status %d.", le16_to_cpu(rej->sts)); 1252 "Connect rejected: status %d (%s) nvme status %d (%s).\n",
1223 /* XXX: Think of something clever to do here... */ 1253 status, rej_msg, sts, nvme_rdma_cm_msg(sts));
1224 } else { 1254 } else {
1225 dev_err(queue->ctrl->ctrl.device, 1255 dev_err(queue->ctrl->ctrl.device,
1226 "Connect rejected, no private data.\n"); 1256 "Connect rejected: status %d (%s).\n", status, rej_msg);
1227 } 1257 }
1228 1258
1229 return -ECONNRESET; 1259 return -ECONNRESET;
diff --git a/drivers/nvme/target/rdma.c b/drivers/nvme/target/rdma.c
index 3fbcdb7a583c..8c3760a78ac0 100644
--- a/drivers/nvme/target/rdma.c
+++ b/drivers/nvme/target/rdma.c
@@ -1374,6 +1374,9 @@ static int nvmet_rdma_cm_handler(struct rdma_cm_id *cm_id,
1374 ret = nvmet_rdma_device_removal(cm_id, queue); 1374 ret = nvmet_rdma_device_removal(cm_id, queue);
1375 break; 1375 break;
1376 case RDMA_CM_EVENT_REJECTED: 1376 case RDMA_CM_EVENT_REJECTED:
1377 pr_debug("Connection rejected: %s\n",
1378 rdma_reject_msg(cm_id, event->status));
1379 /* FALLTHROUGH */
1377 case RDMA_CM_EVENT_UNREACHABLE: 1380 case RDMA_CM_EVENT_UNREACHABLE:
1378 case RDMA_CM_EVENT_CONNECT_ERROR: 1381 case RDMA_CM_EVENT_CONNECT_ERROR:
1379 nvmet_rdma_queue_connect_fail(cm_id, queue); 1382 nvmet_rdma_queue_connect_fail(cm_id, queue);