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authorMichael Chan <mchan@broadcom.com>2007-12-20 22:56:37 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 17:57:35 -0500
commit35efa7c1f4aa868d4a948a9069f20ccef1b3b28d (patch)
tree9369da5bfcd93139ce0ac961059d29b57c66626c /drivers
parent6d866ffc69b0c3e584782f212a3f783708d31e9a (diff)
[BNX2]: Introduce new bnx2_napi structure.
Introduce a bnx2_napi structure that will hold a napi_struct and other fields to handle NAPI polling for the napi_struct. Various tx and rx indexes and status block pointers will be moved from the main bnx2 structure to this bnx2_napi structure. Most NAPI path functions are modified to be passed this bnx2_napi struct pointer. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2.c146
-rw-r--r--drivers/net/bnx2.h16
2 files changed, 100 insertions, 62 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 83cdbde5d2d6..3f754e6b48d6 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -407,12 +407,14 @@ bnx2_disable_int(struct bnx2 *bp)
407static void 407static void
408bnx2_enable_int(struct bnx2 *bp) 408bnx2_enable_int(struct bnx2 *bp)
409{ 409{
410 struct bnx2_napi *bnapi = &bp->bnx2_napi;
411
410 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 412 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
411 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 413 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
412 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx); 414 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bnapi->last_status_idx);
413 415
414 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 416 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
415 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx); 417 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bnapi->last_status_idx);
416 418
417 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW); 419 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
418} 420}
@@ -426,11 +428,23 @@ bnx2_disable_int_sync(struct bnx2 *bp)
426} 428}
427 429
428static void 430static void
431bnx2_napi_disable(struct bnx2 *bp)
432{
433 napi_disable(&bp->bnx2_napi.napi);
434}
435
436static void
437bnx2_napi_enable(struct bnx2 *bp)
438{
439 napi_enable(&bp->bnx2_napi.napi);
440}
441
442static void
429bnx2_netif_stop(struct bnx2 *bp) 443bnx2_netif_stop(struct bnx2 *bp)
430{ 444{
431 bnx2_disable_int_sync(bp); 445 bnx2_disable_int_sync(bp);
432 if (netif_running(bp->dev)) { 446 if (netif_running(bp->dev)) {
433 napi_disable(&bp->napi); 447 bnx2_napi_disable(bp);
434 netif_tx_disable(bp->dev); 448 netif_tx_disable(bp->dev);
435 bp->dev->trans_start = jiffies; /* prevent tx timeout */ 449 bp->dev->trans_start = jiffies; /* prevent tx timeout */
436 } 450 }
@@ -442,7 +456,7 @@ bnx2_netif_start(struct bnx2 *bp)
442 if (atomic_dec_and_test(&bp->intr_sem)) { 456 if (atomic_dec_and_test(&bp->intr_sem)) {
443 if (netif_running(bp->dev)) { 457 if (netif_running(bp->dev)) {
444 netif_wake_queue(bp->dev); 458 netif_wake_queue(bp->dev);
445 napi_enable(&bp->napi); 459 bnx2_napi_enable(bp);
446 bnx2_enable_int(bp); 460 bnx2_enable_int(bp);
447 } 461 }
448 } 462 }
@@ -555,6 +569,8 @@ bnx2_alloc_mem(struct bnx2 *bp)
555 569
556 memset(bp->status_blk, 0, bp->status_stats_size); 570 memset(bp->status_blk, 0, bp->status_stats_size);
557 571
572 bp->bnx2_napi.status_blk = bp->status_blk;
573
558 bp->stats_blk = (void *) ((unsigned long) bp->status_blk + 574 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
559 status_blk_size); 575 status_blk_size);
560 576
@@ -2291,9 +2307,9 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
2291} 2307}
2292 2308
2293static int 2309static int
2294bnx2_phy_event_is_set(struct bnx2 *bp, u32 event) 2310bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2295{ 2311{
2296 struct status_block *sblk = bp->status_blk; 2312 struct status_block *sblk = bnapi->status_blk;
2297 u32 new_link_state, old_link_state; 2313 u32 new_link_state, old_link_state;
2298 int is_set = 1; 2314 int is_set = 1;
2299 2315
@@ -2311,24 +2327,24 @@ bnx2_phy_event_is_set(struct bnx2 *bp, u32 event)
2311} 2327}
2312 2328
2313static void 2329static void
2314bnx2_phy_int(struct bnx2 *bp) 2330bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2315{ 2331{
2316 if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_LINK_STATE)) { 2332 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) {
2317 spin_lock(&bp->phy_lock); 2333 spin_lock(&bp->phy_lock);
2318 bnx2_set_link(bp); 2334 bnx2_set_link(bp);
2319 spin_unlock(&bp->phy_lock); 2335 spin_unlock(&bp->phy_lock);
2320 } 2336 }
2321 if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_TIMER_ABORT)) 2337 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2322 bnx2_set_remote_link(bp); 2338 bnx2_set_remote_link(bp);
2323 2339
2324} 2340}
2325 2341
2326static inline u16 2342static inline u16
2327bnx2_get_hw_tx_cons(struct bnx2 *bp) 2343bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2328{ 2344{
2329 u16 cons; 2345 u16 cons;
2330 2346
2331 cons = bp->status_blk->status_tx_quick_consumer_index0; 2347 cons = bnapi->status_blk->status_tx_quick_consumer_index0;
2332 2348
2333 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT)) 2349 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2334 cons++; 2350 cons++;
@@ -2336,12 +2352,12 @@ bnx2_get_hw_tx_cons(struct bnx2 *bp)
2336} 2352}
2337 2353
2338static void 2354static void
2339bnx2_tx_int(struct bnx2 *bp) 2355bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2340{ 2356{
2341 u16 hw_cons, sw_cons, sw_ring_cons; 2357 u16 hw_cons, sw_cons, sw_ring_cons;
2342 int tx_free_bd = 0; 2358 int tx_free_bd = 0;
2343 2359
2344 hw_cons = bnx2_get_hw_tx_cons(bp); 2360 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2345 sw_cons = bp->tx_cons; 2361 sw_cons = bp->tx_cons;
2346 2362
2347 while (sw_cons != hw_cons) { 2363 while (sw_cons != hw_cons) {
@@ -2393,7 +2409,7 @@ bnx2_tx_int(struct bnx2 *bp)
2393 2409
2394 dev_kfree_skb(skb); 2410 dev_kfree_skb(skb);
2395 2411
2396 hw_cons = bnx2_get_hw_tx_cons(bp); 2412 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2397 } 2413 }
2398 2414
2399 bp->hw_tx_cons = hw_cons; 2415 bp->hw_tx_cons = hw_cons;
@@ -2584,9 +2600,9 @@ bnx2_rx_skb(struct bnx2 *bp, struct sk_buff *skb, unsigned int len,
2584} 2600}
2585 2601
2586static inline u16 2602static inline u16
2587bnx2_get_hw_rx_cons(struct bnx2 *bp) 2603bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2588{ 2604{
2589 u16 cons = bp->status_blk->status_rx_quick_consumer_index0; 2605 u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0;
2590 2606
2591 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)) 2607 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2592 cons++; 2608 cons++;
@@ -2594,13 +2610,13 @@ bnx2_get_hw_rx_cons(struct bnx2 *bp)
2594} 2610}
2595 2611
2596static int 2612static int
2597bnx2_rx_int(struct bnx2 *bp, int budget) 2613bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2598{ 2614{
2599 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; 2615 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2600 struct l2_fhdr *rx_hdr; 2616 struct l2_fhdr *rx_hdr;
2601 int rx_pkt = 0, pg_ring_used = 0; 2617 int rx_pkt = 0, pg_ring_used = 0;
2602 2618
2603 hw_cons = bnx2_get_hw_rx_cons(bp); 2619 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2604 sw_cons = bp->rx_cons; 2620 sw_cons = bp->rx_cons;
2605 sw_prod = bp->rx_prod; 2621 sw_prod = bp->rx_prod;
2606 2622
@@ -2717,7 +2733,7 @@ next_rx:
2717 2733
2718 /* Refresh hw_cons to see if there is new work */ 2734 /* Refresh hw_cons to see if there is new work */
2719 if (sw_cons == hw_cons) { 2735 if (sw_cons == hw_cons) {
2720 hw_cons = bnx2_get_hw_rx_cons(bp); 2736 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2721 rmb(); 2737 rmb();
2722 } 2738 }
2723 } 2739 }
@@ -2746,8 +2762,9 @@ bnx2_msi(int irq, void *dev_instance)
2746{ 2762{
2747 struct net_device *dev = dev_instance; 2763 struct net_device *dev = dev_instance;
2748 struct bnx2 *bp = netdev_priv(dev); 2764 struct bnx2 *bp = netdev_priv(dev);
2765 struct bnx2_napi *bnapi = &bp->bnx2_napi;
2749 2766
2750 prefetch(bp->status_blk); 2767 prefetch(bnapi->status_blk);
2751 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 2768 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2752 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 2769 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2753 BNX2_PCICFG_INT_ACK_CMD_MASK_INT); 2770 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
@@ -2756,7 +2773,7 @@ bnx2_msi(int irq, void *dev_instance)
2756 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 2773 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2757 return IRQ_HANDLED; 2774 return IRQ_HANDLED;
2758 2775
2759 netif_rx_schedule(dev, &bp->napi); 2776 netif_rx_schedule(dev, &bnapi->napi);
2760 2777
2761 return IRQ_HANDLED; 2778 return IRQ_HANDLED;
2762} 2779}
@@ -2766,14 +2783,15 @@ bnx2_msi_1shot(int irq, void *dev_instance)
2766{ 2783{
2767 struct net_device *dev = dev_instance; 2784 struct net_device *dev = dev_instance;
2768 struct bnx2 *bp = netdev_priv(dev); 2785 struct bnx2 *bp = netdev_priv(dev);
2786 struct bnx2_napi *bnapi = &bp->bnx2_napi;
2769 2787
2770 prefetch(bp->status_blk); 2788 prefetch(bnapi->status_blk);
2771 2789
2772 /* Return here if interrupt is disabled. */ 2790 /* Return here if interrupt is disabled. */
2773 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 2791 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2774 return IRQ_HANDLED; 2792 return IRQ_HANDLED;
2775 2793
2776 netif_rx_schedule(dev, &bp->napi); 2794 netif_rx_schedule(dev, &bnapi->napi);
2777 2795
2778 return IRQ_HANDLED; 2796 return IRQ_HANDLED;
2779} 2797}
@@ -2783,7 +2801,8 @@ bnx2_interrupt(int irq, void *dev_instance)
2783{ 2801{
2784 struct net_device *dev = dev_instance; 2802 struct net_device *dev = dev_instance;
2785 struct bnx2 *bp = netdev_priv(dev); 2803 struct bnx2 *bp = netdev_priv(dev);
2786 struct status_block *sblk = bp->status_blk; 2804 struct bnx2_napi *bnapi = &bp->bnx2_napi;
2805 struct status_block *sblk = bnapi->status_blk;
2787 2806
2788 /* When using INTx, it is possible for the interrupt to arrive 2807 /* When using INTx, it is possible for the interrupt to arrive
2789 * at the CPU before the status block posted prior to the 2808 * at the CPU before the status block posted prior to the
@@ -2791,7 +2810,7 @@ bnx2_interrupt(int irq, void *dev_instance)
2791 * When using MSI, the MSI message will always complete after 2810 * When using MSI, the MSI message will always complete after
2792 * the status block write. 2811 * the status block write.
2793 */ 2812 */
2794 if ((sblk->status_idx == bp->last_status_idx) && 2813 if ((sblk->status_idx == bnapi->last_status_idx) &&
2795 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) & 2814 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2796 BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) 2815 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2797 return IRQ_NONE; 2816 return IRQ_NONE;
@@ -2809,9 +2828,9 @@ bnx2_interrupt(int irq, void *dev_instance)
2809 if (unlikely(atomic_read(&bp->intr_sem) != 0)) 2828 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2810 return IRQ_HANDLED; 2829 return IRQ_HANDLED;
2811 2830
2812 if (netif_rx_schedule_prep(dev, &bp->napi)) { 2831 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
2813 bp->last_status_idx = sblk->status_idx; 2832 bnapi->last_status_idx = sblk->status_idx;
2814 __netif_rx_schedule(dev, &bp->napi); 2833 __netif_rx_schedule(dev, &bnapi->napi);
2815 } 2834 }
2816 2835
2817 return IRQ_HANDLED; 2836 return IRQ_HANDLED;
@@ -2821,12 +2840,13 @@ bnx2_interrupt(int irq, void *dev_instance)
2821 STATUS_ATTN_BITS_TIMER_ABORT) 2840 STATUS_ATTN_BITS_TIMER_ABORT)
2822 2841
2823static inline int 2842static inline int
2824bnx2_has_work(struct bnx2 *bp) 2843bnx2_has_work(struct bnx2_napi *bnapi)
2825{ 2844{
2845 struct bnx2 *bp = bnapi->bp;
2826 struct status_block *sblk = bp->status_blk; 2846 struct status_block *sblk = bp->status_blk;
2827 2847
2828 if ((bnx2_get_hw_rx_cons(bp) != bp->rx_cons) || 2848 if ((bnx2_get_hw_rx_cons(bnapi) != bp->rx_cons) ||
2829 (bnx2_get_hw_tx_cons(bp) != bp->hw_tx_cons)) 2849 (bnx2_get_hw_tx_cons(bnapi) != bp->hw_tx_cons))
2830 return 1; 2850 return 1;
2831 2851
2832 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) != 2852 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
@@ -2836,16 +2856,17 @@ bnx2_has_work(struct bnx2 *bp)
2836 return 0; 2856 return 0;
2837} 2857}
2838 2858
2839static int bnx2_poll_work(struct bnx2 *bp, int work_done, int budget) 2859static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
2860 int work_done, int budget)
2840{ 2861{
2841 struct status_block *sblk = bp->status_blk; 2862 struct status_block *sblk = bnapi->status_blk;
2842 u32 status_attn_bits = sblk->status_attn_bits; 2863 u32 status_attn_bits = sblk->status_attn_bits;
2843 u32 status_attn_bits_ack = sblk->status_attn_bits_ack; 2864 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
2844 2865
2845 if ((status_attn_bits & STATUS_ATTN_EVENTS) != 2866 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
2846 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) { 2867 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
2847 2868
2848 bnx2_phy_int(bp); 2869 bnx2_phy_int(bp, bnapi);
2849 2870
2850 /* This is needed to take care of transient status 2871 /* This is needed to take care of transient status
2851 * during link changes. 2872 * during link changes.
@@ -2855,49 +2876,50 @@ static int bnx2_poll_work(struct bnx2 *bp, int work_done, int budget)
2855 REG_RD(bp, BNX2_HC_COMMAND); 2876 REG_RD(bp, BNX2_HC_COMMAND);
2856 } 2877 }
2857 2878
2858 if (bnx2_get_hw_tx_cons(bp) != bp->hw_tx_cons) 2879 if (bnx2_get_hw_tx_cons(bnapi) != bp->hw_tx_cons)
2859 bnx2_tx_int(bp); 2880 bnx2_tx_int(bp, bnapi);
2860 2881
2861 if (bnx2_get_hw_rx_cons(bp) != bp->rx_cons) 2882 if (bnx2_get_hw_rx_cons(bnapi) != bp->rx_cons)
2862 work_done += bnx2_rx_int(bp, budget - work_done); 2883 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
2863 2884
2864 return work_done; 2885 return work_done;
2865} 2886}
2866 2887
2867static int bnx2_poll(struct napi_struct *napi, int budget) 2888static int bnx2_poll(struct napi_struct *napi, int budget)
2868{ 2889{
2869 struct bnx2 *bp = container_of(napi, struct bnx2, napi); 2890 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
2891 struct bnx2 *bp = bnapi->bp;
2870 int work_done = 0; 2892 int work_done = 0;
2871 struct status_block *sblk = bp->status_blk; 2893 struct status_block *sblk = bnapi->status_blk;
2872 2894
2873 while (1) { 2895 while (1) {
2874 work_done = bnx2_poll_work(bp, work_done, budget); 2896 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
2875 2897
2876 if (unlikely(work_done >= budget)) 2898 if (unlikely(work_done >= budget))
2877 break; 2899 break;
2878 2900
2879 /* bp->last_status_idx is used below to tell the hw how 2901 /* bnapi->last_status_idx is used below to tell the hw how
2880 * much work has been processed, so we must read it before 2902 * much work has been processed, so we must read it before
2881 * checking for more work. 2903 * checking for more work.
2882 */ 2904 */
2883 bp->last_status_idx = sblk->status_idx; 2905 bnapi->last_status_idx = sblk->status_idx;
2884 rmb(); 2906 rmb();
2885 if (likely(!bnx2_has_work(bp))) { 2907 if (likely(!bnx2_has_work(bnapi))) {
2886 netif_rx_complete(bp->dev, napi); 2908 netif_rx_complete(bp->dev, napi);
2887 if (likely(bp->flags & USING_MSI_FLAG)) { 2909 if (likely(bp->flags & USING_MSI_FLAG)) {
2888 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 2910 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2889 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 2911 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2890 bp->last_status_idx); 2912 bnapi->last_status_idx);
2891 break; 2913 break;
2892 } 2914 }
2893 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 2915 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2894 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 2916 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2895 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | 2917 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2896 bp->last_status_idx); 2918 bnapi->last_status_idx);
2897 2919
2898 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, 2920 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2899 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | 2921 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2900 bp->last_status_idx); 2922 bnapi->last_status_idx);
2901 break; 2923 break;
2902 } 2924 }
2903 } 2925 }
@@ -4247,7 +4269,7 @@ bnx2_init_chip(struct bnx2 *bp)
4247 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; 4269 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4248 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); 4270 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4249 4271
4250 bp->last_status_idx = 0; 4272 bp->bnx2_napi.last_status_idx = 0;
4251 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE; 4273 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4252 4274
4253 /* Set up how to generate a link change interrupt. */ 4275 /* Set up how to generate a link change interrupt. */
@@ -4887,6 +4909,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
4887 struct sw_bd *rx_buf; 4909 struct sw_bd *rx_buf;
4888 struct l2_fhdr *rx_hdr; 4910 struct l2_fhdr *rx_hdr;
4889 int ret = -ENODEV; 4911 int ret = -ENODEV;
4912 struct bnx2_napi *bnapi = &bp->bnx2_napi;
4890 4913
4891 if (loopback_mode == BNX2_MAC_LOOPBACK) { 4914 if (loopback_mode == BNX2_MAC_LOOPBACK) {
4892 bp->loopback = MAC_LOOPBACK; 4915 bp->loopback = MAC_LOOPBACK;
@@ -4921,7 +4944,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
4921 REG_RD(bp, BNX2_HC_COMMAND); 4944 REG_RD(bp, BNX2_HC_COMMAND);
4922 4945
4923 udelay(5); 4946 udelay(5);
4924 rx_start_idx = bnx2_get_hw_rx_cons(bp); 4947 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
4925 4948
4926 num_pkts = 0; 4949 num_pkts = 0;
4927 4950
@@ -4951,10 +4974,10 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
4951 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE); 4974 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
4952 dev_kfree_skb(skb); 4975 dev_kfree_skb(skb);
4953 4976
4954 if (bnx2_get_hw_tx_cons(bp) != bp->tx_prod) 4977 if (bnx2_get_hw_tx_cons(bnapi) != bp->tx_prod)
4955 goto loopback_test_done; 4978 goto loopback_test_done;
4956 4979
4957 rx_idx = bnx2_get_hw_rx_cons(bp); 4980 rx_idx = bnx2_get_hw_rx_cons(bnapi);
4958 if (rx_idx != rx_start_idx + num_pkts) { 4981 if (rx_idx != rx_start_idx + num_pkts) {
4959 goto loopback_test_done; 4982 goto loopback_test_done;
4960 } 4983 }
@@ -5295,11 +5318,11 @@ bnx2_open(struct net_device *dev)
5295 return rc; 5318 return rc;
5296 5319
5297 bnx2_setup_int_mode(bp, disable_msi); 5320 bnx2_setup_int_mode(bp, disable_msi);
5298 napi_enable(&bp->napi); 5321 bnx2_napi_enable(bp);
5299 rc = bnx2_request_irq(bp); 5322 rc = bnx2_request_irq(bp);
5300 5323
5301 if (rc) { 5324 if (rc) {
5302 napi_disable(&bp->napi); 5325 bnx2_napi_disable(bp);
5303 bnx2_free_mem(bp); 5326 bnx2_free_mem(bp);
5304 return rc; 5327 return rc;
5305 } 5328 }
@@ -5307,7 +5330,7 @@ bnx2_open(struct net_device *dev)
5307 rc = bnx2_init_nic(bp); 5330 rc = bnx2_init_nic(bp);
5308 5331
5309 if (rc) { 5332 if (rc) {
5310 napi_disable(&bp->napi); 5333 bnx2_napi_disable(bp);
5311 bnx2_free_irq(bp); 5334 bnx2_free_irq(bp);
5312 bnx2_free_skbs(bp); 5335 bnx2_free_skbs(bp);
5313 bnx2_free_mem(bp); 5336 bnx2_free_mem(bp);
@@ -5342,7 +5365,7 @@ bnx2_open(struct net_device *dev)
5342 rc = bnx2_request_irq(bp); 5365 rc = bnx2_request_irq(bp);
5343 5366
5344 if (rc) { 5367 if (rc) {
5345 napi_disable(&bp->napi); 5368 bnx2_napi_disable(bp);
5346 bnx2_free_skbs(bp); 5369 bnx2_free_skbs(bp);
5347 bnx2_free_mem(bp); 5370 bnx2_free_mem(bp);
5348 del_timer_sync(&bp->timer); 5371 del_timer_sync(&bp->timer);
@@ -5557,7 +5580,7 @@ bnx2_close(struct net_device *dev)
5557 msleep(1); 5580 msleep(1);
5558 5581
5559 bnx2_disable_int_sync(bp); 5582 bnx2_disable_int_sync(bp);
5560 napi_disable(&bp->napi); 5583 bnx2_napi_disable(bp);
5561 del_timer_sync(&bp->timer); 5584 del_timer_sync(&bp->timer);
5562 if (bp->flags & NO_WOL_FLAG) 5585 if (bp->flags & NO_WOL_FLAG)
5563 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN; 5586 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
@@ -7083,6 +7106,15 @@ bnx2_bus_string(struct bnx2 *bp, char *str)
7083} 7106}
7084 7107
7085static int __devinit 7108static int __devinit
7109bnx2_init_napi(struct bnx2 *bp)
7110{
7111 struct bnx2_napi *bnapi = &bp->bnx2_napi;
7112
7113 bnapi->bp = bp;
7114 netif_napi_add(bp->dev, &bnapi->napi, bnx2_poll, 64);
7115}
7116
7117static int __devinit
7086bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 7118bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7087{ 7119{
7088 static int version_printed = 0; 7120 static int version_printed = 0;
@@ -7123,7 +7155,7 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7123 dev->ethtool_ops = &bnx2_ethtool_ops; 7155 dev->ethtool_ops = &bnx2_ethtool_ops;
7124 7156
7125 bp = netdev_priv(dev); 7157 bp = netdev_priv(dev);
7126 netif_napi_add(dev, &bp->napi, bnx2_poll, 64); 7158 bnx2_init_napi(bp);
7127 7159
7128#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) 7160#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7129 dev->poll_controller = poll_bnx2; 7161 dev->poll_controller = poll_bnx2;
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index 1accf0093126..345b6db9a947 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -6503,6 +6503,14 @@ struct bnx2_irq {
6503 char name[16]; 6503 char name[16];
6504}; 6504};
6505 6505
6506struct bnx2_napi {
6507 struct napi_struct napi ____cacheline_aligned;
6508 struct bnx2 *bp;
6509 struct status_block *status_blk;
6510 u32 last_status_idx;
6511 u32 int_num;
6512};
6513
6506struct bnx2 { 6514struct bnx2 {
6507 /* Fields used in the tx and intr/napi performance paths are grouped */ 6515 /* Fields used in the tx and intr/napi performance paths are grouped */
6508 /* together in the beginning of the structure. */ 6516 /* together in the beginning of the structure. */
@@ -6511,13 +6519,8 @@ struct bnx2 {
6511 struct net_device *dev; 6519 struct net_device *dev;
6512 struct pci_dev *pdev; 6520 struct pci_dev *pdev;
6513 6521
6514 struct napi_struct napi;
6515
6516 atomic_t intr_sem; 6522 atomic_t intr_sem;
6517 6523
6518 struct status_block *status_blk;
6519 u32 last_status_idx;
6520
6521 u32 flags; 6524 u32 flags;
6522#define PCIX_FLAG 0x00000001 6525#define PCIX_FLAG 0x00000001
6523#define PCI_32BIT_FLAG 0x00000002 6526#define PCI_32BIT_FLAG 0x00000002
@@ -6539,6 +6542,8 @@ struct bnx2 {
6539 u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES))); 6542 u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
6540 u16 hw_tx_cons; 6543 u16 hw_tx_cons;
6541 6544
6545 struct bnx2_napi bnx2_napi;
6546
6542#ifdef BCM_VLAN 6547#ifdef BCM_VLAN
6543 struct vlan_group *vlgrp; 6548 struct vlan_group *vlgrp;
6544#endif 6549#endif
@@ -6672,6 +6677,7 @@ struct bnx2 {
6672 6677
6673 u32 stats_ticks; 6678 u32 stats_ticks;
6674 6679
6680 struct status_block *status_blk;
6675 dma_addr_t status_blk_mapping; 6681 dma_addr_t status_blk_mapping;
6676 6682
6677 struct statistics_block *stats_blk; 6683 struct statistics_block *stats_blk;
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-16 23:26:42 -0400
d='n4844' href='#n4844'>4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 
/* $Id: serial.c,v 1.25 2004/09/29 10:33:49 starvik Exp $
 *
 * Serial port driver for the ETRAX 100LX chip
 *
 *    Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003  Axis Communications AB
 *
 *    Many, many authors. Based once upon a time on serial.c for 16x50.
 *
 * $Log: serial.c,v $
 * Revision 1.25  2004/09/29 10:33:49  starvik
 * Resolved a dealock when printing debug from kernel.
 *
 * Revision 1.24  2004/08/27 23:25:59  johana
 * rs_set_termios() must call change_speed() if c_iflag has changed or
 * automatic XOFF handling will be enabled and transmitter will stop
 * if 0x13 is received.
 *
 * Revision 1.23  2004/08/24 06:57:13  starvik
 * More whitespace cleanup
 *
 * Revision 1.22  2004/08/24 06:12:20  starvik
 * Whitespace cleanup
 *
 * Revision 1.20  2004/05/24 12:00:20  starvik
 * Big merge of stuff from Linux 2.4 (e.g. manual mode for the serial port).
 *
 * Revision 1.19  2004/05/17 13:12:15  starvik
 * Kernel console hook
 * Big merge from Linux 2.4 still pending.
 *
 * Revision 1.18  2003/10/28 07:18:30  starvik
 * Compiles with debug info
 *
 * Revision 1.17  2003/07/04 08:27:37  starvik
 * Merge of Linux 2.5.74
 *
 * Revision 1.16  2003/06/13 10:05:19  johana
 * Help the user to avoid trouble by:
 * Forcing mixed mode for status/control lines if not all pins are used.
 *
 * Revision 1.15  2003/06/13 09:43:01  johana
 * Merged in the following changes from os/linux/arch/cris/drivers/serial.c
 * + some minor changes to reduce diff.
 *
 * Revision 1.49  2003/05/30 11:31:54  johana
 * Merged in change-branch--serial9bit that adds CMSPAR support for sticky
 * parity (mark/space)
 *
 * Revision 1.48  2003/05/30 11:03:57  johana
 * Implemented rs_send_xchar() by disabling the DMA and writing manually.
 * Added e100_disable_txdma_channel() and e100_enable_txdma_channel().
 * Fixed rs_throttle() and rs_unthrottle() to properly call rs_send_xchar
 * instead of setting info->x_char and check the CRTSCTS flag before
 * controlling the rts pin.
 *
 * Revision 1.14  2003/04/09 08:12:44  pkj
 * Corrected typo changes made upstream.
 *
 * Revision 1.13  2003/04/09 05:20:47  starvik
 * Merge of Linux 2.5.67
 *
 * Revision 1.11  2003/01/22 06:48:37  starvik
 * Fixed warnings issued by GCC 3.2.1
 *
 * Revision 1.9  2002/12/13 09:07:47  starvik
 * Alert user that RX_TIMEOUT_TICKS==0 doesn't work
 *
 * Revision 1.8  2002/12/11 13:13:57  starvik
 * Added arch/ to v10 specific includes
 * Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
 *
 * Revision 1.7  2002/12/06 07:13:57  starvik
 * Corrected work queue stuff
 * Removed CONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST
 *
 * Revision 1.6  2002/11/21 07:17:46  starvik
 * Change static inline to extern inline where otherwise outlined with gcc-3.2
 *
 * Revision 1.5  2002/11/14 15:59:49  starvik
 * Linux 2.5 port of the latest serial driver from 2.4. The work queue stuff
 * probably doesn't work yet.
 *
 * Revision 1.42  2002/11/05 09:08:47  johana
 * Better implementation of rs_stop() and rs_start() that uses the XOFF
 * register to start/stop transmission.
 * change_speed() also initilises XOFF register correctly so that
 * auto_xoff is enabled when IXON flag is set by user.
 * This gives fast XOFF response times.
 *
 * Revision 1.41  2002/11/04 18:40:57  johana
 * Implemented rs_stop() and rs_start().
 * Simple tests using hwtestserial indicates that this should be enough
 * to make it work.
 *
 * Revision 1.40  2002/10/14 05:33:18  starvik
 * RS-485 uses fast timers even if SERIAL_FAST_TIMER is disabled
 *
 * Revision 1.39  2002/09/30 21:00:57  johana
 * Support for CONFIG_ETRAX_SERx_DTR_RI_DSR_CD_MIXED where the status and
 * control pins can be mixed between PA and PB.
 * If no serial port uses MIXED old solution is used
 * (saves a few bytes and cycles).
 * control_pins struct uses masks instead of bit numbers.
 * Corrected dummy values and polarity in line_info() so
 * /proc/tty/driver/serial is now correct.
 * (the E100_xxx_GET() macros is really active low - perhaps not obvious)
 *
 * Revision 1.38  2002/08/23 11:01:36  starvik
 * Check that serial port is enabled in all interrupt handlers to avoid
 * restarts of DMA channels not assigned to serial ports
 *
 * Revision 1.37  2002/08/13 13:02:37  bjornw
 * Removed some warnings because of unused code
 *
 * Revision 1.36  2002/08/08 12:50:01  starvik
 * Serial interrupt is shared with synchronous serial port driver
 *
 * Revision 1.35  2002/06/03 10:40:49  starvik
 * Increased RS-485 RTS toggle timer to 2 characters
 *
 * Revision 1.34  2002/05/28 18:59:36  johana
 * Whitespace and comment fixing to be more like etrax100ser.c 1.71.
 *
 * Revision 1.33  2002/05/28 17:55:43  johana
 * RS-485 uses FAST_TIMER if enabled, and starts a short (one char time)
 * timer from tranismit_chars (interrupt context).
 * The timer toggles RTS in interrupt context when expired giving minimum
 * latencies.
 *
 * Revision 1.32  2002/05/22 13:58:00  johana
 * Renamed rs_write() to raw_write() and made it inline.
 * New rs_write() handles RS-485 if configured and enabled
 * (moved code from e100_write_rs485()).
 * RS-485 ioctl's uses copy_from_user() instead of verify_area().
 *
 * Revision 1.31  2002/04/22 11:20:03  johana
 * Updated copyright years.
 *
 * Revision 1.30  2002/04/22 09:39:12  johana
 * RS-485 support compiles.
 *
 * Revision 1.29  2002/01/14 16:10:01  pkj
 * Allocate the receive buffers dynamically. The static 4kB buffer was
 * too small for the peaks. This means that we can get rid of the extra
 * buffer and the copying to it. It also means we require less memory
 * under normal operations, but can use more when needed (there is a
 * cap at 64kB for safety reasons). If there is no memory available
 * we panic(), and die a horrible death...
 *
 * Revision 1.28  2001/12/18 15:04:53  johana
 * Cleaned up write_rs485() - now it works correctly without padding extra
 * char.
 * Added sane default initialisation of rs485.
 * Added #ifdef around dummy variables.
 *
 * Revision 1.27  2001/11/29 17:00:41  pkj
 * 2kB seems to be too small a buffer when using 921600 bps,
 * so increase it to 4kB (this was already done for the elinux
 * version of the serial driver).
 *
 * Revision 1.26  2001/11/19 14:20:41  pkj
 * Minor changes to comments and unused code.
 *
 * Revision 1.25  2001/11/12 20:03:43  pkj
 * Fixed compiler warnings.
 *
 * Revision 1.24  2001/11/12 15:10:05  pkj
 * Total redesign of the receiving part of the serial driver.
 * Uses eight chained descriptors to write to a 4kB buffer.
 * This data is then serialised into a 2kB buffer. From there it
 * is copied into the TTY's flip buffers when they become available.
 * A lot of copying, and the sizes of the buffers might need to be
 * tweaked, but all in all it should work better than the previous
 * version, without the need to modify the TTY code in any way.
 * Also note that erroneous bytes are now correctly marked in the
 * flag buffers (instead of always marking the first byte).
 *
 * Revision 1.23  2001/10/30 17:53:26  pkj
 * * Set info->uses_dma to 0 when a port is closed.
 * * Mark the timer1 interrupt as a fast one (SA_INTERRUPT).
 * * Call start_flush_timer() in start_receive() if
 *   CONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST is defined.
 *
 * Revision 1.22  2001/10/30 17:44:03  pkj
 * Use %lu for received and transmitted counters in line_info().
 *
 * Revision 1.21  2001/10/30 17:40:34  pkj
 * Clean-up. The only change to functionality is that
 * CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS(=5) is used instead of
 * MAX_FLUSH_TIME(=8).
 *
 * Revision 1.20  2001/10/30 15:24:49  johana
 * Added char_time stuff from 2.0 driver.
 *
 * Revision 1.19  2001/10/30 15:23:03  johana
 * Merged with 1.13.2 branch + fixed indentation
 * and changed CONFIG_ETRAX100_XYS to CONFIG_ETRAX_XYZ
 *
 * Revision 1.18  2001/09/24 09:27:22  pkj
 * Completed ext_baud_table[] in cflag_to_baud() and cflag_to_etrax_baud().
 *
 * Revision 1.17  2001/08/24 11:32:49  ronny
 * More fixes for the CONFIG_ETRAX_SERIAL_PORT0 define.
 *
 * Revision 1.16  2001/08/24 07:56:22  ronny
 * Added config ifdefs around ser0 irq requests.
 *
 * Revision 1.15  2001/08/16 09:10:31  bjarne
 * serial.c - corrected the initialization of rs_table, the wrong defines
 *            where used.
 *            Corrected a test in timed_flush_handler.
 *            Changed configured to enabled.
 * serial.h - Changed configured to enabled.
 *
 * Revision 1.14  2001/08/15 07:31:23  bjarne
 * Introduced two new members to the e100_serial struct.
 * configured - Will be set to 1 if the port has been configured in .config
 * uses_dma   - Should be set to 1 if the port uses DMA. Currently it is set
 *              to 1
 *              when a port is opened. This is used to limit the DMA interrupt
 *              routines to only manipulate DMA channels actually used by the
 *              serial driver.
 *
 * Revision 1.13.2.2  2001/10/17 13:57:13  starvik
 * Receiver was broken by the break fixes
 *
 * Revision 1.13.2.1  2001/07/20 13:57:39  ronny
 * Merge with new stuff from etrax100ser.c. Works but haven't checked stuff
 * like break handling.
 *
 * Revision 1.13  2001/05/09 12:40:31  johana
 * Use DMA_NBR and IRQ_NBR defines from dma.h and irq.h
 *
 * Revision 1.12  2001/04/19 12:23:07  bjornw
 * CONFIG_RS485 -> CONFIG_ETRAX_RS485
 *
 * Revision 1.11  2001/04/05 14:29:48  markusl
 * Updated according to review remarks i.e.
 * -Use correct types in port structure to avoid compiler warnings
 * -Try to use IO_* macros whenever possible
 * -Open should never return -EBUSY
 *
 * Revision 1.10  2001/03/05 13:14:07  bjornw
 * Another spelling fix
 *
 * Revision 1.9  2001/02/23 13:46:38  bjornw
 * Spellling check
 *
 * Revision 1.8  2001/01/23 14:56:35  markusl
 * Made use of ser1 optional
 * Needed by USB
 *
 * Revision 1.7  2001/01/19 16:14:48  perf
 * Added kernel options for serial ports 234.
 * Changed option names from CONFIG_ETRAX100_XYZ to CONFIG_ETRAX_XYZ.
 *
 * Revision 1.6  2000/11/22 16:36:09  bjornw
 * Please marketing by using the correct case when spelling Etrax.
 *
 * Revision 1.5  2000/11/21 16:43:37  bjornw
 * Fixed so it compiles under CONFIG_SVINTO_SIM
 *
 * Revision 1.4  2000/11/15 17:34:12  bjornw
 * Added a timeout timer for flushing input channels. The interrupt-based
 * fast flush system should be easy to merge with this later (works the same
 * way, only with an irq instead of a system timer_list)
 *
 * Revision 1.3  2000/11/13 17:19:57  bjornw
 * * Incredibly, this almost complete rewrite of serial.c worked (at least
 *   for output) the first time.
 *
 *   Items worth noticing:
 *
 *      No Etrax100 port 1 workarounds (does only compile on 2.4 anyway now)
 *      RS485 is not ported (why can't it be done in userspace as on x86 ?)
 *      Statistics done through async_icount - if any more stats are needed,
 *      that's the place to put them or in an arch-dep version of it.
 *      timeout_interrupt and the other fast timeout stuff not ported yet
 *      There be dragons in this 3k+ line driver
 *
 * Revision 1.2  2000/11/10 16:50:28  bjornw
 * First shot at a 2.4 port, does not compile totally yet
 *
 * Revision 1.1  2000/11/10 16:47:32  bjornw
 * Added verbatim copy of rev 1.49 etrax100ser.c from elinux
 *
 * Revision 1.49  2000/10/30 15:47:14  tobiasa
 * Changed version number.
 *
 * Revision 1.48  2000/10/25 11:02:43  johana
 * Changed %ul to %lu in printf's
 *
 * Revision 1.47  2000/10/18 15:06:53  pkj
 * Compile correctly with CONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST and
 * CONFIG_ETRAX_SERIAL_PROC_ENTRY together.
 * Some clean-up of the /proc/serial file.
 *
 * Revision 1.46  2000/10/16 12:59:40  johana
 * Added CONFIG_ETRAX_SERIAL_PROC_ENTRY for statistics and debug info.
 *
 * Revision 1.45  2000/10/13 17:10:59  pkj
 * Do not flush DMAs while flipping TTY buffers.
 *
 * Revision 1.44  2000/10/13 16:34:29  pkj
 * Added a delay in ser_interrupt() for 2.3ms when an error is detected.
 * We do not know why this delay is required yet, but without it the
 * irmaflash program does not work (this was the program that needed
 * the ser_interrupt() to be needed in the first place). This should not
 * affect normal use of the serial ports.
 *
 * Revision 1.43  2000/10/13 16:30:44  pkj
 * New version of the fast flush of serial buffers code. This time
 * it is localized to the serial driver and uses a fast timer to
 * do the work.
 *
 * Revision 1.42  2000/10/13 14:54:26  bennyo
 * Fix for switching RTS when using rs485
 *
 * Revision 1.41  2000/10/12 11:43:44  pkj
 * Cleaned up a number of comments.
 *
 * Revision 1.40  2000/10/10 11:58:39  johana
 * Made RS485 support generic for all ports.
 * Toggle rts in interrupt if no delay wanted.
 * WARNING: No true transmitter empty check??
 * Set d_wait bit when sending data so interrupt is delayed until
 * fifo flushed. (Fix tcdrain() problem)
 *
 * Revision 1.39  2000/10/04 16:08:02  bjornw
 * * Use virt_to_phys etc. for DMA addresses
 * * Removed CONFIG_FLUSH_DMA_FAST hacks
 * * Indentation fix
 *
 * Revision 1.38  2000/10/02 12:27:10  mattias
 * * added variable used when using fast flush on serial dma.
 *   (CONFIG_FLUSH_DMA_FAST)
 *
 * Revision 1.37  2000/09/27 09:44:24  pkj
 * Uncomment definition of SERIAL_HANDLE_EARLY_ERRORS.
 *
 * Revision 1.36  2000/09/20 13:12:52  johana
 * Support for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS:
 *   Number of timer ticks between flush of receive fifo (1 tick = 10ms).
 *   Try 0-3 for low latency applications. Approx 5 for high load
 *   applications (e.g. PPP). Maybe this should be more adaptive some day...
 *
 * Revision 1.35  2000/09/20 10:36:08  johana
 * Typo in get_lsr_info()
 *
 * Revision 1.34  2000/09/20 10:29:59  johana
 * Let rs_chars_in_buffer() check fifo content as well.
 * get_lsr_info() might work now (not tested).
 * Easier to change the port to debug.
 *
 * Revision 1.33  2000/09/13 07:52:11  torbjore
 * Support RS485
 *
 * Revision 1.32  2000/08/31 14:45:37  bjornw
 * After sending a break we need to reset the transmit DMA channel
 *
 * Revision 1.31  2000/06/21 12:13:29  johana
 * Fixed wait for all chars sent when closing port.
 * (Used to always take 1 second!)
 * Added shadows for directions of status/ctrl signals.
 *
 * Revision 1.30  2000/05/29 16:27:55  bjornw
 * Simulator ifdef moved a bit
 *
 * Revision 1.29  2000/05/09 09:40:30  mattias
 * * Added description of dma registers used in timeout_interrupt
 * * Removed old code
 *
 * Revision 1.28  2000/05/08 16:38:58  mattias
 * * Bugfix for flushing fifo in timeout_interrupt
 *   Problem occurs when bluetooth stack waits for a small number of bytes
 *   containing an event acknowledging free buffers in bluetooth HW
 *   As before, data was stuck in fifo until more data came on uart and
 *   flushed it up to the stack.
 *
 * Revision 1.27  2000/05/02 09:52:28  jonasd
 * Added fix for peculiar etrax behaviour when eop is forced on an empty
 * fifo. This is used when flashing the IRMA chip. Disabled by default.
 *
 * Revision 1.26  2000/03/29 15:32:02  bjornw
 * 2.0.34 updates
 *
 * Revision 1.25  2000/02/16 16:59:36  bjornw
 * * Receive DMA directly into the flip-buffer, eliminating an intermediary
 *   receive buffer and a memcpy. Will avoid some overruns.
 * * Error message on debug port if an overrun or flip buffer overrun occurs.
 * * Just use the first byte in the flag flip buffer for errors.
 * * Check for timeout on the serial ports only each 5/100 s, not 1/100.
 *
 * Revision 1.24  2000/02/09 18:02:28  bjornw
 * * Clear serial errors (overrun, framing, parity) correctly. Before, the
 *   receiver would get stuck if an error occurred and we did not restart
 *   the input DMA.
 * * Cosmetics (indentation, some code made into inlines)
 * * Some more debug options
 * * Actually shut down the serial port (DMA irq, DMA reset, receiver stop)
 *   when the last open is closed. Corresponding fixes in startup().
 * * rs_close() "tx FIFO wait" code moved into right place, bug & -> && fixed
 *   and make a special case out of port 1 (R_DMA_CHx_STATUS is broken for that)
 * * e100_disable_rx/enable_rx just disables/enables the receiver, not RTS
 *
 * Revision 1.23  2000/01/24 17:46:19  johana
 * Wait for flush of DMA/FIFO when closing port.
 *
 * Revision 1.22  2000/01/20 18:10:23  johana
 * Added TIOCMGET ioctl to return modem status.
 * Implemented modem status/control that works with the extra signals
 * (DTR, DSR, RI,CD) as well.
 * 3 different modes supported:
 * ser0 on PB (Bundy), ser1 on PB (Lisa) and ser2 on PA (Bundy)
 * Fixed DEF_TX value that caused the serial transmitter pin (txd) to go to 0 when
 * closing the last filehandle, NASTY!.
 * Added break generation, not tested though!
 * Use SA_SHIRQ when request_irq() for ser2 and ser3 (shared with) par0 and par1.
 * You can't use them at the same time (yet..), but you can hopefully switch
 * between ser2/par0, ser3/par1 with the same kernel config.
 * Replaced some magic constants with defines
 *
 *
 */

static char *serial_version = "$Revision: 1.25 $";

#include <linux/config.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/fcntl.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <asm/uaccess.h>
#include <linux/kernel.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/segment.h>
#include <asm/bitops.h>
#include <linux/delay.h>

#include <asm/arch/svinto.h>

/* non-arch dependent serial structures are in linux/serial.h */
#include <linux/serial.h>
/* while we keep our own stuff (struct e100_serial) in a local .h file */
#include "serial.h"
#include <asm/fasttimer.h>

#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
#ifndef CONFIG_ETRAX_FAST_TIMER
#error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
#endif
#endif

#if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
           (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
#error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
#endif

#if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
#error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
#endif

/*
 * All of the compatibilty code so we can compile serial.c against
 * older kernels is hidden in serial_compat.h
 */
#if defined(LOCAL_HEADERS)
#include "serial_compat.h"
#endif

#define _INLINE_ inline

struct tty_driver *serial_driver;

/* serial subtype definitions */
#ifndef SERIAL_TYPE_NORMAL
#define SERIAL_TYPE_NORMAL	1
#endif

/* number of characters left in xmit buffer before we ask for more */
#define WAKEUP_CHARS 256

//#define SERIAL_DEBUG_INTR
//#define SERIAL_DEBUG_OPEN
//#define SERIAL_DEBUG_FLOW
//#define SERIAL_DEBUG_DATA
//#define SERIAL_DEBUG_THROTTLE
//#define SERIAL_DEBUG_IO  /* Debug for Extra control and status pins */
//#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */

/* Enable this to use serial interrupts to handle when you
   expect the first received event on the serial port to
   be an error, break or similar. Used to be able to flash IRMA
   from eLinux */
#define SERIAL_HANDLE_EARLY_ERRORS

/* Defined and used in n_tty.c, but we need it here as well */
#define TTY_THRESHOLD_THROTTLE 128

/* Due to buffersizes and threshold values, our SERIAL_DESCR_BUF_SIZE
 * must not be to high or flow control won't work if we leave it to the tty
 * layer so we have our own throttling in flush_to_flip
 * TTY_FLIPBUF_SIZE=512,
 * TTY_THRESHOLD_THROTTLE/UNTHROTTLE=128
 * BUF_SIZE can't be > 128
 */
/* Currently 16 descriptors x 128 bytes = 2048 bytes */
#define SERIAL_DESCR_BUF_SIZE 256

#define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
#define DEF_BAUD_BASE SERIAL_PRESCALE_BASE

/* We don't want to load the system with massive fast timer interrupt
 * on high baudrates so limit it to 250 us (4kHz) */
#define MIN_FLUSH_TIME_USEC 250

/* Add an x here to log a lot of timer stuff */
#define TIMERD(x)
/* Debug details of interrupt handling */
#define DINTR1(x)  /* irq on/off, errors */
#define DINTR2(x)    /* tx and rx */
/* Debug flip buffer stuff */
#define DFLIP(x)
/* Debug flow control and overview of data flow */
#define DFLOW(x)
#define DBAUD(x)
#define DLOG_INT_TRIG(x)

//#define DEBUG_LOG_INCLUDED
#ifndef DEBUG_LOG_INCLUDED
#define DEBUG_LOG(line, string, value)
#else
struct debug_log_info
{
	unsigned long time;
	unsigned long timer_data;
//  int line;
	const char *string;
	int value;
};
#define DEBUG_LOG_SIZE 4096

struct debug_log_info debug_log[DEBUG_LOG_SIZE];
int debug_log_pos = 0;

#define DEBUG_LOG(_line, _string, _value) do { \
  if ((_line) == SERIAL_DEBUG_LINE) {\
    debug_log_func(_line, _string, _value); \
  }\
}while(0)

void debug_log_func(int line, const char *string, int value)
{
	if (debug_log_pos < DEBUG_LOG_SIZE) {
		debug_log[debug_log_pos].time = jiffies;
		debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
//    debug_log[debug_log_pos].line = line;
		debug_log[debug_log_pos].string = string;
		debug_log[debug_log_pos].value = value;
		debug_log_pos++;
	}
	/*printk(string, value);*/
}
#endif

#ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
/* Default number of timer ticks before flushing rx fifo
 * When using "little data, low latency applications: use 0
 * When using "much data applications (PPP)" use ~5
 */
#define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
#endif

unsigned long timer_data_to_ns(unsigned long timer_data);

static void change_speed(struct e100_serial *info);
static void rs_throttle(struct tty_struct * tty);
static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
static int rs_write(struct tty_struct * tty, int from_user,
                    const unsigned char *buf, int count);
extern _INLINE_ int rs_raw_write(struct tty_struct * tty, int from_user,
                            const unsigned char *buf, int count);
#ifdef CONFIG_ETRAX_RS485
static int e100_write_rs485(struct tty_struct * tty, int from_user,
                            const unsigned char *buf, int count);
#endif
static int get_lsr_info(struct e100_serial * info, unsigned int *value);


#define DEF_BAUD 115200   /* 115.2 kbit/s */
#define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
#define DEF_RX 0x20  /* or SERIAL_CTRL_W >> 8 */
/* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
#define DEF_TX 0x80  /* or SERIAL_CTRL_B */

/* offsets from R_SERIALx_CTRL */

#define REG_DATA 0
#define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
#define REG_TR_DATA 0
#define REG_STATUS 1
#define REG_TR_CTRL 1
#define REG_REC_CTRL 2
#define REG_BAUD 3
#define REG_XOFF 4  /* this is a 32 bit register */

/* The bitfields are the same for all serial ports */
#define SER_RXD_MASK         IO_MASK(R_SERIAL0_STATUS, rxd)
#define SER_DATA_AVAIL_MASK  IO_MASK(R_SERIAL0_STATUS, data_avail)
#define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
#define SER_PAR_ERR_MASK     IO_MASK(R_SERIAL0_STATUS, par_err)
#define SER_OVERRUN_MASK     IO_MASK(R_SERIAL0_STATUS, overrun)

#define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)

/* Values for info->errorcode */
#define ERRCODE_SET_BREAK    (TTY_BREAK)
#define ERRCODE_INSERT        0x100
#define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)

#define FORCE_EOP(info)  *R_SET_EOP = 1U << info->iseteop;

/*
 * General note regarding the use of IO_* macros in this file:
 *
 * We will use the bits defined for DMA channel 6 when using various
 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
 * the same for all channels (which of course they are).
 *
 * We will also use the bits defined for serial port 0 when writing commands
 * to the different ports, as these bits too are the same for all ports.
 */


/* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
static const unsigned long e100_ser_int_mask = 0
#ifdef CONFIG_ETRAX_SERIAL_PORT0
| IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT1
| IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT2
| IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT3
| IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
#endif
;
unsigned long r_alt_ser_baudrate_shadow = 0;

/* this is the data for the four serial ports in the etrax100 */
/*  DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
/* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */

static struct e100_serial rs_table[] = {
	{ .baud        = DEF_BAUD,
	  .port        = (unsigned char *)R_SERIAL0_CTRL,
	  .irq         = 1U << 12, /* uses DMA 6 and 7 */
	  .oclrintradr = R_DMA_CH6_CLR_INTR,
	  .ofirstadr   = R_DMA_CH6_FIRST,
	  .ocmdadr     = R_DMA_CH6_CMD,
	  .ostatusadr  = R_DMA_CH6_STATUS,
	  .iclrintradr = R_DMA_CH7_CLR_INTR,
	  .ifirstadr   = R_DMA_CH7_FIRST,
	  .icmdadr     = R_DMA_CH7_CMD,
	  .idescradr   = R_DMA_CH7_DESCR,
	  .flags       = STD_FLAGS,
	  .rx_ctrl     = DEF_RX,
	  .tx_ctrl     = DEF_TX,
	  .iseteop     = 2,
#ifdef CONFIG_ETRAX_SERIAL_PORT0
          .enabled  = 1,
#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
	  .dma_out_enabled = 1,
#else
	  .dma_out_enabled = 0,
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
	  .dma_in_enabled = 1,
#else
	  .dma_in_enabled = 0
#endif
#else
          .enabled  = 0,
	  .dma_out_enabled = 0,
	  .dma_in_enabled = 0
#endif

},  /* ttyS0 */
#ifndef CONFIG_SVINTO_SIM
	{ .baud        = DEF_BAUD,
	  .port        = (unsigned char *)R_SERIAL1_CTRL,
	  .irq         = 1U << 16, /* uses DMA 8 and 9 */
	  .oclrintradr = R_DMA_CH8_CLR_INTR,
	  .ofirstadr   = R_DMA_CH8_FIRST,
	  .ocmdadr     = R_DMA_CH8_CMD,
	  .ostatusadr  = R_DMA_CH8_STATUS,
	  .iclrintradr = R_DMA_CH9_CLR_INTR,
	  .ifirstadr   = R_DMA_CH9_FIRST,
	  .icmdadr     = R_DMA_CH9_CMD,
	  .idescradr   = R_DMA_CH9_DESCR,
	  .flags       = STD_FLAGS,
	  .rx_ctrl     = DEF_RX,
	  .tx_ctrl     = DEF_TX,
	  .iseteop     = 3,
#ifdef CONFIG_ETRAX_SERIAL_PORT1
          .enabled  = 1,
#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
	  .dma_out_enabled = 1,
#else
	  .dma_out_enabled = 0,
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
	  .dma_in_enabled = 1,
#else
	  .dma_in_enabled = 0
#endif
#else
          .enabled  = 0,
	  .dma_out_enabled = 0,
	  .dma_in_enabled = 0
#endif
},  /* ttyS1 */

	{ .baud        = DEF_BAUD,
	  .port        = (unsigned char *)R_SERIAL2_CTRL,
	  .irq         = 1U << 4,  /* uses DMA 2 and 3 */
	  .oclrintradr = R_DMA_CH2_CLR_INTR,
	  .ofirstadr   = R_DMA_CH2_FIRST,
	  .ocmdadr     = R_DMA_CH2_CMD,
	  .ostatusadr  = R_DMA_CH2_STATUS,
	  .iclrintradr = R_DMA_CH3_CLR_INTR,
	  .ifirstadr   = R_DMA_CH3_FIRST,
	  .icmdadr     = R_DMA_CH3_CMD,
	  .idescradr   = R_DMA_CH3_DESCR,
	  .flags       = STD_FLAGS,
	  .rx_ctrl     = DEF_RX,
	  .tx_ctrl     = DEF_TX,
	  .iseteop     = 0,
#ifdef CONFIG_ETRAX_SERIAL_PORT2
          .enabled  = 1,
#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
	  .dma_out_enabled = 1,
#else
	  .dma_out_enabled = 0,
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
	  .dma_in_enabled = 1,
#else
	  .dma_in_enabled = 0
#endif
#else
          .enabled  = 0,
	  .dma_out_enabled = 0,
	  .dma_in_enabled = 0
#endif
 },  /* ttyS2 */

	{ .baud        = DEF_BAUD,
	  .port        = (unsigned char *)R_SERIAL3_CTRL,
	  .irq         = 1U << 8,  /* uses DMA 4 and 5 */
	  .oclrintradr = R_DMA_CH4_CLR_INTR,
	  .ofirstadr   = R_DMA_CH4_FIRST,
	  .ocmdadr     = R_DMA_CH4_CMD,
	  .ostatusadr  = R_DMA_CH4_STATUS,
	  .iclrintradr = R_DMA_CH5_CLR_INTR,
	  .ifirstadr   = R_DMA_CH5_FIRST,
	  .icmdadr     = R_DMA_CH5_CMD,
	  .idescradr   = R_DMA_CH5_DESCR,
	  .flags       = STD_FLAGS,
	  .rx_ctrl     = DEF_RX,
	  .tx_ctrl     = DEF_TX,
	  .iseteop     = 1,
#ifdef CONFIG_ETRAX_SERIAL_PORT3
          .enabled  = 1,
#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
	  .dma_out_enabled = 1,
#else
	  .dma_out_enabled = 0,
#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
	  .dma_in_enabled = 1,
#else
	  .dma_in_enabled = 0
#endif
#else
          .enabled  = 0,
	  .dma_out_enabled = 0,
	  .dma_in_enabled = 0
#endif
 }   /* ttyS3 */
#endif
};


#define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))

static struct termios *serial_termios[NR_PORTS];
static struct termios *serial_termios_locked[NR_PORTS];
#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
static struct fast_timer fast_timers[NR_PORTS];
#endif

#ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
#define PROCSTAT(x) x
struct ser_statistics_type {
	int overrun_cnt;
	int early_errors_cnt;
	int ser_ints_ok_cnt;
	int errors_cnt;
	unsigned long int processing_flip;
	unsigned long processing_flip_still_room;
	unsigned long int timeout_flush_cnt;
	int rx_dma_ints;
	int tx_dma_ints;
	int rx_tot;
	int tx_tot;
};

static struct ser_statistics_type ser_stat[NR_PORTS];

#else

#define PROCSTAT(x)

#endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */

/* RS-485 */
#if defined(CONFIG_ETRAX_RS485)
#ifdef CONFIG_ETRAX_FAST_TIMER
static struct fast_timer fast_timers_rs485[NR_PORTS];
#endif
#if defined(CONFIG_ETRAX_RS485_ON_PA)
static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
#endif
#if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
#endif
#endif

/* Info and macros needed for each ports extra control/status signals. */
#define E100_STRUCT_PORT(line, pinname) \
 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
		(R_PORT_PA_DATA): ( \
 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
		(R_PORT_PB_DATA):&dummy_ser[line]))

#define E100_STRUCT_SHADOW(line, pinname) \
 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
		(&port_pa_data_shadow): ( \
 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
		(&port_pb_data_shadow):&dummy_ser[line]))
#define E100_STRUCT_MASK(line, pinname) \
 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
		(1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
		(1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))

#define DUMMY_DTR_MASK 1
#define DUMMY_RI_MASK  2
#define DUMMY_DSR_MASK 4
#define DUMMY_CD_MASK  8
static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};

/* If not all status pins are used or disabled, use mixed mode */
#ifdef CONFIG_ETRAX_SERIAL_PORT0

#define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)

#if SER0_PA_BITSUM != -4
#  if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
#    ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
#    endif
#   endif
# if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
#   ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
#     define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
#   endif
#  endif
#  if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
#    ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#  if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
#    ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#endif

#define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)

#if SER0_PB_BITSUM != -4
#  if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
#    ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
#    endif
#   endif
# if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
#   ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
#     define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
#   endif
#  endif
#  if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
#    ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#  if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
#    ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#endif

#endif /* PORT0 */


#ifdef CONFIG_ETRAX_SERIAL_PORT1

#define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)

#if SER1_PA_BITSUM != -4
#  if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
#    ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
#    endif
#   endif
# if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
#   ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
#     define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
#   endif
#  endif
#  if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
#    ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#  if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
#    ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#endif

#define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)

#if SER1_PB_BITSUM != -4
#  if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
#    ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
#    endif
#   endif
# if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
#   ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
#     define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
#   endif
#  endif
#  if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
#    ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#  if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
#    ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#endif

#endif /* PORT1 */

#ifdef CONFIG_ETRAX_SERIAL_PORT2

#define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)

#if SER2_PA_BITSUM != -4
#  if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
#    ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
#    endif
#   endif
# if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
#   ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
#     define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
#   endif
#  endif
#  if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
#    ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#  if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
#    ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#endif

#define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)

#if SER2_PB_BITSUM != -4
#  if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
#    ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
#    endif
#   endif
# if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
#   ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
#     define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
#   endif
#  endif
#  if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
#    ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#  if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
#    ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#endif

#endif /* PORT2 */

#ifdef CONFIG_ETRAX_SERIAL_PORT3

#define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)

#if SER3_PA_BITSUM != -4
#  if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
#    ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
#    endif
#   endif
# if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
#   ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
#     define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
#   endif
#  endif
#  if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
#    ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#  if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
#    ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#endif

#define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)

#if SER3_PB_BITSUM != -4
#  if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
#    ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
#    endif
#   endif
# if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
#   ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
#     define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
#   endif
#  endif
#  if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
#    ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#  if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
#    ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
#      define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
#    endif
#  endif
#endif

#endif /* PORT3 */


#if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
    defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
    defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
    defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
#define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
#endif

#ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
/* The pins can be mixed on PA and PB */
#define CONTROL_PINS_PORT_NOT_USED(line) \
  &dummy_ser[line], &dummy_ser[line], \
  &dummy_ser[line], &dummy_ser[line], \
  &dummy_ser[line], &dummy_ser[line], \
  &dummy_ser[line], &dummy_ser[line], \
  DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK


struct control_pins
{
	volatile unsigned char *dtr_port;
	unsigned char          *dtr_shadow;
	volatile unsigned char *ri_port;
	unsigned char          *ri_shadow;
	volatile unsigned char *dsr_port;
	unsigned char          *dsr_shadow;
	volatile unsigned char *cd_port;
	unsigned char          *cd_shadow;

	unsigned char dtr_mask;
	unsigned char ri_mask;
	unsigned char dsr_mask;
	unsigned char cd_mask;
};

static const struct control_pins e100_modem_pins[NR_PORTS] =
{
	/* Ser 0 */
	{
#ifdef CONFIG_ETRAX_SERIAL_PORT0
	E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
	E100_STRUCT_PORT(0,RI),  E100_STRUCT_SHADOW(0,RI),
	E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
	E100_STRUCT_PORT(0,CD),  E100_STRUCT_SHADOW(0,CD),
	E100_STRUCT_MASK(0,DTR),
	E100_STRUCT_MASK(0,RI),
	E100_STRUCT_MASK(0,DSR),
	E100_STRUCT_MASK(0,CD)
#else
	CONTROL_PINS_PORT_NOT_USED(0)
#endif
	},

	/* Ser 1 */
	{
#ifdef CONFIG_ETRAX_SERIAL_PORT1
	E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
	E100_STRUCT_PORT(1,RI),  E100_STRUCT_SHADOW(1,RI),
	E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
	E100_STRUCT_PORT(1,CD),  E100_STRUCT_SHADOW(1,CD),
	E100_STRUCT_MASK(1,DTR),
	E100_STRUCT_MASK(1,RI),
	E100_STRUCT_MASK(1,DSR),
	E100_STRUCT_MASK(1,CD)
#else
	CONTROL_PINS_PORT_NOT_USED(1)
#endif
	},

	/* Ser 2 */
	{
#ifdef CONFIG_ETRAX_SERIAL_PORT2
	E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
	E100_STRUCT_PORT(2,RI),  E100_STRUCT_SHADOW(2,RI),
	E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
	E100_STRUCT_PORT(2,CD),  E100_STRUCT_SHADOW(2,CD),
	E100_STRUCT_MASK(2,DTR),
	E100_STRUCT_MASK(2,RI),
	E100_STRUCT_MASK(2,DSR),
	E100_STRUCT_MASK(2,CD)
#else
	CONTROL_PINS_PORT_NOT_USED(2)
#endif
	},

	/* Ser 3 */
	{
#ifdef CONFIG_ETRAX_SERIAL_PORT3
	E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
	E100_STRUCT_PORT(3,RI),  E100_STRUCT_SHADOW(3,RI),
	E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
	E100_STRUCT_PORT(3,CD),  E100_STRUCT_SHADOW(3,CD),
	E100_STRUCT_MASK(3,DTR),
	E100_STRUCT_MASK(3,RI),
	E100_STRUCT_MASK(3,DSR),
	E100_STRUCT_MASK(3,CD)
#else
	CONTROL_PINS_PORT_NOT_USED(3)
#endif
	}
};
#else  /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */

/* All pins are on either PA or PB for each serial port */
#define CONTROL_PINS_PORT_NOT_USED(line) \
  &dummy_ser[line], &dummy_ser[line], \
  DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK


struct control_pins
{
	volatile unsigned char *port;
	unsigned char          *shadow;

	unsigned char dtr_mask;
	unsigned char ri_mask;
	unsigned char dsr_mask;
	unsigned char cd_mask;
};

#define dtr_port port
#define dtr_shadow shadow
#define ri_port port
#define ri_shadow shadow
#define dsr_port port
#define dsr_shadow shadow
#define cd_port port
#define cd_shadow shadow

static const struct control_pins e100_modem_pins[NR_PORTS] =
{
	/* Ser 0 */
	{
#ifdef CONFIG_ETRAX_SERIAL_PORT0
	E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
	E100_STRUCT_MASK(0,DTR),
	E100_STRUCT_MASK(0,RI),
	E100_STRUCT_MASK(0,DSR),
	E100_STRUCT_MASK(0,CD)
#else
	CONTROL_PINS_PORT_NOT_USED(0)
#endif
	},

	/* Ser 1 */
	{
#ifdef CONFIG_ETRAX_SERIAL_PORT1
	E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
	E100_STRUCT_MASK(1,DTR),
	E100_STRUCT_MASK(1,RI),
	E100_STRUCT_MASK(1,DSR),
	E100_STRUCT_MASK(1,CD)
#else
	CONTROL_PINS_PORT_NOT_USED(1)
#endif
	},

	/* Ser 2 */
	{
#ifdef CONFIG_ETRAX_SERIAL_PORT2
	E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
	E100_STRUCT_MASK(2,DTR),
	E100_STRUCT_MASK(2,RI),
	E100_STRUCT_MASK(2,DSR),
	E100_STRUCT_MASK(2,CD)
#else
	CONTROL_PINS_PORT_NOT_USED(2)
#endif
	},

	/* Ser 3 */
	{
#ifdef CONFIG_ETRAX_SERIAL_PORT3
	E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
	E100_STRUCT_MASK(3,DTR),
	E100_STRUCT_MASK(3,RI),
	E100_STRUCT_MASK(3,DSR),
	E100_STRUCT_MASK(3,CD)
#else
	CONTROL_PINS_PORT_NOT_USED(3)
#endif
	}
};
#endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */

#define E100_RTS_MASK 0x20
#define E100_CTS_MASK 0x40

/* All serial port signals are active low:
 * active   = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
 * inactive = 1 -> 0V   to RS-232 driver -> +12V on RS-232 level
 *
 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
 */

/* Output */
#define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
/* Input */
#define E100_CTS_GET(info) ((info)->port[REG_STATUS] & E100_CTS_MASK)

/* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
/* Is an output */
#define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)

/* Normally inputs */
#define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
#define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)

/* Input */
#define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)


/*
 * tmp_buf is used as a temporary buffer by serial_write.  We need to
 * lock it in case the memcpy_fromfs blocks while swapping in a page,
 * and some other program tries to do a serial write at the same time.
 * Since the lock will only come under contention when the system is
 * swapping and available memory is low, it makes sense to share one
 * buffer across all the serial ports, since it significantly saves
 * memory if large numbers of serial ports are open.
 */
static unsigned char *tmp_buf;
#ifdef DECLARE_MUTEX
static DECLARE_MUTEX(tmp_buf_sem);
#else
static struct semaphore tmp_buf_sem = MUTEX;
#endif

/* Calculate the chartime depending on baudrate, numbor of bits etc. */
static void update_char_time(struct e100_serial * info)
{
	tcflag_t cflags = info->tty->termios->c_cflag;
	int bits;

	/* calc. number of bits / data byte */
	/* databits + startbit and 1 stopbit */
	if ((cflags & CSIZE) == CS7)
		bits = 9;
	else
		bits = 10;

	if (cflags & CSTOPB)     /* 2 stopbits ? */
		bits++;

	if (cflags & PARENB)     /* parity bit ? */
		bits++;

	/* calc timeout */
	info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
	info->flush_time_usec = 4*info->char_time_usec;
	if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
		info->flush_time_usec = MIN_FLUSH_TIME_USEC;

}

/*
 * This function maps from the Bxxxx defines in asm/termbits.h into real
 * baud rates.
 */

static int
cflag_to_baud(unsigned int cflag)
{
	static int baud_table[] = {
		0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
		4800, 9600, 19200, 38400 };

	static int ext_baud_table[] = {
		0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
                0, 0, 0, 0, 0, 0, 0, 0 };

	if (cflag & CBAUDEX)
		return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
	else
		return baud_table[cflag & CBAUD];
}

/* and this maps to an etrax100 hardware baud constant */

static unsigned char
cflag_to_etrax_baud(unsigned int cflag)
{
	char retval;

	static char baud_table[] = {
		-1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };

	static char ext_baud_table[] = {
		-1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };

	if (cflag & CBAUDEX)
		retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
	else
		retval = baud_table[cflag & CBAUD];

	if (retval < 0) {
		printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
		retval = 5; /* choose default 9600 instead */
	}

	return retval | (retval << 4); /* choose same for both TX and RX */
}


/* Various static support functions */

/* Functions to set or clear DTR/RTS on the requested line */
/* It is complicated by the fact that RTS is a serial port register, while
 * DTR might not be implemented in the HW at all, and if it is, it can be on
 * any general port.
 */


static inline void
e100_dtr(struct e100_serial *info, int set)
{
#ifndef CONFIG_SVINTO_SIM
	unsigned char mask = e100_modem_pins[info->line].dtr_mask;

#ifdef SERIAL_DEBUG_IO
	printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
	printk("ser%i shadow before 0x%02X get: %i\n",
	       info->line, *e100_modem_pins[info->line].dtr_shadow,
	       E100_DTR_GET(info));
#endif
	/* DTR is active low */
	{
		unsigned long flags;

		save_flags(flags);
		cli();
		*e100_modem_pins[info->line].dtr_shadow &= ~mask;
		*e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
		*e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
		restore_flags(flags);
	}

#ifdef SERIAL_DEBUG_IO
	printk("ser%i shadow after 0x%02X get: %i\n",
	       info->line, *e100_modem_pins[info->line].dtr_shadow,
	       E100_DTR_GET(info));
#endif
#endif
}

/* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
 *                                          0=0V    , 1=3.3V
 */
static inline void
e100_rts(struct e100_serial *info, int set)
{
#ifndef CONFIG_SVINTO_SIM
	unsigned long flags;
	save_flags(flags);
	cli();
	info->rx_ctrl &= ~E100_RTS_MASK;
	info->rx_ctrl |= (set ? 0 : E100_RTS_MASK);  /* RTS is active low */
	info->port[REG_REC_CTRL] = info->rx_ctrl;
	restore_flags(flags);
#ifdef SERIAL_DEBUG_IO
	printk("ser%i rts %i\n", info->line, set);
#endif
#endif
}


/* If this behaves as a modem, RI and CD is an output */
static inline void
e100_ri_out(struct e100_serial *info, int set)
{
#ifndef CONFIG_SVINTO_SIM
	/* RI is active low */
	{
		unsigned char mask = e100_modem_pins[info->line].ri_mask;
		unsigned long flags;

		save_flags(flags);
		cli();
		*e100_modem_pins[info->line].ri_shadow &= ~mask;
		*e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
		*e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
		restore_flags(flags);
	}
#endif
}
static inline void
e100_cd_out(struct e100_serial *info, int set)
{
#ifndef CONFIG_SVINTO_SIM
	/* CD is active low */
	{
		unsigned char mask = e100_modem_pins[info->line].cd_mask;
		unsigned long flags;

		save_flags(flags);
		cli();
		*e100_modem_pins[info->line].cd_shadow &= ~mask;
		*e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
		*e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
		restore_flags(flags);
	}
#endif
}

static inline void
e100_disable_rx(struct e100_serial *info)
{
#ifndef CONFIG_SVINTO_SIM
	/* disable the receiver */
	info->port[REG_REC_CTRL] =
		(info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
#endif
}

static inline void
e100_enable_rx(struct e100_serial *info)
{
#ifndef CONFIG_SVINTO_SIM
	/* enable the receiver */
	info->port[REG_REC_CTRL] =
		(info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
#endif
}

/* the rx DMA uses both the dma_descr and the dma_eop interrupts */

static inline void
e100_disable_rxdma_irq(struct e100_serial *info)
{
#ifdef SERIAL_DEBUG_INTR
	printk("rxdma_irq(%d): 0\n",info->line);
#endif
	DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
	*R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
}

static inline void
e100_enable_rxdma_irq(struct e100_serial *info)
{
#ifdef SERIAL_DEBUG_INTR
	printk("rxdma_irq(%d): 1\n",info->line);
#endif
	DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
	*R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
}

/* the tx DMA uses only dma_descr interrupt */

static _INLINE_ void
e100_disable_txdma_irq(struct e100_serial *info)
{
#ifdef SERIAL_DEBUG_INTR
	printk("txdma_irq(%d): 0\n",info->line);
#endif
	DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
	*R_IRQ_MASK2_CLR = info->irq;
}

static _INLINE_ void
e100_enable_txdma_irq(struct e100_serial *info)
{
#ifdef SERIAL_DEBUG_INTR
	printk("txdma_irq(%d): 1\n",info->line);
#endif
	DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
	*R_IRQ_MASK2_SET = info->irq;
}

static _INLINE_ void
e100_disable_txdma_channel(struct e100_serial *info)
{
	unsigned long flags;

	/* Disable output DMA channel for the serial port in question
	 * ( set to something other then serialX)
	 */
	save_flags(flags);
	cli();
	DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
	if (info->line == 0) {
		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
		    IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma6);
			genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
		}
	} else if (info->line == 1) {
		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
		    IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma8);
			genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
		}
	} else if (info->line == 2) {
		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
		    IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma2);
			genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
		}
	} else if (info->line == 3) {
		if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
		    IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
			genconfig_shadow &=  ~IO_MASK(R_GEN_CONFIG, dma4);
			genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
		}
	}
	*R_GEN_CONFIG = genconfig_shadow;
	restore_flags(flags);
}


static _INLINE_ void
e100_enable_txdma_channel(struct e100_serial *info)
{
	unsigned long flags;

	save_flags(flags);
	cli();
	DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
	/* Enable output DMA channel for the serial port in question */