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authorBarry Song <21cnbao@gmail.com>2013-05-14 10:17:58 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-06-16 05:56:49 -0400
commit3370dc916c90578107cc8485ac86e6d6dc81a88f (patch)
treec6ed46d955f7ecdd0bce6ac22fd361911813542b /drivers
parent76cda6ec39d30a9d40ae2a82a6015381438a87eb (diff)
pinctrl:sirf:re-arch and add support for new SiRFatlas6 SoC
atlas6 is a SoC very similar with primaII, the register layput of pinctrl is same, but the pads, groups and functions of atlas6 have different layout with prima2, this patch 1. pull the definition of pads, groups and functions out of the pinctrl-sirf driver,and put them into soc-specific files 2. add pads, groups and functions tables for atlas6 3. let pads, groups and functions tables become the config data of the related dt compatible node, so the pinctrl-sirf can support all SiRF SoCs with the config data as private data. In this patch,we create a sirf dir, and let the old drivers/pinctrl/pinctrl-sirf.c = drivers/pinctrl/sirf/pinctrl-prima2.c + drivers/pinctrl/sirf/pinctrl-sirf.c drivers/pinctrl/sirf/pinctrl-atlas6.c is a newly created file for the pin layout of atlas6. Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pinctrl/Makefile2
-rw-r--r--drivers/pinctrl/sirf/Makefile5
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas6.c947
-rw-r--r--drivers/pinctrl/sirf/pinctrl-prima2.c (renamed from drivers/pinctrl/pinctrl-sirf.c)946
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c873
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.h116
6 files changed, 1955 insertions, 934 deletions
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 34c4ae6f7a65..0348c0f8856d 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -32,7 +32,7 @@ obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
32obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o 32obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
33obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o 33obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
34obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o 34obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
35obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 35obj-$(CONFIG_PINCTRL_SIRF) += sirf/
36obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o 36obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o
37obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o 37obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
38obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o 38obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
diff --git a/drivers/pinctrl/sirf/Makefile b/drivers/pinctrl/sirf/Makefile
new file mode 100644
index 000000000000..3ffc475ce40c
--- /dev/null
+++ b/drivers/pinctrl/sirf/Makefile
@@ -0,0 +1,5 @@
1# CSR SiRFsoc pinmux support
2
3obj-y += pinctrl-sirf.o
4obj-y += pinctrl-prima2.o
5obj-y += pinctrl-atlas6.o
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
new file mode 100644
index 000000000000..1fa39a444171
--- /dev/null
+++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c
@@ -0,0 +1,947 @@
1/*
2 * pinctrl pads, groups, functions for CSR SiRFatlasVI
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/pinctrl/pinctrl.h>
10#include <linux/bitops.h>
11
12#include "pinctrl-sirf.h"
13
14/*
15 * pad list for the pinmux subsystem
16 * refer to atlasVI_io_table_v0.93.xls
17 */
18static const struct pinctrl_pin_desc sirfsoc_pads[] = {
19 PINCTRL_PIN(0, "gpio0-0"),
20 PINCTRL_PIN(1, "gpio0-1"),
21 PINCTRL_PIN(2, "gpio0-2"),
22 PINCTRL_PIN(3, "gpio0-3"),
23 PINCTRL_PIN(4, "pwm0"),
24 PINCTRL_PIN(5, "pwm1"),
25 PINCTRL_PIN(6, "pwm2"),
26 PINCTRL_PIN(7, "pwm3"),
27 PINCTRL_PIN(8, "warm_rst_b"),
28 PINCTRL_PIN(9, "odo_0"),
29 PINCTRL_PIN(10, "odo_1"),
30 PINCTRL_PIN(11, "dr_dir"),
31 PINCTRL_PIN(12, "rts_0"),
32 PINCTRL_PIN(13, "scl_1"),
33 PINCTRL_PIN(14, "ntrst"),
34 PINCTRL_PIN(15, "sda_1"),
35 PINCTRL_PIN(16, "x_ldd[16]"),
36 PINCTRL_PIN(17, "x_ldd[17]"),
37 PINCTRL_PIN(18, "x_ldd[18]"),
38 PINCTRL_PIN(19, "x_ldd[19]"),
39 PINCTRL_PIN(20, "x_ldd[20]"),
40 PINCTRL_PIN(21, "x_ldd[21]"),
41 PINCTRL_PIN(22, "x_ldd[22]"),
42 PINCTRL_PIN(23, "x_ldd[23]"),
43 PINCTRL_PIN(24, "gps_sgn"),
44 PINCTRL_PIN(25, "gps_mag"),
45 PINCTRL_PIN(26, "gps_clk"),
46 PINCTRL_PIN(27, "sd_cd_b_2"),
47 PINCTRL_PIN(28, "sd_vcc_on_2"),
48 PINCTRL_PIN(29, "sd_wp_b_2"),
49 PINCTRL_PIN(30, "sd_clk_3"),
50 PINCTRL_PIN(31, "sd_cmd_3"),
51
52 PINCTRL_PIN(32, "x_sd_dat_3[0]"),
53 PINCTRL_PIN(33, "x_sd_dat_3[1]"),
54 PINCTRL_PIN(34, "x_sd_dat_3[2]"),
55 PINCTRL_PIN(35, "x_sd_dat_3[3]"),
56 PINCTRL_PIN(36, "usb_clk"),
57 PINCTRL_PIN(37, "usb_dir"),
58 PINCTRL_PIN(38, "usb_nxt"),
59 PINCTRL_PIN(39, "usb_stp"),
60 PINCTRL_PIN(40, "usb_dat[7]"),
61 PINCTRL_PIN(41, "usb_dat[6]"),
62 PINCTRL_PIN(42, "x_cko_1"),
63 PINCTRL_PIN(43, "spi_clk_1"),
64 PINCTRL_PIN(44, "spi_dout_1"),
65 PINCTRL_PIN(45, "spi_din_1"),
66 PINCTRL_PIN(46, "spi_en_1"),
67 PINCTRL_PIN(47, "x_txd_1"),
68 PINCTRL_PIN(48, "x_txd_2"),
69 PINCTRL_PIN(49, "x_rxd_1"),
70 PINCTRL_PIN(50, "x_rxd_2"),
71 PINCTRL_PIN(51, "x_usclk_0"),
72 PINCTRL_PIN(52, "x_utxd_0"),
73 PINCTRL_PIN(53, "x_urxd_0"),
74 PINCTRL_PIN(54, "x_utfs_0"),
75 PINCTRL_PIN(55, "x_urfs_0"),
76 PINCTRL_PIN(56, "usb_dat5"),
77 PINCTRL_PIN(57, "usb_dat4"),
78 PINCTRL_PIN(58, "usb_dat3"),
79 PINCTRL_PIN(59, "usb_dat2"),
80 PINCTRL_PIN(60, "usb_dat1"),
81 PINCTRL_PIN(61, "usb_dat0"),
82 PINCTRL_PIN(62, "x_ldd[14]"),
83 PINCTRL_PIN(63, "x_ldd[15]"),
84
85 PINCTRL_PIN(64, "x_gps_gpio"),
86 PINCTRL_PIN(65, "x_ldd[13]"),
87 PINCTRL_PIN(66, "x_df_we_b"),
88 PINCTRL_PIN(67, "x_df_re_b"),
89 PINCTRL_PIN(68, "x_txd_0"),
90 PINCTRL_PIN(69, "x_rxd_0"),
91 PINCTRL_PIN(70, "x_l_lck"),
92 PINCTRL_PIN(71, "x_l_fck"),
93 PINCTRL_PIN(72, "x_l_de"),
94 PINCTRL_PIN(73, "x_ldd[0]"),
95 PINCTRL_PIN(74, "x_ldd[1]"),
96 PINCTRL_PIN(75, "x_ldd[2]"),
97 PINCTRL_PIN(76, "x_ldd[3]"),
98 PINCTRL_PIN(77, "x_ldd[4]"),
99 PINCTRL_PIN(78, "x_cko_0"),
100 PINCTRL_PIN(79, "x_ldd[5]"),
101 PINCTRL_PIN(80, "x_ldd[6]"),
102 PINCTRL_PIN(81, "x_ldd[7]"),
103 PINCTRL_PIN(82, "x_ldd[8]"),
104 PINCTRL_PIN(83, "x_ldd[9]"),
105 PINCTRL_PIN(84, "x_ldd[10]"),
106 PINCTRL_PIN(85, "x_ldd[11]"),
107 PINCTRL_PIN(86, "x_ldd[12]"),
108 PINCTRL_PIN(87, "x_vip_vsync"),
109 PINCTRL_PIN(88, "x_vip_hsync"),
110 PINCTRL_PIN(89, "x_vip_pxclk"),
111 PINCTRL_PIN(90, "x_sda_0"),
112 PINCTRL_PIN(91, "x_scl_0"),
113 PINCTRL_PIN(92, "x_df_ry_by"),
114 PINCTRL_PIN(93, "x_df_cs_b[1]"),
115 PINCTRL_PIN(94, "x_df_cs_b[0]"),
116 PINCTRL_PIN(95, "x_l_pclk"),
117
118 PINCTRL_PIN(96, "x_df_dqs"),
119 PINCTRL_PIN(97, "x_df_wp_b"),
120 PINCTRL_PIN(98, "ac97_sync"),
121 PINCTRL_PIN(99, "ac97_bit_clk "),
122 PINCTRL_PIN(100, "ac97_dout"),
123 PINCTRL_PIN(101, "ac97_din"),
124 PINCTRL_PIN(102, "x_rtc_io"),
125};
126
127static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
128 {
129 .group = 1,
130 .mask = BIT(30) | BIT(31),
131 }, {
132 .group = 2,
133 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
134 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
135 BIT(20) | BIT(21) | BIT(22) | BIT(31),
136 },
137};
138
139static const struct sirfsoc_padmux lcd_16bits_padmux = {
140 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
141 .muxmask = lcd_16bits_sirfsoc_muxmask,
142 .funcmask = BIT(4),
143 .funcval = 0,
144};
145
146static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
147 84, 85, 86, 95 };
148
149static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
150 {
151 .group = 2,
152 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
153 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
154 BIT(20) | BIT(21) | BIT(22) | BIT(31),
155 }, {
156 .group = 1,
157 .mask = BIT(30) | BIT(31),
158 }, {
159 .group = 0,
160 .mask = BIT(16) | BIT(17),
161 },
162};
163
164static const struct sirfsoc_padmux lcd_18bits_padmux = {
165 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
166 .muxmask = lcd_18bits_muxmask,
167 .funcmask = BIT(4) | BIT(15),
168 .funcval = 0,
169};
170
171static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
172 84, 85, 86, 95 };
173
174static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
175 {
176 .group = 2,
177 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
178 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
179 BIT(20) | BIT(21) | BIT(22) | BIT(31),
180 }, {
181 .group = 1,
182 .mask = BIT(30) | BIT(31),
183 }, {
184 .group = 0,
185 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
186 },
187};
188
189static const struct sirfsoc_padmux lcd_24bits_padmux = {
190 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
191 .muxmask = lcd_24bits_muxmask,
192 .funcmask = BIT(4) | BIT(15),
193 .funcval = 0,
194};
195
196static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79,
197 80, 81, 82, 83, 84, 85, 86, 95};
198
199static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
200 {
201 .group = 2,
202 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
203 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
204 BIT(20) | BIT(21) | BIT(22) | BIT(31),
205 }, {
206 .group = 1,
207 .mask = BIT(30) | BIT(31),
208 }, {
209 .group = 0,
210 .mask = BIT(8),
211 },
212};
213
214static const struct sirfsoc_padmux lcdrom_padmux = {
215 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
216 .muxmask = lcdrom_muxmask,
217 .funcmask = BIT(4),
218 .funcval = BIT(4),
219};
220
221static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
222 84, 85, 86, 95};
223
224static const struct sirfsoc_muxmask uart0_muxmask[] = {
225 {
226 .group = 0,
227 .mask = BIT(12),
228 }, {
229 .group = 1,
230 .mask = BIT(23),
231 }, {
232 .group = 2,
233 .mask = BIT(4) | BIT(5),
234 },
235};
236
237static const struct sirfsoc_padmux uart0_padmux = {
238 .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
239 .muxmask = uart0_muxmask,
240 .funcmask = BIT(9),
241 .funcval = BIT(9),
242};
243
244static const unsigned uart0_pins[] = { 12, 55, 68, 69 };
245
246static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
247 {
248 .group = 2,
249 .mask = BIT(4) | BIT(5),
250 },
251};
252
253static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
254 .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
255 .muxmask = uart0_nostreamctrl_muxmask,
256};
257
258static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
259
260static const struct sirfsoc_muxmask uart1_muxmask[] = {
261 {
262 .group = 1,
263 .mask = BIT(15) | BIT(17),
264 },
265};
266
267static const struct sirfsoc_padmux uart1_padmux = {
268 .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
269 .muxmask = uart1_muxmask,
270};
271
272static const unsigned uart1_pins[] = { 47, 49 };
273
274static const struct sirfsoc_muxmask uart2_muxmask[] = {
275 {
276 .group = 0,
277 .mask = BIT(10) | BIT(14),
278 }, {
279 .group = 1,
280 .mask = BIT(16) | BIT(18),
281 },
282};
283
284static const struct sirfsoc_padmux uart2_padmux = {
285 .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
286 .muxmask = uart2_muxmask,
287 .funcmask = BIT(10),
288 .funcval = BIT(10),
289};
290
291static const unsigned uart2_pins[] = { 10, 14, 48, 50 };
292
293static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
294 {
295 .group = 1,
296 .mask = BIT(16) | BIT(18),
297 },
298};
299
300static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
301 .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
302 .muxmask = uart2_nostreamctrl_muxmask,
303};
304
305static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
306
307static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
308 {
309 .group = 0,
310 .mask = BIT(30) | BIT(31),
311 }, {
312 .group = 1,
313 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
314 },
315};
316
317static const struct sirfsoc_padmux sdmmc3_padmux = {
318 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
319 .muxmask = sdmmc3_muxmask,
320 .funcmask = BIT(7),
321 .funcval = 0,
322};
323
324static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
325
326static const struct sirfsoc_muxmask spi0_muxmask[] = {
327 {
328 .group = 0,
329 .mask = BIT(30),
330 }, {
331 .group = 1,
332 .mask = BIT(0) | BIT(2) | BIT(3),
333 },
334};
335
336static const struct sirfsoc_padmux spi0_padmux = {
337 .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
338 .muxmask = spi0_muxmask,
339 .funcmask = BIT(7),
340 .funcval = BIT(7),
341};
342
343static const unsigned spi0_pins[] = { 30, 32, 34, 35 };
344
345static const struct sirfsoc_muxmask cko1_muxmask[] = {
346 {
347 .group = 1,
348 .mask = BIT(10),
349 },
350};
351
352static const struct sirfsoc_padmux cko1_padmux = {
353 .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
354 .muxmask = cko1_muxmask,
355 .funcmask = BIT(3),
356 .funcval = 0,
357};
358
359static const unsigned cko1_pins[] = { 42 };
360
361static const struct sirfsoc_muxmask i2s_muxmask[] = {
362 {
363 .group = 1,
364 .mask = BIT(10),
365 }, {
366 .group = 3,
367 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
368 },
369};
370
371static const struct sirfsoc_padmux i2s_padmux = {
372 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
373 .muxmask = i2s_muxmask,
374 .funcmask = BIT(3),
375 .funcval = BIT(3),
376};
377
378static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 };
379
380static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
381 {
382 .group = 1,
383 .mask = BIT(10),
384 }, {
385 .group = 3,
386 .mask = BIT(2) | BIT(3) | BIT(4),
387 },
388};
389
390static const struct sirfsoc_padmux i2s_no_din_padmux = {
391 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
392 .muxmask = i2s_no_din_muxmask,
393 .funcmask = BIT(3),
394 .funcval = BIT(3),
395};
396
397static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 };
398
399static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
400 {
401 .group = 1,
402 .mask = BIT(10) | BIT(20) | BIT(23),
403 }, {
404 .group = 3,
405 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
406 },
407};
408
409static const struct sirfsoc_padmux i2s_6chn_padmux = {
410 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
411 .muxmask = i2s_6chn_muxmask,
412 .funcmask = BIT(1) | BIT(3) | BIT(9),
413 .funcval = BIT(1) | BIT(3) | BIT(9),
414};
415
416static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 };
417
418static const struct sirfsoc_muxmask ac97_muxmask[] = {
419 {
420 .group = 3,
421 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
422 },
423};
424
425static const struct sirfsoc_padmux ac97_padmux = {
426 .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
427 .muxmask = ac97_muxmask,
428};
429
430static const unsigned ac97_pins[] = { 98, 99, 100, 101 };
431
432static const struct sirfsoc_muxmask spi1_muxmask[] = {
433 {
434 .group = 1,
435 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
436 },
437};
438
439static const struct sirfsoc_padmux spi1_padmux = {
440 .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
441 .muxmask = spi1_muxmask,
442 .funcmask = BIT(16),
443 .funcval = 0,
444};
445
446static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
447
448static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
449 {
450 .group = 2,
451 .mask = BIT(2) | BIT(3),
452 },
453};
454
455static const struct sirfsoc_padmux sdmmc1_padmux = {
456 .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
457 .muxmask = sdmmc1_muxmask,
458 .funcmask = BIT(5),
459 .funcval = BIT(5),
460};
461
462static const unsigned sdmmc1_pins[] = { 66, 67 };
463
464static const struct sirfsoc_muxmask gps_muxmask[] = {
465 {
466 .group = 0,
467 .mask = BIT(24) | BIT(25) | BIT(26),
468 },
469};
470
471static const struct sirfsoc_padmux gps_padmux = {
472 .muxmask_counts = ARRAY_SIZE(gps_muxmask),
473 .muxmask = gps_muxmask,
474 .funcmask = BIT(13),
475 .funcval = 0,
476};
477
478static const unsigned gps_pins[] = { 24, 25, 26 };
479
480static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
481 {
482 .group = 0,
483 .mask = BIT(24) | BIT(25) | BIT(26),
484 },
485};
486
487static const struct sirfsoc_padmux sdmmc5_padmux = {
488 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
489 .muxmask = sdmmc5_muxmask,
490 .funcmask = BIT(13),
491 .funcval = BIT(13),
492};
493
494static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
495
496static const struct sirfsoc_muxmask usp0_muxmask[] = {
497 {
498 .group = 1,
499 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
500 },
501};
502
503static const struct sirfsoc_padmux usp0_padmux = {
504 .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
505 .muxmask = usp0_muxmask,
506 .funcmask = BIT(1) | BIT(2) | BIT(9),
507 .funcval = 0,
508};
509
510static const unsigned usp0_pins[] = { 51, 52, 53, 54 };
511
512static const struct sirfsoc_muxmask usp1_muxmask[] = {
513 {
514 .group = 0,
515 .mask = BIT(15),
516 }, {
517 .group = 1,
518 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
519 },
520};
521
522static const struct sirfsoc_padmux usp1_padmux = {
523 .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
524 .muxmask = usp1_muxmask,
525 .funcmask = BIT(16),
526 .funcval = BIT(16),
527};
528
529static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
530
531static const struct sirfsoc_muxmask nand_muxmask[] = {
532 {
533 .group = 2,
534 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
535 }, {
536 .group = 3,
537 .mask = BIT(0) | BIT(1),
538 },
539};
540
541static const struct sirfsoc_padmux nand_padmux = {
542 .muxmask_counts = ARRAY_SIZE(nand_muxmask),
543 .muxmask = nand_muxmask,
544 .funcmask = BIT(5) | BIT(19),
545 .funcval = 0,
546};
547
548static const unsigned nand_pins[] = { 66, 67, 92, 93, 94, 96, 97 };
549
550static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
551 {
552 .group = 3,
553 .mask = BIT(1),
554 },
555};
556
557static const struct sirfsoc_padmux sdmmc0_padmux = {
558 .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
559 .muxmask = sdmmc0_muxmask,
560 .funcmask = BIT(5) | BIT(19),
561 .funcval = BIT(19),
562};
563
564static const unsigned sdmmc0_pins[] = { 97 };
565
566static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
567 {
568 .group = 0,
569 .mask = BIT(27) | BIT(28) | BIT(29),
570 },
571};
572
573static const struct sirfsoc_padmux sdmmc2_padmux = {
574 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
575 .muxmask = sdmmc2_muxmask,
576 .funcmask = BIT(11),
577 .funcval = 0,
578};
579
580static const unsigned sdmmc2_pins[] = { 27, 28, 29 };
581
582static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
583 {
584 .group = 0,
585 .mask = BIT(27) | BIT(28),
586 },
587};
588
589static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
590 .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
591 .muxmask = sdmmc2_nowp_muxmask,
592 .funcmask = BIT(11),
593 .funcval = 0,
594};
595
596static const unsigned sdmmc2_nowp_pins[] = { 27, 28 };
597
598static const struct sirfsoc_muxmask cko0_muxmask[] = {
599 {
600 .group = 2,
601 .mask = BIT(14),
602 },
603};
604
605static const struct sirfsoc_padmux cko0_padmux = {
606 .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
607 .muxmask = cko0_muxmask,
608};
609
610static const unsigned cko0_pins[] = { 78 };
611
612static const struct sirfsoc_muxmask vip_muxmask[] = {
613 {
614 .group = 1,
615 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9)
616 | BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) |
617 BIT(29),
618 },
619};
620
621static const struct sirfsoc_padmux vip_padmux = {
622 .muxmask_counts = ARRAY_SIZE(vip_muxmask),
623 .muxmask = vip_muxmask,
624 .funcmask = BIT(18),
625 .funcval = BIT(18),
626};
627
628static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 60, 61 };
629
630static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
631 {
632 .group = 0,
633 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20)
634 | BIT(21) | BIT(22) | BIT(23),
635 }, {
636 .group = 2,
637 .mask = BIT(23) | BIT(24) | BIT(25),
638 },
639};
640
641static const struct sirfsoc_padmux vip_noupli_padmux = {
642 .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
643 .muxmask = vip_noupli_muxmask,
644 .funcmask = BIT(15),
645 .funcval = BIT(15),
646};
647
648static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 87, 88, 89 };
649
650static const struct sirfsoc_muxmask i2c0_muxmask[] = {
651 {
652 .group = 2,
653 .mask = BIT(26) | BIT(27),
654 },
655};
656
657static const struct sirfsoc_padmux i2c0_padmux = {
658 .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
659 .muxmask = i2c0_muxmask,
660};
661
662static const unsigned i2c0_pins[] = { 90, 91 };
663
664static const struct sirfsoc_muxmask i2c1_muxmask[] = {
665 {
666 .group = 0,
667 .mask = BIT(13) | BIT(15),
668 },
669};
670
671static const struct sirfsoc_padmux i2c1_padmux = {
672 .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
673 .muxmask = i2c1_muxmask,
674 .funcmask = BIT(16),
675 .funcval = 0,
676};
677
678static const unsigned i2c1_pins[] = { 13, 15 };
679
680static const struct sirfsoc_muxmask pwm0_muxmask[] = {
681 {
682 .group = 0,
683 .mask = BIT(4),
684 },
685};
686
687static const struct sirfsoc_padmux pwm0_padmux = {
688 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
689 .muxmask = pwm0_muxmask,
690 .funcmask = BIT(12),
691 .funcval = 0,
692};
693
694static const unsigned pwm0_pins[] = { 4 };
695
696static const struct sirfsoc_muxmask pwm1_muxmask[] = {
697 {
698 .group = 0,
699 .mask = BIT(5),
700 },
701};
702
703static const struct sirfsoc_padmux pwm1_padmux = {
704 .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
705 .muxmask = pwm1_muxmask,
706};
707
708static const unsigned pwm1_pins[] = { 5 };
709
710static const struct sirfsoc_muxmask pwm2_muxmask[] = {
711 {
712 .group = 0,
713 .mask = BIT(6),
714 },
715};
716
717static const struct sirfsoc_padmux pwm2_padmux = {
718 .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
719 .muxmask = pwm2_muxmask,
720};
721
722static const unsigned pwm2_pins[] = { 6 };
723
724static const struct sirfsoc_muxmask pwm3_muxmask[] = {
725 {
726 .group = 0,
727 .mask = BIT(7),
728 },
729};
730
731static const struct sirfsoc_padmux pwm3_padmux = {
732 .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
733 .muxmask = pwm3_muxmask,
734};
735
736static const unsigned pwm3_pins[] = { 7 };
737
738static const struct sirfsoc_muxmask pwm4_muxmask[] = {
739 {
740 .group = 2,
741 .mask = BIT(14),
742 },
743};
744
745static const struct sirfsoc_padmux pwm4_padmux = {
746 .muxmask_counts = ARRAY_SIZE(pwm4_muxmask),
747 .muxmask = pwm4_muxmask,
748};
749
750static const unsigned pwm4_pins[] = { 78 };
751
752static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
753 {
754 .group = 0,
755 .mask = BIT(8),
756 },
757};
758
759static const struct sirfsoc_padmux warm_rst_padmux = {
760 .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
761 .muxmask = warm_rst_muxmask,
762 .funcmask = BIT(4),
763 .funcval = 0,
764};
765
766static const unsigned warm_rst_pins[] = { 8 };
767
768static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
769 {
770 .group = 1,
771 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8)
772 | BIT(9) | BIT(24) | BIT(25) | BIT(26) |
773 BIT(27) | BIT(28) | BIT(29),
774 },
775};
776static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
777 .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
778 .muxmask = usb0_upli_drvbus_muxmask,
779 .funcmask = BIT(18),
780 .funcval = 0,
781};
782
783static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 41, 56, 57, 58, 59, 60, 61 };
784
785static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
786 {
787 .group = 0,
788 .mask = BIT(28),
789 },
790};
791
792static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
793 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
794 .muxmask = usb1_utmi_drvbus_muxmask,
795 .funcmask = BIT(11),
796 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
797};
798
799static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
800
801static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
802 {
803 .group = 0,
804 .mask = BIT(9) | BIT(10) | BIT(11),
805 },
806};
807
808static const struct sirfsoc_padmux pulse_count_padmux = {
809 .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
810 .muxmask = pulse_count_muxmask,
811};
812
813static const unsigned pulse_count_pins[] = { 9, 10, 11 };
814
815static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
816 SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
817 SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
818 SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
819 SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
820 SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
821 SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
822 SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
823 SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
824 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
825 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
826 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
827 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
828 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
829 SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
830 SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
831 SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
832 SIRFSOC_PIN_GROUP("pwm4grp", pwm4_pins),
833 SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
834 SIRFSOC_PIN_GROUP("vip_noupligrp", vip_noupli_pins),
835 SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
836 SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
837 SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
838 SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
839 SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
840 SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
841 SIRFSOC_PIN_GROUP("sdmmc2_nowpgrp", sdmmc2_nowp_pins),
842 SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
843 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
844 SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
845 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
846 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
847 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
848 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
849 SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
850 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
851 SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
852 SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
853 SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
854 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
855};
856
857static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
858static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
859static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
860static const char * const lcdromgrp[] = { "lcdromgrp" };
861static const char * const uart0grp[] = { "uart0grp" };
862static const char * const uart1grp[] = { "uart1grp" };
863static const char * const uart2grp[] = { "uart2grp" };
864static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
865static const char * const usp0grp[] = { "usp0grp" };
866static const char * const usp1grp[] = { "usp1grp" };
867static const char * const i2c0grp[] = { "i2c0grp" };
868static const char * const i2c1grp[] = { "i2c1grp" };
869static const char * const pwm0grp[] = { "pwm0grp" };
870static const char * const pwm1grp[] = { "pwm1grp" };
871static const char * const pwm2grp[] = { "pwm2grp" };
872static const char * const pwm3grp[] = { "pwm3grp" };
873static const char * const pwm4grp[] = { "pwm4grp" };
874static const char * const vipgrp[] = { "vipgrp" };
875static const char * const vip_noupligrp[] = { "vip_noupligrp" };
876static const char * const warm_rstgrp[] = { "warm_rstgrp" };
877static const char * const cko0grp[] = { "cko0grp" };
878static const char * const cko1grp[] = { "cko1grp" };
879static const char * const sdmmc0grp[] = { "sdmmc0grp" };
880static const char * const sdmmc1grp[] = { "sdmmc1grp" };
881static const char * const sdmmc2grp[] = { "sdmmc2grp" };
882static const char * const sdmmc3grp[] = { "sdmmc3grp" };
883static const char * const sdmmc5grp[] = { "sdmmc5grp" };
884static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
885static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
886static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
887static const char * const pulse_countgrp[] = { "pulse_countgrp" };
888static const char * const i2sgrp[] = { "i2sgrp" };
889static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
890static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
891static const char * const ac97grp[] = { "ac97grp" };
892static const char * const nandgrp[] = { "nandgrp" };
893static const char * const spi0grp[] = { "spi0grp" };
894static const char * const spi1grp[] = { "spi1grp" };
895static const char * const gpsgrp[] = { "gpsgrp" };
896
897static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
898 SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
899 SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
900 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
901 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
902 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
903 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
904 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
905 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
906 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
907 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
908 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
909 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
910 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
911 SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
912 SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
913 SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
914 SIRFSOC_PMX_FUNCTION("pwm4", pwm4grp, pwm4_padmux),
915 SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
916 SIRFSOC_PMX_FUNCTION("vip_noupli", vip_noupligrp, vip_noupli_padmux),
917 SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
918 SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
919 SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
920 SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
921 SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
922 SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
923 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
924 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
925 SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
926 SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
927 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
928 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
929 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
930 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
931 SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
932 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
933 SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
934 SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
935 SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
936 SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
937};
938
939struct sirfsoc_pinctrl_data atlas6_pinctrl_data = {
940 (struct pinctrl_pin_desc *)sirfsoc_pads,
941 ARRAY_SIZE(sirfsoc_pads),
942 (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
943 ARRAY_SIZE(sirfsoc_pin_groups),
944 (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
945 ARRAY_SIZE(sirfsoc_pmx_functions),
946};
947
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-prima2.c
index d704f3b525f5..1f0ad1ef5a3a 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-prima2.c
@@ -1,70 +1,15 @@
1/* 1/*
2 * pinmux driver for CSR SiRFprimaII 2 * pinctrl pads, groups, functions for CSR SiRFprimaII
3 * 3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 * 5 *
6 * Licensed under GPLv2 or later. 6 * Licensed under GPLv2 or later.
7 */ 7 */
8 8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/irq.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14#include <linux/slab.h>
15#include <linux/err.h>
16#include <linux/irqdomain.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/pinctrl/pinctrl.h> 9#include <linux/pinctrl/pinctrl.h>
19#include <linux/pinctrl/pinmux.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_device.h>
25#include <linux/of_platform.h>
26#include <linux/bitops.h> 10#include <linux/bitops.h>
27#include <linux/gpio.h> 11
28#include <linux/of_gpio.h> 12#include "pinctrl-sirf.h"
29
30#define DRIVER_NAME "pinmux-sirf"
31
32#define SIRFSOC_NUM_PADS 622
33#define SIRFSOC_RSC_PIN_MUX 0x4
34
35#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
36#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90)
37#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4)
38#define SIRFSOC_GPIO_DSP_EN0 (0x80)
39#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C)
40
41#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1
42#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2
43#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4
44#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8
45#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10
46#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20
47#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40
48#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80
49#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100
50#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200
51#define SIRFSOC_GPIO_CTL_DSP_INT 0x400
52
53#define SIRFSOC_GPIO_NO_OF_BANKS 5
54#define SIRFSOC_GPIO_BANK_SIZE 32
55#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index))
56
57struct sirfsoc_gpio_bank {
58 struct of_mm_gpio_chip chip;
59 struct irq_domain *domain;
60 int id;
61 int parent_irq;
62 spinlock_t lock;
63 bool is_marco; /* for marco, some registers are different with prima2 */
64};
65
66static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
67static DEFINE_SPINLOCK(sgpio_lock);
68 13
69/* 14/*
70 * pad list for the pinmux subsystem 15 * pad list for the pinmux subsystem
@@ -183,46 +128,6 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
183 PINCTRL_PIN(114, "x_ldd[15]"), 128 PINCTRL_PIN(114, "x_ldd[15]"),
184}; 129};
185 130
186/**
187 * @dev: a pointer back to containing device
188 * @virtbase: the offset to the controller in virtual memory
189 */
190struct sirfsoc_pmx {
191 struct device *dev;
192 struct pinctrl_dev *pmx;
193 void __iomem *gpio_virtbase;
194 void __iomem *rsc_virtbase;
195 bool is_marco;
196};
197
198/* SIRFSOC_GPIO_PAD_EN set */
199struct sirfsoc_muxmask {
200 unsigned long group;
201 unsigned long mask;
202};
203
204struct sirfsoc_padmux {
205 unsigned long muxmask_counts;
206 const struct sirfsoc_muxmask *muxmask;
207 /* RSC_PIN_MUX set */
208 unsigned long funcmask;
209 unsigned long funcval;
210};
211
212 /**
213 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
214 * @name: the name of this specific pin group
215 * @pins: an array of discrete physical pins used in this group, taken
216 * from the driver-local pin enumeration space
217 * @num_pins: the number of pins in this group array, i.e. the number of
218 * elements in .pins so we can iterate over that array
219 */
220struct sirfsoc_pin_group {
221 const char *name;
222 const unsigned int *pins;
223 const unsigned num_pins;
224};
225
226static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { 131static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
227 { 132 {
228 .group = 3, 133 .group = 3,
@@ -351,7 +256,7 @@ static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
351 .muxmask = uart0_nostreamctrl_muxmask, 256 .muxmask = uart0_nostreamctrl_muxmask,
352}; 257};
353 258
354static const unsigned uart0_nostreamctrl_pins[] = { 68, 39 }; 259static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
355 260
356static const struct sirfsoc_muxmask uart1_muxmask[] = { 261static const struct sirfsoc_muxmask uart1_muxmask[] = {
357 { 262 {
@@ -853,13 +758,6 @@ static const struct sirfsoc_padmux pulse_count_padmux = {
853 758
854static const unsigned pulse_count_pins[] = { 9, 10, 11 }; 759static const unsigned pulse_count_pins[] = { 9, 10, 11 };
855 760
856#define SIRFSOC_PIN_GROUP(n, p) \
857 { \
858 .name = n, \
859 .pins = p, \
860 .num_pins = ARRAY_SIZE(p), \
861 }
862
863static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = { 761static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
864 SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins), 762 SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
865 SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins), 763 SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
@@ -881,8 +779,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
881 SIRFSOC_PIN_GROUP("vipgrp", vip_pins), 779 SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
882 SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins), 780 SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
883 SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins), 781 SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
884 SIRFSOC_PIN_GROUP("cko0_rstgrp", cko0_pins), 782 SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
885 SIRFSOC_PIN_GROUP("cko1_rstgrp", cko1_pins), 783 SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
886 SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins), 784 SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
887 SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins), 785 SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
888 SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins), 786 SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
@@ -900,101 +798,6 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
900 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), 798 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
901}; 799};
902 800
903static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
904{
905 return ARRAY_SIZE(sirfsoc_pin_groups);
906}
907
908static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
909 unsigned selector)
910{
911 return sirfsoc_pin_groups[selector].name;
912}
913
914static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
915 const unsigned **pins,
916 unsigned *num_pins)
917{
918 *pins = sirfsoc_pin_groups[selector].pins;
919 *num_pins = sirfsoc_pin_groups[selector].num_pins;
920 return 0;
921}
922
923static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
924 unsigned offset)
925{
926 seq_printf(s, " " DRIVER_NAME);
927}
928
929static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
930 struct device_node *np_config,
931 struct pinctrl_map **map, unsigned *num_maps)
932{
933 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
934 struct device_node *np;
935 struct property *prop;
936 const char *function, *group;
937 int ret, index = 0, count = 0;
938
939 /* calculate number of maps required */
940 for_each_child_of_node(np_config, np) {
941 ret = of_property_read_string(np, "sirf,function", &function);
942 if (ret < 0)
943 return ret;
944
945 ret = of_property_count_strings(np, "sirf,pins");
946 if (ret < 0)
947 return ret;
948
949 count += ret;
950 }
951
952 if (!count) {
953 dev_err(spmx->dev, "No child nodes passed via DT\n");
954 return -ENODEV;
955 }
956
957 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
958 if (!*map)
959 return -ENOMEM;
960
961 for_each_child_of_node(np_config, np) {
962 of_property_read_string(np, "sirf,function", &function);
963 of_property_for_each_string(np, "sirf,pins", prop, group) {
964 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
965 (*map)[index].data.mux.group = group;
966 (*map)[index].data.mux.function = function;
967 index++;
968 }
969 }
970
971 *num_maps = count;
972
973 return 0;
974}
975
976static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
977 struct pinctrl_map *map, unsigned num_maps)
978{
979 kfree(map);
980}
981
982static const struct pinctrl_ops sirfsoc_pctrl_ops = {
983 .get_groups_count = sirfsoc_get_groups_count,
984 .get_group_name = sirfsoc_get_group_name,
985 .get_group_pins = sirfsoc_get_group_pins,
986 .pin_dbg_show = sirfsoc_pin_dbg_show,
987 .dt_node_to_map = sirfsoc_dt_node_to_map,
988 .dt_free_map = sirfsoc_dt_free_map,
989};
990
991struct sirfsoc_pmx_func {
992 const char *name;
993 const char * const *groups;
994 const unsigned num_groups;
995 const struct sirfsoc_padmux *padmux;
996};
997
998static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" }; 801static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
999static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" }; 802static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
1000static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; 803static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
@@ -1033,14 +836,6 @@ static const char * const spi0grp[] = { "spi0grp" };
1033static const char * const spi1grp[] = { "spi1grp" }; 836static const char * const spi1grp[] = { "spi1grp" };
1034static const char * const gpsgrp[] = { "gpsgrp" }; 837static const char * const gpsgrp[] = { "gpsgrp" };
1035 838
1036#define SIRFSOC_PMX_FUNCTION(n, g, m) \
1037 { \
1038 .name = n, \
1039 .groups = g, \
1040 .num_groups = ARRAY_SIZE(g), \
1041 .padmux = &m, \
1042 }
1043
1044static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = { 839static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1045 SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux), 840 SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
1046 SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux), 841 SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
@@ -1081,727 +876,12 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1081 SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux), 876 SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1082}; 877};
1083 878
1084static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, 879struct sirfsoc_pinctrl_data prima2_pinctrl_data = {
1085 bool enable) 880 (struct pinctrl_pin_desc *)sirfsoc_pads,
1086{ 881 ARRAY_SIZE(sirfsoc_pads),
1087 int i; 882 (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
1088 const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; 883 ARRAY_SIZE(sirfsoc_pin_groups),
1089 const struct sirfsoc_muxmask *mask = mux->muxmask; 884 (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
1090 885 ARRAY_SIZE(sirfsoc_pmx_functions),
1091 for (i = 0; i < mux->muxmask_counts; i++) {
1092 u32 muxval;
1093 if (!spmx->is_marco) {
1094 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1095 if (enable)
1096 muxval = muxval & ~mask[i].mask;
1097 else
1098 muxval = muxval | mask[i].mask;
1099 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1100 } else {
1101 if (enable)
1102 writel(mask[i].mask, spmx->gpio_virtbase +
1103 SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
1104 else
1105 writel(mask[i].mask, spmx->gpio_virtbase +
1106 SIRFSOC_GPIO_PAD_EN(mask[i].group));
1107 }
1108 }
1109
1110 if (mux->funcmask && enable) {
1111 u32 func_en_val;
1112 func_en_val =
1113 readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1114 func_en_val =
1115 (func_en_val & ~mux->funcmask) | (mux->
1116 funcval);
1117 writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1118 }
1119}
1120
1121static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
1122 unsigned group)
1123{
1124 struct sirfsoc_pmx *spmx;
1125
1126 spmx = pinctrl_dev_get_drvdata(pmxdev);
1127 sirfsoc_pinmux_endisable(spmx, selector, true);
1128
1129 return 0;
1130}
1131
1132static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
1133 unsigned group)
1134{
1135 struct sirfsoc_pmx *spmx;
1136
1137 spmx = pinctrl_dev_get_drvdata(pmxdev);
1138 sirfsoc_pinmux_endisable(spmx, selector, false);
1139}
1140
1141static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
1142{
1143 return ARRAY_SIZE(sirfsoc_pmx_functions);
1144}
1145
1146static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
1147 unsigned selector)
1148{
1149 return sirfsoc_pmx_functions[selector].name;
1150}
1151
1152static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1153 const char * const **groups,
1154 unsigned * const num_groups)
1155{
1156 *groups = sirfsoc_pmx_functions[selector].groups;
1157 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
1158 return 0;
1159}
1160
1161static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
1162 struct pinctrl_gpio_range *range, unsigned offset)
1163{
1164 struct sirfsoc_pmx *spmx;
1165
1166 int group = range->id;
1167
1168 u32 muxval;
1169
1170 spmx = pinctrl_dev_get_drvdata(pmxdev);
1171
1172 if (!spmx->is_marco) {
1173 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1174 muxval = muxval | (1 << (offset - range->pin_base));
1175 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1176 } else {
1177 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
1178 SIRFSOC_GPIO_PAD_EN(group));
1179 }
1180
1181 return 0;
1182}
1183
1184static const struct pinmux_ops sirfsoc_pinmux_ops = {
1185 .enable = sirfsoc_pinmux_enable,
1186 .disable = sirfsoc_pinmux_disable,
1187 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
1188 .get_function_name = sirfsoc_pinmux_get_func_name,
1189 .get_function_groups = sirfsoc_pinmux_get_groups,
1190 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
1191};
1192
1193static struct pinctrl_desc sirfsoc_pinmux_desc = {
1194 .name = DRIVER_NAME,
1195 .pins = sirfsoc_pads,
1196 .npins = ARRAY_SIZE(sirfsoc_pads),
1197 .pctlops = &sirfsoc_pctrl_ops,
1198 .pmxops = &sirfsoc_pinmux_ops,
1199 .owner = THIS_MODULE,
1200};
1201
1202/*
1203 * Todo: bind irq_chip to every pinctrl_gpio_range
1204 */
1205static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
1206 {
1207 .name = "sirfsoc-gpio*",
1208 .id = 0,
1209 .base = 0,
1210 .pin_base = 0,
1211 .npins = 32,
1212 }, {
1213 .name = "sirfsoc-gpio*",
1214 .id = 1,
1215 .base = 32,
1216 .pin_base = 32,
1217 .npins = 32,
1218 }, {
1219 .name = "sirfsoc-gpio*",
1220 .id = 2,
1221 .base = 64,
1222 .pin_base = 64,
1223 .npins = 32,
1224 }, {
1225 .name = "sirfsoc-gpio*",
1226 .id = 3,
1227 .base = 96,
1228 .pin_base = 96,
1229 .npins = 19,
1230 },
1231};
1232
1233static void __iomem *sirfsoc_rsc_of_iomap(void)
1234{
1235 const struct of_device_id rsc_ids[] = {
1236 { .compatible = "sirf,prima2-rsc" },
1237 { .compatible = "sirf,marco-rsc" },
1238 {}
1239 };
1240 struct device_node *np;
1241
1242 np = of_find_matching_node(NULL, rsc_ids);
1243 if (!np)
1244 panic("unable to find compatible rsc node in dtb\n");
1245
1246 return of_iomap(np, 0);
1247}
1248
1249static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
1250 const struct of_phandle_args *gpiospec,
1251 u32 *flags)
1252{
1253 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
1254 return -EINVAL;
1255
1256 if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc)
1257 return -EINVAL;
1258
1259 if (flags)
1260 *flags = gpiospec->args[1];
1261
1262 return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE;
1263}
1264
1265static int sirfsoc_pinmux_probe(struct platform_device *pdev)
1266{
1267 int ret;
1268 struct sirfsoc_pmx *spmx;
1269 struct device_node *np = pdev->dev.of_node;
1270 int i;
1271
1272 /* Create state holders etc for this driver */
1273 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
1274 if (!spmx)
1275 return -ENOMEM;
1276
1277 spmx->dev = &pdev->dev;
1278
1279 platform_set_drvdata(pdev, spmx);
1280
1281 spmx->gpio_virtbase = of_iomap(np, 0);
1282 if (!spmx->gpio_virtbase) {
1283 dev_err(&pdev->dev, "can't map gpio registers\n");
1284 return -ENOMEM;
1285 }
1286
1287 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
1288 if (!spmx->rsc_virtbase) {
1289 ret = -ENOMEM;
1290 dev_err(&pdev->dev, "can't map rsc registers\n");
1291 goto out_no_rsc_remap;
1292 }
1293
1294 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
1295 spmx->is_marco = 1;
1296
1297 /* Now register the pin controller and all pins it handles */
1298 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
1299 if (!spmx->pmx) {
1300 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
1301 ret = -EINVAL;
1302 goto out_no_pmx;
1303 }
1304
1305 for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
1306 sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
1307 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
1308 }
1309
1310 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
1311
1312 return 0;
1313
1314out_no_pmx:
1315 iounmap(spmx->rsc_virtbase);
1316out_no_rsc_remap:
1317 iounmap(spmx->gpio_virtbase);
1318 return ret;
1319}
1320
1321static const struct of_device_id pinmux_ids[] = {
1322 { .compatible = "sirf,prima2-pinctrl" },
1323 { .compatible = "sirf,marco-pinctrl" },
1324 {}
1325};
1326
1327static struct platform_driver sirfsoc_pinmux_driver = {
1328 .driver = {
1329 .name = DRIVER_NAME,
1330 .owner = THIS_MODULE,
1331 .of_match_table = pinmux_ids,
1332 },
1333 .probe = sirfsoc_pinmux_probe,
1334}; 886};
1335 887
1336static int __init sirfsoc_pinmux_init(void)
1337{
1338 return platform_driver_register(&sirfsoc_pinmux_driver);
1339}
1340arch_initcall(sirfsoc_pinmux_init);
1341
1342static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1343{
1344 struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
1345 struct sirfsoc_gpio_bank, chip);
1346
1347 return irq_create_mapping(bank->domain, offset);
1348}
1349
1350static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
1351{
1352 return gpio % SIRFSOC_GPIO_BANK_SIZE;
1353}
1354
1355static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
1356{
1357 return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
1358}
1359
1360static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
1361{
1362 return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
1363}
1364
1365static void sirfsoc_gpio_irq_ack(struct irq_data *d)
1366{
1367 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1368 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1369 u32 val, offset;
1370 unsigned long flags;
1371
1372 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1373
1374 spin_lock_irqsave(&sgpio_lock, flags);
1375
1376 val = readl(bank->chip.regs + offset);
1377
1378 writel(val, bank->chip.regs + offset);
1379
1380 spin_unlock_irqrestore(&sgpio_lock, flags);
1381}
1382
1383static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
1384{
1385 u32 val, offset;
1386 unsigned long flags;
1387
1388 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1389
1390 spin_lock_irqsave(&sgpio_lock, flags);
1391
1392 val = readl(bank->chip.regs + offset);
1393 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1394 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1395 writel(val, bank->chip.regs + offset);
1396
1397 spin_unlock_irqrestore(&sgpio_lock, flags);
1398}
1399
1400static void sirfsoc_gpio_irq_mask(struct irq_data *d)
1401{
1402 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1403
1404 __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
1405}
1406
1407static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
1408{
1409 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1410 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1411 u32 val, offset;
1412 unsigned long flags;
1413
1414 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1415
1416 spin_lock_irqsave(&sgpio_lock, flags);
1417
1418 val = readl(bank->chip.regs + offset);
1419 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1420 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1421 writel(val, bank->chip.regs + offset);
1422
1423 spin_unlock_irqrestore(&sgpio_lock, flags);
1424}
1425
1426static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
1427{
1428 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1429 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1430 u32 val, offset;
1431 unsigned long flags;
1432
1433 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1434
1435 spin_lock_irqsave(&sgpio_lock, flags);
1436
1437 val = readl(bank->chip.regs + offset);
1438 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1439
1440 switch (type) {
1441 case IRQ_TYPE_NONE:
1442 break;
1443 case IRQ_TYPE_EDGE_RISING:
1444 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1445 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1446 break;
1447 case IRQ_TYPE_EDGE_FALLING:
1448 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1449 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1450 break;
1451 case IRQ_TYPE_EDGE_BOTH:
1452 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
1453 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1454 break;
1455 case IRQ_TYPE_LEVEL_LOW:
1456 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1457 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1458 break;
1459 case IRQ_TYPE_LEVEL_HIGH:
1460 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1461 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1462 break;
1463 }
1464
1465 writel(val, bank->chip.regs + offset);
1466
1467 spin_unlock_irqrestore(&sgpio_lock, flags);
1468
1469 return 0;
1470}
1471
1472static struct irq_chip sirfsoc_irq_chip = {
1473 .name = "sirf-gpio-irq",
1474 .irq_ack = sirfsoc_gpio_irq_ack,
1475 .irq_mask = sirfsoc_gpio_irq_mask,
1476 .irq_unmask = sirfsoc_gpio_irq_unmask,
1477 .irq_set_type = sirfsoc_gpio_irq_type,
1478};
1479
1480static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
1481{
1482 struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
1483 u32 status, ctrl;
1484 int idx = 0;
1485 struct irq_chip *chip = irq_get_chip(irq);
1486
1487 chained_irq_enter(chip, desc);
1488
1489 status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
1490 if (!status) {
1491 printk(KERN_WARNING
1492 "%s: gpio id %d status %#x no interrupt is flaged\n",
1493 __func__, bank->id, status);
1494 handle_bad_irq(irq, desc);
1495 return;
1496 }
1497
1498 while (status) {
1499 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
1500
1501 /*
1502 * Here we must check whether the corresponding GPIO's interrupt
1503 * has been enabled, otherwise just skip it
1504 */
1505 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
1506 pr_debug("%s: gpio id %d idx %d happens\n",
1507 __func__, bank->id, idx);
1508 generic_handle_irq(irq_find_mapping(bank->domain, idx));
1509 }
1510
1511 idx++;
1512 status = status >> 1;
1513 }
1514
1515 chained_irq_exit(chip, desc);
1516}
1517
1518static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
1519{
1520 u32 val;
1521
1522 val = readl(bank->chip.regs + ctrl_offset);
1523 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1524 writel(val, bank->chip.regs + ctrl_offset);
1525}
1526
1527static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
1528{
1529 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1530 unsigned long flags;
1531
1532 if (pinctrl_request_gpio(chip->base + offset))
1533 return -ENODEV;
1534
1535 spin_lock_irqsave(&bank->lock, flags);
1536
1537 /*
1538 * default status:
1539 * set direction as input and mask irq
1540 */
1541 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1542 __sirfsoc_gpio_irq_mask(bank, offset);
1543
1544 spin_unlock_irqrestore(&bank->lock, flags);
1545
1546 return 0;
1547}
1548
1549static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
1550{
1551 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1552 unsigned long flags;
1553
1554 spin_lock_irqsave(&bank->lock, flags);
1555
1556 __sirfsoc_gpio_irq_mask(bank, offset);
1557 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1558
1559 spin_unlock_irqrestore(&bank->lock, flags);
1560
1561 pinctrl_free_gpio(chip->base + offset);
1562}
1563
1564static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1565{
1566 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1567 int idx = sirfsoc_gpio_to_offset(gpio);
1568 unsigned long flags;
1569 unsigned offset;
1570
1571 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1572
1573 spin_lock_irqsave(&bank->lock, flags);
1574
1575 sirfsoc_gpio_set_input(bank, offset);
1576
1577 spin_unlock_irqrestore(&bank->lock, flags);
1578
1579 return 0;
1580}
1581
1582static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
1583 int value)
1584{
1585 u32 out_ctrl;
1586 unsigned long flags;
1587
1588 spin_lock_irqsave(&bank->lock, flags);
1589
1590 out_ctrl = readl(bank->chip.regs + offset);
1591 if (value)
1592 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1593 else
1594 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1595
1596 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1597 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1598 writel(out_ctrl, bank->chip.regs + offset);
1599
1600 spin_unlock_irqrestore(&bank->lock, flags);
1601}
1602
1603static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1604{
1605 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1606 int idx = sirfsoc_gpio_to_offset(gpio);
1607 u32 offset;
1608 unsigned long flags;
1609
1610 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1611
1612 spin_lock_irqsave(&sgpio_lock, flags);
1613
1614 sirfsoc_gpio_set_output(bank, offset, value);
1615
1616 spin_unlock_irqrestore(&sgpio_lock, flags);
1617
1618 return 0;
1619}
1620
1621static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
1622{
1623 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1624 u32 val;
1625 unsigned long flags;
1626
1627 spin_lock_irqsave(&bank->lock, flags);
1628
1629 val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1630
1631 spin_unlock_irqrestore(&bank->lock, flags);
1632
1633 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
1634}
1635
1636static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
1637 int value)
1638{
1639 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1640 u32 ctrl;
1641 unsigned long flags;
1642
1643 spin_lock_irqsave(&bank->lock, flags);
1644
1645 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1646 if (value)
1647 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1648 else
1649 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1650 writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1651
1652 spin_unlock_irqrestore(&bank->lock, flags);
1653}
1654
1655static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1656 irq_hw_number_t hwirq)
1657{
1658 struct sirfsoc_gpio_bank *bank = d->host_data;
1659
1660 if (!bank)
1661 return -EINVAL;
1662
1663 irq_set_chip(irq, &sirfsoc_irq_chip);
1664 irq_set_handler(irq, handle_level_irq);
1665 irq_set_chip_data(irq, bank);
1666 set_irq_flags(irq, IRQF_VALID);
1667
1668 return 0;
1669}
1670
1671const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
1672 .map = sirfsoc_gpio_irq_map,
1673 .xlate = irq_domain_xlate_twocell,
1674};
1675
1676static void sirfsoc_gpio_set_pullup(const u32 *pullups)
1677{
1678 int i, n;
1679 const unsigned long *p = (const unsigned long *)pullups;
1680
1681 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1682 for_each_set_bit(n, p + i, BITS_PER_LONG) {
1683 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
1684 u32 val = readl(sgpio_bank[i].chip.regs + offset);
1685 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1686 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
1687 writel(val, sgpio_bank[i].chip.regs + offset);
1688 }
1689 }
1690}
1691
1692static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
1693{
1694 int i, n;
1695 const unsigned long *p = (const unsigned long *)pulldowns;
1696
1697 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1698 for_each_set_bit(n, p + i, BITS_PER_LONG) {
1699 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
1700 u32 val = readl(sgpio_bank[i].chip.regs + offset);
1701 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1702 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
1703 writel(val, sgpio_bank[i].chip.regs + offset);
1704 }
1705 }
1706}
1707
1708static int sirfsoc_gpio_probe(struct device_node *np)
1709{
1710 int i, err = 0;
1711 struct sirfsoc_gpio_bank *bank;
1712 void *regs;
1713 struct platform_device *pdev;
1714 bool is_marco = false;
1715
1716 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
1717
1718 pdev = of_find_device_by_node(np);
1719 if (!pdev)
1720 return -ENODEV;
1721
1722 regs = of_iomap(np, 0);
1723 if (!regs)
1724 return -ENOMEM;
1725
1726 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
1727 is_marco = 1;
1728
1729 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1730 bank = &sgpio_bank[i];
1731 spin_lock_init(&bank->lock);
1732 bank->chip.gc.request = sirfsoc_gpio_request;
1733 bank->chip.gc.free = sirfsoc_gpio_free;
1734 bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
1735 bank->chip.gc.get = sirfsoc_gpio_get_value;
1736 bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
1737 bank->chip.gc.set = sirfsoc_gpio_set_value;
1738 bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
1739 bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
1740 bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
1741 bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
1742 bank->chip.gc.of_node = np;
1743 bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
1744 bank->chip.gc.of_gpio_n_cells = 2;
1745 bank->chip.regs = regs;
1746 bank->id = i;
1747 bank->is_marco = is_marco;
1748 bank->parent_irq = platform_get_irq(pdev, i);
1749 if (bank->parent_irq < 0) {
1750 err = bank->parent_irq;
1751 goto out;
1752 }
1753
1754 err = gpiochip_add(&bank->chip.gc);
1755 if (err) {
1756 pr_err("%s: error in probe function with status %d\n",
1757 np->full_name, err);
1758 goto out;
1759 }
1760
1761 bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
1762 &sirfsoc_gpio_irq_simple_ops, bank);
1763
1764 if (!bank->domain) {
1765 pr_err("%s: Failed to create irqdomain\n", np->full_name);
1766 err = -ENOSYS;
1767 goto out;
1768 }
1769
1770 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
1771 irq_set_handler_data(bank->parent_irq, bank);
1772 }
1773
1774 if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
1775 SIRFSOC_GPIO_NO_OF_BANKS))
1776 sirfsoc_gpio_set_pullup(pullups);
1777
1778 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
1779 SIRFSOC_GPIO_NO_OF_BANKS))
1780 sirfsoc_gpio_set_pulldown(pulldowns);
1781
1782 return 0;
1783
1784out:
1785 iounmap(regs);
1786 return err;
1787}
1788
1789static int __init sirfsoc_gpio_init(void)
1790{
1791
1792 struct device_node *np;
1793
1794 np = of_find_matching_node(NULL, pinmux_ids);
1795
1796 if (!np)
1797 return -ENODEV;
1798
1799 return sirfsoc_gpio_probe(np);
1800}
1801subsys_initcall(sirfsoc_gpio_init);
1802
1803MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
1804 "Yuping Luo <yuping.luo@csr.com>, "
1805 "Barry Song <baohua.song@csr.com>");
1806MODULE_DESCRIPTION("SIRFSOC pin control driver");
1807MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
new file mode 100644
index 000000000000..b4727db65504
--- /dev/null
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -0,0 +1,873 @@
1/*
2 * pinmux driver for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/irq.h>
12#include <linux/platform_device.h>
13#include <linux/io.h>
14#include <linux/slab.h>
15#include <linux/err.h>
16#include <linux/irqdomain.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/pinctrl/pinmux.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_device.h>
25#include <linux/of_platform.h>
26#include <linux/bitops.h>
27#include <linux/gpio.h>
28#include <linux/of_gpio.h>
29#include <asm/mach/irq.h>
30
31#include "pinctrl-sirf.h"
32
33#define DRIVER_NAME "pinmux-sirf"
34
35struct sirfsoc_gpio_bank {
36 struct of_mm_gpio_chip chip;
37 struct irq_domain *domain;
38 int id;
39 int parent_irq;
40 spinlock_t lock;
41 bool is_marco; /* for marco, some registers are different with prima2 */
42};
43
44static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
45static DEFINE_SPINLOCK(sgpio_lock);
46
47static struct sirfsoc_pin_group *sirfsoc_pin_groups;
48static int sirfsoc_pingrp_cnt;
49
50static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
51{
52 return sirfsoc_pingrp_cnt;
53}
54
55static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
56 unsigned selector)
57{
58 return sirfsoc_pin_groups[selector].name;
59}
60
61static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
62 const unsigned **pins,
63 unsigned *num_pins)
64{
65 *pins = sirfsoc_pin_groups[selector].pins;
66 *num_pins = sirfsoc_pin_groups[selector].num_pins;
67 return 0;
68}
69
70static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
71 unsigned offset)
72{
73 seq_printf(s, " " DRIVER_NAME);
74}
75
76static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
77 struct device_node *np_config,
78 struct pinctrl_map **map, unsigned *num_maps)
79{
80 struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
81 struct device_node *np;
82 struct property *prop;
83 const char *function, *group;
84 int ret, index = 0, count = 0;
85
86 /* calculate number of maps required */
87 for_each_child_of_node(np_config, np) {
88 ret = of_property_read_string(np, "sirf,function", &function);
89 if (ret < 0)
90 return ret;
91
92 ret = of_property_count_strings(np, "sirf,pins");
93 if (ret < 0)
94 return ret;
95
96 count += ret;
97 }
98
99 if (!count) {
100 dev_err(spmx->dev, "No child nodes passed via DT\n");
101 return -ENODEV;
102 }
103
104 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
105 if (!*map)
106 return -ENOMEM;
107
108 for_each_child_of_node(np_config, np) {
109 of_property_read_string(np, "sirf,function", &function);
110 of_property_for_each_string(np, "sirf,pins", prop, group) {
111 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
112 (*map)[index].data.mux.group = group;
113 (*map)[index].data.mux.function = function;
114 index++;
115 }
116 }
117
118 *num_maps = count;
119
120 return 0;
121}
122
123static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
124 struct pinctrl_map *map, unsigned num_maps)
125{
126 kfree(map);
127}
128
129static struct pinctrl_ops sirfsoc_pctrl_ops = {
130 .get_groups_count = sirfsoc_get_groups_count,
131 .get_group_name = sirfsoc_get_group_name,
132 .get_group_pins = sirfsoc_get_group_pins,
133 .pin_dbg_show = sirfsoc_pin_dbg_show,
134 .dt_node_to_map = sirfsoc_dt_node_to_map,
135 .dt_free_map = sirfsoc_dt_free_map,
136};
137
138static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
139static int sirfsoc_pmxfunc_cnt;
140
141static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
142 bool enable)
143{
144 int i;
145 const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
146 const struct sirfsoc_muxmask *mask = mux->muxmask;
147
148 for (i = 0; i < mux->muxmask_counts; i++) {
149 u32 muxval;
150 if (!spmx->is_marco) {
151 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
152 if (enable)
153 muxval = muxval & ~mask[i].mask;
154 else
155 muxval = muxval | mask[i].mask;
156 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
157 } else {
158 if (enable)
159 writel(mask[i].mask, spmx->gpio_virtbase +
160 SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
161 else
162 writel(mask[i].mask, spmx->gpio_virtbase +
163 SIRFSOC_GPIO_PAD_EN(mask[i].group));
164 }
165 }
166
167 if (mux->funcmask && enable) {
168 u32 func_en_val;
169 func_en_val =
170 readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
171 func_en_val =
172 (func_en_val & ~mux->funcmask) | (mux->
173 funcval);
174 writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
175 }
176}
177
178static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
179 unsigned group)
180{
181 struct sirfsoc_pmx *spmx;
182
183 spmx = pinctrl_dev_get_drvdata(pmxdev);
184 sirfsoc_pinmux_endisable(spmx, selector, true);
185
186 return 0;
187}
188
189static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
190 unsigned group)
191{
192 struct sirfsoc_pmx *spmx;
193
194 spmx = pinctrl_dev_get_drvdata(pmxdev);
195 sirfsoc_pinmux_endisable(spmx, selector, false);
196}
197
198static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
199{
200 return sirfsoc_pmxfunc_cnt;
201}
202
203static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
204 unsigned selector)
205{
206 return sirfsoc_pmx_functions[selector].name;
207}
208
209static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
210 const char * const **groups,
211 unsigned * const num_groups)
212{
213 *groups = sirfsoc_pmx_functions[selector].groups;
214 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
215 return 0;
216}
217
218static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
219 struct pinctrl_gpio_range *range, unsigned offset)
220{
221 struct sirfsoc_pmx *spmx;
222
223 int group = range->id;
224
225 u32 muxval;
226
227 spmx = pinctrl_dev_get_drvdata(pmxdev);
228
229 if (!spmx->is_marco) {
230 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
231 muxval = muxval | (1 << (offset - range->pin_base));
232 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
233 } else {
234 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
235 SIRFSOC_GPIO_PAD_EN(group));
236 }
237
238 return 0;
239}
240
241static struct pinmux_ops sirfsoc_pinmux_ops = {
242 .enable = sirfsoc_pinmux_enable,
243 .disable = sirfsoc_pinmux_disable,
244 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
245 .get_function_name = sirfsoc_pinmux_get_func_name,
246 .get_function_groups = sirfsoc_pinmux_get_groups,
247 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
248};
249
250static struct pinctrl_desc sirfsoc_pinmux_desc = {
251 .name = DRIVER_NAME,
252 .pctlops = &sirfsoc_pctrl_ops,
253 .pmxops = &sirfsoc_pinmux_ops,
254 .owner = THIS_MODULE,
255};
256
257/*
258 * Todo: bind irq_chip to every pinctrl_gpio_range
259 */
260static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
261 {
262 .name = "sirfsoc-gpio*",
263 .id = 0,
264 .base = 0,
265 .pin_base = 0,
266 .npins = 32,
267 }, {
268 .name = "sirfsoc-gpio*",
269 .id = 1,
270 .base = 32,
271 .pin_base = 32,
272 .npins = 32,
273 }, {
274 .name = "sirfsoc-gpio*",
275 .id = 2,
276 .base = 64,
277 .pin_base = 64,
278 .npins = 32,
279 }, {
280 .name = "sirfsoc-gpio*",
281 .id = 3,
282 .base = 96,
283 .pin_base = 96,
284 .npins = 19,
285 },
286};
287
288static void __iomem *sirfsoc_rsc_of_iomap(void)
289{
290 const struct of_device_id rsc_ids[] = {
291 { .compatible = "sirf,prima2-rsc" },
292 { .compatible = "sirf,marco-rsc" },
293 {}
294 };
295 struct device_node *np;
296
297 np = of_find_matching_node(NULL, rsc_ids);
298 if (!np)
299 panic("unable to find compatible rsc node in dtb\n");
300
301 return of_iomap(np, 0);
302}
303
304static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
305 const struct of_phandle_args *gpiospec,
306 u32 *flags)
307{
308 if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
309 return -EINVAL;
310
311 if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc)
312 return -EINVAL;
313
314 if (flags)
315 *flags = gpiospec->args[1];
316
317 return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE;
318}
319
320static const struct of_device_id pinmux_ids[] = {
321 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
322 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
323 { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, },
324 {}
325};
326
327static int sirfsoc_pinmux_probe(struct platform_device *pdev)
328{
329 int ret;
330 struct sirfsoc_pmx *spmx;
331 struct device_node *np = pdev->dev.of_node;
332 const struct sirfsoc_pinctrl_data *pdata;
333 int i;
334
335 /* Create state holders etc for this driver */
336 spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
337 if (!spmx)
338 return -ENOMEM;
339
340 spmx->dev = &pdev->dev;
341
342 platform_set_drvdata(pdev, spmx);
343
344 spmx->gpio_virtbase = of_iomap(np, 0);
345 if (!spmx->gpio_virtbase) {
346 dev_err(&pdev->dev, "can't map gpio registers\n");
347 return -ENOMEM;
348 }
349
350 spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
351 if (!spmx->rsc_virtbase) {
352 ret = -ENOMEM;
353 dev_err(&pdev->dev, "can't map rsc registers\n");
354 goto out_no_rsc_remap;
355 }
356
357 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
358 spmx->is_marco = 1;
359
360 pdata = of_match_node(pinmux_ids, np)->data;
361 sirfsoc_pin_groups = pdata->grps;
362 sirfsoc_pingrp_cnt = pdata->grps_cnt;
363 sirfsoc_pmx_functions = pdata->funcs;
364 sirfsoc_pmxfunc_cnt = pdata->funcs_cnt;
365 sirfsoc_pinmux_desc.pins = pdata->pads;
366 sirfsoc_pinmux_desc.npins = pdata->pads_cnt;
367
368
369 /* Now register the pin controller and all pins it handles */
370 spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
371 if (!spmx->pmx) {
372 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
373 ret = -EINVAL;
374 goto out_no_pmx;
375 }
376
377 for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
378 sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
379 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
380 }
381
382 dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
383
384 return 0;
385
386out_no_pmx:
387 iounmap(spmx->rsc_virtbase);
388out_no_rsc_remap:
389 iounmap(spmx->gpio_virtbase);
390 return ret;
391}
392
393static struct platform_driver sirfsoc_pinmux_driver = {
394 .driver = {
395 .name = DRIVER_NAME,
396 .owner = THIS_MODULE,
397 .of_match_table = pinmux_ids,
398 },
399 .probe = sirfsoc_pinmux_probe,
400};
401
402static int __init sirfsoc_pinmux_init(void)
403{
404 return platform_driver_register(&sirfsoc_pinmux_driver);
405}
406arch_initcall(sirfsoc_pinmux_init);
407
408static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
409{
410 struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
411 struct sirfsoc_gpio_bank, chip);
412
413 return irq_create_mapping(bank->domain, offset);
414}
415
416static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
417{
418 return gpio % SIRFSOC_GPIO_BANK_SIZE;
419}
420
421static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
422{
423 return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
424}
425
426static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
427{
428 return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
429}
430
431static void sirfsoc_gpio_irq_ack(struct irq_data *d)
432{
433 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
434 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
435 u32 val, offset;
436 unsigned long flags;
437
438 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
439
440 spin_lock_irqsave(&sgpio_lock, flags);
441
442 val = readl(bank->chip.regs + offset);
443
444 writel(val, bank->chip.regs + offset);
445
446 spin_unlock_irqrestore(&sgpio_lock, flags);
447}
448
449static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
450{
451 u32 val, offset;
452 unsigned long flags;
453
454 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
455
456 spin_lock_irqsave(&sgpio_lock, flags);
457
458 val = readl(bank->chip.regs + offset);
459 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
460 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
461 writel(val, bank->chip.regs + offset);
462
463 spin_unlock_irqrestore(&sgpio_lock, flags);
464}
465
466static void sirfsoc_gpio_irq_mask(struct irq_data *d)
467{
468 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
469
470 __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
471}
472
473static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
474{
475 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
476 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
477 u32 val, offset;
478 unsigned long flags;
479
480 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
481
482 spin_lock_irqsave(&sgpio_lock, flags);
483
484 val = readl(bank->chip.regs + offset);
485 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
486 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
487 writel(val, bank->chip.regs + offset);
488
489 spin_unlock_irqrestore(&sgpio_lock, flags);
490}
491
492static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
493{
494 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
495 int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
496 u32 val, offset;
497 unsigned long flags;
498
499 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
500
501 spin_lock_irqsave(&sgpio_lock, flags);
502
503 val = readl(bank->chip.regs + offset);
504 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
505
506 switch (type) {
507 case IRQ_TYPE_NONE:
508 break;
509 case IRQ_TYPE_EDGE_RISING:
510 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
511 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
512 break;
513 case IRQ_TYPE_EDGE_FALLING:
514 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
515 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
516 break;
517 case IRQ_TYPE_EDGE_BOTH:
518 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
519 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
520 break;
521 case IRQ_TYPE_LEVEL_LOW:
522 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
523 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
524 break;
525 case IRQ_TYPE_LEVEL_HIGH:
526 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
527 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
528 break;
529 }
530
531 writel(val, bank->chip.regs + offset);
532
533 spin_unlock_irqrestore(&sgpio_lock, flags);
534
535 return 0;
536}
537
538static struct irq_chip sirfsoc_irq_chip = {
539 .name = "sirf-gpio-irq",
540 .irq_ack = sirfsoc_gpio_irq_ack,
541 .irq_mask = sirfsoc_gpio_irq_mask,
542 .irq_unmask = sirfsoc_gpio_irq_unmask,
543 .irq_set_type = sirfsoc_gpio_irq_type,
544};
545
546static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
547{
548 struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
549 u32 status, ctrl;
550 int idx = 0;
551 struct irq_chip *chip = irq_get_chip(irq);
552
553 chained_irq_enter(chip, desc);
554
555 status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
556 if (!status) {
557 printk(KERN_WARNING
558 "%s: gpio id %d status %#x no interrupt is flaged\n",
559 __func__, bank->id, status);
560 handle_bad_irq(irq, desc);
561 return;
562 }
563
564 while (status) {
565 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
566
567 /*
568 * Here we must check whether the corresponding GPIO's interrupt
569 * has been enabled, otherwise just skip it
570 */
571 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
572 pr_debug("%s: gpio id %d idx %d happens\n",
573 __func__, bank->id, idx);
574 generic_handle_irq(irq_find_mapping(bank->domain, idx));
575 }
576
577 idx++;
578 status = status >> 1;
579 }
580
581 chained_irq_exit(chip, desc);
582}
583
584static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
585{
586 u32 val;
587
588 val = readl(bank->chip.regs + ctrl_offset);
589 val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
590 writel(val, bank->chip.regs + ctrl_offset);
591}
592
593static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
594{
595 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
596 unsigned long flags;
597
598 if (pinctrl_request_gpio(chip->base + offset))
599 return -ENODEV;
600
601 spin_lock_irqsave(&bank->lock, flags);
602
603 /*
604 * default status:
605 * set direction as input and mask irq
606 */
607 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
608 __sirfsoc_gpio_irq_mask(bank, offset);
609
610 spin_unlock_irqrestore(&bank->lock, flags);
611
612 return 0;
613}
614
615static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
616{
617 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
618 unsigned long flags;
619
620 spin_lock_irqsave(&bank->lock, flags);
621
622 __sirfsoc_gpio_irq_mask(bank, offset);
623 sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
624
625 spin_unlock_irqrestore(&bank->lock, flags);
626
627 pinctrl_free_gpio(chip->base + offset);
628}
629
630static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
631{
632 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
633 int idx = sirfsoc_gpio_to_offset(gpio);
634 unsigned long flags;
635 unsigned offset;
636
637 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
638
639 spin_lock_irqsave(&bank->lock, flags);
640
641 sirfsoc_gpio_set_input(bank, offset);
642
643 spin_unlock_irqrestore(&bank->lock, flags);
644
645 return 0;
646}
647
648static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
649 int value)
650{
651 u32 out_ctrl;
652 unsigned long flags;
653
654 spin_lock_irqsave(&bank->lock, flags);
655
656 out_ctrl = readl(bank->chip.regs + offset);
657 if (value)
658 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
659 else
660 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
661
662 out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
663 out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
664 writel(out_ctrl, bank->chip.regs + offset);
665
666 spin_unlock_irqrestore(&bank->lock, flags);
667}
668
669static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
670{
671 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
672 int idx = sirfsoc_gpio_to_offset(gpio);
673 u32 offset;
674 unsigned long flags;
675
676 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
677
678 spin_lock_irqsave(&sgpio_lock, flags);
679
680 sirfsoc_gpio_set_output(bank, offset, value);
681
682 spin_unlock_irqrestore(&sgpio_lock, flags);
683
684 return 0;
685}
686
687static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
688{
689 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
690 u32 val;
691 unsigned long flags;
692
693 spin_lock_irqsave(&bank->lock, flags);
694
695 val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
696
697 spin_unlock_irqrestore(&bank->lock, flags);
698
699 return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
700}
701
702static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
703 int value)
704{
705 struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
706 u32 ctrl;
707 unsigned long flags;
708
709 spin_lock_irqsave(&bank->lock, flags);
710
711 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
712 if (value)
713 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
714 else
715 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
716 writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
717
718 spin_unlock_irqrestore(&bank->lock, flags);
719}
720
721static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
722 irq_hw_number_t hwirq)
723{
724 struct sirfsoc_gpio_bank *bank = d->host_data;
725
726 if (!bank)
727 return -EINVAL;
728
729 irq_set_chip(irq, &sirfsoc_irq_chip);
730 irq_set_handler(irq, handle_level_irq);
731 irq_set_chip_data(irq, bank);
732 set_irq_flags(irq, IRQF_VALID);
733
734 return 0;
735}
736
737static const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
738 .map = sirfsoc_gpio_irq_map,
739 .xlate = irq_domain_xlate_twocell,
740};
741
742static void sirfsoc_gpio_set_pullup(const u32 *pullups)
743{
744 int i, n;
745 const unsigned long *p = (const unsigned long *)pullups;
746
747 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
748 for_each_set_bit(n, p + i, BITS_PER_LONG) {
749 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
750 u32 val = readl(sgpio_bank[i].chip.regs + offset);
751 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
752 val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
753 writel(val, sgpio_bank[i].chip.regs + offset);
754 }
755 }
756}
757
758static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
759{
760 int i, n;
761 const unsigned long *p = (const unsigned long *)pulldowns;
762
763 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
764 for_each_set_bit(n, p + i, BITS_PER_LONG) {
765 u32 offset = SIRFSOC_GPIO_CTRL(i, n);
766 u32 val = readl(sgpio_bank[i].chip.regs + offset);
767 val |= SIRFSOC_GPIO_CTL_PULL_MASK;
768 val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
769 writel(val, sgpio_bank[i].chip.regs + offset);
770 }
771 }
772}
773
774static int sirfsoc_gpio_probe(struct device_node *np)
775{
776 int i, err = 0;
777 struct sirfsoc_gpio_bank *bank;
778 void *regs;
779 struct platform_device *pdev;
780 bool is_marco = false;
781
782 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
783
784 pdev = of_find_device_by_node(np);
785 if (!pdev)
786 return -ENODEV;
787
788 regs = of_iomap(np, 0);
789 if (!regs)
790 return -ENOMEM;
791
792 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
793 is_marco = 1;
794
795 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
796 bank = &sgpio_bank[i];
797 spin_lock_init(&bank->lock);
798 bank->chip.gc.request = sirfsoc_gpio_request;
799 bank->chip.gc.free = sirfsoc_gpio_free;
800 bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
801 bank->chip.gc.get = sirfsoc_gpio_get_value;
802 bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
803 bank->chip.gc.set = sirfsoc_gpio_set_value;
804 bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
805 bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
806 bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
807 bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
808 bank->chip.gc.of_node = np;
809 bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
810 bank->chip.gc.of_gpio_n_cells = 2;
811 bank->chip.regs = regs;
812 bank->id = i;
813 bank->is_marco = is_marco;
814 bank->parent_irq = platform_get_irq(pdev, i);
815 if (bank->parent_irq < 0) {
816 err = bank->parent_irq;
817 goto out;
818 }
819
820 err = gpiochip_add(&bank->chip.gc);
821 if (err) {
822 pr_err("%s: error in probe function with status %d\n",
823 np->full_name, err);
824 goto out;
825 }
826
827 bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
828 &sirfsoc_gpio_irq_simple_ops, bank);
829
830 if (!bank->domain) {
831 pr_err("%s: Failed to create irqdomain\n", np->full_name);
832 err = -ENOSYS;
833 goto out;
834 }
835
836 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
837 irq_set_handler_data(bank->parent_irq, bank);
838 }
839
840 if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
841 SIRFSOC_GPIO_NO_OF_BANKS))
842 sirfsoc_gpio_set_pullup(pullups);
843
844 if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
845 SIRFSOC_GPIO_NO_OF_BANKS))
846 sirfsoc_gpio_set_pulldown(pulldowns);
847
848 return 0;
849
850out:
851 iounmap(regs);
852 return err;
853}
854
855static int __init sirfsoc_gpio_init(void)
856{
857
858 struct device_node *np;
859
860 np = of_find_matching_node(NULL, pinmux_ids);
861
862 if (!np)
863 return -ENODEV;
864
865 return sirfsoc_gpio_probe(np);
866}
867subsys_initcall(sirfsoc_gpio_init);
868
869MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
870 "Yuping Luo <yuping.luo@csr.com>, "
871 "Barry Song <baohua.song@csr.com>");
872MODULE_DESCRIPTION("SIRFSOC pin control driver");
873MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h
new file mode 100644
index 000000000000..17cc108510ba
--- /dev/null
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.h
@@ -0,0 +1,116 @@
1/*
2 * pinmux driver shared headfile for CSR SiRFsoc
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __PINMUX_SIRF_H__
10#define __PINMUX_SIRF_H__
11
12#define SIRFSOC_NUM_PADS 622
13#define SIRFSOC_RSC_PIN_MUX 0x4
14
15#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
16#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90)
17#define SIRFSOC_GPIO_CTRL(g, i) ((g)*0x100 + (i)*4)
18#define SIRFSOC_GPIO_DSP_EN0 (0x80)
19#define SIRFSOC_GPIO_INT_STATUS(g) ((g)*0x100 + 0x8C)
20
21#define SIRFSOC_GPIO_CTL_INTR_LOW_MASK 0x1
22#define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK 0x2
23#define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK 0x4
24#define SIRFSOC_GPIO_CTL_INTR_EN_MASK 0x8
25#define SIRFSOC_GPIO_CTL_INTR_STS_MASK 0x10
26#define SIRFSOC_GPIO_CTL_OUT_EN_MASK 0x20
27#define SIRFSOC_GPIO_CTL_DATAOUT_MASK 0x40
28#define SIRFSOC_GPIO_CTL_DATAIN_MASK 0x80
29#define SIRFSOC_GPIO_CTL_PULL_MASK 0x100
30#define SIRFSOC_GPIO_CTL_PULL_HIGH 0x200
31#define SIRFSOC_GPIO_CTL_DSP_INT 0x400
32
33#define SIRFSOC_GPIO_NO_OF_BANKS 5
34#define SIRFSOC_GPIO_BANK_SIZE 32
35#define SIRFSOC_GPIO_NUM(bank, index) (((bank)*(32)) + (index))
36
37/**
38 * @dev: a pointer back to containing device
39 * @virtbase: the offset to the controller in virtual memory
40 */
41struct sirfsoc_pmx {
42 struct device *dev;
43 struct pinctrl_dev *pmx;
44 void __iomem *gpio_virtbase;
45 void __iomem *rsc_virtbase;
46 u32 gpio_regs[SIRFSOC_GPIO_NO_OF_BANKS][SIRFSOC_GPIO_BANK_SIZE];
47 u32 ints_regs[SIRFSOC_GPIO_NO_OF_BANKS];
48 u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS];
49 u32 dspen_regs;
50 u32 rsc_regs[3];
51 bool is_marco;
52};
53
54/* SIRFSOC_GPIO_PAD_EN set */
55struct sirfsoc_muxmask {
56 unsigned long group;
57 unsigned long mask;
58};
59
60struct sirfsoc_padmux {
61 unsigned long muxmask_counts;
62 const struct sirfsoc_muxmask *muxmask;
63 /* RSC_PIN_MUX set */
64 unsigned long funcmask;
65 unsigned long funcval;
66};
67
68 /**
69 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
70 * @name: the name of this specific pin group
71 * @pins: an array of discrete physical pins used in this group, taken
72 * from the driver-local pin enumeration space
73 * @num_pins: the number of pins in this group array, i.e. the number of
74 * elements in .pins so we can iterate over that array
75 */
76struct sirfsoc_pin_group {
77 const char *name;
78 const unsigned int *pins;
79 const unsigned num_pins;
80};
81
82#define SIRFSOC_PIN_GROUP(n, p) \
83 { \
84 .name = n, \
85 .pins = p, \
86 .num_pins = ARRAY_SIZE(p), \
87 }
88
89struct sirfsoc_pmx_func {
90 const char *name;
91 const char * const *groups;
92 const unsigned num_groups;
93 const struct sirfsoc_padmux *padmux;
94};
95
96#define SIRFSOC_PMX_FUNCTION(n, g, m) \
97 { \
98 .name = n, \
99 .groups = g, \
100 .num_groups = ARRAY_SIZE(g), \
101 .padmux = &m, \
102 }
103
104struct sirfsoc_pinctrl_data {
105 struct pinctrl_pin_desc *pads;
106 int pads_cnt;
107 struct sirfsoc_pin_group *grps;
108 int grps_cnt;
109 struct sirfsoc_pmx_func *funcs;
110 int funcs_cnt;
111};
112
113extern struct sirfsoc_pinctrl_data prima2_pinctrl_data;
114extern struct sirfsoc_pinctrl_data atlas6_pinctrl_data;
115
116#endif
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