diff options
author | H Hartley Sweeten <hsweeten@visionengravers.com> | 2017-08-08 16:51:27 -0400 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2017-08-09 12:52:57 -0400 |
commit | 16779622be1c8959d6a665e2b6886bb33885fcb1 (patch) | |
tree | 7be1f51f47534c97d3d9f15daa2a3c918bdcc836 /drivers | |
parent | 8447e4781f033f56cb18c2ec0301ea5d207877fc (diff) |
spi: spi-ep93xx: add spi master prepare_transfer_hardware()
This driver currently enables the hardware at the start of every
message and disabled it when the message is complete. Make it a
bit smarter by adding the prepare_transfer_hardware() and
unprepare_transfer_hardware() callbacks so that the core can
enable/disable the hardware based on spi message queue.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
[chris: use u32 instead of unsigned int]
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/spi/spi-ep93xx.c | 72 |
1 files changed, 33 insertions, 39 deletions
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c index 0bd792020471..ce6ec164f2f2 100644 --- a/drivers/spi/spi-ep93xx.c +++ b/drivers/spi/spi-ep93xx.c | |||
@@ -111,33 +111,6 @@ struct ep93xx_spi { | |||
111 | /* converts bits per word to CR0.DSS value */ | 111 | /* converts bits per word to CR0.DSS value */ |
112 | #define bits_per_word_to_dss(bpw) ((bpw) - 1) | 112 | #define bits_per_word_to_dss(bpw) ((bpw) - 1) |
113 | 113 | ||
114 | static int ep93xx_spi_enable(const struct ep93xx_spi *espi) | ||
115 | { | ||
116 | u32 val; | ||
117 | int err; | ||
118 | |||
119 | err = clk_enable(espi->clk); | ||
120 | if (err) | ||
121 | return err; | ||
122 | |||
123 | val = readl(espi->mmio + SSPCR1); | ||
124 | val |= SSPCR1_SSE; | ||
125 | writel(val, espi->mmio + SSPCR1); | ||
126 | |||
127 | return 0; | ||
128 | } | ||
129 | |||
130 | static void ep93xx_spi_disable(const struct ep93xx_spi *espi) | ||
131 | { | ||
132 | u32 val; | ||
133 | |||
134 | val = readl(espi->mmio + SSPCR1); | ||
135 | val &= ~SSPCR1_SSE; | ||
136 | writel(val, espi->mmio + SSPCR1); | ||
137 | |||
138 | clk_disable(espi->clk); | ||
139 | } | ||
140 | |||
141 | static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi) | 114 | static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi) |
142 | { | 115 | { |
143 | u32 val; | 116 | u32 val; |
@@ -571,17 +544,6 @@ static void ep93xx_spi_process_message(struct ep93xx_spi *espi, | |||
571 | { | 544 | { |
572 | unsigned long timeout; | 545 | unsigned long timeout; |
573 | struct spi_transfer *t; | 546 | struct spi_transfer *t; |
574 | int err; | ||
575 | |||
576 | /* | ||
577 | * Enable the SPI controller and its clock. | ||
578 | */ | ||
579 | err = ep93xx_spi_enable(espi); | ||
580 | if (err) { | ||
581 | dev_err(&espi->pdev->dev, "failed to enable SPI controller\n"); | ||
582 | msg->status = err; | ||
583 | return; | ||
584 | } | ||
585 | 547 | ||
586 | /* | 548 | /* |
587 | * Just to be sure: flush any data from RX FIFO. | 549 | * Just to be sure: flush any data from RX FIFO. |
@@ -619,7 +581,6 @@ static void ep93xx_spi_process_message(struct ep93xx_spi *espi, | |||
619 | * deselect the device and disable the SPI controller. | 581 | * deselect the device and disable the SPI controller. |
620 | */ | 582 | */ |
621 | ep93xx_spi_cs_control(msg->spi, false); | 583 | ep93xx_spi_cs_control(msg->spi, false); |
622 | ep93xx_spi_disable(espi); | ||
623 | } | 584 | } |
624 | 585 | ||
625 | static int ep93xx_spi_transfer_one_message(struct spi_master *master, | 586 | static int ep93xx_spi_transfer_one_message(struct spi_master *master, |
@@ -679,6 +640,37 @@ static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) | |||
679 | return IRQ_HANDLED; | 640 | return IRQ_HANDLED; |
680 | } | 641 | } |
681 | 642 | ||
643 | static int ep93xx_spi_prepare_hardware(struct spi_master *master) | ||
644 | { | ||
645 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | ||
646 | u32 val; | ||
647 | int ret; | ||
648 | |||
649 | ret = clk_enable(espi->clk); | ||
650 | if (ret) | ||
651 | return ret; | ||
652 | |||
653 | val = readl(espi->mmio + SSPCR1); | ||
654 | val |= SSPCR1_SSE; | ||
655 | writel(val, espi->mmio + SSPCR1); | ||
656 | |||
657 | return 0; | ||
658 | } | ||
659 | |||
660 | static int ep93xx_spi_unprepare_hardware(struct spi_master *master) | ||
661 | { | ||
662 | struct ep93xx_spi *espi = spi_master_get_devdata(master); | ||
663 | u32 val; | ||
664 | |||
665 | val = readl(espi->mmio + SSPCR1); | ||
666 | val &= ~SSPCR1_SSE; | ||
667 | writel(val, espi->mmio + SSPCR1); | ||
668 | |||
669 | clk_disable(espi->clk); | ||
670 | |||
671 | return 0; | ||
672 | } | ||
673 | |||
682 | static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param) | 674 | static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param) |
683 | { | 675 | { |
684 | if (ep93xx_dma_chan_is_m2p(chan)) | 676 | if (ep93xx_dma_chan_is_m2p(chan)) |
@@ -780,6 +772,8 @@ static int ep93xx_spi_probe(struct platform_device *pdev) | |||
780 | if (!master) | 772 | if (!master) |
781 | return -ENOMEM; | 773 | return -ENOMEM; |
782 | 774 | ||
775 | master->prepare_transfer_hardware = ep93xx_spi_prepare_hardware; | ||
776 | master->unprepare_transfer_hardware = ep93xx_spi_unprepare_hardware; | ||
783 | master->transfer_one_message = ep93xx_spi_transfer_one_message; | 777 | master->transfer_one_message = ep93xx_spi_transfer_one_message; |
784 | master->bus_num = pdev->id; | 778 | master->bus_num = pdev->id; |
785 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | 779 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |