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authorKeerthy <j-keerthy@ti.com>2017-01-06 01:01:43 -0500
committerEduardo Valentin <edubezval@gmail.com>2017-02-18 20:44:18 -0500
commit13d00b6439f1cf570ef962cf141bb3e329997265 (patch)
tree15bf7200496848ad1440939ff05ebea14c926238 /drivers/thermal
parent96234d44ce3dc598de06b9d7431db9d186dd0d11 (diff)
thermal: arm: dra752: Remove all TSHUT related definitions
No configuration needs to be done for TSHUT from software. Hence remove all the unnecessary definitions. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
Diffstat (limited to 'drivers/thermal')
-rw-r--r--drivers/thermal/ti-soc-thermal/dra752-bandgap.h19
-rw-r--r--drivers/thermal/ti-soc-thermal/dra752-thermal-data.c25
2 files changed, 0 insertions, 44 deletions
diff --git a/drivers/thermal/ti-soc-thermal/dra752-bandgap.h b/drivers/thermal/ti-soc-thermal/dra752-bandgap.h
index 6b0f2b1160f7..a31e4b5e82cd 100644
--- a/drivers/thermal/ti-soc-thermal/dra752-bandgap.h
+++ b/drivers/thermal/ti-soc-thermal/dra752-bandgap.h
@@ -54,7 +54,6 @@
54#define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8 54#define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8
55#define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154 55#define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154
56#define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac 56#define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac
57#define DRA752_BANDGAP_TSHUT_CORE_OFFSET 0x1b8
58#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET 0x1c4 57#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET 0x1c4
59#define DRA752_DTEMP_CORE_0_OFFSET 0x208 58#define DRA752_DTEMP_CORE_0_OFFSET 0x208
60#define DRA752_DTEMP_CORE_1_OFFSET 0x20c 59#define DRA752_DTEMP_CORE_1_OFFSET 0x20c
@@ -66,7 +65,6 @@
66#define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388 65#define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388
67#define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398 66#define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398
68#define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4 67#define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4
69#define DRA752_BANDGAP_TSHUT_IVA_OFFSET 0x3ac
70#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET 0x3b4 68#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET 0x3b4
71#define DRA752_DTEMP_IVA_0_OFFSET 0x3d0 69#define DRA752_DTEMP_IVA_0_OFFSET 0x3d0
72#define DRA752_DTEMP_IVA_1_OFFSET 0x3d4 70#define DRA752_DTEMP_IVA_1_OFFSET 0x3d4
@@ -78,7 +76,6 @@
78#define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4 76#define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4
79#define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c 77#define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c
80#define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4 78#define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4
81#define DRA752_BANDGAP_TSHUT_MPU_OFFSET 0x1b0
82#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET 0x1bc 79#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET 0x1bc
83#define DRA752_DTEMP_MPU_0_OFFSET 0x1e0 80#define DRA752_DTEMP_MPU_0_OFFSET 0x1e0
84#define DRA752_DTEMP_MPU_1_OFFSET 0x1e4 81#define DRA752_DTEMP_MPU_1_OFFSET 0x1e4
@@ -90,7 +87,6 @@
90#define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384 87#define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384
91#define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394 88#define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394
92#define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0 89#define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0
93#define DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET 0x3a8
94#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET 0x3b0 90#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET 0x3b0
95#define DRA752_DTEMP_DSPEVE_0_OFFSET 0x3bc 91#define DRA752_DTEMP_DSPEVE_0_OFFSET 0x3bc
96#define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0 92#define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0
@@ -102,7 +98,6 @@
102#define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0 98#define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0
103#define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150 99#define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150
104#define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8 100#define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8
105#define DRA752_BANDGAP_TSHUT_GPU_OFFSET 0x1b4
106#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET 0x1c0 101#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET 0x1c0
107#define DRA752_DTEMP_GPU_0_OFFSET 0x1f4 102#define DRA752_DTEMP_GPU_0_OFFSET 0x1f4
108#define DRA752_DTEMP_GPU_1_OFFSET 0x1f8 103#define DRA752_DTEMP_GPU_1_OFFSET 0x1f8
@@ -173,10 +168,6 @@
173#define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16) 168#define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16)
174#define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0) 169#define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0)
175 170
176/* DRA752.TSHUT_THRESHOLD */
177#define DRA752_TSHUT_THRESHOLD_MUXCTRL_MASK BIT(31)
178#define DRA752_TSHUT_THRESHOLD_HOT_MASK (0x3ff << 16)
179#define DRA752_TSHUT_THRESHOLD_COLD_MASK (0x3ff << 0)
180 171
181/* DRA752.BANDGAP_CUMUL_DTEMP_CORE */ 172/* DRA752.BANDGAP_CUMUL_DTEMP_CORE */
182#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0) 173#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
@@ -216,8 +207,6 @@
216#define DRA752_GPU_MAX_TEMP 125000 207#define DRA752_GPU_MAX_TEMP 125000
217#define DRA752_GPU_HYST_VAL 5000 208#define DRA752_GPU_HYST_VAL 5000
218/* interrupts thresholds */ 209/* interrupts thresholds */
219#define DRA752_GPU_TSHUT_HOT 915
220#define DRA752_GPU_TSHUT_COLD 900
221#define DRA752_GPU_T_HOT 800 210#define DRA752_GPU_T_HOT 800
222#define DRA752_GPU_T_COLD 795 211#define DRA752_GPU_T_COLD 795
223 212
@@ -230,8 +219,6 @@
230#define DRA752_MPU_MAX_TEMP 125000 219#define DRA752_MPU_MAX_TEMP 125000
231#define DRA752_MPU_HYST_VAL 5000 220#define DRA752_MPU_HYST_VAL 5000
232/* interrupts thresholds */ 221/* interrupts thresholds */
233#define DRA752_MPU_TSHUT_HOT 915
234#define DRA752_MPU_TSHUT_COLD 900
235#define DRA752_MPU_T_HOT 800 222#define DRA752_MPU_T_HOT 800
236#define DRA752_MPU_T_COLD 795 223#define DRA752_MPU_T_COLD 795
237 224
@@ -244,8 +231,6 @@
244#define DRA752_CORE_MAX_TEMP 125000 231#define DRA752_CORE_MAX_TEMP 125000
245#define DRA752_CORE_HYST_VAL 5000 232#define DRA752_CORE_HYST_VAL 5000
246/* interrupts thresholds */ 233/* interrupts thresholds */
247#define DRA752_CORE_TSHUT_HOT 915
248#define DRA752_CORE_TSHUT_COLD 900
249#define DRA752_CORE_T_HOT 800 234#define DRA752_CORE_T_HOT 800
250#define DRA752_CORE_T_COLD 795 235#define DRA752_CORE_T_COLD 795
251 236
@@ -258,8 +243,6 @@
258#define DRA752_DSPEVE_MAX_TEMP 125000 243#define DRA752_DSPEVE_MAX_TEMP 125000
259#define DRA752_DSPEVE_HYST_VAL 5000 244#define DRA752_DSPEVE_HYST_VAL 5000
260/* interrupts thresholds */ 245/* interrupts thresholds */
261#define DRA752_DSPEVE_TSHUT_HOT 915
262#define DRA752_DSPEVE_TSHUT_COLD 900
263#define DRA752_DSPEVE_T_HOT 800 246#define DRA752_DSPEVE_T_HOT 800
264#define DRA752_DSPEVE_T_COLD 795 247#define DRA752_DSPEVE_T_COLD 795
265 248
@@ -272,8 +255,6 @@
272#define DRA752_IVA_MAX_TEMP 125000 255#define DRA752_IVA_MAX_TEMP 125000
273#define DRA752_IVA_HYST_VAL 5000 256#define DRA752_IVA_HYST_VAL 5000
274/* interrupts thresholds */ 257/* interrupts thresholds */
275#define DRA752_IVA_TSHUT_HOT 915
276#define DRA752_IVA_TSHUT_COLD 900
277#define DRA752_IVA_T_HOT 800 258#define DRA752_IVA_T_HOT 800
278#define DRA752_IVA_T_COLD 795 259#define DRA752_IVA_T_COLD 795
279 260
diff --git a/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c b/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c
index 0a3f88dd883e..118d7d847715 100644
--- a/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c
+++ b/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c
@@ -49,9 +49,6 @@ dra752_core_temp_sensor_registers = {
49 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET, 49 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
50 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, 50 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
51 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, 51 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
52 .tshut_threshold = DRA752_BANDGAP_TSHUT_CORE_OFFSET,
53 .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
54 .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
55 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, 52 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
56 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, 53 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
57 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK, 54 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
@@ -85,9 +82,6 @@ dra752_iva_temp_sensor_registers = {
85 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET, 82 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
86 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, 83 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
87 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, 84 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
88 .tshut_threshold = DRA752_BANDGAP_TSHUT_IVA_OFFSET,
89 .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
90 .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
91 .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET, 85 .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
92 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, 86 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
93 .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK, 87 .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
@@ -121,9 +115,6 @@ dra752_mpu_temp_sensor_registers = {
121 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET, 115 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
122 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, 116 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
123 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, 117 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
124 .tshut_threshold = DRA752_BANDGAP_TSHUT_MPU_OFFSET,
125 .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
126 .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
127 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, 118 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
128 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, 119 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
129 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK, 120 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
@@ -157,9 +148,6 @@ dra752_dspeve_temp_sensor_registers = {
157 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET, 148 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
158 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, 149 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
159 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, 150 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
160 .tshut_threshold = DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET,
161 .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
162 .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
163 .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET, 151 .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
164 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, 152 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
165 .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK, 153 .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
@@ -193,9 +181,6 @@ dra752_gpu_temp_sensor_registers = {
193 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET, 181 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
194 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, 182 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
195 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, 183 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
196 .tshut_threshold = DRA752_BANDGAP_TSHUT_GPU_OFFSET,
197 .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
198 .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
199 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, 184 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
200 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK, 185 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
201 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK, 186 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
@@ -211,8 +196,6 @@ dra752_gpu_temp_sensor_registers = {
211 196
212/* Thresholds and limits for DRA752 MPU temperature sensor */ 197/* Thresholds and limits for DRA752 MPU temperature sensor */
213static struct temp_sensor_data dra752_mpu_temp_sensor_data = { 198static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
214 .tshut_hot = DRA752_MPU_TSHUT_HOT,
215 .tshut_cold = DRA752_MPU_TSHUT_COLD,
216 .t_hot = DRA752_MPU_T_HOT, 199 .t_hot = DRA752_MPU_T_HOT,
217 .t_cold = DRA752_MPU_T_COLD, 200 .t_cold = DRA752_MPU_T_COLD,
218 .min_freq = DRA752_MPU_MIN_FREQ, 201 .min_freq = DRA752_MPU_MIN_FREQ,
@@ -226,8 +209,6 @@ static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
226 209
227/* Thresholds and limits for DRA752 GPU temperature sensor */ 210/* Thresholds and limits for DRA752 GPU temperature sensor */
228static struct temp_sensor_data dra752_gpu_temp_sensor_data = { 211static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
229 .tshut_hot = DRA752_GPU_TSHUT_HOT,
230 .tshut_cold = DRA752_GPU_TSHUT_COLD,
231 .t_hot = DRA752_GPU_T_HOT, 212 .t_hot = DRA752_GPU_T_HOT,
232 .t_cold = DRA752_GPU_T_COLD, 213 .t_cold = DRA752_GPU_T_COLD,
233 .min_freq = DRA752_GPU_MIN_FREQ, 214 .min_freq = DRA752_GPU_MIN_FREQ,
@@ -241,8 +222,6 @@ static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
241 222
242/* Thresholds and limits for DRA752 CORE temperature sensor */ 223/* Thresholds and limits for DRA752 CORE temperature sensor */
243static struct temp_sensor_data dra752_core_temp_sensor_data = { 224static struct temp_sensor_data dra752_core_temp_sensor_data = {
244 .tshut_hot = DRA752_CORE_TSHUT_HOT,
245 .tshut_cold = DRA752_CORE_TSHUT_COLD,
246 .t_hot = DRA752_CORE_T_HOT, 225 .t_hot = DRA752_CORE_T_HOT,
247 .t_cold = DRA752_CORE_T_COLD, 226 .t_cold = DRA752_CORE_T_COLD,
248 .min_freq = DRA752_CORE_MIN_FREQ, 227 .min_freq = DRA752_CORE_MIN_FREQ,
@@ -256,8 +235,6 @@ static struct temp_sensor_data dra752_core_temp_sensor_data = {
256 235
257/* Thresholds and limits for DRA752 DSPEVE temperature sensor */ 236/* Thresholds and limits for DRA752 DSPEVE temperature sensor */
258static struct temp_sensor_data dra752_dspeve_temp_sensor_data = { 237static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
259 .tshut_hot = DRA752_DSPEVE_TSHUT_HOT,
260 .tshut_cold = DRA752_DSPEVE_TSHUT_COLD,
261 .t_hot = DRA752_DSPEVE_T_HOT, 238 .t_hot = DRA752_DSPEVE_T_HOT,
262 .t_cold = DRA752_DSPEVE_T_COLD, 239 .t_cold = DRA752_DSPEVE_T_COLD,
263 .min_freq = DRA752_DSPEVE_MIN_FREQ, 240 .min_freq = DRA752_DSPEVE_MIN_FREQ,
@@ -271,8 +248,6 @@ static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
271 248
272/* Thresholds and limits for DRA752 IVA temperature sensor */ 249/* Thresholds and limits for DRA752 IVA temperature sensor */
273static struct temp_sensor_data dra752_iva_temp_sensor_data = { 250static struct temp_sensor_data dra752_iva_temp_sensor_data = {
274 .tshut_hot = DRA752_IVA_TSHUT_HOT,
275 .tshut_cold = DRA752_IVA_TSHUT_COLD,
276 .t_hot = DRA752_IVA_T_HOT, 251 .t_hot = DRA752_IVA_T_HOT,
277 .t_cold = DRA752_IVA_T_COLD, 252 .t_cold = DRA752_IVA_T_COLD,
278 .min_freq = DRA752_IVA_MIN_FREQ, 253 .min_freq = DRA752_IVA_MIN_FREQ,