summaryrefslogtreecommitdiffstats
path: root/drivers/spi/spi-sh-msiof.c
diff options
context:
space:
mode:
authorGeert Uytterhoeven <geert+renesas@glider.be>2019-02-08 04:09:09 -0500
committerMark Brown <broonie@kernel.org>2019-02-08 08:04:32 -0500
commit35c35fd9256442c2a6af23305b1dffd4f5139591 (patch)
treec312a950892940294b6cdaa8ffad852a9eb6a124 /drivers/spi/spi-sh-msiof.c
parent5a0e577fc9155fafc3bfc9fac025ebfad4f4bf14 (diff)
spi: sh-msiof: Replace spi_master by spi_controller
As of commit 8caab75fd2c2a926 ('spi: Generalize SPI "master" to "controller"'), the old master-centric names are compatibility wrappers for the new controller-centric names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-sh-msiof.c')
-rw-r--r--drivers/spi/spi-sh-msiof.c168
1 files changed, 83 insertions, 85 deletions
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 617cdf3be050..b20e70a2bdd1 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -1,6 +1,6 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: GPL-2.0
2/* 2/*
3 * SuperH MSIOF SPI Master Interface 3 * SuperH MSIOF SPI Controller Interface
4 * 4 *
5 * Copyright (c) 2009 Magnus Damm 5 * Copyright (c) 2009 Magnus Damm
6 * Copyright (C) 2014 Renesas Electronics Corporation 6 * Copyright (C) 2014 Renesas Electronics Corporation
@@ -34,12 +34,12 @@
34struct sh_msiof_chipdata { 34struct sh_msiof_chipdata {
35 u16 tx_fifo_size; 35 u16 tx_fifo_size;
36 u16 rx_fifo_size; 36 u16 rx_fifo_size;
37 u16 master_flags; 37 u16 ctlr_flags;
38 u16 min_div_pow; 38 u16 min_div_pow;
39}; 39};
40 40
41struct sh_msiof_spi_priv { 41struct sh_msiof_spi_priv {
42 struct spi_master *master; 42 struct spi_controller *ctlr;
43 void __iomem *mapbase; 43 void __iomem *mapbase;
44 struct clk *clk; 44 struct clk *clk;
45 struct platform_device *pdev; 45 struct platform_device *pdev;
@@ -287,7 +287,7 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
287 287
288 scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps); 288 scr = sh_msiof_spi_div_array[div_pow] | SCR_BRPS(brps);
289 sh_msiof_write(p, TSCR, scr); 289 sh_msiof_write(p, TSCR, scr);
290 if (!(p->master->flags & SPI_MASTER_MUST_TX)) 290 if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
291 sh_msiof_write(p, RSCR, scr); 291 sh_msiof_write(p, RSCR, scr);
292} 292}
293 293
@@ -351,14 +351,14 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
351 tmp |= !cs_high << MDR1_SYNCAC_SHIFT; 351 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
352 tmp |= lsb_first << MDR1_BITLSB_SHIFT; 352 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
353 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p); 353 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
354 if (spi_controller_is_slave(p->master)) { 354 if (spi_controller_is_slave(p->ctlr)) {
355 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON); 355 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
356 } else { 356 } else {
357 sh_msiof_write(p, TMDR1, 357 sh_msiof_write(p, TMDR1,
358 tmp | MDR1_TRMD | TMDR1_PCON | 358 tmp | MDR1_TRMD | TMDR1_PCON |
359 (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT); 359 (ss < MAX_SS ? ss : 0) << TMDR1_SYNCCH_SHIFT);
360 } 360 }
361 if (p->master->flags & SPI_MASTER_MUST_TX) { 361 if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
362 /* These bits are reserved if RX needs TX */ 362 /* These bits are reserved if RX needs TX */
363 tmp &= ~0x0000ffff; 363 tmp &= ~0x0000ffff;
364 } 364 }
@@ -382,7 +382,7 @@ static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
382{ 382{
383 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); 383 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
384 384
385 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX)) 385 if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
386 sh_msiof_write(p, TMDR2, dr2); 386 sh_msiof_write(p, TMDR2, dr2);
387 else 387 else
388 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); 388 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
@@ -539,8 +539,9 @@ static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
539 539
540static int sh_msiof_spi_setup(struct spi_device *spi) 540static int sh_msiof_spi_setup(struct spi_device *spi)
541{ 541{
542 struct device_node *np = spi->master->dev.of_node; 542 struct device_node *np = spi->controller->dev.of_node;
543 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); 543 struct sh_msiof_spi_priv *p =
544 spi_controller_get_devdata(spi->controller);
544 u32 clr, set, tmp; 545 u32 clr, set, tmp;
545 546
546 if (!np) { 547 if (!np) {
@@ -556,7 +557,7 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
556 return 0; 557 return 0;
557 } 558 }
558 559
559 if (spi_controller_is_slave(p->master)) 560 if (spi_controller_is_slave(p->ctlr))
560 return 0; 561 return 0;
561 562
562 if (p->native_cs_inited && 563 if (p->native_cs_inited &&
@@ -581,10 +582,10 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
581 return 0; 582 return 0;
582} 583}
583 584
584static int sh_msiof_prepare_message(struct spi_master *master, 585static int sh_msiof_prepare_message(struct spi_controller *ctlr,
585 struct spi_message *msg) 586 struct spi_message *msg)
586{ 587{
587 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 588 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
588 const struct spi_device *spi = msg->spi; 589 const struct spi_device *spi = msg->spi;
589 u32 ss, cs_high; 590 u32 ss, cs_high;
590 591
@@ -605,7 +606,7 @@ static int sh_msiof_prepare_message(struct spi_master *master,
605 606
606static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) 607static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
607{ 608{
608 bool slave = spi_controller_is_slave(p->master); 609 bool slave = spi_controller_is_slave(p->ctlr);
609 int ret = 0; 610 int ret = 0;
610 611
611 /* setup clock and rx/tx signals */ 612 /* setup clock and rx/tx signals */
@@ -625,7 +626,7 @@ static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
625 626
626static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) 627static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
627{ 628{
628 bool slave = spi_controller_is_slave(p->master); 629 bool slave = spi_controller_is_slave(p->ctlr);
629 int ret = 0; 630 int ret = 0;
630 631
631 /* shut down frame, rx/tx and clock signals */ 632 /* shut down frame, rx/tx and clock signals */
@@ -641,9 +642,9 @@ static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
641 return ret; 642 return ret;
642} 643}
643 644
644static int sh_msiof_slave_abort(struct spi_master *master) 645static int sh_msiof_slave_abort(struct spi_controller *ctlr)
645{ 646{
646 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 647 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
647 648
648 p->slave_aborted = true; 649 p->slave_aborted = true;
649 complete(&p->done); 650 complete(&p->done);
@@ -654,7 +655,7 @@ static int sh_msiof_slave_abort(struct spi_master *master)
654static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p, 655static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
655 struct completion *x) 656 struct completion *x)
656{ 657{
657 if (spi_controller_is_slave(p->master)) { 658 if (spi_controller_is_slave(p->ctlr)) {
658 if (wait_for_completion_interruptible(x) || 659 if (wait_for_completion_interruptible(x) ||
659 p->slave_aborted) { 660 p->slave_aborted) {
660 dev_dbg(&p->pdev->dev, "interrupted\n"); 661 dev_dbg(&p->pdev->dev, "interrupted\n");
@@ -754,7 +755,7 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
754 /* First prepare and submit the DMA request(s), as this may fail */ 755 /* First prepare and submit the DMA request(s), as this may fail */
755 if (rx) { 756 if (rx) {
756 ier_bits |= IER_RDREQE | IER_RDMAE; 757 ier_bits |= IER_RDREQE | IER_RDMAE;
757 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx, 758 desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx,
758 p->rx_dma_addr, len, DMA_DEV_TO_MEM, 759 p->rx_dma_addr, len, DMA_DEV_TO_MEM,
759 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 760 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
760 if (!desc_rx) 761 if (!desc_rx)
@@ -769,9 +770,9 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
769 770
770 if (tx) { 771 if (tx) {
771 ier_bits |= IER_TDREQE | IER_TDMAE; 772 ier_bits |= IER_TDREQE | IER_TDMAE;
772 dma_sync_single_for_device(p->master->dma_tx->device->dev, 773 dma_sync_single_for_device(p->ctlr->dma_tx->device->dev,
773 p->tx_dma_addr, len, DMA_TO_DEVICE); 774 p->tx_dma_addr, len, DMA_TO_DEVICE);
774 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx, 775 desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx,
775 p->tx_dma_addr, len, DMA_MEM_TO_DEV, 776 p->tx_dma_addr, len, DMA_MEM_TO_DEV,
776 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 777 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
777 if (!desc_tx) { 778 if (!desc_tx) {
@@ -803,9 +804,9 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
803 804
804 /* Now start DMA */ 805 /* Now start DMA */
805 if (rx) 806 if (rx)
806 dma_async_issue_pending(p->master->dma_rx); 807 dma_async_issue_pending(p->ctlr->dma_rx);
807 if (tx) 808 if (tx)
808 dma_async_issue_pending(p->master->dma_tx); 809 dma_async_issue_pending(p->ctlr->dma_tx);
809 810
810 ret = sh_msiof_spi_start(p, rx); 811 ret = sh_msiof_spi_start(p, rx);
811 if (ret) { 812 if (ret) {
@@ -845,9 +846,8 @@ static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
845 } 846 }
846 847
847 if (rx) 848 if (rx)
848 dma_sync_single_for_cpu(p->master->dma_rx->device->dev, 849 dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev,
849 p->rx_dma_addr, len, 850 p->rx_dma_addr, len, DMA_FROM_DEVICE);
850 DMA_FROM_DEVICE);
851 851
852 return 0; 852 return 0;
853 853
@@ -856,10 +856,10 @@ stop_reset:
856 sh_msiof_spi_stop(p, rx); 856 sh_msiof_spi_stop(p, rx);
857stop_dma: 857stop_dma:
858 if (tx) 858 if (tx)
859 dmaengine_terminate_all(p->master->dma_tx); 859 dmaengine_terminate_all(p->ctlr->dma_tx);
860no_dma_tx: 860no_dma_tx:
861 if (rx) 861 if (rx)
862 dmaengine_terminate_all(p->master->dma_rx); 862 dmaengine_terminate_all(p->ctlr->dma_rx);
863 sh_msiof_write(p, IER, 0); 863 sh_msiof_write(p, IER, 0);
864 return ret; 864 return ret;
865} 865}
@@ -907,11 +907,11 @@ static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
907 memcpy(dst, src, words * 4); 907 memcpy(dst, src, words * 4);
908} 908}
909 909
910static int sh_msiof_transfer_one(struct spi_master *master, 910static int sh_msiof_transfer_one(struct spi_controller *ctlr,
911 struct spi_device *spi, 911 struct spi_device *spi,
912 struct spi_transfer *t) 912 struct spi_transfer *t)
913{ 913{
914 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); 914 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
915 void (*copy32)(u32 *, const u32 *, unsigned int); 915 void (*copy32)(u32 *, const u32 *, unsigned int);
916 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); 916 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
917 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); 917 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
@@ -926,10 +926,10 @@ static int sh_msiof_transfer_one(struct spi_master *master,
926 int ret; 926 int ret;
927 927
928 /* setup clocks (clock already enabled in chipselect()) */ 928 /* setup clocks (clock already enabled in chipselect()) */
929 if (!spi_controller_is_slave(p->master)) 929 if (!spi_controller_is_slave(p->ctlr))
930 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); 930 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
931 931
932 while (master->dma_tx && len > 15) { 932 while (ctlr->dma_tx && len > 15) {
933 /* 933 /*
934 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit 934 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
935 * words, with byte resp. word swapping. 935 * words, with byte resp. word swapping.
@@ -1050,21 +1050,21 @@ static int sh_msiof_transfer_one(struct spi_master *master,
1050static const struct sh_msiof_chipdata sh_data = { 1050static const struct sh_msiof_chipdata sh_data = {
1051 .tx_fifo_size = 64, 1051 .tx_fifo_size = 64,
1052 .rx_fifo_size = 64, 1052 .rx_fifo_size = 64,
1053 .master_flags = 0, 1053 .ctlr_flags = 0,
1054 .min_div_pow = 0, 1054 .min_div_pow = 0,
1055}; 1055};
1056 1056
1057static const struct sh_msiof_chipdata rcar_gen2_data = { 1057static const struct sh_msiof_chipdata rcar_gen2_data = {
1058 .tx_fifo_size = 64, 1058 .tx_fifo_size = 64,
1059 .rx_fifo_size = 64, 1059 .rx_fifo_size = 64,
1060 .master_flags = SPI_MASTER_MUST_TX, 1060 .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1061 .min_div_pow = 0, 1061 .min_div_pow = 0,
1062}; 1062};
1063 1063
1064static const struct sh_msiof_chipdata rcar_gen3_data = { 1064static const struct sh_msiof_chipdata rcar_gen3_data = {
1065 .tx_fifo_size = 64, 1065 .tx_fifo_size = 64,
1066 .rx_fifo_size = 64, 1066 .rx_fifo_size = 64,
1067 .master_flags = SPI_MASTER_MUST_TX, 1067 .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1068 .min_div_pow = 1, 1068 .min_div_pow = 1,
1069}; 1069};
1070 1070
@@ -1132,7 +1132,7 @@ static int sh_msiof_get_cs_gpios(struct sh_msiof_spi_priv *p)
1132 if (ret <= 0) 1132 if (ret <= 0)
1133 return 0; 1133 return 0;
1134 1134
1135 num_cs = max_t(unsigned int, ret, p->master->num_chipselect); 1135 num_cs = max_t(unsigned int, ret, p->ctlr->num_chipselect);
1136 for (i = 0; i < num_cs; i++) { 1136 for (i = 0; i < num_cs; i++) {
1137 struct gpio_desc *gpiod; 1137 struct gpio_desc *gpiod;
1138 1138
@@ -1205,7 +1205,7 @@ static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1205 const struct sh_msiof_spi_info *info = p->info; 1205 const struct sh_msiof_spi_info *info = p->info;
1206 unsigned int dma_tx_id, dma_rx_id; 1206 unsigned int dma_tx_id, dma_rx_id;
1207 const struct resource *res; 1207 const struct resource *res;
1208 struct spi_master *master; 1208 struct spi_controller *ctlr;
1209 struct device *tx_dev, *rx_dev; 1209 struct device *tx_dev, *rx_dev;
1210 1210
1211 if (dev->of_node) { 1211 if (dev->of_node) {
@@ -1225,17 +1225,15 @@ static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1225 if (!res) 1225 if (!res)
1226 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1226 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1227 1227
1228 master = p->master; 1228 ctlr = p->ctlr;
1229 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV, 1229 ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1230 dma_tx_id, 1230 dma_tx_id, res->start + TFDR);
1231 res->start + TFDR); 1231 if (!ctlr->dma_tx)
1232 if (!master->dma_tx)
1233 return -ENODEV; 1232 return -ENODEV;
1234 1233
1235 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM, 1234 ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1236 dma_rx_id, 1235 dma_rx_id, res->start + RFDR);
1237 res->start + RFDR); 1236 if (!ctlr->dma_rx)
1238 if (!master->dma_rx)
1239 goto free_tx_chan; 1237 goto free_tx_chan;
1240 1238
1241 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1239 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
@@ -1246,13 +1244,13 @@ static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1246 if (!p->rx_dma_page) 1244 if (!p->rx_dma_page)
1247 goto free_tx_page; 1245 goto free_tx_page;
1248 1246
1249 tx_dev = master->dma_tx->device->dev; 1247 tx_dev = ctlr->dma_tx->device->dev;
1250 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE, 1248 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1251 DMA_TO_DEVICE); 1249 DMA_TO_DEVICE);
1252 if (dma_mapping_error(tx_dev, p->tx_dma_addr)) 1250 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1253 goto free_rx_page; 1251 goto free_rx_page;
1254 1252
1255 rx_dev = master->dma_rx->device->dev; 1253 rx_dev = ctlr->dma_rx->device->dev;
1256 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE, 1254 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1257 DMA_FROM_DEVICE); 1255 DMA_FROM_DEVICE);
1258 if (dma_mapping_error(rx_dev, p->rx_dma_addr)) 1256 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
@@ -1268,34 +1266,34 @@ free_rx_page:
1268free_tx_page: 1266free_tx_page:
1269 free_page((unsigned long)p->tx_dma_page); 1267 free_page((unsigned long)p->tx_dma_page);
1270free_rx_chan: 1268free_rx_chan:
1271 dma_release_channel(master->dma_rx); 1269 dma_release_channel(ctlr->dma_rx);
1272free_tx_chan: 1270free_tx_chan:
1273 dma_release_channel(master->dma_tx); 1271 dma_release_channel(ctlr->dma_tx);
1274 master->dma_tx = NULL; 1272 ctlr->dma_tx = NULL;
1275 return -ENODEV; 1273 return -ENODEV;
1276} 1274}
1277 1275
1278static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) 1276static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1279{ 1277{
1280 struct spi_master *master = p->master; 1278 struct spi_controller *ctlr = p->ctlr;
1281 1279
1282 if (!master->dma_tx) 1280 if (!ctlr->dma_tx)
1283 return; 1281 return;
1284 1282
1285 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr, 1283 dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE,
1286 PAGE_SIZE, DMA_FROM_DEVICE); 1284 DMA_FROM_DEVICE);
1287 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr, 1285 dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE,
1288 PAGE_SIZE, DMA_TO_DEVICE); 1286 DMA_TO_DEVICE);
1289 free_page((unsigned long)p->rx_dma_page); 1287 free_page((unsigned long)p->rx_dma_page);
1290 free_page((unsigned long)p->tx_dma_page); 1288 free_page((unsigned long)p->tx_dma_page);
1291 dma_release_channel(master->dma_rx); 1289 dma_release_channel(ctlr->dma_rx);
1292 dma_release_channel(master->dma_tx); 1290 dma_release_channel(ctlr->dma_tx);
1293} 1291}
1294 1292
1295static int sh_msiof_spi_probe(struct platform_device *pdev) 1293static int sh_msiof_spi_probe(struct platform_device *pdev)
1296{ 1294{
1297 struct resource *r; 1295 struct resource *r;
1298 struct spi_master *master; 1296 struct spi_controller *ctlr;
1299 const struct sh_msiof_chipdata *chipdata; 1297 const struct sh_msiof_chipdata *chipdata;
1300 struct sh_msiof_spi_info *info; 1298 struct sh_msiof_spi_info *info;
1301 struct sh_msiof_spi_priv *p; 1299 struct sh_msiof_spi_priv *p;
@@ -1316,18 +1314,18 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
1316 } 1314 }
1317 1315
1318 if (info->mode == MSIOF_SPI_SLAVE) 1316 if (info->mode == MSIOF_SPI_SLAVE)
1319 master = spi_alloc_slave(&pdev->dev, 1317 ctlr = spi_alloc_slave(&pdev->dev,
1320 sizeof(struct sh_msiof_spi_priv)); 1318 sizeof(struct sh_msiof_spi_priv));
1321 else 1319 else
1322 master = spi_alloc_master(&pdev->dev, 1320 ctlr = spi_alloc_master(&pdev->dev,
1323 sizeof(struct sh_msiof_spi_priv)); 1321 sizeof(struct sh_msiof_spi_priv));
1324 if (master == NULL) 1322 if (ctlr == NULL)
1325 return -ENOMEM; 1323 return -ENOMEM;
1326 1324
1327 p = spi_master_get_devdata(master); 1325 p = spi_controller_get_devdata(ctlr);
1328 1326
1329 platform_set_drvdata(pdev, p); 1327 platform_set_drvdata(pdev, p);
1330 p->master = master; 1328 p->ctlr = ctlr;
1331 p->info = info; 1329 p->info = info;
1332 p->min_div_pow = chipdata->min_div_pow; 1330 p->min_div_pow = chipdata->min_div_pow;
1333 1331
@@ -1374,31 +1372,31 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
1374 p->rx_fifo_size = p->info->rx_fifo_override; 1372 p->rx_fifo_size = p->info->rx_fifo_override;
1375 1373
1376 /* Setup GPIO chip selects */ 1374 /* Setup GPIO chip selects */
1377 master->num_chipselect = p->info->num_chipselect; 1375 ctlr->num_chipselect = p->info->num_chipselect;
1378 ret = sh_msiof_get_cs_gpios(p); 1376 ret = sh_msiof_get_cs_gpios(p);
1379 if (ret) 1377 if (ret)
1380 goto err1; 1378 goto err1;
1381 1379
1382 /* init master code */ 1380 /* init controller code */
1383 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1381 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1384 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; 1382 ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1385 master->flags = chipdata->master_flags; 1383 ctlr->flags = chipdata->ctlr_flags;
1386 master->bus_num = pdev->id; 1384 ctlr->bus_num = pdev->id;
1387 master->dev.of_node = pdev->dev.of_node; 1385 ctlr->dev.of_node = pdev->dev.of_node;
1388 master->setup = sh_msiof_spi_setup; 1386 ctlr->setup = sh_msiof_spi_setup;
1389 master->prepare_message = sh_msiof_prepare_message; 1387 ctlr->prepare_message = sh_msiof_prepare_message;
1390 master->slave_abort = sh_msiof_slave_abort; 1388 ctlr->slave_abort = sh_msiof_slave_abort;
1391 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); 1389 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1392 master->auto_runtime_pm = true; 1390 ctlr->auto_runtime_pm = true;
1393 master->transfer_one = sh_msiof_transfer_one; 1391 ctlr->transfer_one = sh_msiof_transfer_one;
1394 1392
1395 ret = sh_msiof_request_dma(p); 1393 ret = sh_msiof_request_dma(p);
1396 if (ret < 0) 1394 if (ret < 0)
1397 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1395 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1398 1396
1399 ret = devm_spi_register_master(&pdev->dev, master); 1397 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1400 if (ret < 0) { 1398 if (ret < 0) {
1401 dev_err(&pdev->dev, "spi_register_master error.\n"); 1399 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1402 goto err2; 1400 goto err2;
1403 } 1401 }
1404 1402
@@ -1408,7 +1406,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
1408 sh_msiof_release_dma(p); 1406 sh_msiof_release_dma(p);
1409 pm_runtime_disable(&pdev->dev); 1407 pm_runtime_disable(&pdev->dev);
1410 err1: 1408 err1:
1411 spi_master_put(master); 1409 spi_controller_put(ctlr);
1412 return ret; 1410 return ret;
1413} 1411}
1414 1412
@@ -1432,14 +1430,14 @@ static int sh_msiof_spi_suspend(struct device *dev)
1432{ 1430{
1433 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev); 1431 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1434 1432
1435 return spi_master_suspend(p->master); 1433 return spi_controller_suspend(p->ctlr);
1436} 1434}
1437 1435
1438static int sh_msiof_spi_resume(struct device *dev) 1436static int sh_msiof_spi_resume(struct device *dev)
1439{ 1437{
1440 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev); 1438 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1441 1439
1442 return spi_master_resume(p->master); 1440 return spi_controller_resume(p->ctlr);
1443} 1441}
1444 1442
1445static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend, 1443static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
@@ -1461,7 +1459,7 @@ static struct platform_driver sh_msiof_spi_drv = {
1461}; 1459};
1462module_platform_driver(sh_msiof_spi_drv); 1460module_platform_driver(sh_msiof_spi_drv);
1463 1461
1464MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); 1462MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver");
1465MODULE_AUTHOR("Magnus Damm"); 1463MODULE_AUTHOR("Magnus Damm");
1466MODULE_LICENSE("GPL v2"); 1464MODULE_LICENSE("GPL v2");
1467MODULE_ALIAS("platform:spi_sh_msiof"); 1465MODULE_ALIAS("platform:spi_sh_msiof");