summaryrefslogtreecommitdiffstats
path: root/drivers/spi/spi-pxa2xx.h
diff options
context:
space:
mode:
authorWeike Chen <alvin.chen@intel.com>2014-11-26 05:35:10 -0500
committerMark Brown <broonie@kernel.org>2014-11-26 13:07:45 -0500
commite5262d0568dc9e10de79a726dfd7edb712a2c10b (patch)
treefb8cd4ca58e8f0ef1b1a016ac88139401ed55cfe /drivers/spi/spi-pxa2xx.h
parent4fdb2424cc4499237197a8c9d35b34d68c750475 (diff)
spi: spi-pxa2xx: SPI support for Intel Quark X1000
There are two SPI controllers exported by PCI subsystem for Intel Quark X1000. The SPI memory mapped I/O registers supported by Quark are different from the current implementation, and Quark only supports the registers of 'SSCR0', 'SSCR1', 'SSSR', 'SSDR', and 'DDS_RATE'. This patch is to enable the SPI for Intel Quark X1000. This piece of work is derived from Dan O'Donovan's initial work for Intel Quark X1000 SPI enabling. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Weike Chen <alvin.chen@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-pxa2xx.h')
-rw-r--r--drivers/spi/spi-pxa2xx.h16
1 files changed, 11 insertions, 5 deletions
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h
index 5adc2a11c7bc..6bec59c90cd4 100644
--- a/drivers/spi/spi-pxa2xx.h
+++ b/drivers/spi/spi-pxa2xx.h
@@ -93,6 +93,7 @@ struct driver_data {
93struct chip_data { 93struct chip_data {
94 u32 cr0; 94 u32 cr0;
95 u32 cr1; 95 u32 cr1;
96 u32 dds_rate;
96 u32 psp; 97 u32 psp;
97 u32 timeout; 98 u32 timeout;
98 u8 n_bytes; 99 u8 n_bytes;
@@ -126,6 +127,7 @@ DEFINE_SSP_REG(SSCR1, 0x04)
126DEFINE_SSP_REG(SSSR, 0x08) 127DEFINE_SSP_REG(SSSR, 0x08)
127DEFINE_SSP_REG(SSITR, 0x0c) 128DEFINE_SSP_REG(SSITR, 0x0c)
128DEFINE_SSP_REG(SSDR, 0x10) 129DEFINE_SSP_REG(SSDR, 0x10)
130DEFINE_SSP_REG(DDS_RATE, 0x28) /* DDS Clock Rate */
129DEFINE_SSP_REG(SSTO, 0x28) 131DEFINE_SSP_REG(SSTO, 0x28)
130DEFINE_SSP_REG(SSPSP, 0x2c) 132DEFINE_SSP_REG(SSPSP, 0x2c)
131DEFINE_SSP_REG(SSITF, SSITF) 133DEFINE_SSP_REG(SSITF, SSITF)
@@ -141,18 +143,22 @@ DEFINE_SSP_REG(SSIRF, SSIRF)
141 143
142static inline int pxa25x_ssp_comp(struct driver_data *drv_data) 144static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
143{ 145{
144 if (drv_data->ssp_type == PXA25x_SSP) 146 switch (drv_data->ssp_type) {
147 case PXA25x_SSP:
148 case CE4100_SSP:
149 case QUARK_X1000_SSP:
145 return 1; 150 return 1;
146 if (drv_data->ssp_type == CE4100_SSP) 151 default:
147 return 1; 152 return 0;
148 return 0; 153 }
149} 154}
150 155
151static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val) 156static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
152{ 157{
153 void __iomem *reg = drv_data->ioaddr; 158 void __iomem *reg = drv_data->ioaddr;
154 159
155 if (drv_data->ssp_type == CE4100_SSP) 160 if (drv_data->ssp_type == CE4100_SSP ||
161 drv_data->ssp_type == QUARK_X1000_SSP)
156 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK; 162 val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
157 163
158 write_SSSR(val, reg); 164 write_SSSR(val, reg);