summaryrefslogtreecommitdiffstats
path: root/drivers/spi/spi-fsl-spi.c
diff options
context:
space:
mode:
authorAndreas Larsson <andreas@gaisler.com>2013-02-15 10:52:21 -0500
committerGrant Likely <grant.likely@secretlab.ca>2013-04-07 05:07:54 -0400
commite8beacbb85a5c1de1117400c5ddb450514a8372c (patch)
tree3853de80b818360820443a34eb22885224c5628f /drivers/spi/spi-fsl-spi.c
parent58ad60bbb2abada33fbeae88943ab038e2fcc0ef (diff)
spi/spi-fsl-spi: Make driver usable in CPU mode outside of an FSL_SOC environment
This makes the spi-fsl-spi driver usable in CPU mode outside of an FSL_SOC and even an powerpc environment by moving CPM mode functionality to a separate file that is only compiled and linked in an FSL_SOC environment and adding some ifdefs to hide types and functions or provide alternatives. For devicetree probing a "clock-frequency" property is used for clock frequency instead of calls to FSL_SOC-specific functions. Acked-by: Anton Vorontsov <anton@enomsg.org> Signed-off-by: Andreas Larsson <andreas@gaisler.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/spi/spi-fsl-spi.c')
-rw-r--r--drivers/spi/spi-fsl-spi.c411
1 files changed, 9 insertions, 402 deletions
diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c
index 1985ba38032e..9878911ee6af 100644
--- a/drivers/spi/spi-fsl-spi.c
+++ b/drivers/spi/spi-fsl-spi.c
@@ -30,75 +30,14 @@
30#include <linux/mutex.h> 30#include <linux/mutex.h>
31#include <linux/of.h> 31#include <linux/of.h>
32#include <linux/of_platform.h> 32#include <linux/of_platform.h>
33#include <linux/of_address.h>
34#include <linux/of_irq.h>
33#include <linux/gpio.h> 35#include <linux/gpio.h>
34#include <linux/of_gpio.h> 36#include <linux/of_gpio.h>
35 37
36#include <sysdev/fsl_soc.h>
37#include <asm/cpm.h>
38#include <asm/qe.h>
39
40#include "spi-fsl-lib.h" 38#include "spi-fsl-lib.h"
41 39#include "spi-fsl-cpm.h"
42/* CPM1 and CPM2 are mutually exclusive. */ 40#include "spi-fsl-spi.h"
43#ifdef CONFIG_CPM1
44#include <asm/cpm1.h>
45#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
46#else
47#include <asm/cpm2.h>
48#define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
49#endif
50
51/* SPI Controller registers */
52struct fsl_spi_reg {
53 u8 res1[0x20];
54 __be32 mode;
55 __be32 event;
56 __be32 mask;
57 __be32 command;
58 __be32 transmit;
59 __be32 receive;
60};
61
62/* SPI Controller mode register definitions */
63#define SPMODE_LOOP (1 << 30)
64#define SPMODE_CI_INACTIVEHIGH (1 << 29)
65#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
66#define SPMODE_DIV16 (1 << 27)
67#define SPMODE_REV (1 << 26)
68#define SPMODE_MS (1 << 25)
69#define SPMODE_ENABLE (1 << 24)
70#define SPMODE_LEN(x) ((x) << 20)
71#define SPMODE_PM(x) ((x) << 16)
72#define SPMODE_OP (1 << 14)
73#define SPMODE_CG(x) ((x) << 7)
74
75/*
76 * Default for SPI Mode:
77 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
78 */
79#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
80 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
81
82/* SPIE register values */
83#define SPIE_NE 0x00000200 /* Not empty */
84#define SPIE_NF 0x00000100 /* Not full */
85
86/* SPIM register values */
87#define SPIM_NE 0x00000200 /* Not empty */
88#define SPIM_NF 0x00000100 /* Not full */
89
90#define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */
91#define SPIE_RXB 0x00000100 /* Last char is written to rx buf */
92
93/* SPCOM register values */
94#define SPCOM_STR (1 << 23) /* Start transmit */
95
96#define SPI_PRAM_SIZE 0x100
97#define SPI_MRBLR ((unsigned int)PAGE_SIZE)
98
99static void *fsl_dummy_rx;
100static DEFINE_MUTEX(fsl_dummy_rx_lock);
101static int fsl_dummy_rx_refcnt;
102 41
103static void fsl_spi_change_mode(struct spi_device *spi) 42static void fsl_spi_change_mode(struct spi_device *spi)
104{ 43{
@@ -119,18 +58,7 @@ static void fsl_spi_change_mode(struct spi_device *spi)
119 58
120 /* When in CPM mode, we need to reinit tx and rx. */ 59 /* When in CPM mode, we need to reinit tx and rx. */
121 if (mspi->flags & SPI_CPM_MODE) { 60 if (mspi->flags & SPI_CPM_MODE) {
122 if (mspi->flags & SPI_QE) { 61 fsl_spi_cpm_reinit_txrx(mspi);
123 qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
124 QE_CR_PROTOCOL_UNSPECIFIED, 0);
125 } else {
126 cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
127 if (mspi->flags & SPI_CPM1) {
128 out_be16(&mspi->pram->rbptr,
129 in_be16(&mspi->pram->rbase));
130 out_be16(&mspi->pram->tbptr,
131 in_be16(&mspi->pram->tbase));
132 }
133 }
134 } 62 }
135 mpc8xxx_spi_write_reg(mode, cs->hw_mode); 63 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
136 local_irq_restore(flags); 64 local_irq_restore(flags);
@@ -295,112 +223,6 @@ static int fsl_spi_setup_transfer(struct spi_device *spi,
295 return 0; 223 return 0;
296} 224}
297 225
298static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
299{
300 struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
301 struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
302 unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
303 unsigned int xfer_ofs;
304 struct fsl_spi_reg *reg_base = mspi->reg_base;
305
306 xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
307
308 if (mspi->rx_dma == mspi->dma_dummy_rx)
309 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma);
310 else
311 out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
312 out_be16(&rx_bd->cbd_datlen, 0);
313 out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
314
315 if (mspi->tx_dma == mspi->dma_dummy_tx)
316 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma);
317 else
318 out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
319 out_be16(&tx_bd->cbd_datlen, xfer_len);
320 out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
321 BD_SC_LAST);
322
323 /* start transfer */
324 mpc8xxx_spi_write_reg(&reg_base->command, SPCOM_STR);
325}
326
327static int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
328 struct spi_transfer *t, bool is_dma_mapped)
329{
330 struct device *dev = mspi->dev;
331 struct fsl_spi_reg *reg_base = mspi->reg_base;
332
333 if (is_dma_mapped) {
334 mspi->map_tx_dma = 0;
335 mspi->map_rx_dma = 0;
336 } else {
337 mspi->map_tx_dma = 1;
338 mspi->map_rx_dma = 1;
339 }
340
341 if (!t->tx_buf) {
342 mspi->tx_dma = mspi->dma_dummy_tx;
343 mspi->map_tx_dma = 0;
344 }
345
346 if (!t->rx_buf) {
347 mspi->rx_dma = mspi->dma_dummy_rx;
348 mspi->map_rx_dma = 0;
349 }
350
351 if (mspi->map_tx_dma) {
352 void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
353
354 mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
355 DMA_TO_DEVICE);
356 if (dma_mapping_error(dev, mspi->tx_dma)) {
357 dev_err(dev, "unable to map tx dma\n");
358 return -ENOMEM;
359 }
360 } else if (t->tx_buf) {
361 mspi->tx_dma = t->tx_dma;
362 }
363
364 if (mspi->map_rx_dma) {
365 mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
366 DMA_FROM_DEVICE);
367 if (dma_mapping_error(dev, mspi->rx_dma)) {
368 dev_err(dev, "unable to map rx dma\n");
369 goto err_rx_dma;
370 }
371 } else if (t->rx_buf) {
372 mspi->rx_dma = t->rx_dma;
373 }
374
375 /* enable rx ints */
376 mpc8xxx_spi_write_reg(&reg_base->mask, SPIE_RXB);
377
378 mspi->xfer_in_progress = t;
379 mspi->count = t->len;
380
381 /* start CPM transfers */
382 fsl_spi_cpm_bufs_start(mspi);
383
384 return 0;
385
386err_rx_dma:
387 if (mspi->map_tx_dma)
388 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
389 return -ENOMEM;
390}
391
392static void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
393{
394 struct device *dev = mspi->dev;
395 struct spi_transfer *t = mspi->xfer_in_progress;
396
397 if (mspi->map_tx_dma)
398 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
399 if (mspi->map_rx_dma)
400 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
401 mspi->xfer_in_progress = NULL;
402}
403
404static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, 226static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
405 struct spi_transfer *t, unsigned int len) 227 struct spi_transfer *t, unsigned int len)
406{ 228{
@@ -568,30 +390,6 @@ static int fsl_spi_setup(struct spi_device *spi)
568 return 0; 390 return 0;
569} 391}
570 392
571static void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
572{
573 u16 len;
574 struct fsl_spi_reg *reg_base = mspi->reg_base;
575
576 dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
577 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
578
579 len = in_be16(&mspi->rx_bd->cbd_datlen);
580 if (len > mspi->count) {
581 WARN_ON(1);
582 len = mspi->count;
583 }
584
585 /* Clear the events */
586 mpc8xxx_spi_write_reg(&reg_base->event, events);
587
588 mspi->count -= len;
589 if (mspi->count)
590 fsl_spi_cpm_bufs_start(mspi);
591 else
592 complete(&mspi->done);
593}
594
595static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) 393static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
596{ 394{
597 struct fsl_spi_reg *reg_base = mspi->reg_base; 395 struct fsl_spi_reg *reg_base = mspi->reg_base;
@@ -646,197 +444,6 @@ static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
646 return ret; 444 return ret;
647} 445}
648 446
649static void *fsl_spi_alloc_dummy_rx(void)
650{
651 mutex_lock(&fsl_dummy_rx_lock);
652
653 if (!fsl_dummy_rx)
654 fsl_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
655 if (fsl_dummy_rx)
656 fsl_dummy_rx_refcnt++;
657
658 mutex_unlock(&fsl_dummy_rx_lock);
659
660 return fsl_dummy_rx;
661}
662
663static void fsl_spi_free_dummy_rx(void)
664{
665 mutex_lock(&fsl_dummy_rx_lock);
666
667 switch (fsl_dummy_rx_refcnt) {
668 case 0:
669 WARN_ON(1);
670 break;
671 case 1:
672 kfree(fsl_dummy_rx);
673 fsl_dummy_rx = NULL;
674 /* fall through */
675 default:
676 fsl_dummy_rx_refcnt--;
677 break;
678 }
679
680 mutex_unlock(&fsl_dummy_rx_lock);
681}
682
683static unsigned long fsl_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
684{
685 struct device *dev = mspi->dev;
686 struct device_node *np = dev->of_node;
687 const u32 *iprop;
688 int size;
689 void __iomem *spi_base;
690 unsigned long pram_ofs = -ENOMEM;
691
692 /* Can't use of_address_to_resource(), QE muram isn't at 0. */
693 iprop = of_get_property(np, "reg", &size);
694
695 /* QE with a fixed pram location? */
696 if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
697 return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
698
699 /* QE but with a dynamic pram location? */
700 if (mspi->flags & SPI_QE) {
701 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
702 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
703 QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
704 return pram_ofs;
705 }
706
707 spi_base = of_iomap(np, 1);
708 if (spi_base == NULL)
709 return -EINVAL;
710
711 if (mspi->flags & SPI_CPM2) {
712 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
713 out_be16(spi_base, pram_ofs);
714 } else {
715 struct spi_pram __iomem *pram = spi_base;
716 u16 rpbase = in_be16(&pram->rpbase);
717
718 /* Microcode relocation patch applied? */
719 if (rpbase)
720 pram_ofs = rpbase;
721 else {
722 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
723 out_be16(spi_base, pram_ofs);
724 }
725 }
726
727 iounmap(spi_base);
728 return pram_ofs;
729}
730
731static int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi)
732{
733 struct device *dev = mspi->dev;
734 struct device_node *np = dev->of_node;
735 const u32 *iprop;
736 int size;
737 unsigned long pram_ofs;
738 unsigned long bds_ofs;
739
740 if (!(mspi->flags & SPI_CPM_MODE))
741 return 0;
742
743 if (!fsl_spi_alloc_dummy_rx())
744 return -ENOMEM;
745
746 if (mspi->flags & SPI_QE) {
747 iprop = of_get_property(np, "cell-index", &size);
748 if (iprop && size == sizeof(*iprop))
749 mspi->subblock = *iprop;
750
751 switch (mspi->subblock) {
752 default:
753 dev_warn(dev, "cell-index unspecified, assuming SPI1");
754 /* fall through */
755 case 0:
756 mspi->subblock = QE_CR_SUBBLOCK_SPI1;
757 break;
758 case 1:
759 mspi->subblock = QE_CR_SUBBLOCK_SPI2;
760 break;
761 }
762 }
763
764 pram_ofs = fsl_spi_cpm_get_pram(mspi);
765 if (IS_ERR_VALUE(pram_ofs)) {
766 dev_err(dev, "can't allocate spi parameter ram\n");
767 goto err_pram;
768 }
769
770 bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
771 sizeof(*mspi->rx_bd), 8);
772 if (IS_ERR_VALUE(bds_ofs)) {
773 dev_err(dev, "can't allocate bds\n");
774 goto err_bds;
775 }
776
777 mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
778 DMA_TO_DEVICE);
779 if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
780 dev_err(dev, "unable to map dummy tx buffer\n");
781 goto err_dummy_tx;
782 }
783
784 mspi->dma_dummy_rx = dma_map_single(dev, fsl_dummy_rx, SPI_MRBLR,
785 DMA_FROM_DEVICE);
786 if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
787 dev_err(dev, "unable to map dummy rx buffer\n");
788 goto err_dummy_rx;
789 }
790
791 mspi->pram = cpm_muram_addr(pram_ofs);
792
793 mspi->tx_bd = cpm_muram_addr(bds_ofs);
794 mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
795
796 /* Initialize parameter ram. */
797 out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
798 out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
799 out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
800 out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
801 out_be16(&mspi->pram->mrblr, SPI_MRBLR);
802 out_be32(&mspi->pram->rstate, 0);
803 out_be32(&mspi->pram->rdp, 0);
804 out_be16(&mspi->pram->rbptr, 0);
805 out_be16(&mspi->pram->rbc, 0);
806 out_be32(&mspi->pram->rxtmp, 0);
807 out_be32(&mspi->pram->tstate, 0);
808 out_be32(&mspi->pram->tdp, 0);
809 out_be16(&mspi->pram->tbptr, 0);
810 out_be16(&mspi->pram->tbc, 0);
811 out_be32(&mspi->pram->txtmp, 0);
812
813 return 0;
814
815err_dummy_rx:
816 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
817err_dummy_tx:
818 cpm_muram_free(bds_ofs);
819err_bds:
820 cpm_muram_free(pram_ofs);
821err_pram:
822 fsl_spi_free_dummy_rx();
823 return -ENOMEM;
824}
825
826static void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi)
827{
828 struct device *dev = mspi->dev;
829
830 if (!(mspi->flags & SPI_CPM_MODE))
831 return;
832
833 dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
834 dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
835 cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
836 cpm_muram_free(cpm_muram_offset(mspi->pram));
837 fsl_spi_free_dummy_rx();
838}
839
840static void fsl_spi_remove(struct mpc8xxx_spi *mspi) 447static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
841{ 448{
842 iounmap(mspi->reg_base); 449 iounmap(mspi->reg_base);
@@ -1047,7 +654,7 @@ static int of_fsl_spi_probe(struct platform_device *ofdev)
1047 struct device_node *np = ofdev->dev.of_node; 654 struct device_node *np = ofdev->dev.of_node;
1048 struct spi_master *master; 655 struct spi_master *master;
1049 struct resource mem; 656 struct resource mem;
1050 struct resource irq; 657 int irq;
1051 int ret = -ENOMEM; 658 int ret = -ENOMEM;
1052 659
1053 ret = of_mpc8xxx_spi_probe(ofdev); 660 ret = of_mpc8xxx_spi_probe(ofdev);
@@ -1062,13 +669,13 @@ static int of_fsl_spi_probe(struct platform_device *ofdev)
1062 if (ret) 669 if (ret)
1063 goto err; 670 goto err;
1064 671
1065 ret = of_irq_to_resource(np, 0, &irq); 672 irq = irq_of_parse_and_map(np, 0);
1066 if (!ret) { 673 if (!irq) {
1067 ret = -EINVAL; 674 ret = -EINVAL;
1068 goto err; 675 goto err;
1069 } 676 }
1070 677
1071 master = fsl_spi_probe(dev, &mem, irq.start); 678 master = fsl_spi_probe(dev, &mem, irq);
1072 if (IS_ERR(master)) { 679 if (IS_ERR(master)) {
1073 ret = PTR_ERR(master); 680 ret = PTR_ERR(master);
1074 goto err; 681 goto err;