Merge branch 'spi-5.4' into spi-next

1 files changed, 366 insertions, 354 deletions

diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 545fc8189fb0..bec758e978fb 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -9,26 +9,16 @@
 #include <linux/delay.h>
 #include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
-#include <linux/err.h>
-#include <linux/errno.h>
 #include <linux/interrupt.h>
-#include <linux/io.h>
 #include <linux/kernel.h>
-#include <linux/math64.h>
 #include <linux/module.h>
-#include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/pinctrl/consumer.h>
-#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
 #include <linux/regmap.h>
-#include <linux/sched.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/spi-fsl-dspi.h>
-#include <linux/spi/spi_bitbang.h>
-#include <linux/time.h>
 
-#define DRIVER_NAME "fsl-dspi"
+#define DRIVER_NAME                     "fsl-dspi"
 
 #ifdef CONFIG_M5441x
 #define DSPI_FIFO_SIZE                  16
@@ -37,101 +27,97 @@
 #endif
 #define DSPI_DMA_BUFSIZE                (DSPI_FIFO_SIZE * 1024)
 
-#define SPI_MCR         0x00
-#define SPI_MCR_MASTER          (1 << 31)
-#define SPI_MCR_PCSIS           (0x3F << 16)
-#define SPI_MCR_CLR_TXF (1 << 11)
-#define SPI_MCR_CLR_RXF (1 << 10)
-#define SPI_MCR_XSPI            (1 << 3)
-
-#define SPI_TCR                 0x08
-#define SPI_TCR_GET_TCNT(x)     (((x) & 0xffff0000) >> 16)
-
-#define SPI_CTAR(x)             (0x0c + (((x) & 0x3) * 4))
-#define SPI_CTAR_FMSZ(x)        (((x) & 0x0000000f) << 27)
-#define SPI_CTAR_CPOL(x)        ((x) << 26)
-#define SPI_CTAR_CPHA(x)        ((x) << 25)
-#define SPI_CTAR_LSBFE(x)       ((x) << 24)
-#define SPI_CTAR_PCSSCK(x)      (((x) & 0x00000003) << 22)
-#define SPI_CTAR_PASC(x)        (((x) & 0x00000003) << 20)
-#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
-#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
-#define SPI_CTAR_CSSCK(x)       (((x) & 0x0000000f) << 12)
-#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
-#define SPI_CTAR_DT(x)          (((x) & 0x0000000f) << 4)
-#define SPI_CTAR_BR(x)          ((x) & 0x0000000f)
-#define SPI_CTAR_SCALE_BITS     0xf
-
-#define SPI_CTAR0_SLAVE 0x0c
-
-#define SPI_SR                  0x2c
-#define SPI_SR_EOQF             0x10000000
-#define SPI_SR_TCFQF            0x80000000
-#define SPI_SR_CLEAR            0x9aaf0000
-
-#define SPI_RSER_TFFFE          BIT(25)
-#define SPI_RSER_TFFFD          BIT(24)
-#define SPI_RSER_RFDFE          BIT(17)
-#define SPI_RSER_RFDFD          BIT(16)
-
-#define SPI_RSER                0x30
-#define SPI_RSER_EOQFE          0x10000000
-#define SPI_RSER_TCFQE          0x80000000
-
-#define SPI_PUSHR               0x34
-#define SPI_PUSHR_CMD_CONT      (1 << 15)
-#define SPI_PUSHR_CONT          (SPI_PUSHR_CMD_CONT << 16)
-#define SPI_PUSHR_CMD_CTAS(x)   (((x) & 0x0003) << 12)
-#define SPI_PUSHR_CTAS(x)       (SPI_PUSHR_CMD_CTAS(x) << 16)
-#define SPI_PUSHR_CMD_EOQ       (1 << 11)
-#define SPI_PUSHR_EOQ           (SPI_PUSHR_CMD_EOQ << 16)
-#define SPI_PUSHR_CMD_CTCNT     (1 << 10)
-#define SPI_PUSHR_CTCNT         (SPI_PUSHR_CMD_CTCNT << 16)
-#define SPI_PUSHR_CMD_PCS(x)    ((1 << x) & 0x003f)
-#define SPI_PUSHR_PCS(x)        (SPI_PUSHR_CMD_PCS(x) << 16)
-#define SPI_PUSHR_TXDATA(x)     ((x) & 0x0000ffff)
-
-#define SPI_PUSHR_SLAVE 0x34
-
-#define SPI_POPR                0x38
-#define SPI_POPR_RXDATA(x)      ((x) & 0x0000ffff)
-
-#define SPI_TXFR0               0x3c
-#define SPI_TXFR1               0x40
-#define SPI_TXFR2               0x44
-#define SPI_TXFR3               0x48
-#define SPI_RXFR0               0x7c
-#define SPI_RXFR1               0x80
-#define SPI_RXFR2               0x84
-#define SPI_RXFR3               0x88
-
-#define SPI_CTARE(x)            (0x11c + (((x) & 0x3) * 4))
-#define SPI_CTARE_FMSZE(x)      (((x) & 0x1) << 16)
-#define SPI_CTARE_DTCP(x)       ((x) & 0x7ff)
-
-#define SPI_SREX                0x13c
-
-#define SPI_FRAME_BITS(bits)    SPI_CTAR_FMSZ((bits) - 1)
-#define SPI_FRAME_BITS_MASK     SPI_CTAR_FMSZ(0xf)
-#define SPI_FRAME_BITS_16       SPI_CTAR_FMSZ(0xf)
-#define SPI_FRAME_BITS_8        SPI_CTAR_FMSZ(0x7)
-
-#define SPI_FRAME_EBITS(bits)   SPI_CTARE_FMSZE(((bits) - 1) >> 4)
-#define SPI_FRAME_EBITS_MASK    SPI_CTARE_FMSZE(1)
+#define SPI_MCR                         0x00
+#define SPI_MCR_MASTER                  BIT(31)
+#define SPI_MCR_PCSIS                   (0x3F << 16)
+#define SPI_MCR_CLR_TXF                 BIT(11)
+#define SPI_MCR_CLR_RXF                 BIT(10)
+#define SPI_MCR_XSPI                    BIT(3)
+
+#define SPI_TCR                         0x08
+#define SPI_TCR_GET_TCNT(x)             (((x) & GENMASK(31, 16)) >> 16)
+
+#define SPI_CTAR(x)                     (0x0c + (((x) & GENMASK(1, 0)) * 4))
+#define SPI_CTAR_FMSZ(x)                (((x) << 27) & GENMASK(30, 27))
+#define SPI_CTAR_CPOL                   BIT(26)
+#define SPI_CTAR_CPHA                   BIT(25)
+#define SPI_CTAR_LSBFE                  BIT(24)
+#define SPI_CTAR_PCSSCK(x)              (((x) << 22) & GENMASK(23, 22))
+#define SPI_CTAR_PASC(x)                (((x) << 20) & GENMASK(21, 20))
+#define SPI_CTAR_PDT(x)                 (((x) << 18) & GENMASK(19, 18))
+#define SPI_CTAR_PBR(x)                 (((x) << 16) & GENMASK(17, 16))
+#define SPI_CTAR_CSSCK(x)               (((x) << 12) & GENMASK(15, 12))
+#define SPI_CTAR_ASC(x)                 (((x) << 8) & GENMASK(11, 8))
+#define SPI_CTAR_DT(x)                  (((x) << 4) & GENMASK(7, 4))
+#define SPI_CTAR_BR(x)                  ((x) & GENMASK(3, 0))
+#define SPI_CTAR_SCALE_BITS             0xf
+
+#define SPI_CTAR0_SLAVE                 0x0c
+
+#define SPI_SR                          0x2c
+#define SPI_SR_TCFQF                    BIT(31)
+#define SPI_SR_EOQF                     BIT(28)
+#define SPI_SR_TFUF                     BIT(27)
+#define SPI_SR_TFFF                     BIT(25)
+#define SPI_SR_CMDTCF                   BIT(23)
+#define SPI_SR_SPEF                     BIT(21)
+#define SPI_SR_RFOF                     BIT(19)
+#define SPI_SR_TFIWF                    BIT(18)
+#define SPI_SR_RFDF                     BIT(17)
+#define SPI_SR_CMDFFF                   BIT(16)
+#define SPI_SR_CLEAR                    (SPI_SR_TCFQF | SPI_SR_EOQF | \
+                                        SPI_SR_TFUF | SPI_SR_TFFF | \
+                                        SPI_SR_CMDTCF | SPI_SR_SPEF | \
+                                        SPI_SR_RFOF | SPI_SR_TFIWF | \
+                                        SPI_SR_RFDF | SPI_SR_CMDFFF)
+
+#define SPI_RSER_TFFFE                  BIT(25)
+#define SPI_RSER_TFFFD                  BIT(24)
+#define SPI_RSER_RFDFE                  BIT(17)
+#define SPI_RSER_RFDFD                  BIT(16)
+
+#define SPI_RSER                        0x30
+#define SPI_RSER_TCFQE                  BIT(31)
+#define SPI_RSER_EOQFE                  BIT(28)
+
+#define SPI_PUSHR                       0x34
+#define SPI_PUSHR_CMD_CONT              BIT(15)
+#define SPI_PUSHR_CMD_CTAS(x)           (((x) << 12 & GENMASK(14, 12)))
+#define SPI_PUSHR_CMD_EOQ               BIT(11)
+#define SPI_PUSHR_CMD_CTCNT             BIT(10)
+#define SPI_PUSHR_CMD_PCS(x)            (BIT(x) & GENMASK(5, 0))
+
+#define SPI_PUSHR_SLAVE                 0x34
+
+#define SPI_POPR                        0x38
+
+#define SPI_TXFR0                       0x3c
+#define SPI_TXFR1                       0x40
+#define SPI_TXFR2                       0x44
+#define SPI_TXFR3                       0x48
+#define SPI_RXFR0                       0x7c
+#define SPI_RXFR1                       0x80
+#define SPI_RXFR2                       0x84
+#define SPI_RXFR3                       0x88
+
+#define SPI_CTARE(x)                    (0x11c + (((x) & GENMASK(1, 0)) * 4))
+#define SPI_CTARE_FMSZE(x)              (((x) & 0x1) << 16)
+#define SPI_CTARE_DTCP(x)               ((x) & 0x7ff)
+
+#define SPI_SREX                        0x13c
+
+#define SPI_FRAME_BITS(bits)            SPI_CTAR_FMSZ((bits) - 1)
+#define SPI_FRAME_EBITS(bits)           SPI_CTARE_FMSZE(((bits) - 1) >> 4)
 
 /* Register offsets for regmap_pushr */
-#define PUSHR_CMD               0x0
-#define PUSHR_TX                0x2
+#define PUSHR_CMD                       0x0
+#define PUSHR_TX                        0x2
 
-#define SPI_CS_INIT             0x01
-#define SPI_CS_ASSERT           0x02
-#define SPI_CS_DROP             0x04
-
-#define DMA_COMPLETION_TIMEOUT  msecs_to_jiffies(3000)
+#define DMA_COMPLETION_TIMEOUT          msecs_to_jiffies(3000)
 
 struct chip_data {
-        u32 ctar_val;
-        u16 void_write_data;
+        u32                     ctar_val;
+        u16                     void_write_data;
 };
 
 enum dspi_trans_mode {
@@ -141,75 +127,75 @@ enum dspi_trans_mode {
 };
 
 struct fsl_dspi_devtype_data {
-        enum dspi_trans_mode trans_mode;
-        u8 max_clock_factor;
-        bool xspi_mode;
+        enum dspi_trans_mode    trans_mode;
+        u8                      max_clock_factor;
+        bool                    xspi_mode;
 };
 
 static const struct fsl_dspi_devtype_data vf610_data = {
-        .trans_mode = DSPI_DMA_MODE,
-        .max_clock_factor = 2,
+        .trans_mode             = DSPI_DMA_MODE,
+        .max_clock_factor       = 2,
 };
 
 static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
-        .trans_mode = DSPI_TCFQ_MODE,
-        .max_clock_factor = 8,
-        .xspi_mode = true,
+        .trans_mode             = DSPI_TCFQ_MODE,
+        .max_clock_factor       = 8,
+        .xspi_mode              = true,
 };
 
 static const struct fsl_dspi_devtype_data ls2085a_data = {
-        .trans_mode = DSPI_TCFQ_MODE,
-        .max_clock_factor = 8,
+        .trans_mode             = DSPI_TCFQ_MODE,
+        .max_clock_factor       = 8,
 };
 
 static const struct fsl_dspi_devtype_data coldfire_data = {
-        .trans_mode = DSPI_EOQ_MODE,
-        .max_clock_factor = 8,
+        .trans_mode             = DSPI_EOQ_MODE,
+        .max_clock_factor       = 8,
 };
 
 struct fsl_dspi_dma {
         /* Length of transfer in words of DSPI_FIFO_SIZE */
-        u32 curr_xfer_len;
-
-        u32 *tx_dma_buf;
-        struct dma_chan *chan_tx;
-        dma_addr_t tx_dma_phys;
-        struct completion cmd_tx_complete;
-        struct dma_async_tx_descriptor *tx_desc;
-
-        u32 *rx_dma_buf;
-        struct dma_chan *chan_rx;
-        dma_addr_t rx_dma_phys;
-        struct completion cmd_rx_complete;
-        struct dma_async_tx_descriptor *rx_desc;
+        u32                                     curr_xfer_len;
+
+        u32                                     *tx_dma_buf;
+        struct dma_chan                         *chan_tx;
+        dma_addr_t                              tx_dma_phys;
+        struct completion                       cmd_tx_complete;
+        struct dma_async_tx_descriptor          *tx_desc;
+
+        u32                                     *rx_dma_buf;
+        struct dma_chan                         *chan_rx;
+        dma_addr_t                              rx_dma_phys;
+        struct completion                       cmd_rx_complete;
+        struct dma_async_tx_descriptor          *rx_desc;
 };
 
 struct fsl_dspi {
-        struct spi_master       *master;
-        struct platform_device  *pdev;
-
-        struct regmap           *regmap;
-        struct regmap           *regmap_pushr;
-        int                     irq;
-        struct clk              *clk;
-
-        struct spi_transfer     *cur_transfer;
-        struct spi_message      *cur_msg;
-        struct chip_data        *cur_chip;
-        size_t                  len;
-        const void              *tx;
-        void                    *rx;
-        void                    *rx_end;
-        u16                     void_write_data;
-        u16                     tx_cmd;
-        u8                      bits_per_word;
-        u8                      bytes_per_word;
-        const struct fsl_dspi_devtype_data *devtype_data;
-
-        wait_queue_head_t       waitq;
-        u32                     waitflags;
-
-        struct fsl_dspi_dma     *dma;
+        struct spi_controller                   *ctlr;
+        struct platform_device                  *pdev;
+
+        struct regmap                           *regmap;
+        struct regmap                           *regmap_pushr;
+        int                                     irq;
+        struct clk                              *clk;
+
+        struct spi_transfer                     *cur_transfer;
+        struct spi_message                      *cur_msg;
+        struct chip_data                        *cur_chip;
+        size_t                                  len;
+        const void                              *tx;
+        void                                    *rx;
+        void                                    *rx_end;
+        u16                                     void_write_data;
+        u16                                     tx_cmd;
+        u8                                      bits_per_word;
+        u8                                      bytes_per_word;
+        const struct fsl_dspi_devtype_data      *devtype_data;
+
+        wait_queue_head_t                       waitq;
+        u32                                     waitflags;
+
+        struct fsl_dspi_dma                     *dma;
 };
 
 static u32 dspi_pop_tx(struct fsl_dspi *dspi)
@@ -233,7 +219,7 @@ static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
 {
         u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
 
-        if (spi_controller_is_slave(dspi->master))
+        if (spi_controller_is_slave(dspi->ctlr))
                 return data;
 
         if (dspi->len > 0)
@@ -246,7 +232,7 @@ static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
         if (!dspi->rx)
                 return;
 
-        /* Mask of undefined bits */
+        /* Mask off undefined bits */
         rxdata &= (1 << dspi->bits_per_word) - 1;
 
         if (dspi->bytes_per_word == 1)
@@ -282,8 +268,8 @@ static void dspi_rx_dma_callback(void *arg)
 
 static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
 {
-        struct fsl_dspi_dma *dma = dspi->dma;
         struct device *dev = &dspi->pdev->dev;
+        struct fsl_dspi_dma *dma = dspi->dma;
         int time_left;
         int i;
 
@@ -332,13 +318,13 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
         dma_async_issue_pending(dma->chan_rx);
         dma_async_issue_pending(dma->chan_tx);
 
-        if (spi_controller_is_slave(dspi->master)) {
+        if (spi_controller_is_slave(dspi->ctlr)) {
                 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
                 return 0;
         }
 
         time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
-                                        DMA_COMPLETION_TIMEOUT);
+                                                DMA_COMPLETION_TIMEOUT);
         if (time_left == 0) {
                 dev_err(dev, "DMA tx timeout\n");
                 dmaengine_terminate_all(dma->chan_tx);
@@ -347,7 +333,7 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
         }
 
         time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
-                                        DMA_COMPLETION_TIMEOUT);
+                                                DMA_COMPLETION_TIMEOUT);
         if (time_left == 0) {
                 dev_err(dev, "DMA rx timeout\n");
                 dmaengine_terminate_all(dma->chan_tx);
@@ -360,9 +346,9 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
 
 static int dspi_dma_xfer(struct fsl_dspi *dspi)
 {
-        struct fsl_dspi_dma *dma = dspi->dma;
-        struct device *dev = &dspi->pdev->dev;
         struct spi_message *message = dspi->cur_msg;
+        struct device *dev = &dspi->pdev->dev;
+        struct fsl_dspi_dma *dma = dspi->dma;
         int curr_remaining_bytes;
         int bytes_per_buffer;
         int ret = 0;
@@ -397,9 +383,9 @@ exit:
 
 static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
 {
-        struct fsl_dspi_dma *dma;
-        struct dma_slave_config cfg;
         struct device *dev = &dspi->pdev->dev;
+        struct dma_slave_config cfg;
+        struct fsl_dspi_dma *dma;
         int ret;
 
         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
@@ -421,14 +407,14 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
         }
 
         dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
-                                        &dma->tx_dma_phys, GFP_KERNEL);
+                                             &dma->tx_dma_phys, GFP_KERNEL);
         if (!dma->tx_dma_buf) {
                 ret = -ENOMEM;
                 goto err_tx_dma_buf;
         }
 
         dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
-                                        &dma->rx_dma_phys, GFP_KERNEL);
+                                             &dma->rx_dma_phys, GFP_KERNEL);
         if (!dma->rx_dma_buf) {
                 ret = -ENOMEM;
                 goto err_rx_dma_buf;
@@ -485,30 +471,31 @@ static void dspi_release_dma(struct fsl_dspi *dspi)
         struct fsl_dspi_dma *dma = dspi->dma;
         struct device *dev = &dspi->pdev->dev;
 
-        if (dma) {
-                if (dma->chan_tx) {
-                        dma_unmap_single(dev, dma->tx_dma_phys,
-                                        DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
-                        dma_release_channel(dma->chan_tx);
-                }
+        if (!dma)
+                return;
 
-                if (dma->chan_rx) {
-                        dma_unmap_single(dev, dma->rx_dma_phys,
-                                        DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
-                        dma_release_channel(dma->chan_rx);
-                }
+        if (dma->chan_tx) {
+                dma_unmap_single(dev, dma->tx_dma_phys,
+                                 DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
+                dma_release_channel(dma->chan_tx);
+        }
+
+        if (dma->chan_rx) {
+                dma_unmap_single(dev, dma->rx_dma_phys,
+                                 DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
+                dma_release_channel(dma->chan_rx);
         }
 }
 
 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
-                unsigned long clkrate)
+                           unsigned long clkrate)
 {
         /* Valid baud rate pre-scaler values */
         int pbr_tbl[4] = {2, 3, 5, 7};
         int brs[16] = { 2,      4,      6,      8,
-                16,     32,     64,     128,
-                256,    512,    1024,   2048,
-                4096,   8192,   16384,  32768 };
+                        16,     32,     64,     128,
+                        256,    512,    1024,   2048,
+                        4096,   8192,   16384,  32768 };
         int scale_needed, scale, minscale = INT_MAX;
         int i, j;
 
@@ -538,15 +525,15 @@ static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
 }
 
 static void ns_delay_scale(char *psc, char *sc, int delay_ns,
-                unsigned long clkrate)
+                           unsigned long clkrate)
 {
-        int pscale_tbl[4] = {1, 3, 5, 7};
         int scale_needed, scale, minscale = INT_MAX;
-        int i, j;
+        int pscale_tbl[4] = {1, 3, 5, 7};
         u32 remainder;
+        int i, j;
 
         scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
-                        &remainder);
+                                   &remainder);
         if (remainder)
                 scale_needed++;
 
@@ -601,7 +588,7 @@ static void dspi_tcfq_write(struct fsl_dspi *dspi)
                  */
                 u32 data = dspi_pop_tx(dspi);
 
-                if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE(1)) {
+                if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE) {
                         /* LSB */
                         tx_fifo_write(dspi, data & 0xFFFF);
                         tx_fifo_write(dspi, data >> 16);
@@ -655,19 +642,90 @@ static void dspi_eoq_read(struct fsl_dspi *dspi)
 {
         int fifo_size = DSPI_FIFO_SIZE;
 
-        /* Read one FIFO entry at and push to rx buffer */
+        /* Read one FIFO entry and push to rx buffer */
         while ((dspi->rx < dspi->rx_end) && fifo_size--)
                 dspi_push_rx(dspi, fifo_read(dspi));
 }
 
-static int dspi_transfer_one_message(struct spi_master *master,
-                struct spi_message *message)
+static int dspi_rxtx(struct fsl_dspi *dspi)
+{
+        struct spi_message *msg = dspi->cur_msg;
+        enum dspi_trans_mode trans_mode;
+        u16 spi_tcnt;
+        u32 spi_tcr;
+
+        /* Get transfer counter (in number of SPI transfers). It was
+         * reset to 0 when transfer(s) were started.
+         */
+        regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
+        spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
+        /* Update total number of bytes that were transferred */
+        msg->actual_length += spi_tcnt * dspi->bytes_per_word;
+
+        trans_mode = dspi->devtype_data->trans_mode;
+        if (trans_mode == DSPI_EOQ_MODE)
+                dspi_eoq_read(dspi);
+        else if (trans_mode == DSPI_TCFQ_MODE)
+                dspi_tcfq_read(dspi);
+
+        if (!dspi->len)
+                /* Success! */
+                return 0;
+
+        if (trans_mode == DSPI_EOQ_MODE)
+                dspi_eoq_write(dspi);
+        else if (trans_mode == DSPI_TCFQ_MODE)
+                dspi_tcfq_write(dspi);
+
+        return -EINPROGRESS;
+}
+
+static int dspi_poll(struct fsl_dspi *dspi)
+{
+        int tries = 1000;
+        u32 spi_sr;
+
+        do {
+                regmap_read(dspi->regmap, SPI_SR, &spi_sr);
+                regmap_write(dspi->regmap, SPI_SR, spi_sr);
+
+                if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF))
+                        break;
+        } while (--tries);
+
+        if (!tries)
+                return -ETIMEDOUT;
+
+        return dspi_rxtx(dspi);
+}
+
+static irqreturn_t dspi_interrupt(int irq, void *dev_id)
+{
+        struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
+        u32 spi_sr;
+
+        regmap_read(dspi->regmap, SPI_SR, &spi_sr);
+        regmap_write(dspi->regmap, SPI_SR, spi_sr);
+
+        if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)))
+                return IRQ_NONE;
+
+        if (dspi_rxtx(dspi) == 0) {
+                dspi->waitflags = 1;
+                wake_up_interruptible(&dspi->waitq);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static int dspi_transfer_one_message(struct spi_controller *ctlr,
+                                     struct spi_message *message)
 {
-        struct fsl_dspi *dspi = spi_master_get_devdata(master);
+        struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
         struct spi_device *spi = message->spi;
+        enum dspi_trans_mode trans_mode;
         struct spi_transfer *transfer;
         int status = 0;
-        enum dspi_trans_mode trans_mode;
 
         message->actual_length = 0;
 
@@ -677,7 +735,7 @@ static int dspi_transfer_one_message(struct spi_master *master,
                 dspi->cur_chip = spi_get_ctldata(spi);
                 /* Prepare command word for CMD FIFO */
                 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
-                        SPI_PUSHR_CMD_PCS(spi->chip_select);
+                               SPI_PUSHR_CMD_PCS(spi->chip_select);
                 if (list_is_last(&dspi->cur_transfer->transfer_list,
                                  &dspi->cur_msg->transfers)) {
                         /* Leave PCS activated after last transfer when
@@ -718,8 +776,8 @@ static int dspi_transfer_one_message(struct spi_master *master,
                              SPI_FRAME_BITS(transfer->bits_per_word));
                 if (dspi->devtype_data->xspi_mode)
                         regmap_write(dspi->regmap, SPI_CTARE(0),
-                                     SPI_FRAME_EBITS(transfer->bits_per_word)
-                                     | SPI_CTARE_DTCP(1));
+                                     SPI_FRAME_EBITS(transfer->bits_per_word) |
+                                     SPI_CTARE_DTCP(1));
 
                 trans_mode = dspi->devtype_data->trans_mode;
                 switch (trans_mode) {
@@ -733,8 +791,8 @@ static int dspi_transfer_one_message(struct spi_master *master,
                         break;
                 case DSPI_DMA_MODE:
                         regmap_write(dspi->regmap, SPI_RSER,
-                                SPI_RSER_TFFFE | SPI_RSER_TFFFD |
-                                SPI_RSER_RFDFE | SPI_RSER_RFDFD);
+                                     SPI_RSER_TFFFE | SPI_RSER_TFFFD |
+                                     SPI_RSER_RFDFE | SPI_RSER_RFDFD);
                         status = dspi_dma_xfer(dspi);
                         break;
                 default:
@@ -744,13 +802,18 @@ static int dspi_transfer_one_message(struct spi_master *master,
                         goto out;
                 }
 
-                if (trans_mode != DSPI_DMA_MODE) {
-                        if (wait_event_interruptible(dspi->waitq,
-                                                dspi->waitflags))
-                                dev_err(&dspi->pdev->dev,
-                                        "wait transfer complete fail!\n");
+                if (!dspi->irq) {
+                        do {
+                                status = dspi_poll(dspi);
+                        } while (status == -EINPROGRESS);
+                } else if (trans_mode != DSPI_DMA_MODE) {
+                        status = wait_event_interruptible(dspi->waitq,
+                                                          dspi->waitflags);
                         dspi->waitflags = 0;
                 }
+                if (status)
+                        dev_err(&dspi->pdev->dev,
+                                "Waiting for transfer to complete failed!\n");
 
                 if (transfer->delay_usecs)
                         udelay(transfer->delay_usecs);
@@ -758,19 +821,19 @@ static int dspi_transfer_one_message(struct spi_master *master,
 
 out:
         message->status = status;
-        spi_finalize_current_message(master);
+        spi_finalize_current_message(ctlr);
 
         return status;
 }
 
 static int dspi_setup(struct spi_device *spi)
 {
-        struct chip_data *chip;
-        struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
-        struct fsl_dspi_platform_data *pdata;
-        u32 cs_sck_delay = 0, sck_cs_delay = 0;
+        struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
         unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
+        u32 cs_sck_delay = 0, sck_cs_delay = 0;
+        struct fsl_dspi_platform_data *pdata;
         unsigned char pasc = 0, asc = 0;
+        struct chip_data *chip;
         unsigned long clkrate;
 
         /* Only alloc on first setup */
@@ -785,10 +848,10 @@ static int dspi_setup(struct spi_device *spi)
 
         if (!pdata) {
                 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
-                                &cs_sck_delay);
+                                     &cs_sck_delay);
 
                 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
-                                &sck_cs_delay);
+                                     &sck_cs_delay);
         } else {
                 cs_sck_delay = pdata->cs_sck_delay;
                 sck_cs_delay = pdata->sck_cs_delay;
@@ -805,18 +868,22 @@ static int dspi_setup(struct spi_device *spi)
         /* Set After SCK delay scale values */
         ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
 
-        chip->ctar_val = SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
-                | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0);
-
-        if (!spi_controller_is_slave(dspi->master)) {
-                chip->ctar_val |= SPI_CTAR_LSBFE(spi->mode &
-                                                 SPI_LSB_FIRST ? 1 : 0)
-                        | SPI_CTAR_PCSSCK(pcssck)
-                        | SPI_CTAR_CSSCK(cssck)
-                        | SPI_CTAR_PASC(pasc)
-                        | SPI_CTAR_ASC(asc)
-                        | SPI_CTAR_PBR(pbr)
-                        | SPI_CTAR_BR(br);
+        chip->ctar_val = 0;
+        if (spi->mode & SPI_CPOL)
+                chip->ctar_val |= SPI_CTAR_CPOL;
+        if (spi->mode & SPI_CPHA)
+                chip->ctar_val |= SPI_CTAR_CPHA;
+
+        if (!spi_controller_is_slave(dspi->ctlr)) {
+                chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
+                                  SPI_CTAR_CSSCK(cssck) |
+                                  SPI_CTAR_PASC(pasc) |
+                                  SPI_CTAR_ASC(asc) |
+                                  SPI_CTAR_PBR(pbr) |
+                                  SPI_CTAR_BR(br);
+
+                if (spi->mode & SPI_LSB_FIRST)
+                        chip->ctar_val |= SPI_CTAR_LSBFE;
         }
 
         spi_set_ctldata(spi, chip);
@@ -829,70 +896,11 @@ static void dspi_cleanup(struct spi_device *spi)
         struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
 
         dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
-                        spi->master->bus_num, spi->chip_select);
+                spi->controller->bus_num, spi->chip_select);
 
         kfree(chip);
 }
 
-static irqreturn_t dspi_interrupt(int irq, void *dev_id)
-{
-        struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
-        struct spi_message *msg = dspi->cur_msg;
-        enum dspi_trans_mode trans_mode;
-        u32 spi_sr, spi_tcr;
-        u16 spi_tcnt;
-
-        regmap_read(dspi->regmap, SPI_SR, &spi_sr);
-        regmap_write(dspi->regmap, SPI_SR, spi_sr);
-
-
-        if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) {
-                /* Get transfer counter (in number of SPI transfers). It was
-                 * reset to 0 when transfer(s) were started.
-                 */
-                regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
-                spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
-                /* Update total number of bytes that were transferred */
-                msg->actual_length += spi_tcnt * dspi->bytes_per_word;
-
-                trans_mode = dspi->devtype_data->trans_mode;
-                switch (trans_mode) {
-                case DSPI_EOQ_MODE:
-                        dspi_eoq_read(dspi);
-                        break;
-                case DSPI_TCFQ_MODE:
-                        dspi_tcfq_read(dspi);
-                        break;
-                default:
-                        dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
-                                trans_mode);
-                                return IRQ_HANDLED;
-                }
-
-                if (!dspi->len) {
-                        dspi->waitflags = 1;
-                        wake_up_interruptible(&dspi->waitq);
-                } else {
-                        switch (trans_mode) {
-                        case DSPI_EOQ_MODE:
-                                dspi_eoq_write(dspi);
-                                break;
-                        case DSPI_TCFQ_MODE:
-                                dspi_tcfq_write(dspi);
-                                break;
-                        default:
-                                dev_err(&dspi->pdev->dev,
-                                        "unsupported trans_mode %u\n",
-                                        trans_mode);
-                        }
-                }
-
-                return IRQ_HANDLED;
-        }
-
-        return IRQ_NONE;
-}
-
 static const struct of_device_id fsl_dspi_dt_ids[] = {
         { .compatible = "fsl,vf610-dspi", .data = &vf610_data, },
         { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, },
@@ -904,10 +912,10 @@ MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
 #ifdef CONFIG_PM_SLEEP
 static int dspi_suspend(struct device *dev)
 {
-        struct spi_master *master = dev_get_drvdata(dev);
-        struct fsl_dspi *dspi = spi_master_get_devdata(master);
+        struct spi_controller *ctlr = dev_get_drvdata(dev);
+        struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
 
-        spi_master_suspend(master);
+        spi_controller_suspend(ctlr);
         clk_disable_unprepare(dspi->clk);
 
         pinctrl_pm_select_sleep_state(dev);
@@ -917,8 +925,8 @@ static int dspi_suspend(struct device *dev)
 
 static int dspi_resume(struct device *dev)
 {
-        struct spi_master *master = dev_get_drvdata(dev);
-        struct fsl_dspi *dspi = spi_master_get_devdata(master);
+        struct spi_controller *ctlr = dev_get_drvdata(dev);
+        struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
         int ret;
 
         pinctrl_pm_select_default_state(dev);
@@ -926,7 +934,7 @@ static int dspi_resume(struct device *dev)
         ret = clk_prepare_enable(dspi->clk);
         if (ret)
                 return ret;
-        spi_master_resume(master);
+        spi_controller_resume(ctlr);
 
         return 0;
 }
@@ -941,16 +949,16 @@ static const struct regmap_range dspi_volatile_ranges[] = {
 };
 
 static const struct regmap_access_table dspi_volatile_table = {
-        .yes_ranges     = dspi_volatile_ranges,
-        .n_yes_ranges   = ARRAY_SIZE(dspi_volatile_ranges),
+        .yes_ranges     = dspi_volatile_ranges,
+        .n_yes_ranges   = ARRAY_SIZE(dspi_volatile_ranges),
 };
 
 static const struct regmap_config dspi_regmap_config = {
-        .reg_bits = 32,
-        .val_bits = 32,
-        .reg_stride = 4,
-        .max_register = 0x88,
-        .volatile_table = &dspi_volatile_table,
+        .reg_bits       = 32,
+        .val_bits       = 32,
+        .reg_stride     = 4,
+        .max_register   = 0x88,
+        .volatile_table = &dspi_volatile_table,
 };
 
 static const struct regmap_range dspi_xspi_volatile_ranges[] = {
@@ -961,33 +969,34 @@ static const struct regmap_range dspi_xspi_volatile_ranges[] = {
 };
 
 static const struct regmap_access_table dspi_xspi_volatile_table = {
-        .yes_ranges     = dspi_xspi_volatile_ranges,
-        .n_yes_ranges   = ARRAY_SIZE(dspi_xspi_volatile_ranges),
+        .yes_ranges     = dspi_xspi_volatile_ranges,
+        .n_yes_ranges   = ARRAY_SIZE(dspi_xspi_volatile_ranges),
 };
 
 static const struct regmap_config dspi_xspi_regmap_config[] = {
         {
-                .reg_bits = 32,
-                .val_bits = 32,
-                .reg_stride = 4,
-                .max_register = 0x13c,
-                .volatile_table = &dspi_xspi_volatile_table,
+                .reg_bits       = 32,
+                .val_bits       = 32,
+                .reg_stride     = 4,
+                .max_register   = 0x13c,
+                .volatile_table = &dspi_xspi_volatile_table,
         },
         {
-                .name = "pushr",
-                .reg_bits = 16,
-                .val_bits = 16,
-                .reg_stride = 2,
-                .max_register = 0x2,
+                .name           = "pushr",
+                .reg_bits       = 16,
+                .val_bits       = 16,
+                .reg_stride     = 2,
+                .max_register   = 0x2,
         },
 };
 
 static void dspi_init(struct fsl_dspi *dspi)
 {
-        unsigned int mcr = SPI_MCR_PCSIS |
-                (dspi->devtype_data->xspi_mode ? SPI_MCR_XSPI : 0);
+        unsigned int mcr = SPI_MCR_PCSIS;
 
-        if (!spi_controller_is_slave(dspi->master))
+        if (dspi->devtype_data->xspi_mode)
+                mcr |= SPI_MCR_XSPI;
+        if (!spi_controller_is_slave(dspi->ctlr))
                 mcr |= SPI_MCR_MASTER;
 
         regmap_write(dspi->regmap, SPI_MCR, mcr);
@@ -1000,34 +1009,33 @@ static void dspi_init(struct fsl_dspi *dspi)
 static int dspi_probe(struct platform_device *pdev)
 {
         struct device_node *np = pdev->dev.of_node;
-        struct spi_master *master;
+        const struct regmap_config *regmap_config;
+        struct fsl_dspi_platform_data *pdata;
+        struct spi_controller *ctlr;
+        int ret, cs_num, bus_num;
         struct fsl_dspi *dspi;
         struct resource *res;
-        const struct regmap_config *regmap_config;
         void __iomem *base;
-        struct fsl_dspi_platform_data *pdata;
-        int ret = 0, cs_num, bus_num;
 
-        master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
-        if (!master)
+        ctlr = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
+        if (!ctlr)
                 return -ENOMEM;
 
-        dspi = spi_master_get_devdata(master);
+        dspi = spi_controller_get_devdata(ctlr);
         dspi->pdev = pdev;
-        dspi->master = master;
+        dspi->ctlr = ctlr;
 
-        master->transfer = NULL;
-        master->setup = dspi_setup;
-        master->transfer_one_message = dspi_transfer_one_message;
-        master->dev.of_node = pdev->dev.of_node;
+        ctlr->setup = dspi_setup;
+        ctlr->transfer_one_message = dspi_transfer_one_message;
+        ctlr->dev.of_node = pdev->dev.of_node;
 
-        master->cleanup = dspi_cleanup;
-        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
+        ctlr->cleanup = dspi_cleanup;
+        ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
 
         pdata = dev_get_platdata(&pdev->dev);
         if (pdata) {
-                master->num_chipselect = pdata->cs_num;
-                master->bus_num = pdata->bus_num;
+                ctlr->num_chipselect = pdata->cs_num;
+                ctlr->bus_num = pdata->bus_num;
 
                 dspi->devtype_data = &coldfire_data;
         } else {
@@ -1035,38 +1043,38 @@ static int dspi_probe(struct platform_device *pdev)
                 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
                 if (ret < 0) {
                         dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
-                        goto out_master_put;
+                        goto out_ctlr_put;
                 }
-                master->num_chipselect = cs_num;
+                ctlr->num_chipselect = cs_num;
 
                 ret = of_property_read_u32(np, "bus-num", &bus_num);
                 if (ret < 0) {
                         dev_err(&pdev->dev, "can't get bus-num\n");
-                        goto out_master_put;
+                        goto out_ctlr_put;
                 }
-                master->bus_num = bus_num;
+                ctlr->bus_num = bus_num;
 
                 if (of_property_read_bool(np, "spi-slave"))
-                        master->slave = true;
+                        ctlr->slave = true;
 
                 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
                 if (!dspi->devtype_data) {
                         dev_err(&pdev->dev, "can't get devtype_data\n");
                         ret = -EFAULT;
-                        goto out_master_put;
+                        goto out_ctlr_put;
                 }
         }
 
         if (dspi->devtype_data->xspi_mode)
-                master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
+                ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
         else
-                master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
+                ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         base = devm_ioremap_resource(&pdev->dev, res);
         if (IS_ERR(base)) {
                 ret = PTR_ERR(base);
-                goto out_master_put;
+                goto out_ctlr_put;
         }
 
         if (dspi->devtype_data->xspi_mode)
@@ -1078,7 +1086,7 @@ static int dspi_probe(struct platform_device *pdev)
                 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
                                 PTR_ERR(dspi->regmap));
                 ret = PTR_ERR(dspi->regmap);
-                goto out_master_put;
+                goto out_ctlr_put;
         }
 
         if (dspi->devtype_data->xspi_mode) {
@@ -1090,7 +1098,7 @@ static int dspi_probe(struct platform_device *pdev)
                                 "failed to init pushr regmap: %ld\n",
                                 PTR_ERR(dspi->regmap_pushr));
                         ret = PTR_ERR(dspi->regmap_pushr);
-                        goto out_master_put;
+                        goto out_ctlr_put;
                 }
         }
 
@@ -1098,18 +1106,20 @@ static int dspi_probe(struct platform_device *pdev)
         if (IS_ERR(dspi->clk)) {
                 ret = PTR_ERR(dspi->clk);
                 dev_err(&pdev->dev, "unable to get clock\n");
-                goto out_master_put;
+                goto out_ctlr_put;
         }
         ret = clk_prepare_enable(dspi->clk);
         if (ret)
-                goto out_master_put;
+                goto out_ctlr_put;
 
         dspi_init(dspi);
+
         dspi->irq = platform_get_irq(pdev, 0);
-        if (dspi->irq < 0) {
-                dev_err(&pdev->dev, "can't get platform irq\n");
-                ret = dspi->irq;
-                goto out_clk_put;
+        if (dspi->irq <= 0) {
+                dev_info(&pdev->dev,
+                         "can't get platform irq, using poll mode\n");
+                dspi->irq = 0;
+                goto poll_mode;
         }
 
         ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt,
@@ -1119,6 +1129,9 @@ static int dspi_probe(struct platform_device *pdev)
                 goto out_clk_put;
         }
 
+        init_waitqueue_head(&dspi->waitq);
+
+poll_mode:
         if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
                 ret = dspi_request_dma(dspi, res->start);
                 if (ret < 0) {
@@ -1127,15 +1140,14 @@ static int dspi_probe(struct platform_device *pdev)
                 }
         }
 
-        master->max_speed_hz =
+        ctlr->max_speed_hz =
                 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
 
-        init_waitqueue_head(&dspi->waitq);
-        platform_set_drvdata(pdev, master);
+        platform_set_drvdata(pdev, ctlr);
 
-        ret = spi_register_master(master);
+        ret = spi_register_controller(ctlr);
         if (ret != 0) {
-                dev_err(&pdev->dev, "Problem registering DSPI master\n");
+                dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
                 goto out_clk_put;
         }
 
@@ -1143,32 +1155,32 @@ static int dspi_probe(struct platform_device *pdev)
 
 out_clk_put:
         clk_disable_unprepare(dspi->clk);
-out_master_put:
-        spi_master_put(master);
+out_ctlr_put:
+        spi_controller_put(ctlr);
 
         return ret;
 }
 
 static int dspi_remove(struct platform_device *pdev)
 {
-        struct spi_master *master = platform_get_drvdata(pdev);
-        struct fsl_dspi *dspi = spi_master_get_devdata(master);
+        struct spi_controller *ctlr = platform_get_drvdata(pdev);
+        struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
 
         /* Disconnect from the SPI framework */
         dspi_release_dma(dspi);
         clk_disable_unprepare(dspi->clk);
-        spi_unregister_master(dspi->master);
+        spi_unregister_controller(dspi->ctlr);
 
         return 0;
 }
 
 static struct platform_driver fsl_dspi_driver = {
-        .driver.name    = DRIVER_NAME,
-        .driver.of_match_table = fsl_dspi_dt_ids,
-        .driver.owner   = THIS_MODULE,
-        .driver.pm = &dspi_pm,
-        .probe          = dspi_probe,
-        .remove         = dspi_remove,
+        .driver.name            = DRIVER_NAME,
+        .driver.of_match_table  = fsl_dspi_dt_ids,
+        .driver.owner           = THIS_MODULE,
+        .driver.pm              = &dspi_pm,
+        .probe                  = dspi_probe,
+        .remove                 = dspi_remove,
 };
 module_platform_driver(fsl_dspi_driver);