diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-08-07 11:47:00 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-08-07 11:47:00 -0400 |
commit | e669830526a0abaf301bf408df69cde33901ac63 (patch) | |
tree | 0b6043375006d1754bbd1ab2370b0a0536546cc9 /drivers/spi/spi-au1550.c | |
parent | ebb067d2f4e2db59b076f9c9cba0375a8ad1e07c (diff) | |
parent | 475d5928b79bb78326a645863d46ff95c5e25e5a (diff) |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for 3.17. It contains:
- misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy updates
- MIPS ptrace updates and cleanups
- various fixes that will also go to -stable
- a number of cleanups and small non-critical fixes.
- NUMA support for the Loongson 3.
- more support for MSA
- support for MAAR
- various FP enhancements and fixes"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
MIPS: jz4740: remove unnecessary null test before debugfs_remove
MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive
MIPS: ZBOOT: implement stack protector in compressed boot phase
MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT
MIPS: Bonito64: remove a duplicate define
MIPS: Malta: initialise MAARs
MIPS: Initialise MAARs
MIPS: detect presence of MAARs
MIPS: define MAAR register accessors & bits
MIPS: mark MSA experimental
MIPS: Don't build MSA support unless it can be used
MIPS: consistently clear MSA flags when starting & copying threads
MIPS: 16 byte align MSA vector context
MIPS: disable preemption whilst initialising MSA
MIPS: ensure MSA gets disabled during boot
MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains
MIPS: fix MSA context for tasks which don't use FP first
MIPS: init upper 64b of vector registers when MSA is first used
MIPS: save/disable MSA in lose_fpu
MIPS: preserve scalar FP CSR when switching vector context
...
Diffstat (limited to 'drivers/spi/spi-au1550.c')
-rw-r--r-- | drivers/spi/spi-au1550.c | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/drivers/spi/spi-au1550.c b/drivers/spi/spi-au1550.c index fb61464348a1..40c3d43c9292 100644 --- a/drivers/spi/spi-au1550.c +++ b/drivers/spi/spi-au1550.c | |||
@@ -141,13 +141,13 @@ static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw) | |||
141 | PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO | 141 | PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO |
142 | | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO | 142 | | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO |
143 | | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD; | 143 | | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD; |
144 | au_sync(); | 144 | wmb(); /* drain writebuffer */ |
145 | 145 | ||
146 | hw->regs->psc_spievent = | 146 | hw->regs->psc_spievent = |
147 | PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO | 147 | PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO |
148 | | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO | 148 | | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO |
149 | | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD; | 149 | | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD; |
150 | au_sync(); | 150 | wmb(); /* drain writebuffer */ |
151 | } | 151 | } |
152 | 152 | ||
153 | static void au1550_spi_reset_fifos(struct au1550_spi *hw) | 153 | static void au1550_spi_reset_fifos(struct au1550_spi *hw) |
@@ -155,10 +155,10 @@ static void au1550_spi_reset_fifos(struct au1550_spi *hw) | |||
155 | u32 pcr; | 155 | u32 pcr; |
156 | 156 | ||
157 | hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC; | 157 | hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC; |
158 | au_sync(); | 158 | wmb(); /* drain writebuffer */ |
159 | do { | 159 | do { |
160 | pcr = hw->regs->psc_spipcr; | 160 | pcr = hw->regs->psc_spipcr; |
161 | au_sync(); | 161 | wmb(); /* drain writebuffer */ |
162 | } while (pcr != 0); | 162 | } while (pcr != 0); |
163 | } | 163 | } |
164 | 164 | ||
@@ -188,9 +188,9 @@ static void au1550_spi_chipsel(struct spi_device *spi, int value) | |||
188 | au1550_spi_bits_handlers_set(hw, spi->bits_per_word); | 188 | au1550_spi_bits_handlers_set(hw, spi->bits_per_word); |
189 | 189 | ||
190 | cfg = hw->regs->psc_spicfg; | 190 | cfg = hw->regs->psc_spicfg; |
191 | au_sync(); | 191 | wmb(); /* drain writebuffer */ |
192 | hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; | 192 | hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; |
193 | au_sync(); | 193 | wmb(); /* drain writebuffer */ |
194 | 194 | ||
195 | if (spi->mode & SPI_CPOL) | 195 | if (spi->mode & SPI_CPOL) |
196 | cfg |= PSC_SPICFG_BI; | 196 | cfg |= PSC_SPICFG_BI; |
@@ -218,10 +218,10 @@ static void au1550_spi_chipsel(struct spi_device *spi, int value) | |||
218 | cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz); | 218 | cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz); |
219 | 219 | ||
220 | hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE; | 220 | hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE; |
221 | au_sync(); | 221 | wmb(); /* drain writebuffer */ |
222 | do { | 222 | do { |
223 | stat = hw->regs->psc_spistat; | 223 | stat = hw->regs->psc_spistat; |
224 | au_sync(); | 224 | wmb(); /* drain writebuffer */ |
225 | } while ((stat & PSC_SPISTAT_DR) == 0); | 225 | } while ((stat & PSC_SPISTAT_DR) == 0); |
226 | 226 | ||
227 | if (hw->pdata->activate_cs) | 227 | if (hw->pdata->activate_cs) |
@@ -252,9 +252,9 @@ static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t) | |||
252 | au1550_spi_bits_handlers_set(hw, spi->bits_per_word); | 252 | au1550_spi_bits_handlers_set(hw, spi->bits_per_word); |
253 | 253 | ||
254 | cfg = hw->regs->psc_spicfg; | 254 | cfg = hw->regs->psc_spicfg; |
255 | au_sync(); | 255 | wmb(); /* drain writebuffer */ |
256 | hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; | 256 | hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE; |
257 | au_sync(); | 257 | wmb(); /* drain writebuffer */ |
258 | 258 | ||
259 | if (hw->usedma && bpw <= 8) | 259 | if (hw->usedma && bpw <= 8) |
260 | cfg &= ~PSC_SPICFG_DD_DISABLE; | 260 | cfg &= ~PSC_SPICFG_DD_DISABLE; |
@@ -268,12 +268,12 @@ static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t) | |||
268 | cfg |= au1550_spi_baudcfg(hw, hz); | 268 | cfg |= au1550_spi_baudcfg(hw, hz); |
269 | 269 | ||
270 | hw->regs->psc_spicfg = cfg; | 270 | hw->regs->psc_spicfg = cfg; |
271 | au_sync(); | 271 | wmb(); /* drain writebuffer */ |
272 | 272 | ||
273 | if (cfg & PSC_SPICFG_DE_ENABLE) { | 273 | if (cfg & PSC_SPICFG_DE_ENABLE) { |
274 | do { | 274 | do { |
275 | stat = hw->regs->psc_spistat; | 275 | stat = hw->regs->psc_spistat; |
276 | au_sync(); | 276 | wmb(); /* drain writebuffer */ |
277 | } while ((stat & PSC_SPISTAT_DR) == 0); | 277 | } while ((stat & PSC_SPISTAT_DR) == 0); |
278 | } | 278 | } |
279 | 279 | ||
@@ -396,11 +396,11 @@ static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t) | |||
396 | 396 | ||
397 | /* by default enable nearly all events interrupt */ | 397 | /* by default enable nearly all events interrupt */ |
398 | hw->regs->psc_spimsk = PSC_SPIMSK_SD; | 398 | hw->regs->psc_spimsk = PSC_SPIMSK_SD; |
399 | au_sync(); | 399 | wmb(); /* drain writebuffer */ |
400 | 400 | ||
401 | /* start the transfer */ | 401 | /* start the transfer */ |
402 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; | 402 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; |
403 | au_sync(); | 403 | wmb(); /* drain writebuffer */ |
404 | 404 | ||
405 | wait_for_completion(&hw->master_done); | 405 | wait_for_completion(&hw->master_done); |
406 | 406 | ||
@@ -429,7 +429,7 @@ static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw) | |||
429 | 429 | ||
430 | stat = hw->regs->psc_spistat; | 430 | stat = hw->regs->psc_spistat; |
431 | evnt = hw->regs->psc_spievent; | 431 | evnt = hw->regs->psc_spievent; |
432 | au_sync(); | 432 | wmb(); /* drain writebuffer */ |
433 | if ((stat & PSC_SPISTAT_DI) == 0) { | 433 | if ((stat & PSC_SPISTAT_DI) == 0) { |
434 | dev_err(hw->dev, "Unexpected IRQ!\n"); | 434 | dev_err(hw->dev, "Unexpected IRQ!\n"); |
435 | return IRQ_NONE; | 435 | return IRQ_NONE; |
@@ -484,7 +484,7 @@ static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw) | |||
484 | static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \ | 484 | static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \ |
485 | { \ | 485 | { \ |
486 | u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \ | 486 | u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \ |
487 | au_sync(); \ | 487 | wmb(); /* drain writebuffer */ \ |
488 | if (hw->rx) { \ | 488 | if (hw->rx) { \ |
489 | *(u##size *)hw->rx = (u##size)fifoword; \ | 489 | *(u##size *)hw->rx = (u##size)fifoword; \ |
490 | hw->rx += (size) / 8; \ | 490 | hw->rx += (size) / 8; \ |
@@ -504,7 +504,7 @@ static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \ | |||
504 | if (hw->tx_count >= hw->len) \ | 504 | if (hw->tx_count >= hw->len) \ |
505 | fifoword |= PSC_SPITXRX_LC; \ | 505 | fifoword |= PSC_SPITXRX_LC; \ |
506 | hw->regs->psc_spitxrx = fifoword; \ | 506 | hw->regs->psc_spitxrx = fifoword; \ |
507 | au_sync(); \ | 507 | wmb(); /* drain writebuffer */ \ |
508 | } | 508 | } |
509 | 509 | ||
510 | AU1550_SPI_RX_WORD(8,0xff) | 510 | AU1550_SPI_RX_WORD(8,0xff) |
@@ -539,18 +539,18 @@ static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t) | |||
539 | } | 539 | } |
540 | 540 | ||
541 | stat = hw->regs->psc_spistat; | 541 | stat = hw->regs->psc_spistat; |
542 | au_sync(); | 542 | wmb(); /* drain writebuffer */ |
543 | if (stat & PSC_SPISTAT_TF) | 543 | if (stat & PSC_SPISTAT_TF) |
544 | break; | 544 | break; |
545 | } | 545 | } |
546 | 546 | ||
547 | /* enable event interrupts */ | 547 | /* enable event interrupts */ |
548 | hw->regs->psc_spimsk = mask; | 548 | hw->regs->psc_spimsk = mask; |
549 | au_sync(); | 549 | wmb(); /* drain writebuffer */ |
550 | 550 | ||
551 | /* start the transfer */ | 551 | /* start the transfer */ |
552 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; | 552 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; |
553 | au_sync(); | 553 | wmb(); /* drain writebuffer */ |
554 | 554 | ||
555 | wait_for_completion(&hw->master_done); | 555 | wait_for_completion(&hw->master_done); |
556 | 556 | ||
@@ -564,7 +564,7 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) | |||
564 | 564 | ||
565 | stat = hw->regs->psc_spistat; | 565 | stat = hw->regs->psc_spistat; |
566 | evnt = hw->regs->psc_spievent; | 566 | evnt = hw->regs->psc_spievent; |
567 | au_sync(); | 567 | wmb(); /* drain writebuffer */ |
568 | if ((stat & PSC_SPISTAT_DI) == 0) { | 568 | if ((stat & PSC_SPISTAT_DI) == 0) { |
569 | dev_err(hw->dev, "Unexpected IRQ!\n"); | 569 | dev_err(hw->dev, "Unexpected IRQ!\n"); |
570 | return IRQ_NONE; | 570 | return IRQ_NONE; |
@@ -594,7 +594,7 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) | |||
594 | do { | 594 | do { |
595 | busy = 0; | 595 | busy = 0; |
596 | stat = hw->regs->psc_spistat; | 596 | stat = hw->regs->psc_spistat; |
597 | au_sync(); | 597 | wmb(); /* drain writebuffer */ |
598 | 598 | ||
599 | /* | 599 | /* |
600 | * Take care to not let the Rx FIFO overflow. | 600 | * Take care to not let the Rx FIFO overflow. |
@@ -615,7 +615,7 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) | |||
615 | } while (busy); | 615 | } while (busy); |
616 | 616 | ||
617 | hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR; | 617 | hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR; |
618 | au_sync(); | 618 | wmb(); /* drain writebuffer */ |
619 | 619 | ||
620 | /* | 620 | /* |
621 | * Restart the SPI transmission in case of a transmit underflow. | 621 | * Restart the SPI transmission in case of a transmit underflow. |
@@ -634,9 +634,9 @@ static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw) | |||
634 | */ | 634 | */ |
635 | if (evnt & PSC_SPIEVNT_TU) { | 635 | if (evnt & PSC_SPIEVNT_TU) { |
636 | hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD; | 636 | hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD; |
637 | au_sync(); | 637 | wmb(); /* drain writebuffer */ |
638 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; | 638 | hw->regs->psc_spipcr = PSC_SPIPCR_MS; |
639 | au_sync(); | 639 | wmb(); /* drain writebuffer */ |
640 | } | 640 | } |
641 | 641 | ||
642 | if (hw->rx_count >= hw->len) { | 642 | if (hw->rx_count >= hw->len) { |
@@ -690,19 +690,19 @@ static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw) | |||
690 | 690 | ||
691 | /* set up the PSC for SPI mode */ | 691 | /* set up the PSC for SPI mode */ |
692 | hw->regs->psc_ctrl = PSC_CTRL_DISABLE; | 692 | hw->regs->psc_ctrl = PSC_CTRL_DISABLE; |
693 | au_sync(); | 693 | wmb(); /* drain writebuffer */ |
694 | hw->regs->psc_sel = PSC_SEL_PS_SPIMODE; | 694 | hw->regs->psc_sel = PSC_SEL_PS_SPIMODE; |
695 | au_sync(); | 695 | wmb(); /* drain writebuffer */ |
696 | 696 | ||
697 | hw->regs->psc_spicfg = 0; | 697 | hw->regs->psc_spicfg = 0; |
698 | au_sync(); | 698 | wmb(); /* drain writebuffer */ |
699 | 699 | ||
700 | hw->regs->psc_ctrl = PSC_CTRL_ENABLE; | 700 | hw->regs->psc_ctrl = PSC_CTRL_ENABLE; |
701 | au_sync(); | 701 | wmb(); /* drain writebuffer */ |
702 | 702 | ||
703 | do { | 703 | do { |
704 | stat = hw->regs->psc_spistat; | 704 | stat = hw->regs->psc_spistat; |
705 | au_sync(); | 705 | wmb(); /* drain writebuffer */ |
706 | } while ((stat & PSC_SPISTAT_SR) == 0); | 706 | } while ((stat & PSC_SPISTAT_SR) == 0); |
707 | 707 | ||
708 | 708 | ||
@@ -717,16 +717,16 @@ static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw) | |||
717 | #endif | 717 | #endif |
718 | 718 | ||
719 | hw->regs->psc_spicfg = cfg; | 719 | hw->regs->psc_spicfg = cfg; |
720 | au_sync(); | 720 | wmb(); /* drain writebuffer */ |
721 | 721 | ||
722 | au1550_spi_mask_ack_all(hw); | 722 | au1550_spi_mask_ack_all(hw); |
723 | 723 | ||
724 | hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE; | 724 | hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE; |
725 | au_sync(); | 725 | wmb(); /* drain writebuffer */ |
726 | 726 | ||
727 | do { | 727 | do { |
728 | stat = hw->regs->psc_spistat; | 728 | stat = hw->regs->psc_spistat; |
729 | au_sync(); | 729 | wmb(); /* drain writebuffer */ |
730 | } while ((stat & PSC_SPISTAT_DR) == 0); | 730 | } while ((stat & PSC_SPISTAT_DR) == 0); |
731 | 731 | ||
732 | au1550_spi_reset_fifos(hw); | 732 | au1550_spi_reset_fifos(hw); |