diff options
author | Hannes Reinecke <hare@suse.de> | 2015-04-24 07:18:28 -0400 |
---|---|---|
committer | James Bottomley <JBottomley@Odin.com> | 2015-05-25 15:34:20 -0400 |
commit | ae26759e1ceb686ce725e91f0048b90dd98c91ee (patch) | |
tree | 531ccee0bd1431f7a20a869bb7cf23720582b2ae /drivers/scsi/advansys.c | |
parent | 95cfab6c11180f13f0dc47cfef36092189e05801 (diff) |
advansys: Remove 'TRUE' and 'FALSE' definitions
Use 'bool' type instead.
Signed-off-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: James Bottomley <JBottomley@Odin.com>
Diffstat (limited to 'drivers/scsi/advansys.c')
-rw-r--r-- | drivers/scsi/advansys.c | 79 |
1 files changed, 38 insertions, 41 deletions
diff --git a/drivers/scsi/advansys.c b/drivers/scsi/advansys.c index 4e52625f7929..9c3297769490 100644 --- a/drivers/scsi/advansys.c +++ b/drivers/scsi/advansys.c | |||
@@ -78,13 +78,6 @@ | |||
78 | 78 | ||
79 | typedef unsigned char uchar; | 79 | typedef unsigned char uchar; |
80 | 80 | ||
81 | #ifndef TRUE | ||
82 | #define TRUE (1) | ||
83 | #endif | ||
84 | #ifndef FALSE | ||
85 | #define FALSE (0) | ||
86 | #endif | ||
87 | |||
88 | #define ERR (-1) | 81 | #define ERR (-1) |
89 | #define UW_ERR (uint)(0xFFFF) | 82 | #define UW_ERR (uint)(0xFFFF) |
90 | #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0) | 83 | #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0) |
@@ -556,7 +549,7 @@ typedef struct asc_dvc_var { | |||
556 | dma_addr_t overrun_dma; | 549 | dma_addr_t overrun_dma; |
557 | uchar scsi_reset_wait; | 550 | uchar scsi_reset_wait; |
558 | uchar chip_no; | 551 | uchar chip_no; |
559 | char is_in_int; | 552 | bool is_in_int; |
560 | uchar max_total_qng; | 553 | uchar max_total_qng; |
561 | uchar cur_total_qng; | 554 | uchar cur_total_qng; |
562 | uchar in_critical_cnt; | 555 | uchar in_critical_cnt; |
@@ -3754,7 +3747,7 @@ static int AscStartChip(PortAddr iop_base) | |||
3754 | return (1); | 3747 | return (1); |
3755 | } | 3748 | } |
3756 | 3749 | ||
3757 | static int AscStopChip(PortAddr iop_base) | 3750 | static bool AscStopChip(PortAddr iop_base) |
3758 | { | 3751 | { |
3759 | uchar cc_val; | 3752 | uchar cc_val; |
3760 | 3753 | ||
@@ -3765,9 +3758,9 @@ static int AscStopChip(PortAddr iop_base) | |||
3765 | AscSetChipIH(iop_base, INS_HALT); | 3758 | AscSetChipIH(iop_base, INS_HALT); |
3766 | AscSetChipIH(iop_base, INS_RFLAG_WTM); | 3759 | AscSetChipIH(iop_base, INS_RFLAG_WTM); |
3767 | if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) { | 3760 | if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) { |
3768 | return (0); | 3761 | return false; |
3769 | } | 3762 | } |
3770 | return (1); | 3763 | return true; |
3771 | } | 3764 | } |
3772 | 3765 | ||
3773 | static bool AscIsChipHalted(PortAddr iop_base) | 3766 | static bool AscIsChipHalted(PortAddr iop_base) |
@@ -6453,7 +6446,7 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc) | |||
6453 | EXT_MSG ext_msg; | 6446 | EXT_MSG ext_msg; |
6454 | EXT_MSG out_msg; | 6447 | EXT_MSG out_msg; |
6455 | ushort halt_q_addr; | 6448 | ushort halt_q_addr; |
6456 | int sdtr_accept; | 6449 | bool sdtr_accept; |
6457 | ushort int_halt_code; | 6450 | ushort int_halt_code; |
6458 | ASC_SCSI_BIT_ID_TYPE scsi_busy; | 6451 | ASC_SCSI_BIT_ID_TYPE scsi_busy; |
6459 | ASC_SCSI_BIT_ID_TYPE target_id; | 6452 | ASC_SCSI_BIT_ID_TYPE target_id; |
@@ -6512,10 +6505,10 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc) | |||
6512 | if (ext_msg.msg_type == EXTENDED_MESSAGE && | 6505 | if (ext_msg.msg_type == EXTENDED_MESSAGE && |
6513 | ext_msg.msg_req == EXTENDED_SDTR && | 6506 | ext_msg.msg_req == EXTENDED_SDTR && |
6514 | ext_msg.msg_len == MS_SDTR_LEN) { | 6507 | ext_msg.msg_len == MS_SDTR_LEN) { |
6515 | sdtr_accept = TRUE; | 6508 | sdtr_accept = true; |
6516 | if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) { | 6509 | if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) { |
6517 | 6510 | ||
6518 | sdtr_accept = FALSE; | 6511 | sdtr_accept = false; |
6519 | ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; | 6512 | ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; |
6520 | } | 6513 | } |
6521 | if ((ext_msg.xfer_period < | 6514 | if ((ext_msg.xfer_period < |
@@ -6523,7 +6516,7 @@ static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc) | |||
6523 | || (ext_msg.xfer_period > | 6516 | || (ext_msg.xfer_period > |
6524 | asc_dvc->sdtr_period_tbl[asc_dvc-> | 6517 | asc_dvc->sdtr_period_tbl[asc_dvc-> |
6525 | max_sdtr_index])) { | 6518 | max_sdtr_index])) { |
6526 | sdtr_accept = FALSE; | 6519 | sdtr_accept = false; |
6527 | ext_msg.xfer_period = | 6520 | ext_msg.xfer_period = |
6528 | asc_dvc->sdtr_period_tbl[asc_dvc-> | 6521 | asc_dvc->sdtr_period_tbl[asc_dvc-> |
6529 | min_sdtr_index]; | 6522 | min_sdtr_index]; |
@@ -7111,7 +7104,7 @@ static int AscIsrQDone(ASC_DVC_VAR *asc_dvc) | |||
7111 | uchar cur_target_qng; | 7104 | uchar cur_target_qng; |
7112 | ASC_QDONE_INFO scsiq_buf; | 7105 | ASC_QDONE_INFO scsiq_buf; |
7113 | ASC_QDONE_INFO *scsiq; | 7106 | ASC_QDONE_INFO *scsiq; |
7114 | int false_overrun; | 7107 | bool false_overrun; |
7115 | 7108 | ||
7116 | iop_base = asc_dvc->iop_base; | 7109 | iop_base = asc_dvc->iop_base; |
7117 | n_q_used = 1; | 7110 | n_q_used = 1; |
@@ -7189,7 +7182,11 @@ static int AscIsrQDone(ASC_DVC_VAR *asc_dvc) | |||
7189 | ((scsiq->q_status & QS_ABORTED) != 0)) { | 7182 | ((scsiq->q_status & QS_ABORTED) != 0)) { |
7190 | return (0x11); | 7183 | return (0x11); |
7191 | } else if (scsiq->q_status == QS_DONE) { | 7184 | } else if (scsiq->q_status == QS_DONE) { |
7192 | false_overrun = FALSE; | 7185 | /* |
7186 | * This is also curious. | ||
7187 | * false_overrun will _always_ be set to 'false' | ||
7188 | */ | ||
7189 | false_overrun = false; | ||
7193 | if (scsiq->extra_bytes != 0) { | 7190 | if (scsiq->extra_bytes != 0) { |
7194 | scsiq->remain_bytes += scsiq->extra_bytes; | 7191 | scsiq->remain_bytes += scsiq->extra_bytes; |
7195 | } | 7192 | } |
@@ -7262,23 +7259,23 @@ static int AscISR(ASC_DVC_VAR *asc_dvc) | |||
7262 | uchar host_flag; | 7259 | uchar host_flag; |
7263 | 7260 | ||
7264 | iop_base = asc_dvc->iop_base; | 7261 | iop_base = asc_dvc->iop_base; |
7265 | int_pending = FALSE; | 7262 | int_pending = ASC_FALSE; |
7266 | 7263 | ||
7267 | if (AscIsIntPending(iop_base) == 0) | 7264 | if (AscIsIntPending(iop_base) == 0) |
7268 | return int_pending; | 7265 | return int_pending; |
7269 | 7266 | ||
7270 | if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) { | 7267 | if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) { |
7271 | return ERR; | 7268 | return ASC_ERROR; |
7272 | } | 7269 | } |
7273 | if (asc_dvc->in_critical_cnt != 0) { | 7270 | if (asc_dvc->in_critical_cnt != 0) { |
7274 | AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL); | 7271 | AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL); |
7275 | return ERR; | 7272 | return ASC_ERROR; |
7276 | } | 7273 | } |
7277 | if (asc_dvc->is_in_int) { | 7274 | if (asc_dvc->is_in_int) { |
7278 | AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY); | 7275 | AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY); |
7279 | return ERR; | 7276 | return ASC_ERROR; |
7280 | } | 7277 | } |
7281 | asc_dvc->is_in_int = TRUE; | 7278 | asc_dvc->is_in_int = true; |
7282 | ctrl_reg = AscGetChipControl(iop_base); | 7279 | ctrl_reg = AscGetChipControl(iop_base); |
7283 | saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET | | 7280 | saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET | |
7284 | CC_SINGLE_STEP | CC_DIAG | CC_TEST)); | 7281 | CC_SINGLE_STEP | CC_DIAG | CC_TEST)); |
@@ -7286,7 +7283,7 @@ static int AscISR(ASC_DVC_VAR *asc_dvc) | |||
7286 | if (chipstat & CSW_SCSI_RESET_LATCH) { | 7283 | if (chipstat & CSW_SCSI_RESET_LATCH) { |
7287 | if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { | 7284 | if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { |
7288 | int i = 10; | 7285 | int i = 10; |
7289 | int_pending = TRUE; | 7286 | int_pending = ASC_TRUE; |
7290 | asc_dvc->sdtr_done = 0; | 7287 | asc_dvc->sdtr_done = 0; |
7291 | saved_ctrl_reg &= (uchar)(~CC_HALT); | 7288 | saved_ctrl_reg &= (uchar)(~CC_HALT); |
7292 | while ((AscGetChipStatus(iop_base) & | 7289 | while ((AscGetChipStatus(iop_base) & |
@@ -7308,7 +7305,7 @@ static int AscISR(ASC_DVC_VAR *asc_dvc) | |||
7308 | (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR)); | 7305 | (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR)); |
7309 | if ((chipstat & CSW_INT_PENDING) || (int_pending)) { | 7306 | if ((chipstat & CSW_INT_PENDING) || (int_pending)) { |
7310 | AscAckInterrupt(iop_base); | 7307 | AscAckInterrupt(iop_base); |
7311 | int_pending = TRUE; | 7308 | int_pending = ASC_TRUE; |
7312 | if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) { | 7309 | if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) { |
7313 | if (AscIsrChipHalted(asc_dvc) == ERR) { | 7310 | if (AscIsrChipHalted(asc_dvc) == ERR) { |
7314 | goto ISR_REPORT_QDONE_FATAL_ERROR; | 7311 | goto ISR_REPORT_QDONE_FATAL_ERROR; |
@@ -7330,13 +7327,13 @@ static int AscISR(ASC_DVC_VAR *asc_dvc) | |||
7330 | } while (status == 0x11); | 7327 | } while (status == 0x11); |
7331 | } | 7328 | } |
7332 | if ((status & 0x80) != 0) | 7329 | if ((status & 0x80) != 0) |
7333 | int_pending = ERR; | 7330 | int_pending = ASC_ERROR; |
7334 | } | 7331 | } |
7335 | } | 7332 | } |
7336 | AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag); | 7333 | AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag); |
7337 | AscSetChipLramAddr(iop_base, saved_ram_addr); | 7334 | AscSetChipLramAddr(iop_base, saved_ram_addr); |
7338 | AscSetChipControl(iop_base, saved_ctrl_reg); | 7335 | AscSetChipControl(iop_base, saved_ctrl_reg); |
7339 | asc_dvc->is_in_int = FALSE; | 7336 | asc_dvc->is_in_int = false; |
7340 | return int_pending; | 7337 | return int_pending; |
7341 | } | 7338 | } |
7342 | 7339 | ||
@@ -8423,7 +8420,7 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) | |||
8423 | PortAddr iop_base; | 8420 | PortAddr iop_base; |
8424 | int sta; | 8421 | int sta; |
8425 | int n_q_required; | 8422 | int n_q_required; |
8426 | int disable_syn_offset_one_fix; | 8423 | bool disable_syn_offset_one_fix; |
8427 | int i; | 8424 | int i; |
8428 | u32 addr; | 8425 | u32 addr; |
8429 | ushort sg_entry_cnt = 0; | 8426 | ushort sg_entry_cnt = 0; |
@@ -8488,7 +8485,7 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) | |||
8488 | sg_entry_cnt_minus_one = sg_entry_cnt - 1; | 8485 | sg_entry_cnt_minus_one = sg_entry_cnt - 1; |
8489 | } | 8486 | } |
8490 | scsi_cmd = scsiq->cdbptr[0]; | 8487 | scsi_cmd = scsiq->cdbptr[0]; |
8491 | disable_syn_offset_one_fix = FALSE; | 8488 | disable_syn_offset_one_fix = false; |
8492 | if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) && | 8489 | if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) && |
8493 | !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { | 8490 | !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { |
8494 | if (scsiq->q1.cntl & QC_SG_HEAD) { | 8491 | if (scsiq->q1.cntl & QC_SG_HEAD) { |
@@ -8502,7 +8499,7 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) | |||
8502 | } | 8499 | } |
8503 | if (data_cnt != 0UL) { | 8500 | if (data_cnt != 0UL) { |
8504 | if (data_cnt < 512UL) { | 8501 | if (data_cnt < 512UL) { |
8505 | disable_syn_offset_one_fix = TRUE; | 8502 | disable_syn_offset_one_fix = true; |
8506 | } else { | 8503 | } else { |
8507 | for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST; | 8504 | for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST; |
8508 | i++) { | 8505 | i++) { |
@@ -8513,7 +8510,7 @@ static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) | |||
8513 | } | 8510 | } |
8514 | if (scsi_cmd == disable_cmd) { | 8511 | if (scsi_cmd == disable_cmd) { |
8515 | disable_syn_offset_one_fix = | 8512 | disable_syn_offset_one_fix = |
8516 | TRUE; | 8513 | true; |
8517 | break; | 8514 | break; |
8518 | } | 8515 | } |
8519 | } | 8516 | } |
@@ -9058,7 +9055,7 @@ static ushort AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc) | |||
9058 | /* asc_dvc->init_state initialized in AscInitGetConfig(). */ | 9055 | /* asc_dvc->init_state initialized in AscInitGetConfig(). */ |
9059 | asc_dvc->sdtr_done = 0; | 9056 | asc_dvc->sdtr_done = 0; |
9060 | asc_dvc->cur_total_qng = 0; | 9057 | asc_dvc->cur_total_qng = 0; |
9061 | asc_dvc->is_in_int = 0; | 9058 | asc_dvc->is_in_int = false; |
9062 | asc_dvc->in_critical_cnt = 0; | 9059 | asc_dvc->in_critical_cnt = 0; |
9063 | asc_dvc->last_q_shortage = 0; | 9060 | asc_dvc->last_q_shortage = 0; |
9064 | asc_dvc->use_tagged_qng = 0; | 9061 | asc_dvc->use_tagged_qng = 0; |
@@ -9238,7 +9235,7 @@ static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg) | |||
9238 | int retry; | 9235 | int retry; |
9239 | 9236 | ||
9240 | retry = 0; | 9237 | retry = 0; |
9241 | while (TRUE) { | 9238 | while (true) { |
9242 | AscSetChipEEPData(iop_base, data_reg); | 9239 | AscSetChipEEPData(iop_base, data_reg); |
9243 | mdelay(1); | 9240 | mdelay(1); |
9244 | read_back = AscGetChipEEPData(iop_base); | 9241 | read_back = AscGetChipEEPData(iop_base); |
@@ -9374,7 +9371,7 @@ static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, | |||
9374 | int n_error; | 9371 | int n_error; |
9375 | 9372 | ||
9376 | retry = 0; | 9373 | retry = 0; |
9377 | while (TRUE) { | 9374 | while (true) { |
9378 | if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf, | 9375 | if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf, |
9379 | bus_type)) == 0) { | 9376 | bus_type)) == 0) { |
9380 | break; | 9377 | break; |
@@ -9401,7 +9398,7 @@ static ushort AscInitFromEEP(ASC_DVC_VAR *asc_dvc) | |||
9401 | warn_code = 0; | 9398 | warn_code = 0; |
9402 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE); | 9399 | AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE); |
9403 | AscStopQueueExe(iop_base); | 9400 | AscStopQueueExe(iop_base); |
9404 | if ((AscStopChip(iop_base) == FALSE) || | 9401 | if ((AscStopChip(iop_base)) || |
9405 | (AscGetChipScsiCtrl(iop_base) != 0)) { | 9402 | (AscGetChipScsiCtrl(iop_base) != 0)) { |
9406 | asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE; | 9403 | asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE; |
9407 | AscResetChipAndScsiBus(asc_dvc); | 9404 | AscResetChipAndScsiBus(asc_dvc); |
@@ -11093,7 +11090,7 @@ static struct scsi_host_template advansys_template = { | |||
11093 | * must be set. The flag will be cleared in advansys_board_found | 11090 | * must be set. The flag will be cleared in advansys_board_found |
11094 | * for non-ISA adapters. | 11091 | * for non-ISA adapters. |
11095 | */ | 11092 | */ |
11096 | .unchecked_isa_dma = 1, | 11093 | .unchecked_isa_dma = true, |
11097 | /* | 11094 | /* |
11098 | * All adapters controlled by this driver are capable of large | 11095 | * All adapters controlled by this driver are capable of large |
11099 | * scatter-gather lists. According to the mid-level SCSI documentation | 11096 | * scatter-gather lists. According to the mid-level SCSI documentation |
@@ -11269,28 +11266,28 @@ static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop, | |||
11269 | switch (asc_dvc_varp->bus_type) { | 11266 | switch (asc_dvc_varp->bus_type) { |
11270 | #ifdef CONFIG_ISA | 11267 | #ifdef CONFIG_ISA |
11271 | case ASC_IS_ISA: | 11268 | case ASC_IS_ISA: |
11272 | shost->unchecked_isa_dma = TRUE; | 11269 | shost->unchecked_isa_dma = true; |
11273 | share_irq = 0; | 11270 | share_irq = 0; |
11274 | break; | 11271 | break; |
11275 | case ASC_IS_VL: | 11272 | case ASC_IS_VL: |
11276 | shost->unchecked_isa_dma = FALSE; | 11273 | shost->unchecked_isa_dma = false; |
11277 | share_irq = 0; | 11274 | share_irq = 0; |
11278 | break; | 11275 | break; |
11279 | case ASC_IS_EISA: | 11276 | case ASC_IS_EISA: |
11280 | shost->unchecked_isa_dma = FALSE; | 11277 | shost->unchecked_isa_dma = false; |
11281 | share_irq = IRQF_SHARED; | 11278 | share_irq = IRQF_SHARED; |
11282 | break; | 11279 | break; |
11283 | #endif /* CONFIG_ISA */ | 11280 | #endif /* CONFIG_ISA */ |
11284 | #ifdef CONFIG_PCI | 11281 | #ifdef CONFIG_PCI |
11285 | case ASC_IS_PCI: | 11282 | case ASC_IS_PCI: |
11286 | shost->unchecked_isa_dma = FALSE; | 11283 | shost->unchecked_isa_dma = false; |
11287 | share_irq = IRQF_SHARED; | 11284 | share_irq = IRQF_SHARED; |
11288 | break; | 11285 | break; |
11289 | #endif /* CONFIG_PCI */ | 11286 | #endif /* CONFIG_PCI */ |
11290 | default: | 11287 | default: |
11291 | shost_printk(KERN_ERR, shost, "unknown adapter type: " | 11288 | shost_printk(KERN_ERR, shost, "unknown adapter type: " |
11292 | "%d\n", asc_dvc_varp->bus_type); | 11289 | "%d\n", asc_dvc_varp->bus_type); |
11293 | shost->unchecked_isa_dma = TRUE; | 11290 | shost->unchecked_isa_dma = false; |
11294 | share_irq = 0; | 11291 | share_irq = 0; |
11295 | break; | 11292 | break; |
11296 | } | 11293 | } |
@@ -11309,7 +11306,7 @@ static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop, | |||
11309 | * For Wide boards set PCI information before calling | 11306 | * For Wide boards set PCI information before calling |
11310 | * AdvInitGetConfig(). | 11307 | * AdvInitGetConfig(). |
11311 | */ | 11308 | */ |
11312 | shost->unchecked_isa_dma = FALSE; | 11309 | shost->unchecked_isa_dma = false; |
11313 | share_irq = IRQF_SHARED; | 11310 | share_irq = IRQF_SHARED; |
11314 | ASC_DBG(2, "AdvInitGetConfig()\n"); | 11311 | ASC_DBG(2, "AdvInitGetConfig()\n"); |
11315 | 11312 | ||