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authorKunihiko Hayashi <hayashi.kunihiko@socionext.com>2018-03-30 05:44:44 -0400
committerPhilipp Zabel <p.zabel@pengutronix.de>2018-04-27 05:55:59 -0400
commit786367176d61cacaeaad90a2690c0637971323ea (patch)
tree752c903194b15c2f05c282bd6fffb16b4b149f06 /drivers/reset
parentfdc0f235d19492e64914ee60bb93a34d063a319b (diff)
reset: uniphier: add SATA reset control support and change SATA-PHY ID
Add reset lines for SATA controller on UniPhier SoCs. This adds support for Pro4 and PXs3 in addition to PXs2. And this changes the ID of the reset line for SATA-PHY on PXs2. Since some SoCs have two controller instances with a common PHY, this moves the ID of SATA-PHY for consistency. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'drivers/reset')
-rw-r--r--drivers/reset/reset-uniphier.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index d044b717fe49..55821846672b 100644
--- a/drivers/reset/reset-uniphier.c
+++ b/drivers/reset/reset-uniphier.c
@@ -63,6 +63,9 @@ static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
63 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */ 63 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
64 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ 64 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
65 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ 65 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
66 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
67 UNIPHIER_RESETX(29, 0x2004, 18), /* SATA1 */
68 UNIPHIER_RESETX(30, 0x2000, 19), /* SATA-PHY */
66 UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */ 69 UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */
67 UNIPHIER_RESET_END, 70 UNIPHIER_RESET_END,
68}; 71};
@@ -90,7 +93,7 @@ static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
90 UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */ 93 UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
91 UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */ 94 UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */
92 UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */ 95 UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */
93 UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */ 96 UNIPHIER_RESET(30, 0x2014, 8), /* SATA-PHY (active high) */
94 UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */ 97 UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */
95 UNIPHIER_RESET_END, 98 UNIPHIER_RESET_END,
96}; 99};
@@ -137,6 +140,9 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
137 UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */ 140 UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */
138 UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */ 141 UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */
139 UNIPHIER_RESETX(24, 0x200c, 3), /* PCIe */ 142 UNIPHIER_RESETX(24, 0x200c, 3), /* PCIe */
143 UNIPHIER_RESETX(28, 0x200c, 7), /* SATA0 */
144 UNIPHIER_RESETX(29, 0x200c, 8), /* SATA1 */
145 UNIPHIER_RESETX(30, 0x200c, 21), /* SATA-PHY */
140 UNIPHIER_RESET_END, 146 UNIPHIER_RESET_END,
141}; 147};
142 148