Merge tag 'platform-drivers-x86-v4.16-3' of git://github.com/dvhart/linux-pdx86

Pull x86 platform driver updates from Darren Hart:
 "Mellanox fixes and new system type support.

  Mostly data for new system types with a correction and an
  uninitialized variable fix"

[ Pulling from github because git.infradead.org currently seems to be
  down for some reason, but Darren had a backup location    - Linus ]

* tag 'platform-drivers-x86-v4.16-3' of git://github.com/dvhart/linux-pdx86:
  platform/x86: mlx-platform: Add support for new 200G IB and Ethernet systems
  platform/x86: mlx-platform: Add support for new msn201x system type
  platform/x86: mlx-platform: Add support for new msn274x system type
  platform/x86: mlx-platform: Fix power cable setting for msn21xx family
  platform/x86: mlx-platform: Add define for the negative bus
  platform/x86: mlx-platform: Use defines for bus assignment
  platform/mellanox: mlxreg-hotplug: Fix uninitialized variable

2 files changed, 363 insertions, 11 deletions

diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c
index 0dfa1ca0d05b..313cf8ad77bf 100644
--- a/drivers/platform/mellanox/mlxreg-hotplug.c
+++ b/drivers/platform/mellanox/mlxreg-hotplug.c
@@ -300,7 +300,7 @@ mlxreg_hotplug_health_work_helper(struct mlxreg_hotplug_priv_data *priv,
 {
         struct mlxreg_core_data *data = item->data;
         u32 regval;
-        int i, ret;
+        int i, ret = 0;
 
         for (i = 0; i < item->count; i++, data++) {
                 /* Mask event. */
diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c
index 27de29961f5e..454e14f02285 100644
--- a/drivers/platform/x86/mlx-platform.c
+++ b/drivers/platform/x86/mlx-platform.c
@@ -77,10 +77,13 @@
 #define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF  0x40
 #define MLXPLAT_CPLD_AGGR_MASK_DEF      (MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \
                                          MLXPLAT_CPLD_AGGR_FAN_MASK_DEF)
+#define MLXPLAT_CPLD_AGGR_MASK_NG_DEF   0x04
+#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW  0xc0
 #define MLXPLAT_CPLD_AGGR_MASK_MSN21XX  0x04
 #define MLXPLAT_CPLD_PSU_MASK           GENMASK(1, 0)
 #define MLXPLAT_CPLD_PWR_MASK           GENMASK(1, 0)
 #define MLXPLAT_CPLD_FAN_MASK           GENMASK(3, 0)
+#define MLXPLAT_CPLD_FAN_NG_MASK        GENMASK(5, 0)
 
 /* Start channel numbers */
 #define MLXPLAT_CPLD_CH1                        2
@@ -89,6 +92,15 @@
 /* Number of LPC attached MUX platform devices */
 #define MLXPLAT_CPLD_LPC_MUX_DEVS               2
 
+/* Hotplug devices adapter numbers */
+#define MLXPLAT_CPLD_NR_NONE                    -1
+#define MLXPLAT_CPLD_PSU_DEFAULT_NR             10
+#define MLXPLAT_CPLD_PSU_MSNXXXX_NR             4
+#define MLXPLAT_CPLD_FAN1_DEFAULT_NR            11
+#define MLXPLAT_CPLD_FAN2_DEFAULT_NR            12
+#define MLXPLAT_CPLD_FAN3_DEFAULT_NR            13
+#define MLXPLAT_CPLD_FAN4_DEFAULT_NR            14
+
 /* mlxplat_priv - platform private data
  * @pdev_i2c - i2c controller platform device
  * @pdev_mux - array of mux platform devices
@@ -159,6 +171,15 @@ static struct i2c_board_info mlxplat_mlxcpld_psu[] = {
         },
 };
 
+static struct i2c_board_info mlxplat_mlxcpld_ng_psu[] = {
+        {
+                I2C_BOARD_INFO("24c32", 0x51),
+        },
+        {
+                I2C_BOARD_INFO("24c32", 0x50),
+        },
+};
+
 static struct i2c_board_info mlxplat_mlxcpld_pwr[] = {
         {
                 I2C_BOARD_INFO("dps460", 0x59),
@@ -190,14 +211,14 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = {
                 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
                 .mask = BIT(0),
                 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[0],
-                .hpdev.nr = 10,
+                .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
         },
         {
                 .label = "psu2",
                 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
                 .mask = BIT(1),
                 .hpdev.brdinfo = &mlxplat_mlxcpld_psu[1],
-                .hpdev.nr = 10,
+                .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
         },
 };
 
@@ -207,14 +228,14 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = {
                 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
                 .mask = BIT(0),
                 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
-                .hpdev.nr = 10,
+                .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
         },
         {
                 .label = "pwr2",
                 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
                 .mask = BIT(1),
                 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
-                .hpdev.nr = 10,
+                .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR,
         },
 };
 
@@ -224,28 +245,28 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = {
                 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
                 .mask = BIT(0),
                 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0],
-                .hpdev.nr = 11,
+                .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR,
         },
         {
                 .label = "fan2",
                 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
                 .mask = BIT(1),
                 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1],
-                .hpdev.nr = 12,
+                .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR,
         },
         {
                 .label = "fan3",
                 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
                 .mask = BIT(2),
                 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2],
-                .hpdev.nr = 13,
+                .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR,
         },
         {
                 .label = "fan4",
                 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
                 .mask = BIT(3),
                 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3],
-                .hpdev.nr = 14,
+                .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR,
         },
 };
 
@@ -287,14 +308,29 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = {
         .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
 };
 
+static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = {
+        {
+                .label = "pwr1",
+                .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
+                .mask = BIT(0),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+        {
+                .label = "pwr2",
+                .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
+                .mask = BIT(1),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+};
+
 /* Platform hotplug MSN21xx system family data */
 static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = {
         {
-                .data = mlxplat_mlxcpld_default_pwr_items_data,
+                .data = mlxplat_mlxcpld_msn21xx_pwr_items_data,
                 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
                 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
                 .mask = MLXPLAT_CPLD_PWR_MASK,
-                .count = ARRAY_SIZE(mlxplat_mlxcpld_pwr),
+                .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data),
                 .inversed = 0,
                 .health = false,
         },
@@ -306,6 +342,245 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = {
         .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items),
         .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
         .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
+        .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
+        .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
+};
+
+/* Platform hotplug msn274x system family data */
+static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = {
+        {
+                .label = "psu1",
+                .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
+                .mask = BIT(0),
+                .hpdev.brdinfo = &mlxplat_mlxcpld_psu[0],
+                .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
+        },
+        {
+                .label = "psu2",
+                .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
+                .mask = BIT(1),
+                .hpdev.brdinfo = &mlxplat_mlxcpld_psu[1],
+                .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
+        },
+};
+
+static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = {
+        {
+                .label = "pwr1",
+                .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
+                .mask = BIT(0),
+                .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0],
+                .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
+        },
+        {
+                .label = "pwr2",
+                .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
+                .mask = BIT(1),
+                .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1],
+                .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
+        },
+};
+
+static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = {
+        {
+                .label = "fan1",
+                .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+                .mask = BIT(0),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+        {
+                .label = "fan2",
+                .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+                .mask = BIT(1),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+        {
+                .label = "fan3",
+                .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+                .mask = BIT(2),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+        {
+                .label = "fan4",
+                .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+                .mask = BIT(3),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+};
+
+static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = {
+        {
+                .data = mlxplat_mlxcpld_msn274x_psu_items_data,
+                .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
+                .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
+                .mask = MLXPLAT_CPLD_PSU_MASK,
+                .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data),
+                .inversed = 1,
+                .health = false,
+        },
+        {
+                .data = mlxplat_mlxcpld_default_ng_pwr_items_data,
+                .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
+                .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
+                .mask = MLXPLAT_CPLD_PWR_MASK,
+                .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data),
+                .inversed = 0,
+                .health = false,
+        },
+        {
+                .data = mlxplat_mlxcpld_msn274x_fan_items_data,
+                .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
+                .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+                .mask = MLXPLAT_CPLD_FAN_MASK,
+                .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data),
+                .inversed = 1,
+                .health = false,
+        },
+};
+
+static
+struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = {
+        .items = mlxplat_mlxcpld_msn274x_items,
+        .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items),
+        .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
+        .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
+        .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
+        .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
+};
+
+/* Platform hotplug MSN201x system family data */
+static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = {
+        {
+                .label = "pwr1",
+                .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
+                .mask = BIT(0),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+        {
+                .label = "pwr2",
+                .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
+                .mask = BIT(1),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+};
+
+static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = {
+        {
+                .data = mlxplat_mlxcpld_msn201x_pwr_items_data,
+                .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF,
+                .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
+                .mask = MLXPLAT_CPLD_PWR_MASK,
+                .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data),
+                .inversed = 0,
+                .health = false,
+        },
+};
+
+static
+struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = {
+        .items = mlxplat_mlxcpld_msn21xx_items,
+        .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items),
+        .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
+        .mask = MLXPLAT_CPLD_AGGR_MASK_DEF,
+        .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
+        .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
+};
+
+/* Platform hotplug next generation system family data */
+static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = {
+        {
+                .label = "psu1",
+                .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
+                .mask = BIT(0),
+                .hpdev.brdinfo = &mlxplat_mlxcpld_ng_psu[0],
+                .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
+        },
+        {
+                .label = "psu2",
+                .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
+                .mask = BIT(1),
+                .hpdev.brdinfo = &mlxplat_mlxcpld_ng_psu[1],
+                .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR,
+        },
+};
+
+static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = {
+        {
+                .label = "fan1",
+                .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+                .mask = BIT(0),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+        {
+                .label = "fan2",
+                .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+                .mask = BIT(1),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+        {
+                .label = "fan3",
+                .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+                .mask = BIT(2),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+        {
+                .label = "fan4",
+                .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+                .mask = BIT(3),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+        {
+                .label = "fan5",
+                .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+                .mask = BIT(4),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+        {
+                .label = "fan6",
+                .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+                .mask = BIT(5),
+                .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
+        },
+};
+
+static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = {
+        {
+                .data = mlxplat_mlxcpld_default_ng_psu_items_data,
+                .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
+                .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET,
+                .mask = MLXPLAT_CPLD_PSU_MASK,
+                .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data),
+                .inversed = 1,
+                .health = false,
+        },
+        {
+                .data = mlxplat_mlxcpld_default_ng_pwr_items_data,
+                .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
+                .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET,
+                .mask = MLXPLAT_CPLD_PWR_MASK,
+                .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data),
+                .inversed = 0,
+                .health = false,
+        },
+        {
+                .data = mlxplat_mlxcpld_default_ng_fan_items_data,
+                .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
+                .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
+                .mask = MLXPLAT_CPLD_FAN_NG_MASK,
+                .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data),
+                .inversed = 1,
+                .health = false,
+        },
+};
+
+static
+struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = {
+        .items = mlxplat_mlxcpld_default_ng_items,
+        .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items),
+        .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET,
+        .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF,
+        .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET,
+        .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW,
 };
 
 static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
@@ -437,8 +712,57 @@ static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi)
         return 1;
 };
 
+static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
+                mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
+                mlxplat_mux_data[i].n_values =
+                                ARRAY_SIZE(mlxplat_msn21xx_channels);
+        }
+        mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data;
+
+        return 1;
+};
+
+static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
+                mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
+                mlxplat_mux_data[i].n_values =
+                                ARRAY_SIZE(mlxplat_msn21xx_channels);
+        }
+        mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data;
+
+        return 1;
+};
+
+static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(mlxplat_mux_data); i++) {
+                mlxplat_mux_data[i].values = mlxplat_msn21xx_channels;
+                mlxplat_mux_data[i].n_values =
+                                ARRAY_SIZE(mlxplat_msn21xx_channels);
+        }
+        mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data;
+
+        return 1;
+};
+
 static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
         {
+                .callback = mlxplat_dmi_msn274x_matched,
+                .matches = {
+                        DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"),
+                },
+        },
+        {
                 .callback = mlxplat_dmi_default_matched,
                 .matches = {
                         DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
@@ -473,6 +797,34 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
                         DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"),
                 },
         },
+        {
+                .callback = mlxplat_dmi_msn201x_matched,
+                .matches = {
+                        DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"),
+                },
+        },
+        {
+                .callback = mlxplat_dmi_qmb7xx_matched,
+                .matches = {
+                        DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "QMB7"),
+                },
+        },
+        {
+                .callback = mlxplat_dmi_qmb7xx_matched,
+                .matches = {
+                        DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "SN37"),
+                },
+        },
+        {
+                .callback = mlxplat_dmi_qmb7xx_matched,
+                .matches = {
+                        DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "SN34"),
+                },
+        },
         { }
 };