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authorLinus Walleij <linus.walleij@linaro.org>2019-01-28 09:02:04 -0500
committerLinus Walleij <linus.walleij@linaro.org>2019-01-28 09:02:04 -0500
commitc6868f7cab3d31a7e8de20104e1d7690e48f732f (patch)
tree691273fdf57c522338cce5cbc187bc016ec36bc8 /drivers/pinctrl
parent4f41e66cf555f74b5aa490684e72b4a6aa34988d (diff)
parent8e32e881947be98abaa917157fefc4a3319e90af (diff)
Merge tag 'sh-pfc-for-v5.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v5.1 - Add TMU pin groups on R-Car E3, - Miscellaneous fixes and cleanups.
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c6
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c17
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c68
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7794.c16
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795.c90
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7796.c90
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77965.c6
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77970.c128
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77980.c64
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77990.c133
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77995.c11
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c2
12 files changed, 288 insertions, 343 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 6bcdb4b5e69e..068b5e6334d1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1264,8 +1264,8 @@ static const struct sh_pfc_pin pinmux_pins[] = {
1264 1264
1265 /* Pins not associated with a GPIO port */ 1265 /* Pins not associated with a GPIO port */
1266 SH_PFC_PIN_NAMED(3, 20, C20), 1266 SH_PFC_PIN_NAMED(3, 20, C20),
1267 SH_PFC_PIN_NAMED(20, 1, T1), 1267 SH_PFC_PIN_NAMED(1, 20, A20),
1268 SH_PFC_PIN_NAMED(25, 2, Y2), 1268 SH_PFC_PIN_NAMED(2, 25, B25),
1269}; 1269};
1270 1270
1271/* - macro */ 1271/* - macro */
@@ -1400,7 +1400,7 @@ HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A,
1400 HSPI_RX1_A, HSPI_TX1_A); 1400 HSPI_RX1_A, HSPI_TX1_A);
1401 1401
1402HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26), 1402HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26),
1403 PIN_NUMBER(20, 1), PIN_NUMBER(25, 2)); 1403 PIN_NUMBER(1, 20), PIN_NUMBER(2, 25));
1404HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B, 1404HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B,
1405 HSPI_RX1_B, HSPI_TX1_B); 1405 HSPI_RX1_B, HSPI_TX1_B);
1406 1406
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index ab7a35392cd8..a84229cb8cd4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -10,7 +10,9 @@
10 10
11#include <linux/io.h> 11#include <linux/io.h>
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/sys_soc.h>
13 14
15#include "core.h"
14#include "sh_pfc.h" 16#include "sh_pfc.h"
15 17
16/* 18/*
@@ -5691,7 +5693,22 @@ static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
5691 return 31 - (pin & 0x1f); 5693 return 31 - (pin & 0x1f);
5692} 5694}
5693 5695
5696static const struct soc_device_attribute r8a7790_tdsel[] = {
5697 { .soc_id = "r8a7790", .revision = "ES1.0" },
5698 { /* sentinel */ }
5699};
5700
5701static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
5702{
5703 /* Initialize TDSEL on old revisions */
5704 if (soc_device_match(r8a7790_tdsel))
5705 sh_pfc_write(pfc, 0xe6060088, 0x00155554);
5706
5707 return 0;
5708}
5709
5694static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { 5710static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
5711 .init = r8a7790_pinmux_soc_init,
5695 .pin_to_pocctrl = r8a7790_pin_to_pocctrl, 5712 .pin_to_pocctrl = r8a7790_pin_to_pocctrl,
5696}; 5713};
5697 5714
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 2859231aaffc..bd363f2e196f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -4317,7 +4317,7 @@ static const unsigned int vin1_clk_pins[] = {
4317static const unsigned int vin1_clk_mux[] = { 4317static const unsigned int vin1_clk_mux[] = {
4318 VI1_CLK_MARK, 4318 VI1_CLK_MARK,
4319}; 4319};
4320static const union vin_data vin1_b_data_pins = { 4320static const union vin_data vin1_data_b_pins = {
4321 .data24 = { 4321 .data24 = {
4322 /* B */ 4322 /* B */
4323 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), 4323 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
@@ -4336,7 +4336,7 @@ static const union vin_data vin1_b_data_pins = {
4336 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 4336 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4337 }, 4337 },
4338}; 4338};
4339static const union vin_data vin1_b_data_mux = { 4339static const union vin_data vin1_data_b_mux = {
4340 .data24 = { 4340 .data24 = {
4341 /* B */ 4341 /* B */
4342 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, 4342 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
@@ -4355,7 +4355,7 @@ static const union vin_data vin1_b_data_mux = {
4355 VI1_R6_B_MARK, VI1_R7_B_MARK, 4355 VI1_R6_B_MARK, VI1_R7_B_MARK,
4356 }, 4356 },
4357}; 4357};
4358static const unsigned int vin1_b_data18_pins[] = { 4358static const unsigned int vin1_data18_b_pins[] = {
4359 /* B */ 4359 /* B */
4360 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 4360 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4361 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 4361 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
@@ -4369,7 +4369,7 @@ static const unsigned int vin1_b_data18_pins[] = {
4369 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), 4369 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4370 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), 4370 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4371}; 4371};
4372static const unsigned int vin1_b_data18_mux[] = { 4372static const unsigned int vin1_data18_b_mux[] = {
4373 /* B */ 4373 /* B */
4374 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, 4374 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4375 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, 4375 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
@@ -4383,30 +4383,30 @@ static const unsigned int vin1_b_data18_mux[] = {
4383 VI1_R4_B_MARK, VI1_R5_B_MARK, 4383 VI1_R4_B_MARK, VI1_R5_B_MARK,
4384 VI1_R6_B_MARK, VI1_R7_B_MARK, 4384 VI1_R6_B_MARK, VI1_R7_B_MARK,
4385}; 4385};
4386static const unsigned int vin1_b_sync_pins[] = { 4386static const unsigned int vin1_sync_b_pins[] = {
4387 RCAR_GP_PIN(3, 17), /* HSYNC */ 4387 RCAR_GP_PIN(3, 17), /* HSYNC */
4388 RCAR_GP_PIN(3, 18), /* VSYNC */ 4388 RCAR_GP_PIN(3, 18), /* VSYNC */
4389}; 4389};
4390static const unsigned int vin1_b_sync_mux[] = { 4390static const unsigned int vin1_sync_b_mux[] = {
4391 VI1_HSYNC_N_B_MARK, 4391 VI1_HSYNC_N_B_MARK,
4392 VI1_VSYNC_N_B_MARK, 4392 VI1_VSYNC_N_B_MARK,
4393}; 4393};
4394static const unsigned int vin1_b_field_pins[] = { 4394static const unsigned int vin1_field_b_pins[] = {
4395 RCAR_GP_PIN(3, 20), 4395 RCAR_GP_PIN(3, 20),
4396}; 4396};
4397static const unsigned int vin1_b_field_mux[] = { 4397static const unsigned int vin1_field_b_mux[] = {
4398 VI1_FIELD_B_MARK, 4398 VI1_FIELD_B_MARK,
4399}; 4399};
4400static const unsigned int vin1_b_clkenb_pins[] = { 4400static const unsigned int vin1_clkenb_b_pins[] = {
4401 RCAR_GP_PIN(3, 19), 4401 RCAR_GP_PIN(3, 19),
4402}; 4402};
4403static const unsigned int vin1_b_clkenb_mux[] = { 4403static const unsigned int vin1_clkenb_b_mux[] = {
4404 VI1_CLKENB_B_MARK, 4404 VI1_CLKENB_B_MARK,
4405}; 4405};
4406static const unsigned int vin1_b_clk_pins[] = { 4406static const unsigned int vin1_clk_b_pins[] = {
4407 RCAR_GP_PIN(3, 16), 4407 RCAR_GP_PIN(3, 16),
4408}; 4408};
4409static const unsigned int vin1_b_clk_mux[] = { 4409static const unsigned int vin1_clk_b_mux[] = {
4410 VI1_CLK_B_MARK, 4410 VI1_CLK_B_MARK,
4411}; 4411};
4412/* - VIN2 ----------------------------------------------------------------- */ 4412/* - VIN2 ----------------------------------------------------------------- */
@@ -4784,17 +4784,17 @@ static const struct {
4784 SH_PFC_PIN_GROUP(vin1_field), 4784 SH_PFC_PIN_GROUP(vin1_field),
4785 SH_PFC_PIN_GROUP(vin1_clkenb), 4785 SH_PFC_PIN_GROUP(vin1_clkenb),
4786 SH_PFC_PIN_GROUP(vin1_clk), 4786 SH_PFC_PIN_GROUP(vin1_clk),
4787 VIN_DATA_PIN_GROUP(vin1_b_data, 24), 4787 VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
4788 VIN_DATA_PIN_GROUP(vin1_b_data, 20), 4788 VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
4789 SH_PFC_PIN_GROUP(vin1_b_data18), 4789 SH_PFC_PIN_GROUP(vin1_data18_b),
4790 VIN_DATA_PIN_GROUP(vin1_b_data, 16), 4790 VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
4791 VIN_DATA_PIN_GROUP(vin1_b_data, 12), 4791 VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
4792 VIN_DATA_PIN_GROUP(vin1_b_data, 10), 4792 VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
4793 VIN_DATA_PIN_GROUP(vin1_b_data, 8), 4793 VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
4794 SH_PFC_PIN_GROUP(vin1_b_sync), 4794 SH_PFC_PIN_GROUP(vin1_sync_b),
4795 SH_PFC_PIN_GROUP(vin1_b_field), 4795 SH_PFC_PIN_GROUP(vin1_field_b),
4796 SH_PFC_PIN_GROUP(vin1_b_clkenb), 4796 SH_PFC_PIN_GROUP(vin1_clkenb_b),
4797 SH_PFC_PIN_GROUP(vin1_b_clk), 4797 SH_PFC_PIN_GROUP(vin1_clk_b),
4798 SH_PFC_PIN_GROUP(vin2_data8), 4798 SH_PFC_PIN_GROUP(vin2_data8),
4799 SH_PFC_PIN_GROUP(vin2_sync), 4799 SH_PFC_PIN_GROUP(vin2_sync),
4800 SH_PFC_PIN_GROUP(vin2_field), 4800 SH_PFC_PIN_GROUP(vin2_field),
@@ -5335,17 +5335,17 @@ static const char * const vin1_groups[] = {
5335 "vin1_field", 5335 "vin1_field",
5336 "vin1_clkenb", 5336 "vin1_clkenb",
5337 "vin1_clk", 5337 "vin1_clk",
5338 "vin1_b_data24", 5338 "vin1_data24_b",
5339 "vin1_b_data20", 5339 "vin1_data20_b",
5340 "vin1_b_data18", 5340 "vin1_data18_b",
5341 "vin1_b_data16", 5341 "vin1_data16_b",
5342 "vin1_b_data12", 5342 "vin1_data12_b",
5343 "vin1_b_data10", 5343 "vin1_data10_b",
5344 "vin1_b_data8", 5344 "vin1_data8_b",
5345 "vin1_b_sync", 5345 "vin1_sync_b",
5346 "vin1_b_field", 5346 "vin1_field_b",
5347 "vin1_b_clkenb", 5347 "vin1_clkenb_b",
5348 "vin1_b_clk", 5348 "vin1_clk_b",
5349}; 5349};
5350 5350
5351static const char * const vin2_groups[] = { 5351static const char * const vin2_groups[] = {
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
index fcf1339c4058..958a5f714c93 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -8,6 +8,7 @@
8 */ 8 */
9 9
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/sys_soc.h>
11 12
12#include "core.h" 13#include "core.h"
13#include "sh_pfc.h" 14#include "sh_pfc.h"
@@ -5560,7 +5561,22 @@ static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
5560 return -EINVAL; 5561 return -EINVAL;
5561} 5562}
5562 5563
5564static const struct soc_device_attribute r8a7794_tdsel[] = {
5565 { .soc_id = "r8a7794", .revision = "ES1.0" },
5566 { /* sentinel */ }
5567};
5568
5569static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
5570{
5571 /* Initialize TDSEL on old revisions */
5572 if (soc_device_match(r8a7794_tdsel))
5573 sh_pfc_write(pfc, 0xe6060068, 0x55555500);
5574
5575 return 0;
5576}
5577
5563static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { 5578static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
5579 .init = r8a7794_pinmux_soc_init,
5564 .pin_to_pocctrl = r8a7794_pin_to_pocctrl, 5580 .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
5565}; 5581};
5566 5582
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 01105bb83598..db9add1405c5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -4098,67 +4098,29 @@ static const unsigned int vin4_clk_mux[] = {
4098}; 4098};
4099 4099
4100/* - VIN5 ------------------------------------------------------------------- */ 4100/* - VIN5 ------------------------------------------------------------------- */
4101static const unsigned int vin5_data8_pins[] = { 4101static const union vin_data16 vin5_data_pins = {
4102 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4102 .data16 = {
4103 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4103 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4104 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4104 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4105 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4105 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4106}; 4106 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4107static const unsigned int vin5_data8_mux[] = { 4107 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4108 VI5_DATA0_MARK, VI5_DATA1_MARK, 4108 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4109 VI5_DATA2_MARK, VI5_DATA3_MARK, 4109 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4110 VI5_DATA4_MARK, VI5_DATA5_MARK, 4110 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4111 VI5_DATA6_MARK, VI5_DATA7_MARK, 4111 },
4112};
4113static const unsigned int vin5_data10_pins[] = {
4114 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4115 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4116 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4117 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4118 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4119};
4120static const unsigned int vin5_data10_mux[] = {
4121 VI5_DATA0_MARK, VI5_DATA1_MARK,
4122 VI5_DATA2_MARK, VI5_DATA3_MARK,
4123 VI5_DATA4_MARK, VI5_DATA5_MARK,
4124 VI5_DATA6_MARK, VI5_DATA7_MARK,
4125 VI5_DATA8_MARK, VI5_DATA9_MARK,
4126};
4127static const unsigned int vin5_data12_pins[] = {
4128 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4129 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4130 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4131 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4132 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4133 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4134};
4135static const unsigned int vin5_data12_mux[] = {
4136 VI5_DATA0_MARK, VI5_DATA1_MARK,
4137 VI5_DATA2_MARK, VI5_DATA3_MARK,
4138 VI5_DATA4_MARK, VI5_DATA5_MARK,
4139 VI5_DATA6_MARK, VI5_DATA7_MARK,
4140 VI5_DATA8_MARK, VI5_DATA9_MARK,
4141 VI5_DATA10_MARK, VI5_DATA11_MARK,
4142};
4143static const unsigned int vin5_data16_pins[] = {
4144 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4145 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4146 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4147 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4148 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4149 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4150 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4151 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4152}; 4112};
4153static const unsigned int vin5_data16_mux[] = { 4113static const union vin_data16 vin5_data_mux = {
4154 VI5_DATA0_MARK, VI5_DATA1_MARK, 4114 .data16 = {
4155 VI5_DATA2_MARK, VI5_DATA3_MARK, 4115 VI5_DATA0_MARK, VI5_DATA1_MARK,
4156 VI5_DATA4_MARK, VI5_DATA5_MARK, 4116 VI5_DATA2_MARK, VI5_DATA3_MARK,
4157 VI5_DATA6_MARK, VI5_DATA7_MARK, 4117 VI5_DATA4_MARK, VI5_DATA5_MARK,
4158 VI5_DATA8_MARK, VI5_DATA9_MARK, 4118 VI5_DATA6_MARK, VI5_DATA7_MARK,
4159 VI5_DATA10_MARK, VI5_DATA11_MARK, 4119 VI5_DATA8_MARK, VI5_DATA9_MARK,
4160 VI5_DATA12_MARK, VI5_DATA13_MARK, 4120 VI5_DATA10_MARK, VI5_DATA11_MARK,
4161 VI5_DATA14_MARK, VI5_DATA15_MARK, 4121 VI5_DATA12_MARK, VI5_DATA13_MARK,
4122 VI5_DATA14_MARK, VI5_DATA15_MARK,
4123 },
4162}; 4124};
4163static const unsigned int vin5_sync_pins[] = { 4125static const unsigned int vin5_sync_pins[] = {
4164 /* HSYNC#, VSYNC# */ 4126 /* HSYNC#, VSYNC# */
@@ -4530,10 +4492,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
4530 SH_PFC_PIN_GROUP(vin4_field), 4492 SH_PFC_PIN_GROUP(vin4_field),
4531 SH_PFC_PIN_GROUP(vin4_clkenb), 4493 SH_PFC_PIN_GROUP(vin4_clkenb),
4532 SH_PFC_PIN_GROUP(vin4_clk), 4494 SH_PFC_PIN_GROUP(vin4_clk),
4533 SH_PFC_PIN_GROUP(vin5_data8), 4495 VIN_DATA_PIN_GROUP(vin5_data, 8),
4534 SH_PFC_PIN_GROUP(vin5_data10), 4496 VIN_DATA_PIN_GROUP(vin5_data, 10),
4535 SH_PFC_PIN_GROUP(vin5_data12), 4497 VIN_DATA_PIN_GROUP(vin5_data, 12),
4536 SH_PFC_PIN_GROUP(vin5_data16), 4498 VIN_DATA_PIN_GROUP(vin5_data, 16),
4537 SH_PFC_PIN_GROUP(vin5_sync), 4499 SH_PFC_PIN_GROUP(vin5_sync),
4538 SH_PFC_PIN_GROUP(vin5_field), 4500 SH_PFC_PIN_GROUP(vin5_field),
4539 SH_PFC_PIN_GROUP(vin5_clkenb), 4501 SH_PFC_PIN_GROUP(vin5_clkenb),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 4b98ad8d93d9..72348a4f2ece 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -4070,67 +4070,29 @@ static const unsigned int vin4_clk_mux[] = {
4070}; 4070};
4071 4071
4072/* - VIN5 ------------------------------------------------------------------- */ 4072/* - VIN5 ------------------------------------------------------------------- */
4073static const unsigned int vin5_data8_pins[] = { 4073static const union vin_data16 vin5_data_pins = {
4074 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 4074 .data16 = {
4075 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 4075 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4076 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), 4076 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4077 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), 4077 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4078}; 4078 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4079static const unsigned int vin5_data8_mux[] = { 4079 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4080 VI5_DATA0_MARK, VI5_DATA1_MARK, 4080 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4081 VI5_DATA2_MARK, VI5_DATA3_MARK, 4081 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4082 VI5_DATA4_MARK, VI5_DATA5_MARK, 4082 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4083 VI5_DATA6_MARK, VI5_DATA7_MARK, 4083 },
4084};
4085static const unsigned int vin5_data10_pins[] = {
4086 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4087 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4088 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4089 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4090 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4091};
4092static const unsigned int vin5_data10_mux[] = {
4093 VI5_DATA0_MARK, VI5_DATA1_MARK,
4094 VI5_DATA2_MARK, VI5_DATA3_MARK,
4095 VI5_DATA4_MARK, VI5_DATA5_MARK,
4096 VI5_DATA6_MARK, VI5_DATA7_MARK,
4097 VI5_DATA8_MARK, VI5_DATA9_MARK,
4098};
4099static const unsigned int vin5_data12_pins[] = {
4100 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4101 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4102 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4103 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4104 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4105 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4106};
4107static const unsigned int vin5_data12_mux[] = {
4108 VI5_DATA0_MARK, VI5_DATA1_MARK,
4109 VI5_DATA2_MARK, VI5_DATA3_MARK,
4110 VI5_DATA4_MARK, VI5_DATA5_MARK,
4111 VI5_DATA6_MARK, VI5_DATA7_MARK,
4112 VI5_DATA8_MARK, VI5_DATA9_MARK,
4113 VI5_DATA10_MARK, VI5_DATA11_MARK,
4114};
4115static const unsigned int vin5_data16_pins[] = {
4116 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4117 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4118 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4119 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4120 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4121 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4122 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4123 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4124}; 4084};
4125static const unsigned int vin5_data16_mux[] = { 4085static const union vin_data16 vin5_data_mux = {
4126 VI5_DATA0_MARK, VI5_DATA1_MARK, 4086 .data16 = {
4127 VI5_DATA2_MARK, VI5_DATA3_MARK, 4087 VI5_DATA0_MARK, VI5_DATA1_MARK,
4128 VI5_DATA4_MARK, VI5_DATA5_MARK, 4088 VI5_DATA2_MARK, VI5_DATA3_MARK,
4129 VI5_DATA6_MARK, VI5_DATA7_MARK, 4089 VI5_DATA4_MARK, VI5_DATA5_MARK,
4130 VI5_DATA8_MARK, VI5_DATA9_MARK, 4090 VI5_DATA6_MARK, VI5_DATA7_MARK,
4131 VI5_DATA10_MARK, VI5_DATA11_MARK, 4091 VI5_DATA8_MARK, VI5_DATA9_MARK,
4132 VI5_DATA12_MARK, VI5_DATA13_MARK, 4092 VI5_DATA10_MARK, VI5_DATA11_MARK,
4133 VI5_DATA14_MARK, VI5_DATA15_MARK, 4093 VI5_DATA12_MARK, VI5_DATA13_MARK,
4094 VI5_DATA14_MARK, VI5_DATA15_MARK,
4095 },
4134}; 4096};
4135static const unsigned int vin5_sync_pins[] = { 4097static const unsigned int vin5_sync_pins[] = {
4136 /* HSYNC#, VSYNC# */ 4098 /* HSYNC#, VSYNC# */
@@ -4468,10 +4430,10 @@ static const struct {
4468 SH_PFC_PIN_GROUP(vin4_field), 4430 SH_PFC_PIN_GROUP(vin4_field),
4469 SH_PFC_PIN_GROUP(vin4_clkenb), 4431 SH_PFC_PIN_GROUP(vin4_clkenb),
4470 SH_PFC_PIN_GROUP(vin4_clk), 4432 SH_PFC_PIN_GROUP(vin4_clk),
4471 SH_PFC_PIN_GROUP(vin5_data8), 4433 VIN_DATA_PIN_GROUP(vin5_data, 8),
4472 SH_PFC_PIN_GROUP(vin5_data10), 4434 VIN_DATA_PIN_GROUP(vin5_data, 10),
4473 SH_PFC_PIN_GROUP(vin5_data12), 4435 VIN_DATA_PIN_GROUP(vin5_data, 12),
4474 SH_PFC_PIN_GROUP(vin5_data16), 4436 VIN_DATA_PIN_GROUP(vin5_data, 16),
4475 SH_PFC_PIN_GROUP(vin5_sync), 4437 SH_PFC_PIN_GROUP(vin5_sync),
4476 SH_PFC_PIN_GROUP(vin5_field), 4438 SH_PFC_PIN_GROUP(vin5_field),
4477 SH_PFC_PIN_GROUP(vin5_clkenb), 4439 SH_PFC_PIN_GROUP(vin5_clkenb),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
index a7c4882de09e..d937b1bc396a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77965.c
@@ -554,7 +554,7 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
554 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \ 554 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
555 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \ 555 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
556 FM(PRESETOUT) \ 556 FM(PRESETOUT) \
557 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \ 557 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
558 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) 558 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
559 559
560enum { 560enum {
@@ -1566,7 +1566,7 @@ static const struct sh_pfc_pin pinmux_pins[] = {
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS), 1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS), 1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS), 1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS), 1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), 1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN), 1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS), 1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
@@ -5740,7 +5740,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5740 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */ 5740 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5741 } }, 5741 } },
5742 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { 5742 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5743 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */ 5743 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
5744 [ 1] = PIN_NONE, 5744 [ 1] = PIN_NONE,
5745 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */ 5745 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
5746 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/ 5746 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
index 4a7ab84b366b..c5e67ba29f7c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77970.c
@@ -1578,47 +1578,25 @@ static const unsigned int tmu_tclk2_b_mux[] = {
1578}; 1578};
1579 1579
1580/* - VIN0 ------------------------------------------------------------------- */ 1580/* - VIN0 ------------------------------------------------------------------- */
1581static const unsigned int vin0_data8_pins[] = { 1581static const union vin_data12 vin0_data_pins = {
1582 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 1582 .data12 = {
1583 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1583 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1584 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1584 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1585 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1585 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1586}; 1586 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1587static const unsigned int vin0_data8_mux[] = { 1587 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1588 VI0_DATA0_MARK, VI0_DATA1_MARK, 1588 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1589 VI0_DATA2_MARK, VI0_DATA3_MARK, 1589 },
1590 VI0_DATA4_MARK, VI0_DATA5_MARK,
1591 VI0_DATA6_MARK, VI0_DATA7_MARK,
1592}; 1590};
1593static const unsigned int vin0_data10_pins[] = { 1591static const union vin_data12 vin0_data_mux = {
1594 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 1592 .data12 = {
1595 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1593 VI0_DATA0_MARK, VI0_DATA1_MARK,
1596 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1594 VI0_DATA2_MARK, VI0_DATA3_MARK,
1597 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1595 VI0_DATA4_MARK, VI0_DATA5_MARK,
1598 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), 1596 VI0_DATA6_MARK, VI0_DATA7_MARK,
1599}; 1597 VI0_DATA8_MARK, VI0_DATA9_MARK,
1600static const unsigned int vin0_data10_mux[] = { 1598 VI0_DATA10_MARK, VI0_DATA11_MARK,
1601 VI0_DATA0_MARK, VI0_DATA1_MARK, 1599 },
1602 VI0_DATA2_MARK, VI0_DATA3_MARK,
1603 VI0_DATA4_MARK, VI0_DATA5_MARK,
1604 VI0_DATA6_MARK, VI0_DATA7_MARK,
1605 VI0_DATA8_MARK, VI0_DATA9_MARK,
1606};
1607static const unsigned int vin0_data12_pins[] = {
1608 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1609 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1610 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1611 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1612 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1613 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1614};
1615static const unsigned int vin0_data12_mux[] = {
1616 VI0_DATA0_MARK, VI0_DATA1_MARK,
1617 VI0_DATA2_MARK, VI0_DATA3_MARK,
1618 VI0_DATA4_MARK, VI0_DATA5_MARK,
1619 VI0_DATA6_MARK, VI0_DATA7_MARK,
1620 VI0_DATA8_MARK, VI0_DATA9_MARK,
1621 VI0_DATA10_MARK, VI0_DATA11_MARK,
1622}; 1600};
1623static const unsigned int vin0_sync_pins[] = { 1601static const unsigned int vin0_sync_pins[] = {
1624 /* HSYNC#, VSYNC# */ 1602 /* HSYNC#, VSYNC# */
@@ -1650,47 +1628,25 @@ static const unsigned int vin0_clk_mux[] = {
1650}; 1628};
1651 1629
1652/* - VIN1 ------------------------------------------------------------------- */ 1630/* - VIN1 ------------------------------------------------------------------- */
1653static const unsigned int vin1_data8_pins[] = { 1631static const union vin_data12 vin1_data_pins = {
1654 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 1632 .data12 = {
1655 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 1633 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1656 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1634 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1657 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 1635 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1658}; 1636 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1659static const unsigned int vin1_data8_mux[] = { 1637 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1660 VI1_DATA0_MARK, VI1_DATA1_MARK, 1638 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1661 VI1_DATA2_MARK, VI1_DATA3_MARK, 1639 },
1662 VI1_DATA4_MARK, VI1_DATA5_MARK,
1663 VI1_DATA6_MARK, VI1_DATA7_MARK,
1664};
1665static const unsigned int vin1_data10_pins[] = {
1666 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1667 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1668 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1669 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1670 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1671};
1672static const unsigned int vin1_data10_mux[] = {
1673 VI1_DATA0_MARK, VI1_DATA1_MARK,
1674 VI1_DATA2_MARK, VI1_DATA3_MARK,
1675 VI1_DATA4_MARK, VI1_DATA5_MARK,
1676 VI1_DATA6_MARK, VI1_DATA7_MARK,
1677 VI1_DATA8_MARK, VI1_DATA9_MARK,
1678};
1679static const unsigned int vin1_data12_pins[] = {
1680 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1681 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1682 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1683 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1684 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1685 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1686}; 1640};
1687static const unsigned int vin1_data12_mux[] = { 1641static const union vin_data12 vin1_data_mux = {
1688 VI1_DATA0_MARK, VI1_DATA1_MARK, 1642 .data12 = {
1689 VI1_DATA2_MARK, VI1_DATA3_MARK, 1643 VI1_DATA0_MARK, VI1_DATA1_MARK,
1690 VI1_DATA4_MARK, VI1_DATA5_MARK, 1644 VI1_DATA2_MARK, VI1_DATA3_MARK,
1691 VI1_DATA6_MARK, VI1_DATA7_MARK, 1645 VI1_DATA4_MARK, VI1_DATA5_MARK,
1692 VI1_DATA8_MARK, VI1_DATA9_MARK, 1646 VI1_DATA6_MARK, VI1_DATA7_MARK,
1693 VI1_DATA10_MARK, VI1_DATA11_MARK, 1647 VI1_DATA8_MARK, VI1_DATA9_MARK,
1648 VI1_DATA10_MARK, VI1_DATA11_MARK,
1649 },
1694}; 1650};
1695static const unsigned int vin1_sync_pins[] = { 1651static const unsigned int vin1_sync_pins[] = {
1696 /* HSYNC#, VSYNC# */ 1652 /* HSYNC#, VSYNC# */
@@ -1831,16 +1787,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1831 SH_PFC_PIN_GROUP(tmu_tclk1_b), 1787 SH_PFC_PIN_GROUP(tmu_tclk1_b),
1832 SH_PFC_PIN_GROUP(tmu_tclk2_a), 1788 SH_PFC_PIN_GROUP(tmu_tclk2_a),
1833 SH_PFC_PIN_GROUP(tmu_tclk2_b), 1789 SH_PFC_PIN_GROUP(tmu_tclk2_b),
1834 SH_PFC_PIN_GROUP(vin0_data8), 1790 VIN_DATA_PIN_GROUP(vin0_data, 8),
1835 SH_PFC_PIN_GROUP(vin0_data10), 1791 VIN_DATA_PIN_GROUP(vin0_data, 10),
1836 SH_PFC_PIN_GROUP(vin0_data12), 1792 VIN_DATA_PIN_GROUP(vin0_data, 12),
1837 SH_PFC_PIN_GROUP(vin0_sync), 1793 SH_PFC_PIN_GROUP(vin0_sync),
1838 SH_PFC_PIN_GROUP(vin0_field), 1794 SH_PFC_PIN_GROUP(vin0_field),
1839 SH_PFC_PIN_GROUP(vin0_clkenb), 1795 SH_PFC_PIN_GROUP(vin0_clkenb),
1840 SH_PFC_PIN_GROUP(vin0_clk), 1796 SH_PFC_PIN_GROUP(vin0_clk),
1841 SH_PFC_PIN_GROUP(vin1_data8), 1797 VIN_DATA_PIN_GROUP(vin1_data, 8),
1842 SH_PFC_PIN_GROUP(vin1_data10), 1798 VIN_DATA_PIN_GROUP(vin1_data, 10),
1843 SH_PFC_PIN_GROUP(vin1_data12), 1799 VIN_DATA_PIN_GROUP(vin1_data, 12),
1844 SH_PFC_PIN_GROUP(vin1_sync), 1800 SH_PFC_PIN_GROUP(vin1_sync),
1845 SH_PFC_PIN_GROUP(vin1_field), 1801 SH_PFC_PIN_GROUP(vin1_field),
1846 SH_PFC_PIN_GROUP(vin1_clkenb), 1802 SH_PFC_PIN_GROUP(vin1_clkenb),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
index 8bef24502f0c..b807b67ae143 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
@@ -1970,47 +1970,25 @@ static const unsigned int vin0_clk_mux[] = {
1970}; 1970};
1971 1971
1972/* - VIN1 ------------------------------------------------------------------- */ 1972/* - VIN1 ------------------------------------------------------------------- */
1973static const unsigned int vin1_data8_pins[] = { 1973static const union vin_data12 vin1_data_pins = {
1974 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), 1974 .data12 = {
1975 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), 1975 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1976 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), 1976 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1977 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), 1977 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1978}; 1978 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1979static const unsigned int vin1_data8_mux[] = { 1979 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1980 VI1_DATA0_MARK, VI1_DATA1_MARK, 1980 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1981 VI1_DATA2_MARK, VI1_DATA3_MARK, 1981 },
1982 VI1_DATA4_MARK, VI1_DATA5_MARK,
1983 VI1_DATA6_MARK, VI1_DATA7_MARK,
1984};
1985static const unsigned int vin1_data10_pins[] = {
1986 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1987 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1988 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1989 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1990 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1991};
1992static const unsigned int vin1_data10_mux[] = {
1993 VI1_DATA0_MARK, VI1_DATA1_MARK,
1994 VI1_DATA2_MARK, VI1_DATA3_MARK,
1995 VI1_DATA4_MARK, VI1_DATA5_MARK,
1996 VI1_DATA6_MARK, VI1_DATA7_MARK,
1997 VI1_DATA8_MARK, VI1_DATA9_MARK,
1998};
1999static const unsigned int vin1_data12_pins[] = {
2000 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2001 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2002 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2003 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2004 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2005 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2006}; 1982};
2007static const unsigned int vin1_data12_mux[] = { 1983static const union vin_data12 vin1_data_mux = {
2008 VI1_DATA0_MARK, VI1_DATA1_MARK, 1984 .data12 = {
2009 VI1_DATA2_MARK, VI1_DATA3_MARK, 1985 VI1_DATA0_MARK, VI1_DATA1_MARK,
2010 VI1_DATA4_MARK, VI1_DATA5_MARK, 1986 VI1_DATA2_MARK, VI1_DATA3_MARK,
2011 VI1_DATA6_MARK, VI1_DATA7_MARK, 1987 VI1_DATA4_MARK, VI1_DATA5_MARK,
2012 VI1_DATA8_MARK, VI1_DATA9_MARK, 1988 VI1_DATA6_MARK, VI1_DATA7_MARK,
2013 VI1_DATA10_MARK, VI1_DATA11_MARK, 1989 VI1_DATA8_MARK, VI1_DATA9_MARK,
1990 VI1_DATA10_MARK, VI1_DATA11_MARK,
1991 },
2014}; 1992};
2015static const unsigned int vin1_sync_pins[] = { 1993static const unsigned int vin1_sync_pins[] = {
2016 /* VI1_VSYNC#, VI1_HSYNC# */ 1994 /* VI1_VSYNC#, VI1_HSYNC# */
@@ -2182,9 +2160,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2182 SH_PFC_PIN_GROUP(vin0_field), 2160 SH_PFC_PIN_GROUP(vin0_field),
2183 SH_PFC_PIN_GROUP(vin0_clkenb), 2161 SH_PFC_PIN_GROUP(vin0_clkenb),
2184 SH_PFC_PIN_GROUP(vin0_clk), 2162 SH_PFC_PIN_GROUP(vin0_clk),
2185 SH_PFC_PIN_GROUP(vin1_data8), 2163 VIN_DATA_PIN_GROUP(vin1_data, 8),
2186 SH_PFC_PIN_GROUP(vin1_data10), 2164 VIN_DATA_PIN_GROUP(vin1_data, 10),
2187 SH_PFC_PIN_GROUP(vin1_data12), 2165 VIN_DATA_PIN_GROUP(vin1_data, 12),
2188 SH_PFC_PIN_GROUP(vin1_sync), 2166 SH_PFC_PIN_GROUP(vin1_sync),
2189 SH_PFC_PIN_GROUP(vin1_field), 2167 SH_PFC_PIN_GROUP(vin1_field),
2190 SH_PFC_PIN_GROUP(vin1_clkenb), 2168 SH_PFC_PIN_GROUP(vin1_clkenb),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index e40908dc37e0..0a9aa62f50bb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -30,7 +30,16 @@
30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ 30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ 31 PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ 32 PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS) 33 PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
35 PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
40 PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
41 PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
42 PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
34/* 43/*
35 * F_() : just information 44 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK 45 * FM() : macro for FN_xxx / xxx_MARK
@@ -391,29 +400,33 @@ FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM
391FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \ 400FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
392FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 401FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28
393 402
403/* The bit numbering in MOD_SEL fields is reversed */
404#define REV4(f0, f1, f2, f3) f0 f2 f1 f3
405#define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7
406
394/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 407/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
395#define MOD_SEL0_30_29 FM(SEL_ADGB_0) FM(SEL_ADGB_1) FM(SEL_ADGB_2) F_(0, 0) 408#define MOD_SEL0_30_29 REV4(FM(SEL_ADGB_0), FM(SEL_ADGB_1), FM(SEL_ADGB_2), F_(0, 0))
396#define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) 409#define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1)
397#define MOD_SEL0_27_26 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) F_(0, 0) 410#define MOD_SEL0_27_26 REV4(FM(SEL_FM_0), FM(SEL_FM_1), FM(SEL_FM_2), F_(0, 0))
398#define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1) 411#define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1)
399#define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1) 412#define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
400#define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1) 413#define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
401#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) 414#define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
402#define MOD_SEL0_21_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1) FM(SEL_I2C1_2) FM(SEL_I2C1_3) 415#define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
403#define MOD_SEL0_19_18_17 FM(SEL_I2C2_0) FM(SEL_I2C2_1) FM(SEL_I2C2_2) FM(SEL_I2C2_3) FM(SEL_I2C2_4) F_(0, 0) F_(0, 0) F_(0, 0) 416#define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
404#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1) 417#define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
405#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1) 418#define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
406#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 419#define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
407#define MOD_SEL0_13_12 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) F_(0, 0) 420#define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
408#define MOD_SEL0_11_10 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) F_(0, 0) 421#define MOD_SEL0_11_10 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
409#define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1) 422#define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
410#define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1) 423#define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
411#define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1) 424#define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
412#define MOD_SEL0_6_5 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1) FM(SEL_REMOCON_2) F_(0, 0) 425#define MOD_SEL0_6_5 REV4(FM(SEL_REMOCON_0), FM(SEL_REMOCON_1), FM(SEL_REMOCON_2), F_(0, 0))
413#define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1) 426#define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
414#define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) 427#define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
415#define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1) 428#define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
416#define MOD_SEL0_1_0 FM(SEL_SPEED_PULSE_IF_0) FM(SEL_SPEED_PULSE_IF_1) FM(SEL_SPEED_PULSE_IF_2) F_(0, 0) 429#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
417 430
418/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 431/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
419#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) 432#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
@@ -422,18 +435,18 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM
422#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1) 435#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
423#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1) 436#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
424#define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1) 437#define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
425#define MOD_SEL1_24_23_22 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3) FM(SEL_HSCIF3_4) F_(0, 0) F_(0, 0) F_(0, 0) 438#define MOD_SEL1_24_23_22 REV8(FM(SEL_HSCIF3_0), FM(SEL_HSCIF3_1), FM(SEL_HSCIF3_2), FM(SEL_HSCIF3_3), FM(SEL_HSCIF3_4), F_(0, 0), F_(0, 0), F_(0, 0))
426#define MOD_SEL1_21_20_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1) FM(SEL_HSCIF4_2) FM(SEL_HSCIF4_3) FM(SEL_HSCIF4_4) F_(0, 0) F_(0, 0) F_(0, 0) 439#define MOD_SEL1_21_20_19 REV8(FM(SEL_HSCIF4_0), FM(SEL_HSCIF4_1), FM(SEL_HSCIF4_2), FM(SEL_HSCIF4_3), FM(SEL_HSCIF4_4), F_(0, 0), F_(0, 0), F_(0, 0))
427#define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1) 440#define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1)
428#define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1) 441#define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1)
429#define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) 442#define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
430#define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) 443#define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
431#define MOD_SEL1_14_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) FM(SEL_SCIF3_2) F_(0, 0) 444#define MOD_SEL1_14_13 REV4(FM(SEL_SCIF3_0), FM(SEL_SCIF3_1), FM(SEL_SCIF3_2), F_(0, 0))
432#define MOD_SEL1_12_11 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0) 445#define MOD_SEL1_12_11 REV4(FM(SEL_SCIF4_0), FM(SEL_SCIF4_1), FM(SEL_SCIF4_2), F_(0, 0))
433#define MOD_SEL1_10_9 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) FM(SEL_SCIF5_2) F_(0, 0) 446#define MOD_SEL1_10_9 REV4(FM(SEL_SCIF5_0), FM(SEL_SCIF5_1), FM(SEL_SCIF5_2), F_(0, 0))
434#define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1) 447#define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
435#define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1) 448#define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1)
436#define MOD_SEL1_6_5 FM(SEL_ADGC_0) FM(SEL_ADGC_1) FM(SEL_ADGC_2) F_(0, 0) 449#define MOD_SEL1_6_5 REV4(FM(SEL_ADGC_0), FM(SEL_ADGC_1), FM(SEL_ADGC_2), F_(0, 0))
437#define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1) 450#define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
438 451
439#define PINMUX_MOD_SELS \ 452#define PINMUX_MOD_SELS \
@@ -1060,7 +1073,7 @@ static const u16 pinmux_data[] = {
1060 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC), 1073 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
1061 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1), 1074 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
1062 1075
1063 PINMUX_IPSR_GPSR(IP11_15_12, TX0_A), 1076 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
1064 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A), 1077 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
1065 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0), 1078 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
1066 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0), 1079 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
@@ -1099,7 +1112,7 @@ static const u16 pinmux_data[] = {
1099 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1), 1112 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1),
1100 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B), 1113 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B),
1101 1114
1102 PINMUX_IPSR_GPSR(IP12_7_4, SCK2_A), 1115 PINMUX_IPSR_MSEL(IP12_7_4, SCK2_A, SEL_SCIF2_0),
1103 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0), 1116 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0),
1104 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0), 1117 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0),
1105 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N), 1118 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N),
@@ -1107,14 +1120,14 @@ static const u16 pinmux_data[] = {
1107 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0), 1120 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0),
1108 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1), 1121 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1),
1109 1122
1110 PINMUX_IPSR_GPSR(IP12_11_8, TX2_A), 1123 PINMUX_IPSR_MSEL(IP12_11_8, TX2_A, SEL_SCIF2_0),
1111 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0), 1124 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0),
1112 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A), 1125 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A),
1113 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0), 1126 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0),
1114 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0), 1127 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0),
1115 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1), 1128 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1),
1116 1129
1117 PINMUX_IPSR_GPSR(IP12_15_12, RX2_A), 1130 PINMUX_IPSR_MSEL(IP12_15_12, RX2_A, SEL_SCIF2_0),
1118 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A), 1131 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A),
1119 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A), 1132 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A),
1120 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0), 1133 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0),
@@ -1126,11 +1139,11 @@ static const u16 pinmux_data[] = {
1126 1139
1127 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD), 1140 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD),
1128 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78), 1141 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78),
1129 PINMUX_IPSR_GPSR(IP12_23_20, TX2_B), 1142 PINMUX_IPSR_MSEL(IP12_23_20, TX2_B, SEL_SCIF2_1),
1130 1143
1131 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD), 1144 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD),
1132 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7), 1145 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7),
1133 PINMUX_IPSR_GPSR(IP12_27_24, RX2_B), 1146 PINMUX_IPSR_MSEL(IP12_27_24, RX2_B, SEL_SCIF2_1),
1134 1147
1135 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC), 1148 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1136 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B), 1149 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B),
@@ -1170,7 +1183,7 @@ static const u16 pinmux_data[] = {
1170 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0), 1183 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
1171 1184
1172 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT), 1185 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
1173 PINMUX_IPSR_GPSR(IP13_23_20, TX0_B), 1186 PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
1174 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0), 1187 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0),
1175 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A), 1188 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A),
1176 1189
@@ -3243,6 +3256,43 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
3243 SSI_SCK9_B_MARK, SSI_WS9_B_MARK, 3256 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3244}; 3257};
3245 3258
3259/* - TMU -------------------------------------------------------------------- */
3260static const unsigned int tmu_tclk1_a_pins[] = {
3261 /* TCLK */
3262 RCAR_GP_PIN(3, 12),
3263};
3264
3265static const unsigned int tmu_tclk1_a_mux[] = {
3266 TCLK1_A_MARK,
3267};
3268
3269static const unsigned int tmu_tclk1_b_pins[] = {
3270 /* TCLK */
3271 RCAR_GP_PIN(5, 17),
3272};
3273
3274static const unsigned int tmu_tclk1_b_mux[] = {
3275 TCLK1_B_MARK,
3276};
3277
3278static const unsigned int tmu_tclk2_a_pins[] = {
3279 /* TCLK */
3280 RCAR_GP_PIN(3, 13),
3281};
3282
3283static const unsigned int tmu_tclk2_a_mux[] = {
3284 TCLK2_A_MARK,
3285};
3286
3287static const unsigned int tmu_tclk2_b_pins[] = {
3288 /* TCLK */
3289 RCAR_GP_PIN(5, 18),
3290};
3291
3292static const unsigned int tmu_tclk2_b_mux[] = {
3293 TCLK2_B_MARK,
3294};
3295
3246/* - USB0 ------------------------------------------------------------------- */ 3296/* - USB0 ------------------------------------------------------------------- */
3247static const unsigned int usb0_a_pins[] = { 3297static const unsigned int usb0_a_pins[] = {
3248 /* PWEN, OVC */ 3298 /* PWEN, OVC */
@@ -3523,7 +3573,7 @@ static const unsigned int vin5_clk_b_mux[] = {
3523}; 3573};
3524 3574
3525static const struct { 3575static const struct {
3526 struct sh_pfc_pin_group common[241]; 3576 struct sh_pfc_pin_group common[245];
3527 struct sh_pfc_pin_group automotive[2]; 3577 struct sh_pfc_pin_group automotive[2];
3528} pinmux_groups = { 3578} pinmux_groups = {
3529 .common = { 3579 .common = {
@@ -3735,6 +3785,10 @@ static const struct {
3735 SH_PFC_PIN_GROUP(ssi9_data), 3785 SH_PFC_PIN_GROUP(ssi9_data),
3736 SH_PFC_PIN_GROUP(ssi9_ctrl_a), 3786 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
3737 SH_PFC_PIN_GROUP(ssi9_ctrl_b), 3787 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3788 SH_PFC_PIN_GROUP(tmu_tclk1_a),
3789 SH_PFC_PIN_GROUP(tmu_tclk1_b),
3790 SH_PFC_PIN_GROUP(tmu_tclk2_a),
3791 SH_PFC_PIN_GROUP(tmu_tclk2_b),
3738 SH_PFC_PIN_GROUP(usb0_a), 3792 SH_PFC_PIN_GROUP(usb0_a),
3739 SH_PFC_PIN_GROUP(usb0_b), 3793 SH_PFC_PIN_GROUP(usb0_b),
3740 SH_PFC_PIN_GROUP(usb0_id), 3794 SH_PFC_PIN_GROUP(usb0_id),
@@ -4111,6 +4165,13 @@ static const char * const ssi_groups[] = {
4111 "ssi9_ctrl_b", 4165 "ssi9_ctrl_b",
4112}; 4166};
4113 4167
4168static const char * const tmu_groups[] = {
4169 "tmu_tclk1_a",
4170 "tmu_tclk1_b",
4171 "tmu_tclk2_a",
4172 "tmu_tclk2_b",
4173};
4174
4114static const char * const usb0_groups[] = { 4175static const char * const usb0_groups[] = {
4115 "usb0_a", 4176 "usb0_a",
4116 "usb0_b", 4177 "usb0_b",
@@ -4157,7 +4218,7 @@ static const char * const vin5_groups[] = {
4157}; 4218};
4158 4219
4159static const struct { 4220static const struct {
4160 struct sh_pfc_function common[44]; 4221 struct sh_pfc_function common[45];
4161 struct sh_pfc_function automotive[2]; 4222 struct sh_pfc_function automotive[2];
4162} pinmux_functions = { 4223} pinmux_functions = {
4163 .common = { 4224 .common = {
@@ -4201,6 +4262,7 @@ static const struct {
4201 SH_PFC_FUNCTION(sdhi1), 4262 SH_PFC_FUNCTION(sdhi1),
4202 SH_PFC_FUNCTION(sdhi3), 4263 SH_PFC_FUNCTION(sdhi3),
4203 SH_PFC_FUNCTION(ssi), 4264 SH_PFC_FUNCTION(ssi),
4265 SH_PFC_FUNCTION(tmu),
4204 SH_PFC_FUNCTION(usb0), 4266 SH_PFC_FUNCTION(usb0),
4205 SH_PFC_FUNCTION(usb30), 4267 SH_PFC_FUNCTION(usb30),
4206 SH_PFC_FUNCTION(vin4), 4268 SH_PFC_FUNCTION(vin4),
@@ -4914,17 +4976,6 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
4914 { /* sentinel */ }, 4976 { /* sentinel */ },
4915}; 4977};
4916 4978
4917static bool pin_has_pud(unsigned int pin)
4918{
4919 /* Some pins are pull-up only */
4920 switch (pin) {
4921 case RCAR_GP_PIN(6, 9): /* USB30_OVC */
4922 return false;
4923 }
4924
4925 return true;
4926}
4927
4928static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc, 4979static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
4929 unsigned int pin) 4980 unsigned int pin)
4930{ 4981{
@@ -4937,7 +4988,7 @@ static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
4937 4988
4938 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) 4989 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
4939 return PIN_CONFIG_BIAS_DISABLE; 4990 return PIN_CONFIG_BIAS_DISABLE;
4940 else if (!pin_has_pud(pin) || (sh_pfc_read(pfc, reg->pud) & BIT(bit))) 4991 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
4941 return PIN_CONFIG_BIAS_PULL_UP; 4992 return PIN_CONFIG_BIAS_PULL_UP;
4942 else 4993 else
4943 return PIN_CONFIG_BIAS_PULL_DOWN; 4994 return PIN_CONFIG_BIAS_PULL_DOWN;
@@ -4958,13 +5009,11 @@ static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4958 if (bias != PIN_CONFIG_BIAS_DISABLE) 5009 if (bias != PIN_CONFIG_BIAS_DISABLE)
4959 enable |= BIT(bit); 5010 enable |= BIT(bit);
4960 5011
4961 if (pin_has_pud(pin)) { 5012 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
4962 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); 5013 if (bias == PIN_CONFIG_BIAS_PULL_UP)
4963 if (bias == PIN_CONFIG_BIAS_PULL_UP) 5014 updown |= BIT(bit);
4964 updown |= BIT(bit);
4965 5015
4966 sh_pfc_write(pfc, reg->pud, updown); 5016 sh_pfc_write(pfc, reg->pud, updown);
4967 }
4968 sh_pfc_write(pfc, reg->puen, enable); 5017 sh_pfc_write(pfc, reg->puen, enable);
4969} 5018}
4970 5019
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index 84d78db381e3..9e377e3b9cb3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -381,6 +381,9 @@ FM(IP12_23_20) IP12_23_20 \
381FM(IP12_27_24) IP12_27_24 \ 381FM(IP12_27_24) IP12_27_24 \
382FM(IP12_31_28) IP12_31_28 \ 382FM(IP12_31_28) IP12_31_28 \
383 383
384/* The bit numbering in MOD_SEL fields is reversed */
385#define REV4(f0, f1, f2, f3) f0 f2 f1 f3
386
384/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ 387/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
385#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) 388#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
386#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1) 389#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
@@ -388,10 +391,10 @@ FM(IP12_31_28) IP12_31_28 \
388#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) 391#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
389#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) 392#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
390#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) 393#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
391#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) F_(0, 0) 394#define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0))
392#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) F_(0, 0) 395#define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0))
393#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) F_(0, 0) 396#define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
394#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) F_(0, 0) 397#define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
395#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1) 398#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
396#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1) 399#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
397#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1) 400#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 274d5ff87078..c97d2ba7677c 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -347,6 +347,8 @@ static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
347 unsigned int i; 347 unsigned int i;
348 int ret = 0; 348 int ret = 0;
349 349
350 dev_dbg(pctldev->dev, "Configuring pin group %s\n", grp->name);
351
350 spin_lock_irqsave(&pfc->lock, flags); 352 spin_lock_irqsave(&pfc->lock, flags);
351 353
352 for (i = 0; i < grp->nr_pins; ++i) { 354 for (i = 0; i < grp->nr_pins; ++i) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-16 00:07:33 -0500