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authorBai Ping <ping.bai@nxp.com>2019-01-28 21:32:53 -0500
committerLinus Walleij <linus.walleij@linaro.org>2019-01-30 04:35:22 -0500
commit85e4e6881dbaae42bbac935c346753bea412ab76 (patch)
tree2d6bae939c9f91acea60c5c03ccb742099473d32 /drivers/pinctrl
parentb71c1844124d670b677bc4724d29ab0d8b71edbb (diff)
pinctrl: freescale: Add imx8mm pinctrl driver support
Add the pinctrl driver support for i.MX8MM. Signed-off-by: Bai Ping <ping.bai@nxp.com> Acked-by: Aisheng Dong <aisheng.dong@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/freescale/Kconfig7
-rw-r--r--drivers/pinctrl/freescale/Makefile1
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx8mm.c348
3 files changed, 356 insertions, 0 deletions
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index b318c24b61be..e6dff3167a67 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -122,6 +122,13 @@ config PINCTRL_IMX7ULP
122 help 122 help
123 Say Y here to enable the imx7ulp pinctrl driver 123 Say Y here to enable the imx7ulp pinctrl driver
124 124
125config PINCTRL_IMX8MM
126 bool "IMX8MM pinctrl driver"
127 depends on ARCH_MXC && ARM64
128 select PINCTRL_IMX
129 help
130 Say Y here to enable the imx8mm pinctrl driver
131
125config PINCTRL_IMX8MQ 132config PINCTRL_IMX8MQ
126 bool "IMX8MQ pinctrl driver" 133 bool "IMX8MQ pinctrl driver"
127 depends on ARCH_MXC && ARM64 134 depends on ARCH_MXC && ARM64
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index a6783f2560ae..02020a76bd9c 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
18obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o 18obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
19obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o 19obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
20obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o 20obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
21obj-$(CONFIG_PINCTRL_IMX8MM) += pinctrl-imx8mm.o
21obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o 22obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
22obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o 23obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
23obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o 24obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8mm.c b/drivers/pinctrl/freescale/pinctrl-imx8mm.c
new file mode 100644
index 000000000000..6d1038af59f4
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx8mm.c
@@ -0,0 +1,348 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2017-2018 NXP
4 */
5
6#include <linux/err.h>
7#include <linux/init.h>
8#include <linux/of_device.h>
9#include <linux/pinctrl/pinctrl.h>
10#include <linux/platform_device.h>
11
12#include "pinctrl-imx.h"
13
14enum imx8mm_pads {
15 MX8MM_PAD_RESERVE0 = 0,
16 MX8MM_PAD_RESERVE1 = 1,
17 MX8MM_PAD_RESERVE2 = 2,
18 MX8MM_PAD_RESERVE3 = 3,
19 MX8MM_PAD_RESERVE4 = 4,
20 MX8MM_PAD_RESERVE5 = 5,
21 MX8MM_PAD_RESERVE6 = 6,
22 MX8MM_PAD_RESERVE7 = 7,
23 MX8MM_PAD_RESERVE8 = 8,
24 MX8MM_PAD_RESERVE9 = 9,
25 MX8MM_IOMUXC_GPIO1_IO00 = 10,
26 MX8MM_IOMUXC_GPIO1_IO01 = 11,
27 MX8MM_IOMUXC_GPIO1_IO02 = 12,
28 MX8MM_IOMUXC_GPIO1_IO03 = 13,
29 MX8MM_IOMUXC_GPIO1_IO04 = 14,
30 MX8MM_IOMUXC_GPIO1_IO05 = 15,
31 MX8MM_IOMUXC_GPIO1_IO06 = 16,
32 MX8MM_IOMUXC_GPIO1_IO07 = 17,
33 MX8MM_IOMUXC_GPIO1_IO08 = 18,
34 MX8MM_IOMUXC_GPIO1_IO09 = 19,
35 MX8MM_IOMUXC_GPIO1_IO10 = 20,
36 MX8MM_IOMUXC_GPIO1_IO11 = 21,
37 MX8MM_IOMUXC_GPIO1_IO12 = 22,
38 MX8MM_IOMUXC_GPIO1_IO13 = 23,
39 MX8MM_IOMUXC_GPIO1_IO14 = 24,
40 MX8MM_IOMUXC_GPIO1_IO15 = 25,
41 MX8MM_IOMUXC_ENET_MDC = 26,
42 MX8MM_IOMUXC_ENET_MDIO = 27,
43 MX8MM_IOMUXC_ENET_TD3 = 28,
44 MX8MM_IOMUXC_ENET_TD2 = 29,
45 MX8MM_IOMUXC_ENET_TD1 = 30,
46 MX8MM_IOMUXC_ENET_TD0 = 31,
47 MX8MM_IOMUXC_ENET_TX_CTL = 32,
48 MX8MM_IOMUXC_ENET_TXC = 33,
49 MX8MM_IOMUXC_ENET_RX_CTL = 34,
50 MX8MM_IOMUXC_ENET_RXC = 35,
51 MX8MM_IOMUXC_ENET_RD0 = 36,
52 MX8MM_IOMUXC_ENET_RD1 = 37,
53 MX8MM_IOMUXC_ENET_RD2 = 38,
54 MX8MM_IOMUXC_ENET_RD3 = 39,
55 MX8MM_IOMUXC_SD1_CLK = 40,
56 MX8MM_IOMUXC_SD1_CMD = 41,
57 MX8MM_IOMUXC_SD1_DATA0 = 42,
58 MX8MM_IOMUXC_SD1_DATA1 = 43,
59 MX8MM_IOMUXC_SD1_DATA2 = 44,
60 MX8MM_IOMUXC_SD1_DATA3 = 45,
61 MX8MM_IOMUXC_SD1_DATA4 = 46,
62 MX8MM_IOMUXC_SD1_DATA5 = 47,
63 MX8MM_IOMUXC_SD1_DATA6 = 48,
64 MX8MM_IOMUXC_SD1_DATA7 = 49,
65 MX8MM_IOMUXC_SD1_RESET_B = 50,
66 MX8MM_IOMUXC_SD1_STROBE = 51,
67 MX8MM_IOMUXC_SD2_CD_B = 52,
68 MX8MM_IOMUXC_SD2_CLK = 53,
69 MX8MM_IOMUXC_SD2_CMD = 54,
70 MX8MM_IOMUXC_SD2_DATA0 = 55,
71 MX8MM_IOMUXC_SD2_DATA1 = 56,
72 MX8MM_IOMUXC_SD2_DATA2 = 57,
73 MX8MM_IOMUXC_SD2_DATA3 = 58,
74 MX8MM_IOMUXC_SD2_RESET_B = 59,
75 MX8MM_IOMUXC_SD2_WP = 60,
76 MX8MM_IOMUXC_NAND_ALE = 61,
77 MX8MM_IOMUXC_NAND_CE0 = 62,
78 MX8MM_IOMUXC_NAND_CE1 = 63,
79 MX8MM_IOMUXC_NAND_CE2 = 64,
80 MX8MM_IOMUXC_NAND_CE3 = 65,
81 MX8MM_IOMUXC_NAND_CLE = 66,
82 MX8MM_IOMUXC_NAND_DATA00 = 67,
83 MX8MM_IOMUXC_NAND_DATA01 = 68,
84 MX8MM_IOMUXC_NAND_DATA02 = 69,
85 MX8MM_IOMUXC_NAND_DATA03 = 70,
86 MX8MM_IOMUXC_NAND_DATA04 = 71,
87 MX8MM_IOMUXC_NAND_DATA05 = 72,
88 MX8MM_IOMUXC_NAND_DATA06 = 73,
89 MX8MM_IOMUXC_NAND_DATA07 = 74,
90 MX8MM_IOMUXC_NAND_DQS = 75,
91 MX8MM_IOMUXC_NAND_RE_B = 76,
92 MX8MM_IOMUXC_NAND_READY_B = 77,
93 MX8MM_IOMUXC_NAND_WE_B = 78,
94 MX8MM_IOMUXC_NAND_WP_B = 79,
95 MX8MM_IOMUXC_SAI5_RXFS = 80,
96 MX8MM_IOMUXC_SAI5_RXC = 81,
97 MX8MM_IOMUXC_SAI5_RXD0 = 82,
98 MX8MM_IOMUXC_SAI5_RXD1 = 83,
99 MX8MM_IOMUXC_SAI5_RXD2 = 84,
100 MX8MM_IOMUXC_SAI5_RXD3 = 85,
101 MX8MM_IOMUXC_SAI5_MCLK = 86,
102 MX8MM_IOMUXC_SAI1_RXFS = 87,
103 MX8MM_IOMUXC_SAI1_RXC = 88,
104 MX8MM_IOMUXC_SAI1_RXD0 = 89,
105 MX8MM_IOMUXC_SAI1_RXD1 = 90,
106 MX8MM_IOMUXC_SAI1_RXD2 = 91,
107 MX8MM_IOMUXC_SAI1_RXD3 = 92,
108 MX8MM_IOMUXC_SAI1_RXD4 = 93,
109 MX8MM_IOMUXC_SAI1_RXD5 = 94,
110 MX8MM_IOMUXC_SAI1_RXD6 = 95,
111 MX8MM_IOMUXC_SAI1_RXD7 = 96,
112 MX8MM_IOMUXC_SAI1_TXFS = 97,
113 MX8MM_IOMUXC_SAI1_TXC = 98,
114 MX8MM_IOMUXC_SAI1_TXD0 = 99,
115 MX8MM_IOMUXC_SAI1_TXD1 = 100,
116 MX8MM_IOMUXC_SAI1_TXD2 = 101,
117 MX8MM_IOMUXC_SAI1_TXD3 = 102,
118 MX8MM_IOMUXC_SAI1_TXD4 = 103,
119 MX8MM_IOMUXC_SAI1_TXD5 = 104,
120 MX8MM_IOMUXC_SAI1_TXD6 = 105,
121 MX8MM_IOMUXC_SAI1_TXD7 = 106,
122 MX8MM_IOMUXC_SAI1_MCLK = 107,
123 MX8MM_IOMUXC_SAI2_RXFS = 108,
124 MX8MM_IOMUXC_SAI2_RXC = 109,
125 MX8MM_IOMUXC_SAI2_RXD0 = 110,
126 MX8MM_IOMUXC_SAI2_TXFS = 111,
127 MX8MM_IOMUXC_SAI2_TXC = 112,
128 MX8MM_IOMUXC_SAI2_TXD0 = 113,
129 MX8MM_IOMUXC_SAI2_MCLK = 114,
130 MX8MM_IOMUXC_SAI3_RXFS = 115,
131 MX8MM_IOMUXC_SAI3_RXC = 116,
132 MX8MM_IOMUXC_SAI3_RXD = 117,
133 MX8MM_IOMUXC_SAI3_TXFS = 118,
134 MX8MM_IOMUXC_SAI3_TXC = 119,
135 MX8MM_IOMUXC_SAI3_TXD = 120,
136 MX8MM_IOMUXC_SAI3_MCLK = 121,
137 MX8MM_IOMUXC_SPDIF_TX = 122,
138 MX8MM_IOMUXC_SPDIF_RX = 123,
139 MX8MM_IOMUXC_SPDIF_EXT_CLK = 124,
140 MX8MM_IOMUXC_ECSPI1_SCLK = 125,
141 MX8MM_IOMUXC_ECSPI1_MOSI = 126,
142 MX8MM_IOMUXC_ECSPI1_MISO = 127,
143 MX8MM_IOMUXC_ECSPI1_SS0 = 128,
144 MX8MM_IOMUXC_ECSPI2_SCLK = 129,
145 MX8MM_IOMUXC_ECSPI2_MOSI = 130,
146 MX8MM_IOMUXC_ECSPI2_MISO = 131,
147 MX8MM_IOMUXC_ECSPI2_SS0 = 132,
148 MX8MM_IOMUXC_I2C1_SCL = 133,
149 MX8MM_IOMUXC_I2C1_SDA = 134,
150 MX8MM_IOMUXC_I2C2_SCL = 135,
151 MX8MM_IOMUXC_I2C2_SDA = 136,
152 MX8MM_IOMUXC_I2C3_SCL = 137,
153 MX8MM_IOMUXC_I2C3_SDA = 138,
154 MX8MM_IOMUXC_I2C4_SCL = 139,
155 MX8MM_IOMUXC_I2C4_SDA = 140,
156 MX8MM_IOMUXC_UART1_RXD = 141,
157 MX8MM_IOMUXC_UART1_TXD = 142,
158 MX8MM_IOMUXC_UART2_RXD = 143,
159 MX8MM_IOMUXC_UART2_TXD = 144,
160 MX8MM_IOMUXC_UART3_RXD = 145,
161 MX8MM_IOMUXC_UART3_TXD = 146,
162 MX8MM_IOMUXC_UART4_RXD = 147,
163 MX8MM_IOMUXC_UART4_TXD = 148,
164};
165
166/* Pad names for the pinmux subsystem */
167static const struct pinctrl_pin_desc imx8mm_pinctrl_pads[] = {
168 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE0),
169 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE1),
170 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE2),
171 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE3),
172 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE4),
173 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE5),
174 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE6),
175 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE7),
176 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE8),
177 IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE9),
178 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO00),
179 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO01),
180 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO02),
181 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO03),
182 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO04),
183 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO05),
184 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO06),
185 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO07),
186 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO08),
187 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO09),
188 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO10),
189 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO11),
190 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO12),
191 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO13),
192 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO14),
193 IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO15),
194 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDC),
195 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDIO),
196 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD3),
197 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD2),
198 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD1),
199 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD0),
200 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TX_CTL),
201 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TXC),
202 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RX_CTL),
203 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RXC),
204 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD0),
205 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD1),
206 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD2),
207 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD3),
208 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CLK),
209 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CMD),
210 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA0),
211 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA1),
212 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA2),
213 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA3),
214 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA4),
215 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA5),
216 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA6),
217 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA7),
218 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_RESET_B),
219 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_STROBE),
220 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CD_B),
221 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CLK),
222 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CMD),
223 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA0),
224 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA1),
225 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA2),
226 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA3),
227 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_RESET_B),
228 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_WP),
229 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_ALE),
230 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE0),
231 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE1),
232 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE2),
233 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE3),
234 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CLE),
235 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA00),
236 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA01),
237 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA02),
238 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA03),
239 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA04),
240 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA05),
241 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA06),
242 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA07),
243 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DQS),
244 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_RE_B),
245 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_READY_B),
246 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WE_B),
247 IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WP_B),
248 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXFS),
249 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXC),
250 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD0),
251 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD1),
252 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD2),
253 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD3),
254 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_MCLK),
255 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXFS),
256 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXC),
257 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD0),
258 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD1),
259 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD2),
260 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD3),
261 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD4),
262 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD5),
263 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD6),
264 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD7),
265 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXFS),
266 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXC),
267 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD0),
268 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD1),
269 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD2),
270 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD3),
271 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD4),
272 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD5),
273 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD6),
274 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD7),
275 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_MCLK),
276 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXFS),
277 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXC),
278 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXD0),
279 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXFS),
280 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXC),
281 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXD0),
282 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_MCLK),
283 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXFS),
284 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXC),
285 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXD),
286 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXFS),
287 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXC),
288 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXD),
289 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_MCLK),
290 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_TX),
291 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_RX),
292 IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_EXT_CLK),
293 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SCLK),
294 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MOSI),
295 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MISO),
296 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SS0),
297 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SCLK),
298 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MOSI),
299 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MISO),
300 IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SS0),
301 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SCL),
302 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SDA),
303 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SCL),
304 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SDA),
305 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SCL),
306 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SDA),
307 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SCL),
308 IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SDA),
309 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_RXD),
310 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_TXD),
311 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_RXD),
312 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_TXD),
313 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_RXD),
314 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_TXD),
315 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_RXD),
316 IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_TXD),
317};
318
319static const struct imx_pinctrl_soc_info imx8mm_pinctrl_info = {
320 .pins = imx8mm_pinctrl_pads,
321 .npins = ARRAY_SIZE(imx8mm_pinctrl_pads),
322 .gpr_compatible = "fsl,imx8mm-iomuxc-gpr",
323};
324
325static const struct of_device_id imx8mm_pinctrl_of_match[] = {
326 { .compatible = "fsl,imx8mm-iomuxc", .data = &imx8mm_pinctrl_info, },
327 { /* sentinel */ }
328};
329
330static int imx8mm_pinctrl_probe(struct platform_device *pdev)
331{
332 return imx_pinctrl_probe(pdev, &imx8mm_pinctrl_info);
333}
334
335static struct platform_driver imx8mm_pinctrl_driver = {
336 .driver = {
337 .name = "imx8mm-pinctrl",
338 .of_match_table = of_match_ptr(imx8mm_pinctrl_of_match),
339 .suppress_bind_attrs = true,
340 },
341 .probe = imx8mm_pinctrl_probe,
342};
343
344static int __init imx8mm_pinctrl_init(void)
345{
346 return platform_driver_register(&imx8mm_pinctrl_driver);
347}
348arch_initcall(imx8mm_pinctrl_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-15 03:28:08 -0500