summaryrefslogtreecommitdiffstats
path: root/drivers/pinctrl
diff options
context:
space:
mode:
authorLudovic Barre <ludovic.barre@st.com>2018-07-17 05:56:27 -0400
committerLinus Walleij <linus.walleij@linaro.org>2018-07-29 16:14:59 -0400
commit2e25a9cbdf8cc300baa8f5eb5130152a6c25dd0a (patch)
tree5fb01a21ede8dfb1ba04c1a1d15c6db138489dcd /drivers/pinctrl
parentde1d08b229746fc650c56ce7ddff34b1c8e778df (diff)
pinctrl: stm32: add syscfg mask parameter
This patch adds mask parameter to define IRQ mux field. This field could vary depend of IRQ mux selection register. To avoid backward compatibility, the drivers set the legacy value by default. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32.c16
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 111225ec075c..a9bec6e6fdd1 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -46,6 +46,8 @@
46#define STM32_GPIO_PINS_PER_BANK 16 46#define STM32_GPIO_PINS_PER_BANK 16
47#define STM32_GPIO_IRQ_LINE 16 47#define STM32_GPIO_IRQ_LINE 16
48 48
49#define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
50
49#define gpio_range_to_bank(chip) \ 51#define gpio_range_to_bank(chip) \
50 container_of(chip, struct stm32_gpio_bank, range) 52 container_of(chip, struct stm32_gpio_bank, range)
51 53
@@ -1054,6 +1056,7 @@ static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1054 struct device *dev = &pdev->dev; 1056 struct device *dev = &pdev->dev;
1055 struct regmap *rm; 1057 struct regmap *rm;
1056 int offset, ret, i; 1058 int offset, ret, i;
1059 int mask, mask_width;
1057 1060
1058 parent = of_irq_find_parent(np); 1061 parent = of_irq_find_parent(np);
1059 if (!parent) 1062 if (!parent)
@@ -1073,12 +1076,21 @@ static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1073 if (ret) 1076 if (ret)
1074 return ret; 1077 return ret;
1075 1078
1079 ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1080 if (ret)
1081 mask = SYSCFG_IRQMUX_MASK;
1082
1083 mask_width = fls(mask);
1084
1076 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { 1085 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1077 struct reg_field mux; 1086 struct reg_field mux;
1078 1087
1079 mux.reg = offset + (i / 4) * 4; 1088 mux.reg = offset + (i / 4) * 4;
1080 mux.lsb = (i % 4) * 4; 1089 mux.lsb = (i % 4) * mask_width;
1081 mux.msb = mux.lsb + 3; 1090 mux.msb = mux.lsb + mask_width - 1;
1091
1092 dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1093 i, mux.reg, mux.lsb, mux.msb);
1082 1094
1083 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); 1095 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1084 if (IS_ERR(pctl->irqmux[i])) 1096 if (IS_ERR(pctl->irqmux[i]))