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authorAlexandre TORGUE <alexandre.torgue@st.com>2017-05-29 12:17:31 -0400
committerLinus Walleij <linus.walleij@linaro.org>2017-05-30 20:04:41 -0400
commit9efa6d1a1eaa1ef392dec8fa68a5de8258dd8e5d (patch)
tree5c7b40beae56e577a959aa7e5fee198e60ba6e0f /drivers/pinctrl/stm32
parentadeac77549ec13dc3bf87ec21f1b8a00f069bb1c (diff)
pinctrl: stm32: set pin to gpio input when used as interrupt
This patch ensures that pin is correctly set as gpio input when it is used as an interrupt. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/stm32')
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32.c39
1 files changed, 29 insertions, 10 deletions
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index d3c5f5dfbbd7..5a15c7deea78 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -219,12 +219,41 @@ static const struct gpio_chip stm32_gpio_template = {
219 .to_irq = stm32_gpio_to_irq, 219 .to_irq = stm32_gpio_to_irq,
220}; 220};
221 221
222static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
223{
224 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
225 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
226 int ret;
227
228 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
229 if (ret)
230 return ret;
231
232 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
233 if (ret) {
234 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
235 irq_data->hwirq);
236 return ret;
237 }
238
239 return 0;
240}
241
242static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
243{
244 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
245
246 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
247}
248
222static struct irq_chip stm32_gpio_irq_chip = { 249static struct irq_chip stm32_gpio_irq_chip = {
223 .name = "stm32gpio", 250 .name = "stm32gpio",
224 .irq_eoi = irq_chip_eoi_parent, 251 .irq_eoi = irq_chip_eoi_parent,
225 .irq_mask = irq_chip_mask_parent, 252 .irq_mask = irq_chip_mask_parent,
226 .irq_unmask = irq_chip_unmask_parent, 253 .irq_unmask = irq_chip_unmask_parent,
227 .irq_set_type = irq_chip_set_type_parent, 254 .irq_set_type = irq_chip_set_type_parent,
255 .irq_request_resources = stm32_gpio_irq_request_resources,
256 .irq_release_resources = stm32_gpio_irq_release_resources,
228}; 257};
229 258
230static int stm32_gpio_domain_translate(struct irq_domain *d, 259static int stm32_gpio_domain_translate(struct irq_domain *d,
@@ -248,15 +277,6 @@ static void stm32_gpio_domain_activate(struct irq_domain *d,
248 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); 277 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
249 278
250 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr); 279 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr);
251 gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
252}
253
254static void stm32_gpio_domain_deactivate(struct irq_domain *d,
255 struct irq_data *irq_data)
256{
257 struct stm32_gpio_bank *bank = d->host_data;
258
259 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
260} 280}
261 281
262static int stm32_gpio_domain_alloc(struct irq_domain *d, 282static int stm32_gpio_domain_alloc(struct irq_domain *d,
@@ -285,7 +305,6 @@ static const struct irq_domain_ops stm32_gpio_domain_ops = {
285 .alloc = stm32_gpio_domain_alloc, 305 .alloc = stm32_gpio_domain_alloc,
286 .free = irq_domain_free_irqs_common, 306 .free = irq_domain_free_irqs_common,
287 .activate = stm32_gpio_domain_activate, 307 .activate = stm32_gpio_domain_activate,
288 .deactivate = stm32_gpio_domain_deactivate,
289}; 308};
290 309
291/* Pinctrl functions */ 310/* Pinctrl functions */