pinctrl: stm32: fix bank io port number

In case the exti line is not in line with the bank number (that is the case
when there is an hole between two banks, for example GPIOK and then GPIOZ),
use "st,bank-ioport" DT property to get the right exti line.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

1 files changed, 8 insertions, 1 deletions

diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index dfed60982a8a..eb6ae1462f4e 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -73,6 +73,7 @@ struct stm32_gpio_bank {
         struct fwnode_handle *fwnode;
         struct irq_domain *domain;
         u32 bank_nr;
+        u32 bank_ioport_nr;
 };
 
 struct stm32_pinctrl {
@@ -298,7 +299,7 @@ static int stm32_gpio_domain_activate(struct irq_domain *d,
         struct stm32_gpio_bank *bank = d->host_data;
         struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
 
-        regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr);
+        regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
         return 0;
 }
 
@@ -948,6 +949,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
         struct device_node *np)
 {
         struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
+        int bank_ioport_nr;
         struct pinctrl_gpio_range *range = &bank->range;
         struct of_phandle_args args;
         struct device *dev = pctl->dev;
@@ -998,12 +1000,17 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
                 pinctrl_add_gpio_range(pctl->pctl_dev,
                                        &pctl->banks[bank_nr].range);
         }
+
+        if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
+                bank_ioport_nr = bank_nr;
+
         bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
 
         bank->gpio_chip.ngpio = npins;
         bank->gpio_chip.of_node = np;
         bank->gpio_chip.parent = dev;
         bank->bank_nr = bank_nr;
+        bank->bank_ioport_nr = bank_ioport_nr;
         spin_lock_init(&bank->lock);
 
         /* create irq hierarchical domain */