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authorMartin Schiller <mschiller@tdt.de>2015-11-26 05:00:07 -0500
committerLinus Walleij <linus.walleij@linaro.org>2015-11-30 07:12:07 -0500
commitbe14811c03cf20c793fd176a347625335110b0e6 (patch)
tree324ebd3b95fa77980de849f9f73616b199695d1a /drivers/pinctrl/pinctrl-xway.c
parentbf714d3780b599731eb18f6a6a3fb67bac38ec21 (diff)
pinctrl/lantiq: introduce new dedicated devicetree bindings
This patch introduces new dedicated "lantiq,<chip>-pinctrl" devicetree bindings, where <chip> is one of "ase", "danube", "xrx100", "xrx200" or "xrx300" and marks the "lantiq,pinctrl-xway", "lantiq,pinctrl-ase" and "lantiq,pinctrl-xr9" bindings as DEPRECATED. Based on the newest Lantiq Hardware Description it turend out, that there are some differences in the GPIO alternative functions of the Danube, xRX100 and xRX200 families, which makes it impossible to use only one xway_mfp table. This patch also adds support for the xRX300 family. Signed-off-by: Martin Schiller <mschiller@tdt.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-xway.c')
-rw-r--r--drivers/pinctrl/pinctrl-xway.c1181
1 files changed, 1051 insertions, 130 deletions
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index ae724bdab3d3..a064962ece8b 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -7,6 +7,7 @@
7 * publishhed by the Free Software Foundation. 7 * publishhed by the Free Software Foundation.
8 * 8 *
9 * Copyright (C) 2012 John Crispin <blogic@openwrt.org> 9 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
10 * Copyright (C) 2015 Martin Schiller <mschiller@tdt.de>
10 */ 11 */
11 12
12#include <linux/err.h> 13#include <linux/err.h>
@@ -24,7 +25,7 @@
24 25
25#include <lantiq_soc.h> 26#include <lantiq_soc.h>
26 27
27/* we have 3 1/2 banks of 16 bit each */ 28/* we have up to 4 banks of 16 bit each */
28#define PINS 16 29#define PINS 16
29#define PORT3 3 30#define PORT3 3
30#define PORT(x) (x / PINS) 31#define PORT(x) (x / PINS)
@@ -35,7 +36,7 @@
35#define MUX_ALT1 0x2 36#define MUX_ALT1 0x2
36 37
37/* 38/*
38 * each bank has this offset apart from the 1/2 bank that is mixed into the 39 * each bank has this offset apart from the 4th bank that is mixed into the
39 * other 3 ranges 40 * other 3 ranges
40 */ 41 */
41#define REG_OFF 0x30 42#define REG_OFF 0x30
@@ -51,7 +52,7 @@
51#define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c) 52#define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c)
52#define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20) 53#define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20)
53 54
54/* the 1/2 port needs special offsets for some registers */ 55/* the 4th port needs special offsets for some registers */
55#define GPIO3_OD (GPIO_BASE(0) + 0x24) 56#define GPIO3_OD (GPIO_BASE(0) + 0x24)
56#define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28) 57#define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28)
57#define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C) 58#define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C)
@@ -80,17 +81,18 @@
80#define FUNC_MUX(f, m) \ 81#define FUNC_MUX(f, m) \
81 { .func = f, .mux = XWAY_MUX_##m, } 82 { .func = f, .mux = XWAY_MUX_##m, }
82 83
83#define XWAY_MAX_PIN 32
84#define XR9_MAX_PIN 56
85
86enum xway_mux { 84enum xway_mux {
87 XWAY_MUX_GPIO = 0, 85 XWAY_MUX_GPIO = 0,
88 XWAY_MUX_SPI, 86 XWAY_MUX_SPI,
89 XWAY_MUX_ASC, 87 XWAY_MUX_ASC,
88 XWAY_MUX_USIF,
90 XWAY_MUX_PCI, 89 XWAY_MUX_PCI,
90 XWAY_MUX_CBUS,
91 XWAY_MUX_CGU, 91 XWAY_MUX_CGU,
92 XWAY_MUX_EBU, 92 XWAY_MUX_EBU,
93 XWAY_MUX_EBU2,
93 XWAY_MUX_JTAG, 94 XWAY_MUX_JTAG,
95 XWAY_MUX_MCD,
94 XWAY_MUX_EXIN, 96 XWAY_MUX_EXIN,
95 XWAY_MUX_TDM, 97 XWAY_MUX_TDM,
96 XWAY_MUX_STP, 98 XWAY_MUX_STP,
@@ -103,9 +105,15 @@ enum xway_mux {
103 XWAY_MUX_DFE, 105 XWAY_MUX_DFE,
104 XWAY_MUX_SDIO, 106 XWAY_MUX_SDIO,
105 XWAY_MUX_GPHY, 107 XWAY_MUX_GPHY,
108 XWAY_MUX_SSI,
109 XWAY_MUX_WIFI,
106 XWAY_MUX_NONE = 0xffff, 110 XWAY_MUX_NONE = 0xffff,
107}; 111};
108 112
113/* --------- DEPRECATED: xr9 related code --------- */
114/* ---------- use xrx100/xrx200 instead ---------- */
115#define XR9_MAX_PIN 56
116
109static const struct ltq_mfp_pin xway_mfp[] = { 117static const struct ltq_mfp_pin xway_mfp[] = {
110 /* pin f0 f1 f2 f3 */ 118 /* pin f0 f1 f2 f3 */
111 MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM), 119 MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM),
@@ -113,7 +121,7 @@ static const struct ltq_mfp_pin xway_mfp[] = {
113 MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY), 121 MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY),
114 MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI), 122 MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI),
115 MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC), 123 MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC),
116 MFP_XWAY(GPIO5, GPIO, STP, NONE, GPHY), 124 MFP_XWAY(GPIO5, GPIO, STP, GPHY, NONE),
117 MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC), 125 MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
118 MFP_XWAY(GPIO7, GPIO, CGU, PCI, GPHY), 126 MFP_XWAY(GPIO7, GPIO, CGU, PCI, GPHY),
119 MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE), 127 MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
@@ -152,7 +160,7 @@ static const struct ltq_mfp_pin xway_mfp[] = {
152 MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE), 160 MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE),
153 MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE), 161 MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
154 MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE), 162 MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
155 MFP_XWAY(GPIO44, GPIO, NONE, GPHY, SIN), 163 MFP_XWAY(GPIO44, GPIO, NONE, SIN, GPHY),
156 MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN), 164 MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN),
157 MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN), 165 MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN),
158 MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN), 166 MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN),
@@ -166,42 +174,6 @@ static const struct ltq_mfp_pin xway_mfp[] = {
166 MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE), 174 MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE),
167}; 175};
168 176
169static const struct ltq_mfp_pin ase_mfp[] = {
170 /* pin f0 f1 f2 f3 */
171 MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM),
172 MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
173 MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY),
174 MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
175 MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
176 MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
177 MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN),
178 MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
179 MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
180 MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
181 MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
182 MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
183 MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
184 MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
185 MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
186 MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
187 MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE),
188 MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE),
189 MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE),
190 MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO),
191 MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO),
192 MFP_XWAY(GPIO21, GPIO, EBU, MII, SDIO),
193 MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU),
194 MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU),
195 MFP_XWAY(GPIO24, GPIO, EBU, NONE, MII),
196 MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT),
197 MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO),
198 MFP_XWAY(GPIO27, GPIO, EBU, NONE, MII),
199 MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO),
200 MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN),
201 MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE),
202 MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE),
203};
204
205static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35}; 177static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35};
206static const unsigned pins_asc0[] = {GPIO11, GPIO12}; 178static const unsigned pins_asc0[] = {GPIO11, GPIO12};
207static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10}; 179static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10};
@@ -231,6 +203,8 @@ static const unsigned pins_nand_cle[] = {GPIO24};
231static const unsigned pins_nand_rdy[] = {GPIO48}; 203static const unsigned pins_nand_rdy[] = {GPIO48};
232static const unsigned pins_nand_rd[] = {GPIO49}; 204static const unsigned pins_nand_rd[] = {GPIO49};
233 205
206static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9};
207
234static const unsigned pins_exin0[] = {GPIO0}; 208static const unsigned pins_exin0[] = {GPIO0};
235static const unsigned pins_exin1[] = {GPIO1}; 209static const unsigned pins_exin1[] = {GPIO1};
236static const unsigned pins_exin2[] = {GPIO2}; 210static const unsigned pins_exin2[] = {GPIO2};
@@ -240,7 +214,7 @@ static const unsigned pins_exin5[] = {GPIO9};
240 214
241static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18}; 215static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18};
242static const unsigned pins_spi_cs1[] = {GPIO15}; 216static const unsigned pins_spi_cs1[] = {GPIO15};
243static const unsigned pins_spi_cs2[] = {GPIO21}; 217static const unsigned pins_spi_cs2[] = {GPIO22};
244static const unsigned pins_spi_cs3[] = {GPIO13}; 218static const unsigned pins_spi_cs3[] = {GPIO13};
245static const unsigned pins_spi_cs4[] = {GPIO10}; 219static const unsigned pins_spi_cs4[] = {GPIO10};
246static const unsigned pins_spi_cs5[] = {GPIO9}; 220static const unsigned pins_spi_cs5[] = {GPIO9};
@@ -264,25 +238,6 @@ static const unsigned pins_pci_req2[] = {GPIO31};
264static const unsigned pins_pci_req3[] = {GPIO3}; 238static const unsigned pins_pci_req3[] = {GPIO3};
265static const unsigned pins_pci_req4[] = {GPIO37}; 239static const unsigned pins_pci_req4[] = {GPIO37};
266 240
267static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
268static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
269static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
270static const unsigned ase_pins_ephy[] = {GPIO2, GPIO3, GPIO4};
271static const unsigned ase_pins_dfe[] = {GPIO1, GPIO2};
272
273static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10};
274static const unsigned ase_pins_spi_cs1[] = {GPIO7};
275static const unsigned ase_pins_spi_cs2[] = {GPIO15};
276static const unsigned ase_pins_spi_cs3[] = {GPIO14};
277
278static const unsigned ase_pins_exin0[] = {GPIO6};
279static const unsigned ase_pins_exin1[] = {GPIO29};
280static const unsigned ase_pins_exin2[] = {GPIO0};
281
282static const unsigned ase_pins_gpt1[] = {GPIO5};
283static const unsigned ase_pins_gpt2[] = {GPIO4};
284static const unsigned ase_pins_gpt3[] = {GPIO25};
285
286static const struct ltq_pin_group xway_grps[] = { 241static const struct ltq_pin_group xway_grps[] = {
287 GRP_MUX("exin0", EXIN, pins_exin0), 242 GRP_MUX("exin0", EXIN, pins_exin0),
288 GRP_MUX("exin1", EXIN, pins_exin1), 243 GRP_MUX("exin1", EXIN, pins_exin1),
@@ -338,24 +293,6 @@ static const struct ltq_pin_group xway_grps[] = {
338 GRP_MUX("gphy1 led2", GPHY, pins_gphy1_led2), 293 GRP_MUX("gphy1 led2", GPHY, pins_gphy1_led2),
339}; 294};
340 295
341static const struct ltq_pin_group ase_grps[] = {
342 GRP_MUX("exin0", EXIN, ase_pins_exin0),
343 GRP_MUX("exin1", EXIN, ase_pins_exin1),
344 GRP_MUX("exin2", EXIN, ase_pins_exin2),
345 GRP_MUX("jtag", JTAG, ase_pins_jtag),
346 GRP_MUX("stp", STP, ase_pins_stp),
347 GRP_MUX("asc", ASC, ase_pins_asc),
348 GRP_MUX("gpt1", GPT, ase_pins_gpt1),
349 GRP_MUX("gpt2", GPT, ase_pins_gpt2),
350 GRP_MUX("gpt3", GPT, ase_pins_gpt3),
351 GRP_MUX("ephy", EPHY, ase_pins_ephy),
352 GRP_MUX("dfe", DFE, ase_pins_dfe),
353 GRP_MUX("spi", SPI, ase_pins_spi),
354 GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
355 GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
356 GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
357};
358
359static const char * const xway_pci_grps[] = {"gnt1", "gnt2", 296static const char * const xway_pci_grps[] = {"gnt1", "gnt2",
360 "gnt3", "req1", 297 "gnt3", "req1",
361 "req2", "req3"}; 298 "req2", "req3"};
@@ -395,30 +332,6 @@ static const char * const xrx_pci_grps[] = {"gnt1", "gnt2",
395 "req1", "req2", 332 "req1", "req2",
396 "req3", "req4"}; 333 "req3", "req4"};
397 334
398/* ase */
399static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
400static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
401static const char * const ase_dfe_grps[] = {"dfe"};
402static const char * const ase_ephy_grps[] = {"ephy"};
403static const char * const ase_asc_grps[] = {"asc"};
404static const char * const ase_jtag_grps[] = {"jtag"};
405static const char * const ase_stp_grps[] = {"stp"};
406static const char * const ase_spi_grps[] = {"spi", "spi_cs1",
407 "spi_cs2", "spi_cs3"};
408
409static const struct ltq_pmx_func danube_funcs[] = {
410 {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
411 {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
412 {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)},
413 {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)},
414 {"exin", ARRAY_AND_SIZE(xway_exin_grps)},
415 {"stp", ARRAY_AND_SIZE(xway_stp_grps)},
416 {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)},
417 {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)},
418 {"pci", ARRAY_AND_SIZE(xway_pci_grps)},
419 {"ebu", ARRAY_AND_SIZE(xway_ebu_grps)},
420};
421
422static const struct ltq_pmx_func xrx_funcs[] = { 335static const struct ltq_pmx_func xrx_funcs[] = {
423 {"spi", ARRAY_AND_SIZE(xway_spi_grps)}, 336 {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
424 {"asc", ARRAY_AND_SIZE(xway_asc_grps)}, 337 {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
@@ -434,17 +347,991 @@ static const struct ltq_pmx_func xrx_funcs[] = {
434 {"gphy", ARRAY_AND_SIZE(xrx_gphy_grps)}, 347 {"gphy", ARRAY_AND_SIZE(xrx_gphy_grps)},
435}; 348};
436 349
350/* --------- ase related code --------- */
351#define ASE_MAX_PIN 32
352
353static const struct ltq_mfp_pin ase_mfp[] = {
354 /* pin f0 f1 f2 f3 */
355 MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM),
356 MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
357 MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY),
358 MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
359 MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
360 MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
361 MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN),
362 MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
363 MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
364 MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
365 MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
366 MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
367 MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
368 MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
369 MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
370 MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
371 MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE),
372 MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE),
373 MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE),
374 MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO),
375 MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO),
376 MFP_XWAY(GPIO21, GPIO, EBU, MII, EBU2),
377 MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU),
378 MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU),
379 MFP_XWAY(GPIO24, GPIO, EBU, EBU2, MDIO),
380 MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT),
381 MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO),
382 MFP_XWAY(GPIO27, GPIO, EBU, NONE, MDIO),
383 MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO),
384 MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN),
385 MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE),
386 MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE),
387};
388
389static const unsigned ase_exin_pin_map[] = {GPIO6, GPIO29, GPIO0};
390
391static const unsigned ase_pins_exin0[] = {GPIO6};
392static const unsigned ase_pins_exin1[] = {GPIO29};
393static const unsigned ase_pins_exin2[] = {GPIO0};
394
395static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
396static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
397static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
398static const unsigned ase_pins_mdio[] = {GPIO24, GPIO27};
399static const unsigned ase_pins_ephy_led0[] = {GPIO2};
400static const unsigned ase_pins_ephy_led1[] = {GPIO3};
401static const unsigned ase_pins_ephy_led2[] = {GPIO4};
402static const unsigned ase_pins_dfe_led0[] = {GPIO1};
403static const unsigned ase_pins_dfe_led1[] = {GPIO2};
404
405static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; /* DEPRECATED */
406static const unsigned ase_pins_spi_di[] = {GPIO8};
407static const unsigned ase_pins_spi_do[] = {GPIO9};
408static const unsigned ase_pins_spi_clk[] = {GPIO10};
409static const unsigned ase_pins_spi_cs1[] = {GPIO7};
410static const unsigned ase_pins_spi_cs2[] = {GPIO15};
411static const unsigned ase_pins_spi_cs3[] = {GPIO14};
412
413static const unsigned ase_pins_gpt1[] = {GPIO5};
414static const unsigned ase_pins_gpt2[] = {GPIO4};
415static const unsigned ase_pins_gpt3[] = {GPIO25};
416
417static const unsigned ase_pins_clkout0[] = {GPIO23};
418static const unsigned ase_pins_clkout1[] = {GPIO22};
419static const unsigned ase_pins_clkout2[] = {GPIO14};
420
421static const struct ltq_pin_group ase_grps[] = {
422 GRP_MUX("exin0", EXIN, ase_pins_exin0),
423 GRP_MUX("exin1", EXIN, ase_pins_exin1),
424 GRP_MUX("exin2", EXIN, ase_pins_exin2),
425 GRP_MUX("jtag", JTAG, ase_pins_jtag),
426 GRP_MUX("spi", SPI, ase_pins_spi), /* DEPRECATED */
427 GRP_MUX("spi_di", SPI, ase_pins_spi_di),
428 GRP_MUX("spi_do", SPI, ase_pins_spi_do),
429 GRP_MUX("spi_clk", SPI, ase_pins_spi_clk),
430 GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
431 GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
432 GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
433 GRP_MUX("asc", ASC, ase_pins_asc),
434 GRP_MUX("stp", STP, ase_pins_stp),
435 GRP_MUX("gpt1", GPT, ase_pins_gpt1),
436 GRP_MUX("gpt2", GPT, ase_pins_gpt2),
437 GRP_MUX("gpt3", GPT, ase_pins_gpt3),
438 GRP_MUX("clkout0", CGU, ase_pins_clkout0),
439 GRP_MUX("clkout1", CGU, ase_pins_clkout1),
440 GRP_MUX("clkout2", CGU, ase_pins_clkout2),
441 GRP_MUX("mdio", MDIO, ase_pins_mdio),
442 GRP_MUX("dfe led0", DFE, ase_pins_dfe_led0),
443 GRP_MUX("dfe led1", DFE, ase_pins_dfe_led1),
444 GRP_MUX("ephy led0", EPHY, ase_pins_ephy_led0),
445 GRP_MUX("ephy led1", EPHY, ase_pins_ephy_led1),
446 GRP_MUX("ephy led2", EPHY, ase_pins_ephy_led2),
447};
448
449static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
450static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
451static const char * const ase_cgu_grps[] = {"clkout0", "clkout1",
452 "clkout2"};
453static const char * const ase_mdio_grps[] = {"mdio"};
454static const char * const ase_dfe_grps[] = {"dfe led0", "dfe led1"};
455static const char * const ase_ephy_grps[] = {"ephy led0", "ephy led1",
456 "ephy led2"};
457static const char * const ase_asc_grps[] = {"asc"};
458static const char * const ase_jtag_grps[] = {"jtag"};
459static const char * const ase_stp_grps[] = {"stp"};
460static const char * const ase_spi_grps[] = {"spi", /* DEPRECATED */
461 "spi_di", "spi_do",
462 "spi_clk", "spi_cs1",
463 "spi_cs2", "spi_cs3"};
464
437static const struct ltq_pmx_func ase_funcs[] = { 465static const struct ltq_pmx_func ase_funcs[] = {
438 {"spi", ARRAY_AND_SIZE(ase_spi_grps)}, 466 {"spi", ARRAY_AND_SIZE(ase_spi_grps)},
439 {"asc", ARRAY_AND_SIZE(ase_asc_grps)}, 467 {"asc", ARRAY_AND_SIZE(ase_asc_grps)},
468 {"cgu", ARRAY_AND_SIZE(ase_cgu_grps)},
440 {"jtag", ARRAY_AND_SIZE(ase_jtag_grps)}, 469 {"jtag", ARRAY_AND_SIZE(ase_jtag_grps)},
441 {"exin", ARRAY_AND_SIZE(ase_exin_grps)}, 470 {"exin", ARRAY_AND_SIZE(ase_exin_grps)},
442 {"stp", ARRAY_AND_SIZE(ase_stp_grps)}, 471 {"stp", ARRAY_AND_SIZE(ase_stp_grps)},
443 {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)}, 472 {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)},
473 {"mdio", ARRAY_AND_SIZE(ase_mdio_grps)},
444 {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)}, 474 {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)},
445 {"dfe", ARRAY_AND_SIZE(ase_dfe_grps)}, 475 {"dfe", ARRAY_AND_SIZE(ase_dfe_grps)},
446}; 476};
447 477
478/* --------- danube related code --------- */
479#define DANUBE_MAX_PIN 32
480
481static const struct ltq_mfp_pin danube_mfp[] = {
482 /* pin f0 f1 f2 f3 */
483 MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM),
484 MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, MII),
485 MFP_XWAY(GPIO2, GPIO, CGU, EXIN, MII),
486 MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI),
487 MFP_XWAY(GPIO4, GPIO, STP, DFE, ASC),
488 MFP_XWAY(GPIO5, GPIO, STP, MII, DFE),
489 MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
490 MFP_XWAY(GPIO7, GPIO, CGU, CBUS, MII),
491 MFP_XWAY(GPIO8, GPIO, CGU, NMI, MII),
492 MFP_XWAY(GPIO9, GPIO, ASC, SPI, MII),
493 MFP_XWAY(GPIO10, GPIO, ASC, SPI, MII),
494 MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
495 MFP_XWAY(GPIO12, GPIO, ASC, CBUS, MCD),
496 MFP_XWAY(GPIO13, GPIO, EBU, SPI, MII),
497 MFP_XWAY(GPIO14, GPIO, CGU, CBUS, MII),
498 MFP_XWAY(GPIO15, GPIO, SPI, SDIO, JTAG),
499 MFP_XWAY(GPIO16, GPIO, SPI, SDIO, JTAG),
500 MFP_XWAY(GPIO17, GPIO, SPI, SDIO, JTAG),
501 MFP_XWAY(GPIO18, GPIO, SPI, SDIO, JTAG),
502 MFP_XWAY(GPIO19, GPIO, PCI, SDIO, MII),
503 MFP_XWAY(GPIO20, GPIO, JTAG, SDIO, MII),
504 MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
505 MFP_XWAY(GPIO22, GPIO, SPI, MCD, MII),
506 MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
507 MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
508 MFP_XWAY(GPIO25, GPIO, TDM, SDIO, ASC),
509 MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO),
510 MFP_XWAY(GPIO27, GPIO, TDM, SDIO, ASC),
511 MFP_XWAY(GPIO28, GPIO, GPT, MII, SDIO),
512 MFP_XWAY(GPIO29, GPIO, PCI, CBUS, MII),
513 MFP_XWAY(GPIO30, GPIO, PCI, CBUS, MII),
514 MFP_XWAY(GPIO31, GPIO, EBU, PCI, MII),
515};
516
517static const unsigned danube_exin_pin_map[] = {GPIO0, GPIO1, GPIO2};
518
519static const unsigned danube_pins_exin0[] = {GPIO0};
520static const unsigned danube_pins_exin1[] = {GPIO1};
521static const unsigned danube_pins_exin2[] = {GPIO2};
522
523static const unsigned danube_pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO18, GPIO20};
524static const unsigned danube_pins_asc0[] = {GPIO11, GPIO12};
525static const unsigned danube_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
526static const unsigned danube_pins_stp[] = {GPIO4, GPIO5, GPIO6};
527static const unsigned danube_pins_nmi[] = {GPIO8};
528
529static const unsigned danube_pins_dfe_led0[] = {GPIO4};
530static const unsigned danube_pins_dfe_led1[] = {GPIO5};
531
532static const unsigned danube_pins_ebu_a24[] = {GPIO13};
533static const unsigned danube_pins_ebu_clk[] = {GPIO21};
534static const unsigned danube_pins_ebu_cs1[] = {GPIO23};
535static const unsigned danube_pins_ebu_a23[] = {GPIO24};
536static const unsigned danube_pins_ebu_wait[] = {GPIO26};
537static const unsigned danube_pins_ebu_a25[] = {GPIO31};
538
539static const unsigned danube_pins_nand_ale[] = {GPIO13};
540static const unsigned danube_pins_nand_cs1[] = {GPIO23};
541static const unsigned danube_pins_nand_cle[] = {GPIO24};
542
543static const unsigned danube_pins_spi[] = {GPIO16, GPIO17, GPIO18}; /* DEPRECATED */
544static const unsigned danube_pins_spi_di[] = {GPIO16};
545static const unsigned danube_pins_spi_do[] = {GPIO17};
546static const unsigned danube_pins_spi_clk[] = {GPIO18};
547static const unsigned danube_pins_spi_cs1[] = {GPIO15};
548static const unsigned danube_pins_spi_cs2[] = {GPIO21};
549static const unsigned danube_pins_spi_cs3[] = {GPIO13};
550static const unsigned danube_pins_spi_cs4[] = {GPIO10};
551static const unsigned danube_pins_spi_cs5[] = {GPIO9};
552static const unsigned danube_pins_spi_cs6[] = {GPIO11};
553
554static const unsigned danube_pins_gpt1[] = {GPIO28};
555static const unsigned danube_pins_gpt2[] = {GPIO21};
556static const unsigned danube_pins_gpt3[] = {GPIO6};
557
558static const unsigned danube_pins_clkout0[] = {GPIO8};
559static const unsigned danube_pins_clkout1[] = {GPIO7};
560static const unsigned danube_pins_clkout2[] = {GPIO3};
561static const unsigned danube_pins_clkout3[] = {GPIO2};
562
563static const unsigned danube_pins_pci_gnt1[] = {GPIO30};
564static const unsigned danube_pins_pci_gnt2[] = {GPIO23};
565static const unsigned danube_pins_pci_gnt3[] = {GPIO19};
566static const unsigned danube_pins_pci_req1[] = {GPIO29};
567static const unsigned danube_pins_pci_req2[] = {GPIO31};
568static const unsigned danube_pins_pci_req3[] = {GPIO3};
569
570static const struct ltq_pin_group danube_grps[] = {
571 GRP_MUX("exin0", EXIN, danube_pins_exin0),
572 GRP_MUX("exin1", EXIN, danube_pins_exin1),
573 GRP_MUX("exin2", EXIN, danube_pins_exin2),
574 GRP_MUX("jtag", JTAG, danube_pins_jtag),
575 GRP_MUX("ebu a23", EBU, danube_pins_ebu_a23),
576 GRP_MUX("ebu a24", EBU, danube_pins_ebu_a24),
577 GRP_MUX("ebu a25", EBU, danube_pins_ebu_a25),
578 GRP_MUX("ebu clk", EBU, danube_pins_ebu_clk),
579 GRP_MUX("ebu cs1", EBU, danube_pins_ebu_cs1),
580 GRP_MUX("ebu wait", EBU, danube_pins_ebu_wait),
581 GRP_MUX("nand ale", EBU, danube_pins_nand_ale),
582 GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1),
583 GRP_MUX("nand cle", EBU, danube_pins_nand_cle),
584 GRP_MUX("spi", SPI, danube_pins_spi), /* DEPRECATED */
585 GRP_MUX("spi_di", SPI, danube_pins_spi_di),
586 GRP_MUX("spi_do", SPI, danube_pins_spi_do),
587 GRP_MUX("spi_clk", SPI, danube_pins_spi_clk),
588 GRP_MUX("spi_cs1", SPI, danube_pins_spi_cs1),
589 GRP_MUX("spi_cs2", SPI, danube_pins_spi_cs2),
590 GRP_MUX("spi_cs3", SPI, danube_pins_spi_cs3),
591 GRP_MUX("spi_cs4", SPI, danube_pins_spi_cs4),
592 GRP_MUX("spi_cs5", SPI, danube_pins_spi_cs5),
593 GRP_MUX("spi_cs6", SPI, danube_pins_spi_cs6),
594 GRP_MUX("asc0", ASC, danube_pins_asc0),
595 GRP_MUX("asc0 cts rts", ASC, danube_pins_asc0_cts_rts),
596 GRP_MUX("stp", STP, danube_pins_stp),
597 GRP_MUX("nmi", NMI, danube_pins_nmi),
598 GRP_MUX("gpt1", GPT, danube_pins_gpt1),
599 GRP_MUX("gpt2", GPT, danube_pins_gpt2),
600 GRP_MUX("gpt3", GPT, danube_pins_gpt3),
601 GRP_MUX("clkout0", CGU, danube_pins_clkout0),
602 GRP_MUX("clkout1", CGU, danube_pins_clkout1),
603 GRP_MUX("clkout2", CGU, danube_pins_clkout2),
604 GRP_MUX("clkout3", CGU, danube_pins_clkout3),
605 GRP_MUX("gnt1", PCI, danube_pins_pci_gnt1),
606 GRP_MUX("gnt2", PCI, danube_pins_pci_gnt2),
607 GRP_MUX("gnt3", PCI, danube_pins_pci_gnt3),
608 GRP_MUX("req1", PCI, danube_pins_pci_req1),
609 GRP_MUX("req2", PCI, danube_pins_pci_req2),
610 GRP_MUX("req3", PCI, danube_pins_pci_req3),
611 GRP_MUX("dfe led0", DFE, danube_pins_dfe_led0),
612 GRP_MUX("dfe led1", DFE, danube_pins_dfe_led1),
613};
614
615static const char * const danube_pci_grps[] = {"gnt1", "gnt2",
616 "gnt3", "req1",
617 "req2", "req3"};
618static const char * const danube_spi_grps[] = {"spi", /* DEPRECATED */
619 "spi_di", "spi_do",
620 "spi_clk", "spi_cs1",
621 "spi_cs2", "spi_cs3",
622 "spi_cs4", "spi_cs5",
623 "spi_cs6"};
624static const char * const danube_cgu_grps[] = {"clkout0", "clkout1",
625 "clkout2", "clkout3"};
626static const char * const danube_ebu_grps[] = {"ebu a23", "ebu a24",
627 "ebu a25", "ebu cs1",
628 "ebu wait", "ebu clk",
629 "nand ale", "nand cs1",
630 "nand cle"};
631static const char * const danube_dfe_grps[] = {"dfe led0", "dfe led1"};
632static const char * const danube_exin_grps[] = {"exin0", "exin1", "exin2"};
633static const char * const danube_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
634static const char * const danube_asc_grps[] = {"asc0", "asc0 cts rts"};
635static const char * const danube_jtag_grps[] = {"jtag"};
636static const char * const danube_stp_grps[] = {"stp"};
637static const char * const danube_nmi_grps[] = {"nmi"};
638
639static const struct ltq_pmx_func danube_funcs[] = {
640 {"spi", ARRAY_AND_SIZE(danube_spi_grps)},
641 {"asc", ARRAY_AND_SIZE(danube_asc_grps)},
642 {"cgu", ARRAY_AND_SIZE(danube_cgu_grps)},
643 {"jtag", ARRAY_AND_SIZE(danube_jtag_grps)},
644 {"exin", ARRAY_AND_SIZE(danube_exin_grps)},
645 {"stp", ARRAY_AND_SIZE(danube_stp_grps)},
646 {"gpt", ARRAY_AND_SIZE(danube_gpt_grps)},
647 {"nmi", ARRAY_AND_SIZE(danube_nmi_grps)},
648 {"pci", ARRAY_AND_SIZE(danube_pci_grps)},
649 {"ebu", ARRAY_AND_SIZE(danube_ebu_grps)},
650 {"dfe", ARRAY_AND_SIZE(danube_dfe_grps)},
651};
652
653/* --------- xrx100 related code --------- */
654#define XRX100_MAX_PIN 56
655
656static const struct ltq_mfp_pin xrx100_mfp[] = {
657 /* pin f0 f1 f2 f3 */
658 MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM),
659 MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, SIN),
660 MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE),
661 MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI),
662 MFP_XWAY(GPIO4, GPIO, STP, DFE, ASC),
663 MFP_XWAY(GPIO5, GPIO, STP, NONE, DFE),
664 MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
665 MFP_XWAY(GPIO7, GPIO, CGU, CBUS, NONE),
666 MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
667 MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
668 MFP_XWAY(GPIO10, GPIO, ASC, SPI, EXIN),
669 MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
670 MFP_XWAY(GPIO12, GPIO, ASC, CBUS, MCD),
671 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
672 MFP_XWAY(GPIO14, GPIO, CGU, NONE, NONE),
673 MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
674 MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
675 MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
676 MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
677 MFP_XWAY(GPIO19, GPIO, PCI, SDIO, CGU),
678 MFP_XWAY(GPIO20, GPIO, NONE, SDIO, EBU),
679 MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
680 MFP_XWAY(GPIO22, GPIO, SPI, NONE, EBU),
681 MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
682 MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
683 MFP_XWAY(GPIO25, GPIO, TDM, SDIO, ASC),
684 MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO),
685 MFP_XWAY(GPIO27, GPIO, TDM, SDIO, ASC),
686 MFP_XWAY(GPIO28, GPIO, GPT, NONE, SDIO),
687 MFP_XWAY(GPIO29, GPIO, PCI, CBUS, NONE),
688 MFP_XWAY(GPIO30, GPIO, PCI, CBUS, NONE),
689 MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
690 MFP_XWAY(GPIO32, GPIO, MII, NONE, EBU),
691 MFP_XWAY(GPIO33, GPIO, MII, NONE, EBU),
692 MFP_XWAY(GPIO34, GPIO, SIN, SSI, NONE),
693 MFP_XWAY(GPIO35, GPIO, SIN, SSI, NONE),
694 MFP_XWAY(GPIO36, GPIO, SIN, SSI, NONE),
695 MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE),
696 MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE),
697 MFP_XWAY(GPIO39, GPIO, NONE, EXIN, NONE),
698 MFP_XWAY(GPIO40, GPIO, MII, TDM, NONE),
699 MFP_XWAY(GPIO41, GPIO, MII, TDM, NONE),
700 MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
701 MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
702 MFP_XWAY(GPIO44, GPIO, MII, SIN, NONE),
703 MFP_XWAY(GPIO45, GPIO, MII, NONE, SIN),
704 MFP_XWAY(GPIO46, GPIO, MII, NONE, EXIN),
705 MFP_XWAY(GPIO47, GPIO, MII, NONE, SIN),
706 MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
707 MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
708 MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),
709 MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE),
710 MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE),
711 MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE),
712 MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE),
713 MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE),
714};
715
716static const unsigned xrx100_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
717
718static const unsigned xrx100_pins_exin0[] = {GPIO0};
719static const unsigned xrx100_pins_exin1[] = {GPIO1};
720static const unsigned xrx100_pins_exin2[] = {GPIO2};
721static const unsigned xrx100_pins_exin3[] = {GPIO39};
722static const unsigned xrx100_pins_exin4[] = {GPIO10};
723static const unsigned xrx100_pins_exin5[] = {GPIO9};
724
725static const unsigned xrx100_pins_asc0[] = {GPIO11, GPIO12};
726static const unsigned xrx100_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
727static const unsigned xrx100_pins_stp[] = {GPIO4, GPIO5, GPIO6};
728static const unsigned xrx100_pins_nmi[] = {GPIO8};
729static const unsigned xrx100_pins_mdio[] = {GPIO42, GPIO43};
730
731static const unsigned xrx100_pins_dfe_led0[] = {GPIO4};
732static const unsigned xrx100_pins_dfe_led1[] = {GPIO5};
733
734static const unsigned xrx100_pins_ebu_a24[] = {GPIO13};
735static const unsigned xrx100_pins_ebu_clk[] = {GPIO21};
736static const unsigned xrx100_pins_ebu_cs1[] = {GPIO23};
737static const unsigned xrx100_pins_ebu_a23[] = {GPIO24};
738static const unsigned xrx100_pins_ebu_wait[] = {GPIO26};
739static const unsigned xrx100_pins_ebu_a25[] = {GPIO31};
740
741static const unsigned xrx100_pins_nand_ale[] = {GPIO13};
742static const unsigned xrx100_pins_nand_cs1[] = {GPIO23};
743static const unsigned xrx100_pins_nand_cle[] = {GPIO24};
744static const unsigned xrx100_pins_nand_rdy[] = {GPIO48};
745static const unsigned xrx100_pins_nand_rd[] = {GPIO49};
746
747static const unsigned xrx100_pins_spi_di[] = {GPIO16};
748static const unsigned xrx100_pins_spi_do[] = {GPIO17};
749static const unsigned xrx100_pins_spi_clk[] = {GPIO18};
750static const unsigned xrx100_pins_spi_cs1[] = {GPIO15};
751static const unsigned xrx100_pins_spi_cs2[] = {GPIO22};
752static const unsigned xrx100_pins_spi_cs3[] = {GPIO13};
753static const unsigned xrx100_pins_spi_cs4[] = {GPIO10};
754static const unsigned xrx100_pins_spi_cs5[] = {GPIO9};
755static const unsigned xrx100_pins_spi_cs6[] = {GPIO11};
756
757static const unsigned xrx100_pins_gpt1[] = {GPIO28};
758static const unsigned xrx100_pins_gpt2[] = {GPIO21};
759static const unsigned xrx100_pins_gpt3[] = {GPIO6};
760
761static const unsigned xrx100_pins_clkout0[] = {GPIO8};
762static const unsigned xrx100_pins_clkout1[] = {GPIO7};
763static const unsigned xrx100_pins_clkout2[] = {GPIO3};
764static const unsigned xrx100_pins_clkout3[] = {GPIO2};
765
766static const unsigned xrx100_pins_pci_gnt1[] = {GPIO30};
767static const unsigned xrx100_pins_pci_gnt2[] = {GPIO23};
768static const unsigned xrx100_pins_pci_gnt3[] = {GPIO19};
769static const unsigned xrx100_pins_pci_gnt4[] = {GPIO38};
770static const unsigned xrx100_pins_pci_req1[] = {GPIO29};
771static const unsigned xrx100_pins_pci_req2[] = {GPIO31};
772static const unsigned xrx100_pins_pci_req3[] = {GPIO3};
773static const unsigned xrx100_pins_pci_req4[] = {GPIO37};
774
775static const struct ltq_pin_group xrx100_grps[] = {
776 GRP_MUX("exin0", EXIN, xrx100_pins_exin0),
777 GRP_MUX("exin1", EXIN, xrx100_pins_exin1),
778 GRP_MUX("exin2", EXIN, xrx100_pins_exin2),
779 GRP_MUX("exin3", EXIN, xrx100_pins_exin3),
780 GRP_MUX("exin4", EXIN, xrx100_pins_exin4),
781 GRP_MUX("exin5", EXIN, xrx100_pins_exin5),
782 GRP_MUX("ebu a23", EBU, xrx100_pins_ebu_a23),
783 GRP_MUX("ebu a24", EBU, xrx100_pins_ebu_a24),
784 GRP_MUX("ebu a25", EBU, xrx100_pins_ebu_a25),
785 GRP_MUX("ebu clk", EBU, xrx100_pins_ebu_clk),
786 GRP_MUX("ebu cs1", EBU, xrx100_pins_ebu_cs1),
787 GRP_MUX("ebu wait", EBU, xrx100_pins_ebu_wait),
788 GRP_MUX("nand ale", EBU, xrx100_pins_nand_ale),
789 GRP_MUX("nand cs1", EBU, xrx100_pins_nand_cs1),
790 GRP_MUX("nand cle", EBU, xrx100_pins_nand_cle),
791 GRP_MUX("nand rdy", EBU, xrx100_pins_nand_rdy),
792 GRP_MUX("nand rd", EBU, xrx100_pins_nand_rd),
793 GRP_MUX("spi_di", SPI, xrx100_pins_spi_di),
794 GRP_MUX("spi_do", SPI, xrx100_pins_spi_do),
795 GRP_MUX("spi_clk", SPI, xrx100_pins_spi_clk),
796 GRP_MUX("spi_cs1", SPI, xrx100_pins_spi_cs1),
797 GRP_MUX("spi_cs2", SPI, xrx100_pins_spi_cs2),
798 GRP_MUX("spi_cs3", SPI, xrx100_pins_spi_cs3),
799 GRP_MUX("spi_cs4", SPI, xrx100_pins_spi_cs4),
800 GRP_MUX("spi_cs5", SPI, xrx100_pins_spi_cs5),
801 GRP_MUX("spi_cs6", SPI, xrx100_pins_spi_cs6),
802 GRP_MUX("asc0", ASC, xrx100_pins_asc0),
803 GRP_MUX("asc0 cts rts", ASC, xrx100_pins_asc0_cts_rts),
804 GRP_MUX("stp", STP, xrx100_pins_stp),
805 GRP_MUX("nmi", NMI, xrx100_pins_nmi),
806 GRP_MUX("gpt1", GPT, xrx100_pins_gpt1),
807 GRP_MUX("gpt2", GPT, xrx100_pins_gpt2),
808 GRP_MUX("gpt3", GPT, xrx100_pins_gpt3),
809 GRP_MUX("clkout0", CGU, xrx100_pins_clkout0),
810 GRP_MUX("clkout1", CGU, xrx100_pins_clkout1),
811 GRP_MUX("clkout2", CGU, xrx100_pins_clkout2),
812 GRP_MUX("clkout3", CGU, xrx100_pins_clkout3),
813 GRP_MUX("gnt1", PCI, xrx100_pins_pci_gnt1),
814 GRP_MUX("gnt2", PCI, xrx100_pins_pci_gnt2),
815 GRP_MUX("gnt3", PCI, xrx100_pins_pci_gnt3),
816 GRP_MUX("gnt4", PCI, xrx100_pins_pci_gnt4),
817 GRP_MUX("req1", PCI, xrx100_pins_pci_req1),
818 GRP_MUX("req2", PCI, xrx100_pins_pci_req2),
819 GRP_MUX("req3", PCI, xrx100_pins_pci_req3),
820 GRP_MUX("req4", PCI, xrx100_pins_pci_req4),
821 GRP_MUX("mdio", MDIO, xrx100_pins_mdio),
822 GRP_MUX("dfe led0", DFE, xrx100_pins_dfe_led0),
823 GRP_MUX("dfe led1", DFE, xrx100_pins_dfe_led1),
824};
825
826static const char * const xrx100_pci_grps[] = {"gnt1", "gnt2",
827 "gnt3", "gnt4",
828 "req1", "req2",
829 "req3", "req4"};
830static const char * const xrx100_spi_grps[] = {"spi_di", "spi_do",
831 "spi_clk", "spi_cs1",
832 "spi_cs2", "spi_cs3",
833 "spi_cs4", "spi_cs5",
834 "spi_cs6"};
835static const char * const xrx100_cgu_grps[] = {"clkout0", "clkout1",
836 "clkout2", "clkout3"};
837static const char * const xrx100_ebu_grps[] = {"ebu a23", "ebu a24",
838 "ebu a25", "ebu cs1",
839 "ebu wait", "ebu clk",
840 "nand ale", "nand cs1",
841 "nand cle", "nand rdy",
842 "nand rd"};
843static const char * const xrx100_exin_grps[] = {"exin0", "exin1", "exin2",
844 "exin3", "exin4", "exin5"};
845static const char * const xrx100_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
846static const char * const xrx100_asc_grps[] = {"asc0", "asc0 cts rts"};
847static const char * const xrx100_stp_grps[] = {"stp"};
848static const char * const xrx100_nmi_grps[] = {"nmi"};
849static const char * const xrx100_mdio_grps[] = {"mdio"};
850static const char * const xrx100_dfe_grps[] = {"dfe led0", "dfe led1"};
851
852static const struct ltq_pmx_func xrx100_funcs[] = {
853 {"spi", ARRAY_AND_SIZE(xrx100_spi_grps)},
854 {"asc", ARRAY_AND_SIZE(xrx100_asc_grps)},
855 {"cgu", ARRAY_AND_SIZE(xrx100_cgu_grps)},
856 {"exin", ARRAY_AND_SIZE(xrx100_exin_grps)},
857 {"stp", ARRAY_AND_SIZE(xrx100_stp_grps)},
858 {"gpt", ARRAY_AND_SIZE(xrx100_gpt_grps)},
859 {"nmi", ARRAY_AND_SIZE(xrx100_nmi_grps)},
860 {"pci", ARRAY_AND_SIZE(xrx100_pci_grps)},
861 {"ebu", ARRAY_AND_SIZE(xrx100_ebu_grps)},
862 {"mdio", ARRAY_AND_SIZE(xrx100_mdio_grps)},
863 {"dfe", ARRAY_AND_SIZE(xrx100_dfe_grps)},
864};
865
866/* --------- xrx200 related code --------- */
867#define XRX200_MAX_PIN 50
868
869static const struct ltq_mfp_pin xrx200_mfp[] = {
870 /* pin f0 f1 f2 f3 */
871 MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM),
872 MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, SIN),
873 MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY),
874 MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI),
875 MFP_XWAY(GPIO4, GPIO, STP, DFE, USIF),
876 MFP_XWAY(GPIO5, GPIO, STP, GPHY, DFE),
877 MFP_XWAY(GPIO6, GPIO, STP, GPT, USIF),
878 MFP_XWAY(GPIO7, GPIO, CGU, CBUS, GPHY),
879 MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
880 MFP_XWAY(GPIO9, GPIO, USIF, SPI, EXIN),
881 MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
882 MFP_XWAY(GPIO11, GPIO, USIF, CBUS, SPI),
883 MFP_XWAY(GPIO12, GPIO, USIF, CBUS, MCD),
884 MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
885 MFP_XWAY(GPIO14, GPIO, CGU, CBUS, USIF),
886 MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
887 MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
888 MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
889 MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
890 MFP_XWAY(GPIO19, GPIO, PCI, SDIO, CGU),
891 MFP_XWAY(GPIO20, GPIO, NONE, SDIO, EBU),
892 MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
893 MFP_XWAY(GPIO22, GPIO, SPI, CGU, EBU),
894 MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
895 MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
896 MFP_XWAY(GPIO25, GPIO, TDM, SDIO, USIF),
897 MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO),
898 MFP_XWAY(GPIO27, GPIO, TDM, SDIO, USIF),
899 MFP_XWAY(GPIO28, GPIO, GPT, PCI, SDIO),
900 MFP_XWAY(GPIO29, GPIO, PCI, CBUS, EXIN),
901 MFP_XWAY(GPIO30, GPIO, PCI, CBUS, NONE),
902 MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
903 MFP_XWAY(GPIO32, GPIO, MII, NONE, EBU),
904 MFP_XWAY(GPIO33, GPIO, MII, NONE, EBU),
905 MFP_XWAY(GPIO34, GPIO, SIN, SSI, NONE),
906 MFP_XWAY(GPIO35, GPIO, SIN, SSI, NONE),
907 MFP_XWAY(GPIO36, GPIO, SIN, SSI, EXIN),
908 MFP_XWAY(GPIO37, GPIO, USIF, NONE, PCI),
909 MFP_XWAY(GPIO38, GPIO, PCI, USIF, NONE),
910 MFP_XWAY(GPIO39, GPIO, USIF, EXIN, NONE),
911 MFP_XWAY(GPIO40, GPIO, MII, TDM, NONE),
912 MFP_XWAY(GPIO41, GPIO, MII, TDM, NONE),
913 MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
914 MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
915 MFP_XWAY(GPIO44, GPIO, MII, SIN, GPHY),
916 MFP_XWAY(GPIO45, GPIO, MII, GPHY, SIN),
917 MFP_XWAY(GPIO46, GPIO, MII, NONE, EXIN),
918 MFP_XWAY(GPIO47, GPIO, MII, GPHY, SIN),
919 MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
920 MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
921};
922
923static const unsigned xrx200_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
924
925static const unsigned xrx200_pins_exin0[] = {GPIO0};
926static const unsigned xrx200_pins_exin1[] = {GPIO1};
927static const unsigned xrx200_pins_exin2[] = {GPIO2};
928static const unsigned xrx200_pins_exin3[] = {GPIO39};
929static const unsigned xrx200_pins_exin4[] = {GPIO10};
930static const unsigned xrx200_pins_exin5[] = {GPIO9};
931
932static const unsigned xrx200_pins_usif_uart_rx[] = {GPIO11};
933static const unsigned xrx200_pins_usif_uart_tx[] = {GPIO12};
934static const unsigned xrx200_pins_usif_uart_rts[] = {GPIO9};
935static const unsigned xrx200_pins_usif_uart_cts[] = {GPIO10};
936static const unsigned xrx200_pins_usif_uart_dtr[] = {GPIO4};
937static const unsigned xrx200_pins_usif_uart_dsr[] = {GPIO6};
938static const unsigned xrx200_pins_usif_uart_dcd[] = {GPIO25};
939static const unsigned xrx200_pins_usif_uart_ri[] = {GPIO27};
940
941static const unsigned xrx200_pins_usif_spi_di[] = {GPIO11};
942static const unsigned xrx200_pins_usif_spi_do[] = {GPIO12};
943static const unsigned xrx200_pins_usif_spi_clk[] = {GPIO38};
944static const unsigned xrx200_pins_usif_spi_cs0[] = {GPIO37};
945static const unsigned xrx200_pins_usif_spi_cs1[] = {GPIO39};
946static const unsigned xrx200_pins_usif_spi_cs2[] = {GPIO14};
947
948static const unsigned xrx200_pins_stp[] = {GPIO4, GPIO5, GPIO6};
949static const unsigned xrx200_pins_nmi[] = {GPIO8};
950static const unsigned xrx200_pins_mdio[] = {GPIO42, GPIO43};
951
952static const unsigned xrx200_pins_dfe_led0[] = {GPIO4};
953static const unsigned xrx200_pins_dfe_led1[] = {GPIO5};
954
955static const unsigned xrx200_pins_gphy0_led0[] = {GPIO5};
956static const unsigned xrx200_pins_gphy0_led1[] = {GPIO7};
957static const unsigned xrx200_pins_gphy0_led2[] = {GPIO2};
958static const unsigned xrx200_pins_gphy1_led0[] = {GPIO44};
959static const unsigned xrx200_pins_gphy1_led1[] = {GPIO45};
960static const unsigned xrx200_pins_gphy1_led2[] = {GPIO47};
961
962static const unsigned xrx200_pins_ebu_a24[] = {GPIO13};
963static const unsigned xrx200_pins_ebu_clk[] = {GPIO21};
964static const unsigned xrx200_pins_ebu_cs1[] = {GPIO23};
965static const unsigned xrx200_pins_ebu_a23[] = {GPIO24};
966static const unsigned xrx200_pins_ebu_wait[] = {GPIO26};
967static const unsigned xrx200_pins_ebu_a25[] = {GPIO31};
968
969static const unsigned xrx200_pins_nand_ale[] = {GPIO13};
970static const unsigned xrx200_pins_nand_cs1[] = {GPIO23};
971static const unsigned xrx200_pins_nand_cle[] = {GPIO24};
972static const unsigned xrx200_pins_nand_rdy[] = {GPIO48};
973static const unsigned xrx200_pins_nand_rd[] = {GPIO49};
974
975static const unsigned xrx200_pins_spi_di[] = {GPIO16};
976static const unsigned xrx200_pins_spi_do[] = {GPIO17};
977static const unsigned xrx200_pins_spi_clk[] = {GPIO18};
978static const unsigned xrx200_pins_spi_cs1[] = {GPIO15};
979static const unsigned xrx200_pins_spi_cs2[] = {GPIO22};
980static const unsigned xrx200_pins_spi_cs3[] = {GPIO13};
981static const unsigned xrx200_pins_spi_cs4[] = {GPIO10};
982static const unsigned xrx200_pins_spi_cs5[] = {GPIO9};
983static const unsigned xrx200_pins_spi_cs6[] = {GPIO11};
984
985static const unsigned xrx200_pins_gpt1[] = {GPIO28};
986static const unsigned xrx200_pins_gpt2[] = {GPIO21};
987static const unsigned xrx200_pins_gpt3[] = {GPIO6};
988
989static const unsigned xrx200_pins_clkout0[] = {GPIO8};
990static const unsigned xrx200_pins_clkout1[] = {GPIO7};
991static const unsigned xrx200_pins_clkout2[] = {GPIO3};
992static const unsigned xrx200_pins_clkout3[] = {GPIO2};
993
994static const unsigned xrx200_pins_pci_gnt1[] = {GPIO28};
995static const unsigned xrx200_pins_pci_gnt2[] = {GPIO23};
996static const unsigned xrx200_pins_pci_gnt3[] = {GPIO19};
997static const unsigned xrx200_pins_pci_gnt4[] = {GPIO38};
998static const unsigned xrx200_pins_pci_req1[] = {GPIO29};
999static const unsigned xrx200_pins_pci_req2[] = {GPIO31};
1000static const unsigned xrx200_pins_pci_req3[] = {GPIO3};
1001static const unsigned xrx200_pins_pci_req4[] = {GPIO37};
1002
1003static const struct ltq_pin_group xrx200_grps[] = {
1004 GRP_MUX("exin0", EXIN, xrx200_pins_exin0),
1005 GRP_MUX("exin1", EXIN, xrx200_pins_exin1),
1006 GRP_MUX("exin2", EXIN, xrx200_pins_exin2),
1007 GRP_MUX("exin3", EXIN, xrx200_pins_exin3),
1008 GRP_MUX("exin4", EXIN, xrx200_pins_exin4),
1009 GRP_MUX("exin5", EXIN, xrx200_pins_exin5),
1010 GRP_MUX("ebu a23", EBU, xrx200_pins_ebu_a23),
1011 GRP_MUX("ebu a24", EBU, xrx200_pins_ebu_a24),
1012 GRP_MUX("ebu a25", EBU, xrx200_pins_ebu_a25),
1013 GRP_MUX("ebu clk", EBU, xrx200_pins_ebu_clk),
1014 GRP_MUX("ebu cs1", EBU, xrx200_pins_ebu_cs1),
1015 GRP_MUX("ebu wait", EBU, xrx200_pins_ebu_wait),
1016 GRP_MUX("nand ale", EBU, xrx200_pins_nand_ale),
1017 GRP_MUX("nand cs1", EBU, xrx200_pins_nand_cs1),
1018 GRP_MUX("nand cle", EBU, xrx200_pins_nand_cle),
1019 GRP_MUX("nand rdy", EBU, xrx200_pins_nand_rdy),
1020 GRP_MUX("nand rd", EBU, xrx200_pins_nand_rd),
1021 GRP_MUX("spi_di", SPI, xrx200_pins_spi_di),
1022 GRP_MUX("spi_do", SPI, xrx200_pins_spi_do),
1023 GRP_MUX("spi_clk", SPI, xrx200_pins_spi_clk),
1024 GRP_MUX("spi_cs1", SPI, xrx200_pins_spi_cs1),
1025 GRP_MUX("spi_cs2", SPI, xrx200_pins_spi_cs2),
1026 GRP_MUX("spi_cs3", SPI, xrx200_pins_spi_cs3),
1027 GRP_MUX("spi_cs4", SPI, xrx200_pins_spi_cs4),
1028 GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5),
1029 GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6),
1030 GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_rx),
1031 GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_tx),
1032 GRP_MUX("usif uart_rts", USIF, xrx200_pins_usif_uart_rts),
1033 GRP_MUX("usif uart_cts", USIF, xrx200_pins_usif_uart_cts),
1034 GRP_MUX("usif uart_dtr", USIF, xrx200_pins_usif_uart_dtr),
1035 GRP_MUX("usif uart_dsr", USIF, xrx200_pins_usif_uart_dsr),
1036 GRP_MUX("usif uart_dcd", USIF, xrx200_pins_usif_uart_dcd),
1037 GRP_MUX("usif uart_ri", USIF, xrx200_pins_usif_uart_ri),
1038 GRP_MUX("usif spi_di", USIF, xrx200_pins_usif_spi_di),
1039 GRP_MUX("usif spi_do", USIF, xrx200_pins_usif_spi_do),
1040 GRP_MUX("usif spi_clk", USIF, xrx200_pins_usif_spi_clk),
1041 GRP_MUX("usif spi_cs0", USIF, xrx200_pins_usif_spi_cs0),
1042 GRP_MUX("usif spi_cs1", USIF, xrx200_pins_usif_spi_cs1),
1043 GRP_MUX("usif spi_cs2", USIF, xrx200_pins_usif_spi_cs2),
1044 GRP_MUX("stp", STP, xrx200_pins_stp),
1045 GRP_MUX("nmi", NMI, xrx200_pins_nmi),
1046 GRP_MUX("gpt1", GPT, xrx200_pins_gpt1),
1047 GRP_MUX("gpt2", GPT, xrx200_pins_gpt2),
1048 GRP_MUX("gpt3", GPT, xrx200_pins_gpt3),
1049 GRP_MUX("clkout0", CGU, xrx200_pins_clkout0),
1050 GRP_MUX("clkout1", CGU, xrx200_pins_clkout1),
1051 GRP_MUX("clkout2", CGU, xrx200_pins_clkout2),
1052 GRP_MUX("clkout3", CGU, xrx200_pins_clkout3),
1053 GRP_MUX("gnt1", PCI, xrx200_pins_pci_gnt1),
1054 GRP_MUX("gnt2", PCI, xrx200_pins_pci_gnt2),
1055 GRP_MUX("gnt3", PCI, xrx200_pins_pci_gnt3),
1056 GRP_MUX("gnt4", PCI, xrx200_pins_pci_gnt4),
1057 GRP_MUX("req1", PCI, xrx200_pins_pci_req1),
1058 GRP_MUX("req2", PCI, xrx200_pins_pci_req2),
1059 GRP_MUX("req3", PCI, xrx200_pins_pci_req3),
1060 GRP_MUX("req4", PCI, xrx200_pins_pci_req4),
1061 GRP_MUX("mdio", MDIO, xrx200_pins_mdio),
1062 GRP_MUX("dfe led0", DFE, xrx200_pins_dfe_led0),
1063 GRP_MUX("dfe led1", DFE, xrx200_pins_dfe_led1),
1064 GRP_MUX("gphy0 led0", GPHY, xrx200_pins_gphy0_led0),
1065 GRP_MUX("gphy0 led1", GPHY, xrx200_pins_gphy0_led1),
1066 GRP_MUX("gphy0 led2", GPHY, xrx200_pins_gphy0_led2),
1067 GRP_MUX("gphy1 led0", GPHY, xrx200_pins_gphy1_led0),
1068 GRP_MUX("gphy1 led1", GPHY, xrx200_pins_gphy1_led1),
1069 GRP_MUX("gphy1 led2", GPHY, xrx200_pins_gphy1_led2),
1070};
1071
1072static const char * const xrx200_pci_grps[] = {"gnt1", "gnt2",
1073 "gnt3", "gnt4",
1074 "req1", "req2",
1075 "req3", "req4"};
1076static const char * const xrx200_spi_grps[] = {"spi_di", "spi_do",
1077 "spi_clk", "spi_cs1",
1078 "spi_cs2", "spi_cs3",
1079 "spi_cs4", "spi_cs5",
1080 "spi_cs6"};
1081static const char * const xrx200_cgu_grps[] = {"clkout0", "clkout1",
1082 "clkout2", "clkout3"};
1083static const char * const xrx200_ebu_grps[] = {"ebu a23", "ebu a24",
1084 "ebu a25", "ebu cs1",
1085 "ebu wait", "ebu clk",
1086 "nand ale", "nand cs1",
1087 "nand cle", "nand rdy",
1088 "nand rd"};
1089static const char * const xrx200_exin_grps[] = {"exin0", "exin1", "exin2",
1090 "exin3", "exin4", "exin5"};
1091static const char * const xrx200_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
1092static const char * const xrx200_usif_grps[] = {"usif uart_rx", "usif uart_tx",
1093 "usif uart_rts", "usif uart_cts",
1094 "usif uart_dtr", "usif uart_dsr",
1095 "usif uart_dcd", "usif uart_ri",
1096 "usif spi_di", "usif spi_do",
1097 "usif spi_clk", "usif spi_cs0",
1098 "usif spi_cs1", "usif spi_cs2"};
1099static const char * const xrx200_stp_grps[] = {"stp"};
1100static const char * const xrx200_nmi_grps[] = {"nmi"};
1101static const char * const xrx200_mdio_grps[] = {"mdio"};
1102static const char * const xrx200_dfe_grps[] = {"dfe led0", "dfe led1"};
1103static const char * const xrx200_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
1104 "gphy0 led2", "gphy1 led0",
1105 "gphy1 led1", "gphy1 led2"};
1106
1107static const struct ltq_pmx_func xrx200_funcs[] = {
1108 {"spi", ARRAY_AND_SIZE(xrx200_spi_grps)},
1109 {"usif", ARRAY_AND_SIZE(xrx200_usif_grps)},
1110 {"cgu", ARRAY_AND_SIZE(xrx200_cgu_grps)},
1111 {"exin", ARRAY_AND_SIZE(xrx200_exin_grps)},
1112 {"stp", ARRAY_AND_SIZE(xrx200_stp_grps)},
1113 {"gpt", ARRAY_AND_SIZE(xrx200_gpt_grps)},
1114 {"nmi", ARRAY_AND_SIZE(xrx200_nmi_grps)},
1115 {"pci", ARRAY_AND_SIZE(xrx200_pci_grps)},
1116 {"ebu", ARRAY_AND_SIZE(xrx200_ebu_grps)},
1117 {"mdio", ARRAY_AND_SIZE(xrx200_mdio_grps)},
1118 {"dfe", ARRAY_AND_SIZE(xrx200_dfe_grps)},
1119 {"gphy", ARRAY_AND_SIZE(xrx200_gphy_grps)},
1120};
1121
1122/* --------- xrx300 related code --------- */
1123#define XRX300_MAX_PIN 64
1124
1125static const struct ltq_mfp_pin xrx300_mfp[] = {
1126 /* pin f0 f1 f2 f3 */
1127 MFP_XWAY(GPIO0, GPIO, EXIN, EPHY, NONE),
1128 MFP_XWAY(GPIO1, GPIO, NONE, EXIN, NONE),
1129 MFP_XWAY(GPIO2, NONE, NONE, NONE, NONE),
1130 MFP_XWAY(GPIO3, GPIO, CGU, NONE, NONE),
1131 MFP_XWAY(GPIO4, GPIO, STP, DFE, NONE),
1132 MFP_XWAY(GPIO5, GPIO, STP, EPHY, DFE),
1133 MFP_XWAY(GPIO6, GPIO, STP, NONE, NONE),
1134 MFP_XWAY(GPIO7, NONE, NONE, NONE, NONE),
1135 MFP_XWAY(GPIO8, GPIO, CGU, GPHY, EPHY),
1136 MFP_XWAY(GPIO9, GPIO, WIFI, NONE, EXIN),
1137 MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
1138 MFP_XWAY(GPIO11, GPIO, USIF, WIFI, SPI),
1139 MFP_XWAY(GPIO12, NONE, NONE, NONE, NONE),
1140 MFP_XWAY(GPIO13, GPIO, EBU, NONE, NONE),
1141 MFP_XWAY(GPIO14, GPIO, CGU, USIF, EPHY),
1142 MFP_XWAY(GPIO15, GPIO, SPI, NONE, MCD),
1143 MFP_XWAY(GPIO16, GPIO, SPI, EXIN, NONE),
1144 MFP_XWAY(GPIO17, GPIO, SPI, NONE, NONE),
1145 MFP_XWAY(GPIO18, GPIO, SPI, NONE, NONE),
1146 MFP_XWAY(GPIO19, GPIO, USIF, NONE, EPHY),
1147 MFP_XWAY(GPIO20, NONE, NONE, NONE, NONE),
1148 MFP_XWAY(GPIO21, NONE, NONE, NONE, NONE),
1149 MFP_XWAY(GPIO22, NONE, NONE, NONE, NONE),
1150 MFP_XWAY(GPIO23, GPIO, EBU, NONE, NONE),
1151 MFP_XWAY(GPIO24, GPIO, EBU, NONE, NONE),
1152 MFP_XWAY(GPIO25, GPIO, TDM, NONE, NONE),
1153 MFP_XWAY(GPIO26, GPIO, TDM, NONE, NONE),
1154 MFP_XWAY(GPIO27, GPIO, TDM, NONE, NONE),
1155 MFP_XWAY(GPIO28, NONE, NONE, NONE, NONE),
1156 MFP_XWAY(GPIO29, NONE, NONE, NONE, NONE),
1157 MFP_XWAY(GPIO30, NONE, NONE, NONE, NONE),
1158 MFP_XWAY(GPIO31, NONE, NONE, NONE, NONE),
1159 MFP_XWAY(GPIO32, NONE, NONE, NONE, NONE),
1160 MFP_XWAY(GPIO33, NONE, NONE, NONE, NONE),
1161 MFP_XWAY(GPIO34, GPIO, NONE, SSI, NONE),
1162 MFP_XWAY(GPIO35, GPIO, NONE, SSI, NONE),
1163 MFP_XWAY(GPIO36, GPIO, NONE, SSI, NONE),
1164 MFP_XWAY(GPIO37, NONE, NONE, NONE, NONE),
1165 MFP_XWAY(GPIO38, NONE, NONE, NONE, NONE),
1166 MFP_XWAY(GPIO39, NONE, NONE, NONE, NONE),
1167 MFP_XWAY(GPIO40, NONE, NONE, NONE, NONE),
1168 MFP_XWAY(GPIO41, NONE, NONE, NONE, NONE),
1169 MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
1170 MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
1171 MFP_XWAY(GPIO44, NONE, NONE, NONE, NONE),
1172 MFP_XWAY(GPIO45, NONE, NONE, NONE, NONE),
1173 MFP_XWAY(GPIO46, NONE, NONE, NONE, NONE),
1174 MFP_XWAY(GPIO47, NONE, NONE, NONE, NONE),
1175 MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
1176 MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
1177 MFP_XWAY(GPIO50, GPIO, EBU, NONE, NONE),
1178 MFP_XWAY(GPIO51, GPIO, EBU, NONE, NONE),
1179 MFP_XWAY(GPIO52, GPIO, EBU, NONE, NONE),
1180 MFP_XWAY(GPIO53, GPIO, EBU, NONE, NONE),
1181 MFP_XWAY(GPIO54, GPIO, EBU, NONE, NONE),
1182 MFP_XWAY(GPIO55, GPIO, EBU, NONE, NONE),
1183 MFP_XWAY(GPIO56, GPIO, EBU, NONE, NONE),
1184 MFP_XWAY(GPIO57, GPIO, EBU, NONE, NONE),
1185 MFP_XWAY(GPIO58, GPIO, EBU, TDM, NONE),
1186 MFP_XWAY(GPIO59, GPIO, EBU, NONE, NONE),
1187 MFP_XWAY(GPIO60, GPIO, EBU, NONE, NONE),
1188 MFP_XWAY(GPIO61, GPIO, EBU, NONE, NONE),
1189 MFP_XWAY(GPIO62, NONE, NONE, NONE, NONE),
1190 MFP_XWAY(GPIO63, NONE, NONE, NONE, NONE),
1191};
1192
1193static const unsigned xrx300_exin_pin_map[] = {GPIO0, GPIO1, GPIO16, GPIO10, GPIO9};
1194
1195static const unsigned xrx300_pins_exin0[] = {GPIO0};
1196static const unsigned xrx300_pins_exin1[] = {GPIO1};
1197static const unsigned xrx300_pins_exin2[] = {GPIO16};
1198/* EXIN3 is not available on xrX300 */
1199static const unsigned xrx300_pins_exin4[] = {GPIO10};
1200static const unsigned xrx300_pins_exin5[] = {GPIO9};
1201
1202static const unsigned xrx300_pins_usif_uart_rx[] = {GPIO11};
1203static const unsigned xrx300_pins_usif_uart_tx[] = {GPIO10};
1204
1205static const unsigned xrx300_pins_usif_spi_di[] = {GPIO11};
1206static const unsigned xrx300_pins_usif_spi_do[] = {GPIO10};
1207static const unsigned xrx300_pins_usif_spi_clk[] = {GPIO19};
1208static const unsigned xrx300_pins_usif_spi_cs0[] = {GPIO14};
1209
1210static const unsigned xrx300_pins_stp[] = {GPIO4, GPIO5, GPIO6};
1211static const unsigned xrx300_pins_mdio[] = {GPIO42, GPIO43};
1212
1213static const unsigned xrx300_pins_dfe_led0[] = {GPIO4};
1214static const unsigned xrx300_pins_dfe_led1[] = {GPIO5};
1215
1216static const unsigned xrx300_pins_ephy0_led0[] = {GPIO5};
1217static const unsigned xrx300_pins_ephy0_led1[] = {GPIO8};
1218static const unsigned xrx300_pins_ephy1_led0[] = {GPIO14};
1219static const unsigned xrx300_pins_ephy1_led1[] = {GPIO19};
1220
1221static const unsigned xrx300_pins_nand_ale[] = {GPIO13};
1222static const unsigned xrx300_pins_nand_cs1[] = {GPIO23};
1223static const unsigned xrx300_pins_nand_cle[] = {GPIO24};
1224static const unsigned xrx300_pins_nand_rdy[] = {GPIO48};
1225static const unsigned xrx300_pins_nand_rd[] = {GPIO49};
1226static const unsigned xrx300_pins_nand_d1[] = {GPIO50};
1227static const unsigned xrx300_pins_nand_d0[] = {GPIO51};
1228static const unsigned xrx300_pins_nand_d2[] = {GPIO52};
1229static const unsigned xrx300_pins_nand_d7[] = {GPIO53};
1230static const unsigned xrx300_pins_nand_d6[] = {GPIO54};
1231static const unsigned xrx300_pins_nand_d5[] = {GPIO55};
1232static const unsigned xrx300_pins_nand_d4[] = {GPIO56};
1233static const unsigned xrx300_pins_nand_d3[] = {GPIO57};
1234static const unsigned xrx300_pins_nand_cs0[] = {GPIO58};
1235static const unsigned xrx300_pins_nand_wr[] = {GPIO59};
1236static const unsigned xrx300_pins_nand_wp[] = {GPIO60};
1237static const unsigned xrx300_pins_nand_se[] = {GPIO61};
1238
1239static const unsigned xrx300_pins_spi_di[] = {GPIO16};
1240static const unsigned xrx300_pins_spi_do[] = {GPIO17};
1241static const unsigned xrx300_pins_spi_clk[] = {GPIO18};
1242static const unsigned xrx300_pins_spi_cs1[] = {GPIO15};
1243/* SPI_CS2 is not available on xrX300 */
1244/* SPI_CS3 is not available on xrX300 */
1245static const unsigned xrx300_pins_spi_cs4[] = {GPIO10};
1246/* SPI_CS5 is not available on xrX300 */
1247static const unsigned xrx300_pins_spi_cs6[] = {GPIO11};
1248
1249/* CLKOUT0 is not available on xrX300 */
1250/* CLKOUT1 is not available on xrX300 */
1251static const unsigned xrx300_pins_clkout2[] = {GPIO3};
1252
1253static const struct ltq_pin_group xrx300_grps[] = {
1254 GRP_MUX("exin0", EXIN, xrx300_pins_exin0),
1255 GRP_MUX("exin1", EXIN, xrx300_pins_exin1),
1256 GRP_MUX("exin2", EXIN, xrx300_pins_exin2),
1257 GRP_MUX("exin4", EXIN, xrx300_pins_exin4),
1258 GRP_MUX("exin5", EXIN, xrx300_pins_exin5),
1259 GRP_MUX("nand ale", EBU, xrx300_pins_nand_ale),
1260 GRP_MUX("nand cs1", EBU, xrx300_pins_nand_cs1),
1261 GRP_MUX("nand cle", EBU, xrx300_pins_nand_cle),
1262 GRP_MUX("nand rdy", EBU, xrx300_pins_nand_rdy),
1263 GRP_MUX("nand rd", EBU, xrx300_pins_nand_rd),
1264 GRP_MUX("nand d1", EBU, xrx300_pins_nand_d1),
1265 GRP_MUX("nand d0", EBU, xrx300_pins_nand_d0),
1266 GRP_MUX("nand d2", EBU, xrx300_pins_nand_d2),
1267 GRP_MUX("nand d7", EBU, xrx300_pins_nand_d7),
1268 GRP_MUX("nand d6", EBU, xrx300_pins_nand_d6),
1269 GRP_MUX("nand d5", EBU, xrx300_pins_nand_d5),
1270 GRP_MUX("nand d4", EBU, xrx300_pins_nand_d4),
1271 GRP_MUX("nand d3", EBU, xrx300_pins_nand_d3),
1272 GRP_MUX("nand cs0", EBU, xrx300_pins_nand_cs0),
1273 GRP_MUX("nand wr", EBU, xrx300_pins_nand_wr),
1274 GRP_MUX("nand wp", EBU, xrx300_pins_nand_wp),
1275 GRP_MUX("nand se", EBU, xrx300_pins_nand_se),
1276 GRP_MUX("spi_di", SPI, xrx300_pins_spi_di),
1277 GRP_MUX("spi_do", SPI, xrx300_pins_spi_do),
1278 GRP_MUX("spi_clk", SPI, xrx300_pins_spi_clk),
1279 GRP_MUX("spi_cs1", SPI, xrx300_pins_spi_cs1),
1280 GRP_MUX("spi_cs4", SPI, xrx300_pins_spi_cs4),
1281 GRP_MUX("spi_cs6", SPI, xrx300_pins_spi_cs6),
1282 GRP_MUX("usif uart_rx", USIF, xrx300_pins_usif_uart_rx),
1283 GRP_MUX("usif uart_tx", USIF, xrx300_pins_usif_uart_tx),
1284 GRP_MUX("usif spi_di", USIF, xrx300_pins_usif_spi_di),
1285 GRP_MUX("usif spi_do", USIF, xrx300_pins_usif_spi_do),
1286 GRP_MUX("usif spi_clk", USIF, xrx300_pins_usif_spi_clk),
1287 GRP_MUX("usif spi_cs0", USIF, xrx300_pins_usif_spi_cs0),
1288 GRP_MUX("stp", STP, xrx300_pins_stp),
1289 GRP_MUX("clkout2", CGU, xrx300_pins_clkout2),
1290 GRP_MUX("mdio", MDIO, xrx300_pins_mdio),
1291 GRP_MUX("dfe led0", DFE, xrx300_pins_dfe_led0),
1292 GRP_MUX("dfe led1", DFE, xrx300_pins_dfe_led1),
1293 GRP_MUX("ephy0 led0", GPHY, xrx300_pins_ephy0_led0),
1294 GRP_MUX("ephy0 led1", GPHY, xrx300_pins_ephy0_led1),
1295 GRP_MUX("ephy1 led0", GPHY, xrx300_pins_ephy1_led0),
1296 GRP_MUX("ephy1 led1", GPHY, xrx300_pins_ephy1_led1),
1297};
1298
1299static const char * const xrx300_spi_grps[] = {"spi_di", "spi_do",
1300 "spi_clk", "spi_cs1",
1301 "spi_cs4", "spi_cs6"};
1302static const char * const xrx300_cgu_grps[] = {"clkout2"};
1303static const char * const xrx300_ebu_grps[] = {"nand ale", "nand cs1",
1304 "nand cle", "nand rdy",
1305 "nand rd", "nand d1",
1306 "nand d0", "nand d2",
1307 "nand d7", "nand d6",
1308 "nand d5", "nand d4",
1309 "nand d3", "nand cs0",
1310 "nand wr", "nand wp",
1311 "nand se"};
1312static const char * const xrx300_exin_grps[] = {"exin0", "exin1", "exin2",
1313 "exin4", "exin5"};
1314static const char * const xrx300_usif_grps[] = {"usif uart_rx", "usif uart_tx",
1315 "usif spi_di", "usif spi_do",
1316 "usif spi_clk", "usif spi_cs0"};
1317static const char * const xrx300_stp_grps[] = {"stp"};
1318static const char * const xrx300_mdio_grps[] = {"mdio"};
1319static const char * const xrx300_dfe_grps[] = {"dfe led0", "dfe led1"};
1320static const char * const xrx300_gphy_grps[] = {"ephy0 led0", "ephy0 led1",
1321 "ephy1 led0", "ephy1 led1"};
1322
1323static const struct ltq_pmx_func xrx300_funcs[] = {
1324 {"spi", ARRAY_AND_SIZE(xrx300_spi_grps)},
1325 {"usif", ARRAY_AND_SIZE(xrx300_usif_grps)},
1326 {"cgu", ARRAY_AND_SIZE(xrx300_cgu_grps)},
1327 {"exin", ARRAY_AND_SIZE(xrx300_exin_grps)},
1328 {"stp", ARRAY_AND_SIZE(xrx300_stp_grps)},
1329 {"ebu", ARRAY_AND_SIZE(xrx300_ebu_grps)},
1330 {"mdio", ARRAY_AND_SIZE(xrx300_mdio_grps)},
1331 {"dfe", ARRAY_AND_SIZE(xrx300_dfe_grps)},
1332 {"ephy", ARRAY_AND_SIZE(xrx300_gphy_grps)},
1333};
1334
448/* --------- pinconf related code --------- */ 1335/* --------- pinconf related code --------- */
449static int xway_pinconf_get(struct pinctrl_dev *pctldev, 1336static int xway_pinconf_get(struct pinctrl_dev *pctldev,
450 unsigned pin, 1337 unsigned pin,
@@ -695,10 +1582,7 @@ static struct gpio_chip xway_chip = {
695 1582
696 1583
697/* --------- register the pinctrl layer --------- */ 1584/* --------- register the pinctrl layer --------- */
698static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9}; 1585struct pinctrl_xway_soc {
699static const unsigned ase_exin_pins_map[] = {GPIO6, GPIO29, GPIO0};
700
701static struct pinctrl_xway_soc {
702 int pin_count; 1586 int pin_count;
703 const struct ltq_mfp_pin *mfp; 1587 const struct ltq_mfp_pin *mfp;
704 const struct ltq_pin_group *grps; 1588 const struct ltq_pin_group *grps;
@@ -707,22 +1591,54 @@ static struct pinctrl_xway_soc {
707 unsigned int num_funcs; 1591 unsigned int num_funcs;
708 const unsigned *exin; 1592 const unsigned *exin;
709 unsigned int num_exin; 1593 unsigned int num_exin;
710} soc_cfg[] = { 1594};
711 /* legacy xway */ 1595
712 {XWAY_MAX_PIN, xway_mfp, 1596/* xway xr9 series (DEPRECATED: Use XWAY xRX100/xRX200 Family) */
713 xway_grps, ARRAY_SIZE(xway_grps), 1597static struct pinctrl_xway_soc xr9_pinctrl = {
714 danube_funcs, ARRAY_SIZE(danube_funcs), 1598 XR9_MAX_PIN, xway_mfp,
715 xway_exin_pin_map, 3}, 1599 xway_grps, ARRAY_SIZE(xway_grps),
716 /* xway xr9 series */ 1600 xrx_funcs, ARRAY_SIZE(xrx_funcs),
717 {XR9_MAX_PIN, xway_mfp, 1601 xway_exin_pin_map, 6
718 xway_grps, ARRAY_SIZE(xway_grps), 1602};
719 xrx_funcs, ARRAY_SIZE(xrx_funcs), 1603
720 xway_exin_pin_map, 6}, 1604/* XWAY AMAZON Family */
721 /* xway ase series */ 1605static struct pinctrl_xway_soc ase_pinctrl = {
722 {XWAY_MAX_PIN, ase_mfp, 1606 ASE_MAX_PIN, ase_mfp,
723 ase_grps, ARRAY_SIZE(ase_grps), 1607 ase_grps, ARRAY_SIZE(ase_grps),
724 ase_funcs, ARRAY_SIZE(ase_funcs), 1608 ase_funcs, ARRAY_SIZE(ase_funcs),
725 ase_exin_pins_map, 3}, 1609 ase_exin_pin_map, 3
1610};
1611
1612/* XWAY DANUBE Family */
1613static struct pinctrl_xway_soc danube_pinctrl = {
1614 DANUBE_MAX_PIN, danube_mfp,
1615 danube_grps, ARRAY_SIZE(danube_grps),
1616 danube_funcs, ARRAY_SIZE(danube_funcs),
1617 danube_exin_pin_map, 3
1618};
1619
1620/* XWAY xRX100 Family */
1621static struct pinctrl_xway_soc xrx100_pinctrl = {
1622 XRX100_MAX_PIN, xrx100_mfp,
1623 xrx100_grps, ARRAY_SIZE(xrx100_grps),
1624 xrx100_funcs, ARRAY_SIZE(xrx100_funcs),
1625 xrx100_exin_pin_map, 6
1626};
1627
1628/* XWAY xRX200 Family */
1629static struct pinctrl_xway_soc xrx200_pinctrl = {
1630 XRX200_MAX_PIN, xrx200_mfp,
1631 xrx200_grps, ARRAY_SIZE(xrx200_grps),
1632 xrx200_funcs, ARRAY_SIZE(xrx200_funcs),
1633 xrx200_exin_pin_map, 6
1634};
1635
1636/* XWAY xRX300 Family */
1637static struct pinctrl_xway_soc xrx300_pinctrl = {
1638 XRX300_MAX_PIN, xrx300_mfp,
1639 xrx300_grps, ARRAY_SIZE(xrx300_grps),
1640 xrx300_funcs, ARRAY_SIZE(xrx300_funcs),
1641 xrx300_exin_pin_map, 5
726}; 1642};
727 1643
728static struct pinctrl_gpio_range xway_gpio_range = { 1644static struct pinctrl_gpio_range xway_gpio_range = {
@@ -731,9 +1647,14 @@ static struct pinctrl_gpio_range xway_gpio_range = {
731}; 1647};
732 1648
733static const struct of_device_id xway_match[] = { 1649static const struct of_device_id xway_match[] = {
734 { .compatible = "lantiq,pinctrl-xway", .data = &soc_cfg[0]}, 1650 { .compatible = "lantiq,pinctrl-xway", .data = &danube_pinctrl}, /*DEPRECATED*/
735 { .compatible = "lantiq,pinctrl-xr9", .data = &soc_cfg[1]}, 1651 { .compatible = "lantiq,pinctrl-xr9", .data = &xr9_pinctrl}, /*DEPRECATED*/
736 { .compatible = "lantiq,pinctrl-ase", .data = &soc_cfg[2]}, 1652 { .compatible = "lantiq,pinctrl-ase", .data = &ase_pinctrl}, /*DEPRECATED*/
1653 { .compatible = "lantiq,ase-pinctrl", .data = &ase_pinctrl},
1654 { .compatible = "lantiq,danube-pinctrl", .data = &danube_pinctrl},
1655 { .compatible = "lantiq,xrx100-pinctrl", .data = &xrx100_pinctrl},
1656 { .compatible = "lantiq,xrx200-pinctrl", .data = &xrx200_pinctrl},
1657 { .compatible = "lantiq,xrx300-pinctrl", .data = &xrx300_pinctrl},
737 {}, 1658 {},
738}; 1659};
739MODULE_DEVICE_TABLE(of, xway_match); 1660MODULE_DEVICE_TABLE(of, xway_match);
@@ -755,7 +1676,7 @@ static int pinmux_xway_probe(struct platform_device *pdev)
755 if (match) 1676 if (match)
756 xway_soc = (const struct pinctrl_xway_soc *) match->data; 1677 xway_soc = (const struct pinctrl_xway_soc *) match->data;
757 else 1678 else
758 xway_soc = &soc_cfg[0]; 1679 xway_soc = &danube_pinctrl;
759 1680
760 /* find out how many pads we have */ 1681 /* find out how many pads we have */
761 xway_chip.ngpio = xway_soc->pin_count; 1682 xway_chip.ngpio = xway_soc->pin_count;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-03 23:31:55 -0500