pinctrl: tegra: add support for rcv-sel and drive type

NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e.
rcv-sel and drive type.

rcv-sel: Select between High and Normal VIL/VIH receivers.
	RCVR_SEL=1: High VIL/VIH
	RCVR_SEL=0: Normal VIL/VIH

drv_type: Ouptput drive type:
	33-50 ohm driver: 0x1
	66-100ohm driver: 0x0

Add support of these parameters to be configure from DTS file.

Tegra20 and Tegra30 does not support this configuration and hence initialize their
pinmux structure with reg = -1.

Originally written by Pritesh Raithatha.
Changes by ldewangan:
	- remove drvtype_width as it is always 2.
	- Better describe the change.

Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

1 files changed, 6 insertions, 0 deletions

diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index e848189038f0..fcfb7d012c5b 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -2624,7 +2624,9 @@ static const struct tegra_function tegra20_functions[] = {
                 .odrain_reg = -1,                               \
                 .lock_reg = -1,                                 \
                 .ioreset_reg = -1,                              \
+                .rcv_sel_reg = -1,                              \
                 .drv_reg = -1,                                  \
+                .drvtype_reg = -1,                              \
         }
 
 /* Pin groups with only pull up and pull down control */
@@ -2642,7 +2644,9 @@ static const struct tegra_function tegra20_functions[] = {
                 .odrain_reg = -1,                               \
                 .lock_reg = -1,                                 \
                 .ioreset_reg = -1,                              \
+                .rcv_sel_reg = -1,                              \
                 .drv_reg = -1,                                  \
+                .drvtype_reg = -1,                              \
         }
 
 /* Pin groups for drive strength registers (configurable version) */
@@ -2660,6 +2664,7 @@ static const struct tegra_function tegra20_functions[] = {
                 .odrain_reg = -1,                               \
                 .lock_reg = -1,                                 \
                 .ioreset_reg = -1,                              \
+                .rcv_sel_reg = -1,                              \
                 .drv_reg = ((r) - PINGROUP_REG_A),              \
                 .drv_bank = 3,                                  \
                 .hsm_bit = hsm_b,                               \
@@ -2673,6 +2678,7 @@ static const struct tegra_function tegra20_functions[] = {
                 .slwr_width = slwr_w,                           \
                 .slwf_bit = slwf_b,                             \
                 .slwf_width = slwf_w,                           \
+                .drvtype_reg = -1,                              \
         }
 
 /* Pin groups for drive strength registers (simple version) */