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authorNeil Armstrong <narmstrong@baylibre.com>2016-10-04 09:41:46 -0400
committerLinus Walleij <linus.walleij@linaro.org>2016-10-24 10:30:14 -0400
commit93f889b9657ff541417f498c2ee0f69775fe3cef (patch)
treeaf96dd803f9d34f0dcdcaa8a402d331cb60b55b6 /drivers/pinctrl/pinctrl-oxnas.c
parent07fe64ba213f36ca8f6ffd8c4d5893f022744fdb (diff)
pinctrl: oxnas: Move OX810SE specific function and structure as separate
Add refactoring to move ox810se specific functions into specific ops structures an add support for the dt match data to get soc specific structures. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-oxnas.c')
-rw-r--r--drivers/pinctrl/pinctrl-oxnas.c176
1 files changed, 101 insertions, 75 deletions
diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c
index 917a7d2535d7..218ad48f455a 100644
--- a/drivers/pinctrl/pinctrl-oxnas.c
+++ b/drivers/pinctrl/pinctrl-oxnas.c
@@ -37,15 +37,15 @@
37 37
38#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK) 38#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK)
39 39
40/* Regmap Offsets */ 40/* OX810 Regmap Offsets */
41#define PINMUX_PRIMARY_SEL0 0x0c 41#define PINMUX_810_PRIMARY_SEL0 0x0c
42#define PINMUX_SECONDARY_SEL0 0x14 42#define PINMUX_810_SECONDARY_SEL0 0x14
43#define PINMUX_TERTIARY_SEL0 0x8c 43#define PINMUX_810_TERTIARY_SEL0 0x8c
44#define PINMUX_PRIMARY_SEL1 0x10 44#define PINMUX_810_PRIMARY_SEL1 0x10
45#define PINMUX_SECONDARY_SEL1 0x18 45#define PINMUX_810_SECONDARY_SEL1 0x18
46#define PINMUX_TERTIARY_SEL1 0x90 46#define PINMUX_810_TERTIARY_SEL1 0x90
47#define PINMUX_PULLUP_CTRL0 0xac 47#define PINMUX_810_PULLUP_CTRL0 0xac
48#define PINMUX_PULLUP_CTRL1 0xb0 48#define PINMUX_810_PULLUP_CTRL1 0xb0
49 49
50/* GPIO Registers */ 50/* GPIO Registers */
51#define INPUT_VALUE 0x00 51#define INPUT_VALUE 0x00
@@ -87,8 +87,6 @@ struct oxnas_pinctrl {
87 struct regmap *regmap; 87 struct regmap *regmap;
88 struct device *dev; 88 struct device *dev;
89 struct pinctrl_dev *pctldev; 89 struct pinctrl_dev *pctldev;
90 const struct pinctrl_pin_desc *pins;
91 unsigned int npins;
92 const struct oxnas_function *functions; 90 const struct oxnas_function *functions;
93 unsigned int nfunctions; 91 unsigned int nfunctions;
94 const struct oxnas_pin_group *groups; 92 const struct oxnas_pin_group *groups;
@@ -97,7 +95,12 @@ struct oxnas_pinctrl {
97 unsigned int nbanks; 95 unsigned int nbanks;
98}; 96};
99 97
100static const struct pinctrl_pin_desc oxnas_pins[] = { 98struct oxnas_pinctrl_data {
99 struct pinctrl_desc *desc;
100 struct oxnas_pinctrl *pctl;
101};
102
103static const struct pinctrl_pin_desc oxnas_ox810se_pins[] = {
101 PINCTRL_PIN(0, "gpio0"), 104 PINCTRL_PIN(0, "gpio0"),
102 PINCTRL_PIN(1, "gpio1"), 105 PINCTRL_PIN(1, "gpio1"),
103 PINCTRL_PIN(2, "gpio2"), 106 PINCTRL_PIN(2, "gpio2"),
@@ -135,7 +138,7 @@ static const struct pinctrl_pin_desc oxnas_pins[] = {
135 PINCTRL_PIN(34, "gpio34"), 138 PINCTRL_PIN(34, "gpio34"),
136}; 139};
137 140
138static const char * const oxnas_fct0_group[] = { 141static const char * const oxnas_ox810se_fct0_group[] = {
139 "gpio0", "gpio1", "gpio2", "gpio3", 142 "gpio0", "gpio1", "gpio2", "gpio3",
140 "gpio4", "gpio5", "gpio6", "gpio7", 143 "gpio4", "gpio5", "gpio6", "gpio7",
141 "gpio8", "gpio9", "gpio10", "gpio11", 144 "gpio8", "gpio9", "gpio10", "gpio11",
@@ -147,7 +150,7 @@ static const char * const oxnas_fct0_group[] = {
147 "gpio32", "gpio33", "gpio34" 150 "gpio32", "gpio33", "gpio34"
148}; 151};
149 152
150static const char * const oxnas_fct3_group[] = { 153static const char * const oxnas_ox810se_fct3_group[] = {
151 "gpio0", "gpio1", "gpio2", "gpio3", 154 "gpio0", "gpio1", "gpio2", "gpio3",
152 "gpio4", "gpio5", "gpio6", "gpio7", 155 "gpio4", "gpio5", "gpio6", "gpio7",
153 "gpio8", "gpio9", 156 "gpio8", "gpio9",
@@ -165,9 +168,9 @@ static const char * const oxnas_fct3_group[] = {
165 .ngroups = ARRAY_SIZE(oxnas_##_gr##_group), \ 168 .ngroups = ARRAY_SIZE(oxnas_##_gr##_group), \
166 } 169 }
167 170
168static const struct oxnas_function oxnas_functions[] = { 171static const struct oxnas_function oxnas_ox810se_functions[] = {
169 FUNCTION(gpio, fct0), 172 FUNCTION(gpio, ox810se_fct0),
170 FUNCTION(fct3, fct3), 173 FUNCTION(fct3, ox810se_fct3),
171}; 174};
172 175
173#define OXNAS_PINCTRL_GROUP(_pin, _name, ...) \ 176#define OXNAS_PINCTRL_GROUP(_pin, _name, ...) \
@@ -185,7 +188,7 @@ static const struct oxnas_function oxnas_functions[] = {
185 .fct = _fct, \ 188 .fct = _fct, \
186 } 189 }
187 190
188static const struct oxnas_pin_group oxnas_groups[] = { 191static const struct oxnas_pin_group oxnas_ox810se_groups[] = {
189 OXNAS_PINCTRL_GROUP(0, gpio0, 192 OXNAS_PINCTRL_GROUP(0, gpio0,
190 OXNAS_PINCTRL_FUNCTION(gpio, 0), 193 OXNAS_PINCTRL_FUNCTION(gpio, 0),
191 OXNAS_PINCTRL_FUNCTION(fct3, 3)), 194 OXNAS_PINCTRL_FUNCTION(fct3, 3)),
@@ -352,8 +355,8 @@ static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
352 return 0; 355 return 0;
353} 356}
354 357
355static int oxnas_pinmux_enable(struct pinctrl_dev *pctldev, 358static int oxnas_ox810se_pinmux_enable(struct pinctrl_dev *pctldev,
356 unsigned int func, unsigned int group) 359 unsigned int func, unsigned int group)
357{ 360{
358 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 361 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
359 const struct oxnas_pin_group *pg = &pctl->groups[group]; 362 const struct oxnas_pin_group *pg = &pctl->groups[group];
@@ -371,22 +374,22 @@ static int oxnas_pinmux_enable(struct pinctrl_dev *pctldev,
371 374
372 regmap_write_bits(pctl->regmap, 375 regmap_write_bits(pctl->regmap,
373 (pg->bank ? 376 (pg->bank ?
374 PINMUX_PRIMARY_SEL1 : 377 PINMUX_810_PRIMARY_SEL1 :
375 PINMUX_PRIMARY_SEL0), 378 PINMUX_810_PRIMARY_SEL0),
376 mask, 379 mask,
377 (functions->fct == 1 ? 380 (functions->fct == 1 ?
378 mask : 0)); 381 mask : 0));
379 regmap_write_bits(pctl->regmap, 382 regmap_write_bits(pctl->regmap,
380 (pg->bank ? 383 (pg->bank ?
381 PINMUX_SECONDARY_SEL1 : 384 PINMUX_810_SECONDARY_SEL1 :
382 PINMUX_SECONDARY_SEL0), 385 PINMUX_810_SECONDARY_SEL0),
383 mask, 386 mask,
384 (functions->fct == 2 ? 387 (functions->fct == 2 ?
385 mask : 0)); 388 mask : 0));
386 regmap_write_bits(pctl->regmap, 389 regmap_write_bits(pctl->regmap,
387 (pg->bank ? 390 (pg->bank ?
388 PINMUX_TERTIARY_SEL1 : 391 PINMUX_810_TERTIARY_SEL1 :
389 PINMUX_TERTIARY_SEL0), 392 PINMUX_810_TERTIARY_SEL0),
390 mask, 393 mask,
391 (functions->fct == 3 ? 394 (functions->fct == 3 ?
392 mask : 0)); 395 mask : 0));
@@ -402,9 +405,9 @@ static int oxnas_pinmux_enable(struct pinctrl_dev *pctldev,
402 return -EINVAL; 405 return -EINVAL;
403} 406}
404 407
405static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev, 408static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev,
406 struct pinctrl_gpio_range *range, 409 struct pinctrl_gpio_range *range,
407 unsigned int offset) 410 unsigned int offset)
408{ 411{
409 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 412 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
410 struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc); 413 struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
@@ -415,18 +418,18 @@ static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev,
415 418
416 regmap_write_bits(pctl->regmap, 419 regmap_write_bits(pctl->regmap,
417 (bank->id ? 420 (bank->id ?
418 PINMUX_PRIMARY_SEL1 : 421 PINMUX_810_PRIMARY_SEL1 :
419 PINMUX_PRIMARY_SEL0), 422 PINMUX_810_PRIMARY_SEL0),
420 mask, 0); 423 mask, 0);
421 regmap_write_bits(pctl->regmap, 424 regmap_write_bits(pctl->regmap,
422 (bank->id ? 425 (bank->id ?
423 PINMUX_SECONDARY_SEL1 : 426 PINMUX_810_SECONDARY_SEL1 :
424 PINMUX_SECONDARY_SEL0), 427 PINMUX_810_SECONDARY_SEL0),
425 mask, 0); 428 mask, 0);
426 regmap_write_bits(pctl->regmap, 429 regmap_write_bits(pctl->regmap,
427 (bank->id ? 430 (bank->id ?
428 PINMUX_TERTIARY_SEL1 : 431 PINMUX_810_TERTIARY_SEL1 :
429 PINMUX_TERTIARY_SEL0), 432 PINMUX_810_TERTIARY_SEL0),
430 mask, 0); 433 mask, 0);
431 434
432 return 0; 435 return 0;
@@ -498,17 +501,17 @@ static int oxnas_gpio_set_direction(struct pinctrl_dev *pctldev,
498 return 0; 501 return 0;
499} 502}
500 503
501static const struct pinmux_ops oxnas_pinmux_ops = { 504static const struct pinmux_ops oxnas_ox810se_pinmux_ops = {
502 .get_functions_count = oxnas_pinmux_get_functions_count, 505 .get_functions_count = oxnas_pinmux_get_functions_count,
503 .get_function_name = oxnas_pinmux_get_function_name, 506 .get_function_name = oxnas_pinmux_get_function_name,
504 .get_function_groups = oxnas_pinmux_get_function_groups, 507 .get_function_groups = oxnas_pinmux_get_function_groups,
505 .set_mux = oxnas_pinmux_enable, 508 .set_mux = oxnas_ox810se_pinmux_enable,
506 .gpio_request_enable = oxnas_gpio_request_enable, 509 .gpio_request_enable = oxnas_ox810se_gpio_request_enable,
507 .gpio_set_direction = oxnas_gpio_set_direction, 510 .gpio_set_direction = oxnas_gpio_set_direction,
508}; 511};
509 512
510static int oxnas_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, 513static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev,
511 unsigned long *config) 514 unsigned int pin, unsigned long *config)
512{ 515{
513 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 516 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
514 struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); 517 struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
@@ -521,8 +524,8 @@ static int oxnas_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
521 case PIN_CONFIG_BIAS_PULL_UP: 524 case PIN_CONFIG_BIAS_PULL_UP:
522 ret = regmap_read(pctl->regmap, 525 ret = regmap_read(pctl->regmap,
523 (bank->id ? 526 (bank->id ?
524 PINMUX_PULLUP_CTRL1 : 527 PINMUX_810_PULLUP_CTRL1 :
525 PINMUX_PULLUP_CTRL0), 528 PINMUX_810_PULLUP_CTRL0),
526 &arg); 529 &arg);
527 if (ret) 530 if (ret)
528 return ret; 531 return ret;
@@ -538,8 +541,9 @@ static int oxnas_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
538 return 0; 541 return 0;
539} 542}
540 543
541static int oxnas_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 544static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev,
542 unsigned long *configs, unsigned int num_configs) 545 unsigned int pin, unsigned long *configs,
546 unsigned int num_configs)
543{ 547{
544 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 548 struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
545 struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); 549 struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
@@ -561,8 +565,8 @@ static int oxnas_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
561 dev_dbg(pctl->dev, " pullup\n"); 565 dev_dbg(pctl->dev, " pullup\n");
562 regmap_write_bits(pctl->regmap, 566 regmap_write_bits(pctl->regmap,
563 (bank->id ? 567 (bank->id ?
564 PINMUX_PULLUP_CTRL1 : 568 PINMUX_810_PULLUP_CTRL1 :
565 PINMUX_PULLUP_CTRL0), 569 PINMUX_810_PULLUP_CTRL0),
566 mask, mask); 570 mask, mask);
567 break; 571 break;
568 default: 572 default:
@@ -575,20 +579,12 @@ static int oxnas_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
575 return 0; 579 return 0;
576} 580}
577 581
578static const struct pinconf_ops oxnas_pinconf_ops = { 582static const struct pinconf_ops oxnas_ox810se_pinconf_ops = {
579 .pin_config_get = oxnas_pinconf_get, 583 .pin_config_get = oxnas_ox810se_pinconf_get,
580 .pin_config_set = oxnas_pinconf_set, 584 .pin_config_set = oxnas_ox810se_pinconf_set,
581 .is_generic = true, 585 .is_generic = true,
582}; 586};
583 587
584static struct pinctrl_desc oxnas_pinctrl_desc = {
585 .name = "oxnas-pinctrl",
586 .pctlops = &oxnas_pinctrl_ops,
587 .pmxops = &oxnas_pinmux_ops,
588 .confops = &oxnas_pinconf_ops,
589 .owner = THIS_MODULE,
590};
591
592static void oxnas_gpio_irq_ack(struct irq_data *data) 588static void oxnas_gpio_irq_ack(struct irq_data *data)
593{ 589{
594 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 590 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
@@ -699,10 +695,51 @@ static struct oxnas_gpio_bank oxnas_gpio_banks[] = {
699 GPIO_BANK(1), 695 GPIO_BANK(1),
700}; 696};
701 697
698static struct oxnas_pinctrl ox810se_pinctrl = {
699 .functions = oxnas_ox810se_functions,
700 .nfunctions = ARRAY_SIZE(oxnas_ox810se_functions),
701 .groups = oxnas_ox810se_groups,
702 .ngroups = ARRAY_SIZE(oxnas_ox810se_groups),
703 .gpio_banks = oxnas_gpio_banks,
704 .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
705};
706
707static struct pinctrl_desc oxnas_ox810se_pinctrl_desc = {
708 .name = "oxnas-pinctrl",
709 .pins = oxnas_ox810se_pins,
710 .npins = ARRAY_SIZE(oxnas_ox810se_pins),
711 .pctlops = &oxnas_pinctrl_ops,
712 .pmxops = &oxnas_ox810se_pinmux_ops,
713 .confops = &oxnas_ox810se_pinconf_ops,
714 .owner = THIS_MODULE,
715};
716
717static struct oxnas_pinctrl_data oxnas_ox810se_pinctrl_data = {
718 .desc = &oxnas_ox810se_pinctrl_desc,
719 .pctl = &ox810se_pinctrl,
720};
721
722static const struct of_device_id oxnas_pinctrl_of_match[] = {
723 { .compatible = "oxsemi,ox810se-pinctrl",
724 .data = &oxnas_ox810se_pinctrl_data
725 },
726 { },
727};
728
702static int oxnas_pinctrl_probe(struct platform_device *pdev) 729static int oxnas_pinctrl_probe(struct platform_device *pdev)
703{ 730{
731 const struct of_device_id *id;
732 const struct oxnas_pinctrl_data *data;
704 struct oxnas_pinctrl *pctl; 733 struct oxnas_pinctrl *pctl;
705 734
735 id = of_match_node(oxnas_pinctrl_of_match, pdev->dev.of_node);
736 if (!id)
737 return -ENODEV;
738
739 data = id->data;
740 if (!data || !data->pctl || !data->desc)
741 return -EINVAL;
742
706 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 743 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
707 if (!pctl) 744 if (!pctl)
708 return -ENOMEM; 745 return -ENOMEM;
@@ -716,20 +753,14 @@ static int oxnas_pinctrl_probe(struct platform_device *pdev)
716 return -ENODEV; 753 return -ENODEV;
717 } 754 }
718 755
719 pctl->pins = oxnas_pins; 756 pctl->functions = data->pctl->functions;
720 pctl->npins = ARRAY_SIZE(oxnas_pins); 757 pctl->nfunctions = data->pctl->nfunctions;
721 pctl->functions = oxnas_functions; 758 pctl->groups = data->pctl->groups;
722 pctl->nfunctions = ARRAY_SIZE(oxnas_functions); 759 pctl->ngroups = data->pctl->ngroups;
723 pctl->groups = oxnas_groups; 760 pctl->gpio_banks = data->pctl->gpio_banks;
724 pctl->ngroups = ARRAY_SIZE(oxnas_groups); 761 pctl->nbanks = data->pctl->nbanks;
725 pctl->gpio_banks = oxnas_gpio_banks;
726 pctl->nbanks = ARRAY_SIZE(oxnas_gpio_banks);
727 762
728 oxnas_pinctrl_desc.pins = pctl->pins; 763 pctl->pctldev = pinctrl_register(data->desc, &pdev->dev, pctl);
729 oxnas_pinctrl_desc.npins = pctl->npins;
730
731 pctl->pctldev = pinctrl_register(&oxnas_pinctrl_desc,
732 &pdev->dev, pctl);
733 if (IS_ERR(pctl->pctldev)) { 764 if (IS_ERR(pctl->pctldev)) {
734 dev_err(&pdev->dev, "Failed to register pinctrl device\n"); 765 dev_err(&pdev->dev, "Failed to register pinctrl device\n");
735 return PTR_ERR(pctl->pctldev); 766 return PTR_ERR(pctl->pctldev);
@@ -805,11 +836,6 @@ static int oxnas_gpio_probe(struct platform_device *pdev)
805 return 0; 836 return 0;
806} 837}
807 838
808static const struct of_device_id oxnas_pinctrl_of_match[] = {
809 { .compatible = "oxsemi,ox810se-pinctrl", },
810 { },
811};
812
813static struct platform_driver oxnas_pinctrl_driver = { 839static struct platform_driver oxnas_pinctrl_driver = {
814 .driver = { 840 .driver = {
815 .name = "oxnas-pinctrl", 841 .name = "oxnas-pinctrl",