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authorFrank Wang <frank.wang@rock-chips.com>2017-06-01 23:20:26 -0400
committerKishon Vijay Abraham I <kishon@ti.com>2017-06-06 05:20:25 -0400
commitb59b1d390483e3ff3342d7b7cd0ec19e847a6142 (patch)
treec9932947e92e7a658b91bf8567b1d46e78949b86 /drivers/phy/rockchip
parent9632781122e5f7adfaf29aeb4387d7b354556593 (diff)
phy: rockchip-inno-usb2: add support of usb2-phy for rk3228 SoCs
This adds support usb2-phy for rk3228 SoCs and amend phy Documentation. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy/rockchip')
-rw-r--r--drivers/phy/rockchip/phy-rockchip-inno-usb2.c60
1 files changed, 60 insertions, 0 deletions
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index d026b4cf7523..626883d9d176 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1144,6 +1144,65 @@ disable_clks:
1144 return ret; 1144 return ret;
1145} 1145}
1146 1146
1147static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
1148 {
1149 .reg = 0x760,
1150 .num_ports = 2,
1151 .clkout_ctl = { 0x0768, 4, 4, 1, 0 },
1152 .port_cfgs = {
1153 [USB2PHY_PORT_OTG] = {
1154 .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 },
1155 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1156 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1157 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1158 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1159 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1160 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1161 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 },
1162 .utmi_ls = { 0x0480, 3, 2, 0, 1 },
1163 },
1164 [USB2PHY_PORT_HOST] = {
1165 .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 },
1166 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1167 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1168 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1169 }
1170 },
1171 .chg_det = {
1172 .opmode = { 0x0760, 3, 0, 5, 1 },
1173 .cp_det = { 0x0884, 4, 4, 0, 1 },
1174 .dcp_det = { 0x0884, 3, 3, 0, 1 },
1175 .dp_det = { 0x0884, 5, 5, 0, 1 },
1176 .idm_sink_en = { 0x0768, 8, 8, 0, 1 },
1177 .idp_sink_en = { 0x0768, 7, 7, 0, 1 },
1178 .idp_src_en = { 0x0768, 9, 9, 0, 1 },
1179 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 },
1180 .vdm_src_en = { 0x0768, 12, 12, 0, 1 },
1181 .vdp_src_en = { 0x0768, 11, 11, 0, 1 },
1182 },
1183 },
1184 {
1185 .reg = 0x800,
1186 .num_ports = 2,
1187 .clkout_ctl = { 0x0808, 4, 4, 1, 0 },
1188 .port_cfgs = {
1189 [USB2PHY_PORT_OTG] = {
1190 .phy_sus = { 0x800, 15, 0, 0, 0x1d1 },
1191 .ls_det_en = { 0x0684, 0, 0, 0, 1 },
1192 .ls_det_st = { 0x0694, 0, 0, 0, 1 },
1193 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 }
1194 },
1195 [USB2PHY_PORT_HOST] = {
1196 .phy_sus = { 0x804, 15, 0, 0, 0x1d1 },
1197 .ls_det_en = { 0x0684, 1, 1, 0, 1 },
1198 .ls_det_st = { 0x0694, 1, 1, 0, 1 },
1199 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 }
1200 }
1201 },
1202 },
1203 { /* sentinel */ }
1204};
1205
1147static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1206static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1148 { 1207 {
1149 .reg = 0x100, 1208 .reg = 0x100,
@@ -1269,6 +1328,7 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1269}; 1328};
1270 1329
1271static const struct of_device_id rockchip_usb2phy_dt_match[] = { 1330static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1331 { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
1272 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, 1332 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
1273 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, 1333 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1274 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, 1334 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },