Merge tag 'pci-v5.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI updates from Bjorn Helgaas:
 "Enumeration:

   - Consolidate _HPP/_HPX stuff in pci-acpi.c and simplify it
     (Krzysztof Wilczynski)

   - Fix incorrect PCIe device types and remove dev->has_secondary_link
     to simplify code that deals with upstream/downstream ports (Mika
     Westerberg)

   - After suspend, restore Resizable BAR size bits correctly for 1MB
     BARs (Sumit Saxena)

   - Enable PCI_MSI_IRQ_DOMAIN support for RISC-V (Wesley Terpstra)

  Virtualization:

   - Add ACS quirks for iProc PAXB (Abhinav Ratna), Amazon Annapurna
     Labs (Ali Saidi)

   - Move sysfs SR-IOV functions to iov.c (Kelsey Skunberg)

   - Remove group write permissions from sysfs sriov_numvfs,
     sriov_drivers_autoprobe (Kelsey Skunberg)

  Hotplug:

   - Simplify pciehp indicator control (Denis Efremov)

  Peer-to-peer DMA:

   - Allow P2P DMA between root ports for whitelisted bridges (Logan
     Gunthorpe)

   - Whitelist some Intel host bridges for P2P DMA (Logan Gunthorpe)

   - DMA map P2P DMA requests that traverse host bridge (Logan
     Gunthorpe)

  Amazon Annapurna Labs host bridge driver:

   - Add DT binding and controller driver (Jonathan Chocron)

  Hyper-V host bridge driver:

   - Fix hv_pci_dev->pci_slot use-after-free (Dexuan Cui)

   - Fix PCI domain number collisions (Haiyang Zhang)

   - Use instance ID bytes 4 & 5 as PCI domain numbers (Haiyang Zhang)

   - Fix build errors on non-SYSFS config (Randy Dunlap)

  i.MX6 host bridge driver:

   - Limit DBI register length (Stefan Agner)

  Intel VMD host bridge driver:

   - Fix config addressing issues (Jon Derrick)

  Layerscape host bridge driver:

   - Add bar_fixed_64bit property to endpoint driver (Xiaowei Bao)

   - Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC drivers separately
     (Xiaowei Bao)

  Mediatek host bridge driver:

   - Add MT7629 controller support (Jianjun Wang)

  Mobiveil host bridge driver:

   - Fix CPU base address setup (Hou Zhiqiang)

   - Make "num-lanes" property optional (Hou Zhiqiang)

  Tegra host bridge driver:

   - Fix OF node reference leak (Nishka Dasgupta)

   - Disable MSI for root ports to work around design problem (Vidya
     Sagar)

   - Add Tegra194 DT binding and controller support (Vidya Sagar)

   - Add support for sideband pins and slot regulators (Vidya Sagar)

   - Add PIPE2UPHY support (Vidya Sagar)

  Misc:

   - Remove unused pci_block_cfg_access() et al (Kelsey Skunberg)

   - Unexport pci_bus_get(), etc (Kelsey Skunberg)

   - Hide PM, VC, link speed, ATS, ECRC, PTM constants and interfaces in
     the PCI core (Kelsey Skunberg)

   - Clean up sysfs DEVICE_ATTR() usage (Kelsey Skunberg)

   - Mark expected switch fall-through (Gustavo A. R. Silva)

   - Propagate errors for optional regulators and PHYs (Thierry Reding)

   - Fix kernel command line resource_alignment parameter issues (Logan
     Gunthorpe)"

* tag 'pci-v5.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (112 commits)
  PCI: Add pci_irq_vector() and other stubs when !CONFIG_PCI
  arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
  arm64: tegra: Add configuration for PCIe C5 sideband signals
  PCI: tegra: Add support to enable slot regulators
  PCI: tegra: Add support to configure sideband pins
  PCI: vmd: Fix shadow offsets to reflect spec changes
  PCI: vmd: Fix config addressing when using bus offsets
  PCI: dwc: Add validation that PCIe core is set to correct mode
  PCI: dwc: al: Add Amazon Annapurna Labs PCIe controller driver
  dt-bindings: PCI: Add Amazon's Annapurna Labs PCIe host bridge binding
  PCI: Add quirk to disable MSI-X support for Amazon's Annapurna Labs Root Port
  PCI/VPD: Prevent VPD access for Amazon's Annapurna Labs Root Port
  PCI: Add ACS quirk for Amazon Annapurna Labs root ports
  PCI: Add Amazon's Annapurna Labs vendor ID
  MAINTAINERS: Add PCI native host/endpoint controllers designated reviewer
  PCI: hv: Use bytes 4 and 5 from instance ID as the PCI domain numbers
  dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries
  dt-bindings: PCI: tegra: Add sideband pins configuration entries
  PCI: tegra: Add Tegra194 PCIe support
  PCI: Get rid of dev->has_secondary_link flag
  ...

1 files changed, 169 insertions, 2 deletions

diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index 525fd3f272b3..b3f972e8cfed 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -240,6 +240,173 @@ void pci_iov_remove_virtfn(struct pci_dev *dev, int id)
         pci_dev_put(dev);
 }
 
+static ssize_t sriov_totalvfs_show(struct device *dev,
+                                   struct device_attribute *attr,
+                                   char *buf)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+
+        return sprintf(buf, "%u\n", pci_sriov_get_totalvfs(pdev));
+}
+
+static ssize_t sriov_numvfs_show(struct device *dev,
+                                 struct device_attribute *attr,
+                                 char *buf)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+
+        return sprintf(buf, "%u\n", pdev->sriov->num_VFs);
+}
+
+/*
+ * num_vfs > 0; number of VFs to enable
+ * num_vfs = 0; disable all VFs
+ *
+ * Note: SRIOV spec does not allow partial VF
+ *       disable, so it's all or none.
+ */
+static ssize_t sriov_numvfs_store(struct device *dev,
+                                  struct device_attribute *attr,
+                                  const char *buf, size_t count)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+        int ret;
+        u16 num_vfs;
+
+        ret = kstrtou16(buf, 0, &num_vfs);
+        if (ret < 0)
+                return ret;
+
+        if (num_vfs > pci_sriov_get_totalvfs(pdev))
+                return -ERANGE;
+
+        device_lock(&pdev->dev);
+
+        if (num_vfs == pdev->sriov->num_VFs)
+                goto exit;
+
+        /* is PF driver loaded w/callback */
+        if (!pdev->driver || !pdev->driver->sriov_configure) {
+                pci_info(pdev, "Driver does not support SRIOV configuration via sysfs\n");
+                ret = -ENOENT;
+                goto exit;
+        }
+
+        if (num_vfs == 0) {
+                /* disable VFs */
+                ret = pdev->driver->sriov_configure(pdev, 0);
+                goto exit;
+        }
+
+        /* enable VFs */
+        if (pdev->sriov->num_VFs) {
+                pci_warn(pdev, "%d VFs already enabled. Disable before enabling %d VFs\n",
+                         pdev->sriov->num_VFs, num_vfs);
+                ret = -EBUSY;
+                goto exit;
+        }
+
+        ret = pdev->driver->sriov_configure(pdev, num_vfs);
+        if (ret < 0)
+                goto exit;
+
+        if (ret != num_vfs)
+                pci_warn(pdev, "%d VFs requested; only %d enabled\n",
+                         num_vfs, ret);
+
+exit:
+        device_unlock(&pdev->dev);
+
+        if (ret < 0)
+                return ret;
+
+        return count;
+}
+
+static ssize_t sriov_offset_show(struct device *dev,
+                                 struct device_attribute *attr,
+                                 char *buf)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+
+        return sprintf(buf, "%u\n", pdev->sriov->offset);
+}
+
+static ssize_t sriov_stride_show(struct device *dev,
+                                 struct device_attribute *attr,
+                                 char *buf)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+
+        return sprintf(buf, "%u\n", pdev->sriov->stride);
+}
+
+static ssize_t sriov_vf_device_show(struct device *dev,
+                                    struct device_attribute *attr,
+                                    char *buf)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+
+        return sprintf(buf, "%x\n", pdev->sriov->vf_device);
+}
+
+static ssize_t sriov_drivers_autoprobe_show(struct device *dev,
+                                            struct device_attribute *attr,
+                                            char *buf)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+
+        return sprintf(buf, "%u\n", pdev->sriov->drivers_autoprobe);
+}
+
+static ssize_t sriov_drivers_autoprobe_store(struct device *dev,
+                                             struct device_attribute *attr,
+                                             const char *buf, size_t count)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+        bool drivers_autoprobe;
+
+        if (kstrtobool(buf, &drivers_autoprobe) < 0)
+                return -EINVAL;
+
+        pdev->sriov->drivers_autoprobe = drivers_autoprobe;
+
+        return count;
+}
+
+static DEVICE_ATTR_RO(sriov_totalvfs);
+static DEVICE_ATTR_RW(sriov_numvfs);
+static DEVICE_ATTR_RO(sriov_offset);
+static DEVICE_ATTR_RO(sriov_stride);
+static DEVICE_ATTR_RO(sriov_vf_device);
+static DEVICE_ATTR_RW(sriov_drivers_autoprobe);
+
+static struct attribute *sriov_dev_attrs[] = {
+        &dev_attr_sriov_totalvfs.attr,
+        &dev_attr_sriov_numvfs.attr,
+        &dev_attr_sriov_offset.attr,
+        &dev_attr_sriov_stride.attr,
+        &dev_attr_sriov_vf_device.attr,
+        &dev_attr_sriov_drivers_autoprobe.attr,
+        NULL,
+};
+
+static umode_t sriov_attrs_are_visible(struct kobject *kobj,
+                                       struct attribute *a, int n)
+{
+        struct device *dev = kobj_to_dev(kobj);
+
+        if (!dev_is_pf(dev))
+                return 0;
+
+        return a->mode;
+}
+
+const struct attribute_group sriov_dev_attr_group = {
+        .attrs = sriov_dev_attrs,
+        .is_visible = sriov_attrs_are_visible,
+};
+
 int __weak pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
 {
         return 0;
@@ -557,8 +724,8 @@ static void sriov_restore_state(struct pci_dev *dev)
         ctrl |= iov->ctrl & PCI_SRIOV_CTRL_ARI;
         pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, ctrl);
 
-        for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++)
-                pci_update_resource(dev, i);
+        for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
+                pci_update_resource(dev, i + PCI_IOV_RESOURCES);
 
         pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz);
         pci_iov_set_numvfs(dev, iov->num_VFs);