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authorCaesar Wang <wxt@rock-chips.com>2015-12-14 04:43:39 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-02-08 02:07:21 -0500
commitc37ff3fbe06f44e8ec3f8077b3a3c468635a8868 (patch)
treea4923291fecb7ed1b66f78f904ec3d44bd9ae6b2 /drivers/nvmem
parentd16abd30b3faee8efab30ed6198d3696e0304b57 (diff)
nvmem: rockchip: trivial: Make the driver more readability
1) Make the include file to sort from order 2) clean up the driver to make more readability Let's clean up such trivial details. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/nvmem')
-rw-r--r--drivers/nvmem/rockchip-efuse.c90
1 files changed, 42 insertions, 48 deletions
diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c
index f55213424222..a009795111e9 100644
--- a/drivers/nvmem/rockchip-efuse.c
+++ b/drivers/nvmem/rockchip-efuse.c
@@ -14,16 +14,16 @@
14 * more details. 14 * more details.
15 */ 15 */
16 16
17#include <linux/platform_device.h> 17#include <linux/clk.h>
18#include <linux/nvmem-provider.h> 18#include <linux/delay.h>
19#include <linux/slab.h>
20#include <linux/regmap.h>
21#include <linux/device.h> 19#include <linux/device.h>
22#include <linux/io.h> 20#include <linux/io.h>
23#include <linux/module.h> 21#include <linux/module.h>
24#include <linux/delay.h> 22#include <linux/nvmem-provider.h>
23#include <linux/slab.h>
25#include <linux/of.h> 24#include <linux/of.h>
26#include <linux/clk.h> 25#include <linux/platform_device.h>
26#include <linux/regmap.h>
27 27
28#define EFUSE_A_SHIFT 6 28#define EFUSE_A_SHIFT 6
29#define EFUSE_A_MASK 0x3ff 29#define EFUSE_A_MASK 0x3ff
@@ -35,10 +35,10 @@
35#define REG_EFUSE_CTRL 0x0000 35#define REG_EFUSE_CTRL 0x0000
36#define REG_EFUSE_DOUT 0x0004 36#define REG_EFUSE_DOUT 0x0004
37 37
38struct rockchip_efuse_context { 38struct rockchip_efuse_chip {
39 struct device *dev; 39 struct device *dev;
40 void __iomem *base; 40 void __iomem *base;
41 struct clk *efuse_clk; 41 struct clk *clk;
42}; 42};
43 43
44static int rockchip_efuse_write(void *context, const void *data, size_t count) 44static int rockchip_efuse_write(void *context, const void *data, size_t count)
@@ -52,34 +52,32 @@ static int rockchip_efuse_read(void *context,
52 void *val, size_t val_size) 52 void *val, size_t val_size)
53{ 53{
54 unsigned int offset = *(u32 *)reg; 54 unsigned int offset = *(u32 *)reg;
55 struct rockchip_efuse_context *_context = context; 55 struct rockchip_efuse_chip *efuse = context;
56 void __iomem *base = _context->base;
57 struct clk *clk = _context->efuse_clk;
58 u8 *buf = val; 56 u8 *buf = val;
59 int ret; 57 int ret;
60 58
61 ret = clk_prepare_enable(clk); 59 ret = clk_prepare_enable(efuse->clk);
62 if (ret < 0) { 60 if (ret < 0) {
63 dev_err(_context->dev, "failed to prepare/enable efuse clk\n"); 61 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
64 return ret; 62 return ret;
65 } 63 }
66 64
67 writel(EFUSE_LOAD | EFUSE_PGENB, base + REG_EFUSE_CTRL); 65 writel(EFUSE_LOAD | EFUSE_PGENB, efuse->base + REG_EFUSE_CTRL);
68 udelay(1); 66 udelay(1);
69 while (val_size) { 67 while (val_size) {
70 writel(readl(base + REG_EFUSE_CTRL) & 68 writel(readl(efuse->base + REG_EFUSE_CTRL) &
71 (~(EFUSE_A_MASK << EFUSE_A_SHIFT)), 69 (~(EFUSE_A_MASK << EFUSE_A_SHIFT)),
72 base + REG_EFUSE_CTRL); 70 efuse->base + REG_EFUSE_CTRL);
73 writel(readl(base + REG_EFUSE_CTRL) | 71 writel(readl(efuse->base + REG_EFUSE_CTRL) |
74 ((offset & EFUSE_A_MASK) << EFUSE_A_SHIFT), 72 ((offset & EFUSE_A_MASK) << EFUSE_A_SHIFT),
75 base + REG_EFUSE_CTRL); 73 efuse->base + REG_EFUSE_CTRL);
76 udelay(1); 74 udelay(1);
77 writel(readl(base + REG_EFUSE_CTRL) | 75 writel(readl(efuse->base + REG_EFUSE_CTRL) |
78 EFUSE_STROBE, base + REG_EFUSE_CTRL); 76 EFUSE_STROBE, efuse->base + REG_EFUSE_CTRL);
79 udelay(1); 77 udelay(1);
80 *buf++ = readb(base + REG_EFUSE_DOUT); 78 *buf++ = readb(efuse->base + REG_EFUSE_DOUT);
81 writel(readl(base + REG_EFUSE_CTRL) & 79 writel(readl(efuse->base + REG_EFUSE_CTRL) &
82 (~EFUSE_STROBE), base + REG_EFUSE_CTRL); 80 (~EFUSE_STROBE), efuse->base + REG_EFUSE_CTRL);
83 udelay(1); 81 udelay(1);
84 82
85 val_size -= 1; 83 val_size -= 1;
@@ -87,9 +85,9 @@ static int rockchip_efuse_read(void *context,
87 } 85 }
88 86
89 /* Switch to standby mode */ 87 /* Switch to standby mode */
90 writel(EFUSE_PGENB | EFUSE_CSB, base + REG_EFUSE_CTRL); 88 writel(EFUSE_PGENB | EFUSE_CSB, efuse->base + REG_EFUSE_CTRL);
91 89
92 clk_disable_unprepare(clk); 90 clk_disable_unprepare(efuse->clk);
93 91
94 return 0; 92 return 0;
95} 93}
@@ -114,48 +112,44 @@ static struct nvmem_config econfig = {
114}; 112};
115 113
116static const struct of_device_id rockchip_efuse_match[] = { 114static const struct of_device_id rockchip_efuse_match[] = {
117 { .compatible = "rockchip,rockchip-efuse",}, 115 { .compatible = "rockchip,rockchip-efuse", },
118 { /* sentinel */}, 116 { /* sentinel */},
119}; 117};
120MODULE_DEVICE_TABLE(of, rockchip_efuse_match); 118MODULE_DEVICE_TABLE(of, rockchip_efuse_match);
121 119
122static int rockchip_efuse_probe(struct platform_device *pdev) 120static int rockchip_efuse_probe(struct platform_device *pdev)
123{ 121{
124 struct device *dev = &pdev->dev;
125 struct resource *res; 122 struct resource *res;
126 struct nvmem_device *nvmem; 123 struct nvmem_device *nvmem;
127 struct regmap *regmap; 124 struct regmap *regmap;
128 void __iomem *base; 125 struct rockchip_efuse_chip *efuse;
129 struct clk *clk;
130 struct rockchip_efuse_context *context;
131 126
132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 127 efuse = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_efuse_chip),
133 base = devm_ioremap_resource(dev, res); 128 GFP_KERNEL);
134 if (IS_ERR(base)) 129 if (!efuse)
135 return PTR_ERR(base); 130 return -ENOMEM;
136 131
137 context = devm_kzalloc(dev, sizeof(struct rockchip_efuse_context), 132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
138 GFP_KERNEL); 133 efuse->base = devm_ioremap_resource(&pdev->dev, res);
139 if (IS_ERR(context)) 134 if (IS_ERR(efuse->base))
140 return PTR_ERR(context); 135 return PTR_ERR(efuse->base);
141 136
142 clk = devm_clk_get(dev, "pclk_efuse"); 137 efuse->clk = devm_clk_get(&pdev->dev, "pclk_efuse");
143 if (IS_ERR(clk)) 138 if (IS_ERR(efuse->clk))
144 return PTR_ERR(clk); 139 return PTR_ERR(efuse->clk);
145 140
146 context->dev = dev; 141 efuse->dev = &pdev->dev;
147 context->base = base;
148 context->efuse_clk = clk;
149 142
150 rockchip_efuse_regmap_config.max_register = resource_size(res) - 1; 143 rockchip_efuse_regmap_config.max_register = resource_size(res) - 1;
151 144
152 regmap = devm_regmap_init(dev, &rockchip_efuse_bus, 145 regmap = devm_regmap_init(efuse->dev, &rockchip_efuse_bus,
153 context, &rockchip_efuse_regmap_config); 146 efuse, &rockchip_efuse_regmap_config);
154 if (IS_ERR(regmap)) { 147 if (IS_ERR(regmap)) {
155 dev_err(dev, "regmap init failed\n"); 148 dev_err(efuse->dev, "regmap init failed\n");
156 return PTR_ERR(regmap); 149 return PTR_ERR(regmap);
157 } 150 }
158 econfig.dev = dev; 151
152 econfig.dev = efuse->dev;
159 nvmem = nvmem_register(&econfig); 153 nvmem = nvmem_register(&econfig);
160 if (IS_ERR(nvmem)) 154 if (IS_ERR(nvmem))
161 return PTR_ERR(nvmem); 155 return PTR_ERR(nvmem);